Semiconductor device

Abstract

To improve the Vf-Err characteristic of a semiconductor device.SOLUTION: A semiconductor device 100 includes a transistor part 70 and a diode part 80. The transistor part includes a trench contact part 60 provided on a front surface 21 of a semiconductor substrate 10, and a first plug region 19 of a second conductivity type with higher doping concentration than that in a base region 14 below the trench contact part. The diode part includes an anode region 84 of the second conductivity type provided over a drift region 18, and a second plug region 29 of the second conductivity type having higher doping concentration than that in the anode region. The second plug region contacts a front surface side electrode 53 at a position shallower than the first plug region in the depth direction of the semiconductor substrate.SELECTED DRAWING: Figure 1B

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Patent Document 1 describes a semiconductor device in which "the trench contact portion 60 is provided in each of the mesa portions 71 and 81" and "the plug region 19 is provided at the bottom of the trench contact portion 60 in each of the mesa portions 71 and 81". Patent Document 2 describes a semiconductor device in which "in the diode portion, the trench contact portion and the plug region are provided discretely". Patent Document 3 describes a semiconductor device in which "the anode contact layer 28 is partially formed on the surface layer portion of the anode layer 30". [Prior Art Documents] [Patent Documents] [Patent Document 1] JP-A-2023-135082 [Patent Document 2] JP-A-2023-19322 [Patent Document 3] WO2014 / 125584

Summary of the Invention

Problems to be Solved by the Invention

[0003] It is desirable to improve the Vf-Err characteristics of the semiconductor device.

Means for Solving the Problems

[0004] In a first aspect of the present invention, there is provided a semiconductor device including a transistor portion and a diode portion, the semiconductor device comprising: a plurality of trench portions provided on a front surface of a semiconductor substrate; a drift region of a first conductivity type provided in the semiconductor substrate; and a front surface side electrode provided above the semiconductor substrate. The transistor portion may include a base region of a second conductivity type provided above the drift region; an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region; a contact region of a second conductivity type provided above the base region and having a higher doping concentration than the base region; a trench contact portion provided on the front surface of the semiconductor substrate; and a first plug region of a second conductivity type having a higher doping concentration than the base region and provided below the trench contact portion. The diode portion may include an anode region of a second conductivity type provided above the drift region; and a second plug region of a second conductivity type having a higher doping concentration than the anode region. The second plug region may be in contact with the front surface side electrode at a position shallower than the first plug region in a depth direction of the semiconductor substrate.

[0005] In the semiconductor device described above, the second plug region may be in contact with the front surface side electrode on the front surface of the semiconductor substrate.

[0006] In any of the semiconductor devices described above, a lower end of the trench contact portion provided in the diode portion may be shallower than a lower end of the trench contact portion provided in the transistor portion.

[0007] In any of the semiconductor devices described above, in the diode portion, the second plug region may be provided alternately with the anode region in a trench extending direction of the plurality of trench portions.

[0008] In any of the semiconductor devices described above, in the trench extending direction, a width of the first plug region provided in the transistor portion may be larger than a width of the second plug region provided in the diode portion.

[0009] In any of the semiconductor devices described above, the lower end of the first plug region may be deeper than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0010] In any of the semiconductor devices described above, the lower end of the first plug region may be at the same depth as the lower end of the emitter region or shallower than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0011] In any of the semiconductor devices described above, the doping concentration of the anode region may be lower than the doping concentration of the base region.

[0012] In any of the semiconductor devices described above, the doping concentration of the anode region may be 1E16 cm -3 or more and 1E18 cm -3 or less.

[0013] In any of the semiconductor devices described above, the lower end of the trench contact portion may be shallower than the lower end of the emitter region in the depth direction of the semiconductor substrate.

[0014] In any of the semiconductor devices described above, the transistor portion may have a main region having the emitter region and a boundary region provided closer to the diode portion than the main region. The boundary region may have a first boundary portion including the contact region on the front surface of the semiconductor substrate and a second boundary portion provided closer to the diode portion than the first boundary portion and including the anode region.

[0015] In any of the semiconductor devices described above, the trench contact portion may not be provided in the boundary region.

[0016] In any of the semiconductor devices described above, the width of the contact region provided in the first boundary portion in the trench extension direction may be larger than the width of the contact region provided in the main region in the trench extension direction.

[0017] In any of the semiconductor devices described above, the second boundary portion may include the second plug region.

[0018] In any of the semiconductor devices described above, in the trench extension direction of the plurality of trench portions, the width of the second plug region provided in the second boundary portion may be smaller than the width of the first plug region.

[0019] In any of the semiconductor devices described above, the diode portion may have a cathode region of a first conductivity type having a doping concentration higher than that of the drift region on the back surface of the semiconductor substrate. The cathode region may include a first cathode portion of a first conductivity type and a second cathode portion of a second conductivity type.

[0020] In any of the semiconductor devices described above, the first cathode portion and the second cathode portion may be alternately and repeatedly arranged in a predetermined direction.

[0021] In any of the semiconductor devices described above, in the transistor portion, an accumulation region of a first conductivity type provided above the drift region and having a doping concentration higher than that of the drift region may be provided.

[0022] In any of the semiconductor devices described above, above the semiconductor substrate, an interlayer insulating film provided with a contact hole for electrically connecting the front surface side electrode to the semiconductor substrate may be provided. The second plug region may be provided along the shape of the contact hole in a top view.

[0023] Note that the above summary of the invention does not list all the features of the present invention. Also, sub-combinations of these feature groups can also be inventions.

Brief Description of the Drawings

[0024]

Figure 1A

Figure 1B

Figure 1C

Figure 1D

Figure 1E

Figure 2

Figure 3

Figure 4

Figure 5

Modes for Carrying Out the Invention

[0025] Hereinafter, the present invention will be described through embodiments of the invention. However, the following embodiments do not limit the invention according to the claims. Also, not all combinations of features described in the embodiments are essential for the solution means of the invention.

[0026] In this specification, one side in the direction parallel to the depth direction of the semiconductor substrate is referred to as "upper", and the other side is referred to as "lower". Of the two main surfaces of the substrate, layer or other member, one surface is referred to as the upper surface and the other surface is referred to as the lower surface. The directions of "upper" and "lower" are not limited to the direction of gravity or the direction at the time of mounting the semiconductor device.

[0027] In this specification, when explaining technical matters, orthogonal coordinate axes of the X-axis, Y-axis, and Z-axis may be used. The orthogonal coordinate axes only specify the relative positions of components and do not limit a specific direction. For example, the Z-axis does not limit and indicate the height direction with respect to the ground. Note that the +Z-axis direction and the -Z-axis direction are opposite directions. When described as the Z-axis direction without specifying positive or negative, it means the directions parallel to the +Z-axis and -Z-axis.

[0028] In this specification, orthogonal axes parallel to the upper surface and the lower surface of the semiconductor substrate are defined as the X-axis and the Y-axis. Also, an axis perpendicular to the upper surface and the lower surface of the semiconductor substrate is defined as the Z-axis. In this specification, the direction of the Z-axis may sometimes be referred to as the depth direction. Also, in this specification, the directions parallel to the upper surface and the lower surface of the semiconductor substrate, including the X-axis and the Y-axis, may sometimes be referred to as the horizontal direction.

[0029] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of the P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of the P type or N type.

[0030] FIG. 1A shows an example of the upper surface of the semiconductor device 100. The semiconductor device 100 in this example includes a transistor portion 70 and a diode portion 80. For example, the semiconductor device 100 is a reverse conducting IGBT (RC-IGBT: Reverse Conducting IGBT).

[0031] The transistor portion 70 is a region obtained by projecting the collector region 22 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The back surface 23 will be described later. The transistor portion 70 includes a transistor such as an IGBT. In this example, the transistor portion 70 is an IGBT. Note that the transistor portion 70 may be other transistors such as a MOSFET.

[0032] The transistor portion 70 in this example includes a main region 75 having an emitter region 12 and a boundary region 90 provided closer to the diode portion 80 than the main region 75. The main region 75 is a region that operates as a transistor during the operation of the semiconductor device 100. In the mesa portion 71 of the main region 75, on the front surface 21 of the semiconductor substrate 10, the emitter region 12 and the contact region 15 are alternately provided in the extending direction. The front surface 21 will be described later.

[0033] The diode portion 80 is a region obtained by projecting a cathode region 82 provided on the back surface 23 side of the semiconductor substrate 10 onto the upper surface of the semiconductor substrate 10. The diode portion 80 includes a diode such as a free wheel diode (FWD) provided adjacent to the transistor portion 70 on the front surface of the semiconductor substrate 10. On the back surface of the semiconductor substrate 10, a P+ type collector region may be provided in a region other than the cathode region.

[0034] The boundary region 90 does not have an emitter region 12. That is, the boundary region 90 is a region that does not operate as a transistor during the operation of the semiconductor device 100. By providing the boundary region 90 that does not perform transistor operation between the main region 75 and the diode portion 80, hole injection during the reverse recovery operation of the semiconductor device 100 can be suppressed. The boundary region 90 has a first boundary portion 190 and a second boundary portion 290.

[0035] The first boundary portion 190 includes the contact region 15 on the front surface 21 of the semiconductor substrate 10. In the first boundary portion 190, the contact region 15 is provided to extend from the base region 14 at the negative end in the trench extending direction (in this example, the Y-axis direction) to the base region 14 at the positive end in the trench extending direction. The first boundary portion 190 may be provided in the mesa portion closest to the main region 75 among one or more mesa portions of the boundary region 90. The first boundary portion 190 may be provided across a plurality of mesa portions. The first boundary portion 190 in this example has one mesa portion 191.

[0036] The second boundary portion 290 is provided closer to the diode portion 80 than the first boundary portion 190 and includes an anode region 84 on the front surface 21 of the semiconductor substrate 10. The second boundary portion 290 may be provided across a plurality of mesa portions. The second boundary portion 290 in this example has two mesa portions 291, but may have three or more mesa portions 291.

[0037] In this figure, a region around the active portion of the semiconductor device 100 is shown, and other regions are omitted. For example, an edge termination structure portion may be provided in the negative side region of the semiconductor device 100 in the Y-axis direction. The edge termination structure portion relaxes the electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure portion has, for example, a guard ring, a field plate, a RESURF, and a structure combining these. In this example, for the sake of convenience, the edge on the negative side in the Y-axis direction is described, but the same applies to other edges of the semiconductor device 100.

[0038] The semiconductor substrate 10 is a substrate formed of a semiconductor material. The semiconductor substrate 10 may be a silicon substrate or a silicon carbide substrate. The semiconductor substrate 10 in this example is a silicon substrate.

[0039] The semiconductor device 100 in this example includes an emitter region 12, a base region 14, a contact region 15, a well region 17, a dummy trench portion 30, a gate trench portion 40, and an anode region 84 on the front surface 21 of the semiconductor substrate 10. The semiconductor device 100 in this example includes a first plug region 19 and a second plug region 29 inside the semiconductor substrate 10. Further, the semiconductor device 100 in this example includes an emitter electrode 52 and a gate metal layer 50 provided above the front surface 21 of the semiconductor substrate 10.

[0040] The emitter region 12 is provided above the base region 14 and is a region of a first conductivity type having a higher doping concentration than the drift region 18 described later. The emitter region 12 is, for example, of N+ type. An example of the dopant in the emitter region 12 is arsenic (As). The emitter region 12 is provided in contact with the gate trench portion 40 on the front surface 21 of the mesa portion 71. The emitter region 12 may be provided to extend in the trench array direction (in this example, the X-axis direction) from one of the two trench portions sandwiching the mesa portion 71 to the other.

[0041] Also, the emitter region 12 may or may not be in contact with the dummy trench portion 30. The emitter region 12 in this example is in contact with the dummy trench portion 30.

[0042] The base region 14 is a region of a second conductivity type provided above the drift region 18. The base region 14 is, for example, of P- type. The doping concentration of the base region 14 may be 1E16 cm -3 or more, and may be 5E18 cm -3 or less. The base region 14 may be provided at both ends in the Y-axis direction of the mesa portion 71 on the front surface 21 of the semiconductor substrate 10. Note that FIG. 1A shows only one end in the Y-axis direction of the base region 14.

[0043] The contact region 15 is provided above the base region 14 and is a region of a second conductivity type having a higher doping concentration than the base region 14. The contact region 15 is, for example, of P+ type. The doping concentration of the contact region 15 may be 1E21 cm -3 or more, and may be 1E22 cm -3 or less.

[0044] The contact region 15 in this example is provided on the front surface 21 of the mesa portion 71 and the mesa portion 191. That is, the contact region 15 in this example is provided in the main region 75 and the first boundary portion 190. The contact region 15 may be provided in the trench array direction (in this example, the X-axis direction) from one of the two trench portions sandwiching the mesa portion 71 and the mesa portion 191 to the other.

[0045] The width Wp2 in the trench extension direction of the contact region 15 provided in the first boundary portion 190 is larger than the width Wp1 in the trench extension direction of the contact region 15 provided in the main region 75. The contact regions 15 are alternately provided in the mesa portion 71 of the main region 75 in the trench extension direction with the emitter regions 12. The contact regions 15 are provided to extend in the trench extension direction in the mesa portion 191 of the first boundary portion 190.

[0046] The contact region 15 may or may not be in contact with the gate trench portion 40 or the dummy trench portion 30. The contact region 15 of this example is in contact with the dummy trench portion 30 and the gate trench portion 40.

[0047] The well region 17 is a region of the second conductivity type provided above the drift region 18. The well region 17 is an example of a well region provided on the peripheral side of the active portion. The well region 17 is, for example, of P+ type. The well region 17 is formed within a predetermined range from the end of the active portion on the side where the gate metal layer 50 is provided. The diffusion depth of the well region 17 may be deeper than the depths of the gate trench portion 40 and the dummy trench portion 30. A partial region of the gate trench portion 40 and the dummy trench portion 30 on the gate metal layer 50 side is formed in the well region 17. The bottoms of the ends in the extension direction of the gate trench portion 40 and the dummy trench portion 30 may be covered by the well region 17.

[0048] The anode region 84 is a region of the second conductivity type provided above the drift region 18. The anode region 84 is, for example, of P- type. The doping concentration of the anode region 84 may be lower than the doping concentration of the base region 14 or may be the same as the doping concentration of the base region 14. In one example, the doping concentration of the anode region 84 is 1E16 cm -3 above, 1E18 cm -3The following is the case. By making the doping concentration of the anode region 84 lower than the doping concentration of the base region 14, the reverse recovery loss Err of the semiconductor device 100 can be reduced.

[0049] The first plug region 19 is a region of the second conductivity type having a higher doping concentration than the base region 14 provided below the trench contact portion 60 in the transistor portion 70. The first plug region 19 is, for example, of P+ type. The doping concentration of the first plug region 19 may be the same as the doping concentration of the contact region 15, or may be higher than the doping concentration of the contact region 15. The doping concentration of the first plug region 19 in this example is the same as the doping concentration of the contact region 15. In one example, the doping concentration of the first plug region 19 is 1E21 cm -3 or more and 1E22 cm -3 or less.

[0050] The second plug region 29 is a region of the second conductivity type having a higher doping concentration than the anode region 84. The second plug region 29 is, for example, of P+ type. The doping concentration of the second plug region 29 may be the same as the doping concentration of the first plug region 19, or may be different. The doping concentration of the second plug region 29 in this example is the same as the doping concentration of the first plug region 19.

[0051] In the diode portion 80, the second plug region 29 is provided alternately with the anode region 84 in the trench extending direction of the plurality of trench portions. That is, the second plug region 29 is selectively provided in the trench extending direction (in this example, the Y-axis direction).

[0052] In the trench extension direction, the width W19 of the first plug region 19 provided in the transistor portion 70 is larger than the width W29 of the second plug region 29 provided in the diode portion 80. The first plug region 19 may be provided so as to entirely cover the lower part of the contact hole 54 in a top view. That is, the first plug region 19 may be continuously provided in the extension direction of the contact hole 54 (in this example, the Y-axis direction). Thereby, the extraction of holes through the first plug region 19 becomes easy, and the latch-up of the semiconductor device 100 can be suppressed. Note that when simply referred to as a top view in this specification, it means viewing from the upper surface side of the semiconductor substrate 10.

[0053] The second plug region 29 may be provided at the second boundary portion 290. That is, the second boundary portion 290 may include the second plug region 29. Also, in the trench extension direction, the width of the second plug region 29 provided at the second boundary portion 290 may be smaller than the width of the first plug region 19 provided in the mesa portion 71. Thereby, the hole injection during the reverse recovery operation of the semiconductor device 100 can be suppressed.

[0054] The first plug region 19 and the second plug region 29 may be simultaneously formed by the same ion implantation process. As an example, the manufacturing method of the semiconductor device 100 includes, in this order, a step of forming a contact hole 54 in the interlayer insulating film 38 of the transistor portion 70 and the diode portion 80, a step of etching the semiconductor substrate 10 exposed through the opening of the contact hole 54 in the transistor portion 70, and a step of ion implanting to form the first plug region 19 and the second plug region 29. The interlayer insulating film 38 will be described later. Note that after forming the contact hole 54 in the transistor portion 70 and etching the semiconductor substrate 10 first, a step of forming the contact hole 54 in the diode portion 80 and ion implanting may be performed.

[0055] The emitter electrode 52 is provided above the gate trench portion 40, the dummy trench portion 30, the emitter region 12, the base region 14, the contact region 15, the well region 17, the connection portion 25, and the anode region 84. Further, the gate metal layer 50 is provided above the well region 17 and the connection portion 25.

[0056] The emitter electrode 52 and the gate metal layer 50 are formed of a material containing metal. At least a part of the emitter electrode 52 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). At least a part of the gate metal layer 50 may be formed of a metal such as aluminum (Al), or a metal alloy such as an aluminum-silicon alloy (AlSi) or an aluminum-silicon-copper alloy (AlSiCu). The emitter electrode 52 and the gate metal layer 50 may have a barrier metal layer formed of titanium or a titanium compound or the like under a region formed of aluminum or the like. The emitter electrode 52 and the gate metal layer 50 are provided separately from each other.

[0057] The emitter electrode 52 and the gate metal layer 50 are provided above the semiconductor substrate 10 with the interlayer insulating film 38 interposed therebetween. The interlayer insulating film 38 is omitted in FIG. 1A. Contact holes 54, 55, and 56 are provided penetrating the interlayer insulating film 38.

[0058] The contact hole 54 is formed above each of the emitter region 12, the contact region 15, and the anode region 84 in the transistor portion 70 and the diode portion 80. The contact hole 54 is not provided above the well regions 17 provided at both ends in the Y-axis direction. Thus, one or more contact holes 54 are formed in the interlayer insulating film. The one or more contact holes 54 may be provided extending in the trench extending direction of the plurality of trench portions.

[0059] The emitter electrode 52 is electrically connected to the semiconductor substrate 10 via the contact hole 54. A trench contact portion 60 provided on the front surface 21 of the semiconductor substrate 10 may be formed below the contact hole 54.

[0060] The trench contact portion 60 electrically connects the emitter electrode 52 and the semiconductor substrate 10. The trench contact portion 60 is provided continuously with the contact hole 54. The trench contact portion 60 of this example is provided in the mesa portion 71 and is not provided in the mesa portion 81, the mesa portion 191, and the mesa portion 291. That is, the trench contact portion 60 is not provided in the diode portion 80 and the boundary region 90.

[0061] The trench contact portion 60 has a conductive material filled in the contact hole 54. The trench contact portion 60 is provided between two adjacent trench portions among the plurality of trench portions. The trench contact portion 60 may have the same material as the emitter electrode 52. Details of the trench contact portion 60 will be described later.

[0062] The contact hole 55 electrically connects the gate metal layer 50 and the gate conductive portion in the gate trench portion 40 via the connection portion 25. A trench contact portion 60 may be formed inside the contact hole 55.

[0063] The contact hole 56 connects the emitter electrode 52 and the dummy conductive portion in the dummy trench portion 30. A trench contact portion 60 may be formed inside the contact hole 56.

[0064] The connection part 25 is connected to a front-side metal layer such as the emitter electrode 52 or the gate metal layer 50. In one example, the connection part 25 is provided between the gate metal layer 50 and the gate conductive part. The connection part 25 in this example is provided to extend in the X-axis direction and may be electrically connected to the gate conductive part. The connection part 25 may also be provided between the emitter electrode 52 and the dummy conductive part. The connection part 25 is a material having conductivity, such as polysilicon doped with impurities. The connection part 25 in this example is polysilicon doped with N-type impurities (N+). The connection part 25 is provided above the front surface 21 of the semiconductor substrate 10 via an insulating film such as an oxide film.

[0065] The gate trench part 40 is an example of a plurality of trench parts extending in a predetermined extending direction on the front surface 21 side of the semiconductor substrate 10. The gate trench part 40 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction). The gate trench part 40 is an example of a MOS gate structure provided in the semiconductor device 100. The gate trench part 40 in this example has two extending parts 41 extending along an extending direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the arrangement direction, and a connecting part 43 connecting the two extending parts 41.

[0066] It is preferable that at least a part of the connecting part 43 is formed in a curved shape. By connecting the ends of the two extending parts 41 of the gate trench part 40, the electric field concentration at the ends of the extending parts 41 can be alleviated. In the connecting part 43 of the gate trench part 40, the gate metal layer 50 may be electrically connected to the gate conductive part via the connection part 25.

[0067] The dummy trench part 30 is an example of a plurality of trench parts extending in a predetermined extending direction on the front surface 21 side of the semiconductor substrate 10. The dummy trench part 30 is a trench part electrically connected to the emitter electrode 52. The dummy trench part 30 is arranged at a predetermined interval along a predetermined arrangement direction (in this example, the X-axis direction), similar to the gate trench part 40.

[0068] In this example, the dummy trench portion 30, similar to the gate trench portion 40, has two extending portions 31 that extend along an extending direction (in this example, the Y-axis direction) parallel to the front surface 21 of the semiconductor substrate 10 and perpendicular to the array direction, and a connecting portion 33 that connects the two extending portions 31. The dummy trench portion 30 may have an I shape on the front surface 21 of the semiconductor substrate 10. That is, the dummy trench portion 30 may have only one extending portion 31 without the connecting portion 33.

[0069] The transistor portion 70 in this example has a structure in which one gate trench portion 40 and two dummy trench portions 30 are repeatedly arranged. That is, the transistor portion 70 in this example has the gate trench portion 40 and the dummy trench portion 30 in a ratio of 1:2. For example, the transistor portion 70 has two extending portions 31 between two extending portions 41.

[0070] However, the ratio of the gate trench portion 40 to the dummy trench portion 30 is not limited to this example. The ratio of the gate trench portion 40 may be larger than the ratio of the dummy trench portion 30, and the ratio of the dummy trench portion 30 may be larger than the ratio of the gate trench portion 40. The ratio of the gate trench portion 40 to the dummy trench portion 30 may be 1:1 or 2:3. Also, the transistor portion 70 may have a structure in which all the trench portions are gate trench portions 40 and no dummy trench portion 30.

[0071] FIG. 1B shows an example of the a-a' cross section in FIG. 1A. The a-a' cross section is an XZ plane passing through the second plug region 29 in the diode portion 80. The semiconductor device 100 in this example has, in the a-a' cross section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the trench contact portion 60, and the collector electrode 24. The collector electrode 24 is an example of a back surface side metal layer provided in contact with the back surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the trench contact portion 60 are examples of a front surface side electrode 53 provided above the semiconductor substrate 10. The front surface side electrode 53 may include a metal layer such as a barrier metal layer.

[0072] The drift region 18 is a region of a first conductivity type provided in the semiconductor substrate 10. The drift region 18 is, for example, N-type. The drift region 18 may be a region remaining in the semiconductor substrate 10 without other doping regions being formed. That is, the doping concentration of the drift region 18 may be the doping concentration of the semiconductor substrate 10.

[0073] The buffer region 20 is a region of a first conductivity type provided on the back surface 23 side of the semiconductor substrate 10 rather than the drift region 18. The doping concentration of the buffer region 20 is higher than the doping concentration of the drift region 18. The buffer region 20 is, for example, N-type. The buffer region 20 may function as a field stop layer that prevents the depletion layer spreading from the lower surface side of the base region 14 from reaching the collector region 22 of the second conductivity type. Note that the buffer region 20 may be omitted.

[0074] The collector region 22 is provided below the buffer region 20 in the transistor portion 70. The collector region 22 has a second conductivity type. The collector region 22 is, for example, P+-type.

[0075] The cathode region 82 is a region of a first conductivity type provided on the back surface 23 of the semiconductor substrate 10 in the diode portion 80 and having a higher doping concentration than the drift region 18. The cathode region 82 is, for example, N+-type.

[0076] The collector electrode 24 is formed on the back surface 23 of the semiconductor substrate 10. The collector electrode 24 is formed of a conductive material such as metal. The material of the collector electrode 24 may be the same as or different from the material of the emitter electrode 52.

[0077] The accumulation region 16 is provided above the drift region 18 and is a region of a first conductivity type having a higher doping concentration than the drift region 18. The accumulation region 16 is, for example, N-type. However, the accumulation region 16 may not be provided.

[0078] The storage region 16 is provided in contact with the gate trench portion 40. The storage region 16 may or may not be in contact with the dummy trench portion 30. The storage region 16 may be provided in multiple stages in the depth direction of the semiconductor substrate 10. In this example, the storage region 16 is provided in two stages. By providing the storage region 16, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage of the transistor portion 70 can be reduced.

[0079] One or more gate trench portions 40 and one or more dummy trench portions 30 are provided on the front surface 21. Each trench portion is provided from the front surface 21 to the drift region 18. In the region where at least any one of the emitter region 12, the base region 14, the contact region 15, the storage region 16, and the anode region 84 is provided, each trench portion penetrates these regions and reaches the drift region 18. The fact that the trench portion penetrates the doping region is not limited to the case where the trench portion is formed in the order of forming the doping region and then the trench portion. The case where the doping region is formed between the trench portions after the trench portions are formed is also included in the case where the trench portion penetrates the doping region.

[0080] The gate trench portion 40 has a gate trench formed on the front surface 21, a gate insulating film 42, and a gate conductive portion 44. The gate insulating film 42 is formed to cover the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is formed inside the gate insulating film 42 inside the gate trench. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered by the interlayer insulating film 38 on the front surface 21.

[0081] The gate conductive portion 44 includes a region that faces the base region 14 adjacent to the mesa portion 71 side with the gate insulating film 42 interposed therebetween in the depth direction of the semiconductor substrate 10. When a predetermined voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that contacts the gate trench.

[0082] The dummy trench portion 30 may have the same structure as the gate trench portion 40. The dummy trench portion 30 has a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 formed on the front surface 21 side. The dummy insulating film 32 is formed to cover the inner wall of the dummy trench. The dummy conductive portion 34 is formed inside the dummy trench and is formed closer to the inside than the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 and the semiconductor substrate 10. The dummy trench portion 30 may be covered by an interlayer insulating film 38 on the front surface 21.

[0083] The interlayer insulating film 38 is provided above the semiconductor substrate 10. The interlayer insulating film 38 of this example is provided in contact with the front surface 21. An emitter electrode 52 is provided above the interlayer insulating film 38. The interlayer insulating film 38 is provided with one or a plurality of contact holes 54 for electrically connecting the front surface side electrode 53 to the semiconductor substrate 10.

[0084] The lower end D1 of the trench contact portion 60 is shallower than the lower end D12 of the emitter region 12 in the depth direction of the semiconductor substrate 10. That is, the trench contact portion 60 does not penetrate the emitter region 12 and terminates inside the emitter region 12. The distance from the front surface 21 of the semiconductor substrate 10 to the lower end D1 of the trench contact portion 60 may be 0.3 μm or more and may be 0.5 μm or less. Thereby, the influence on the threshold value of the semiconductor device 100 is reduced, and the miniaturization of the semiconductor device 100 becomes easy.

[0085] The first plug region 19 is provided so as to cover the bottom of the trench contact portion 60. Thereby, the extraction of holes from the first plug region 19 to the trench contact portion 60 becomes easy, and the latch-up of the semiconductor device 100 can be suppressed.

[0086] The lower end of the first plug region 19 is at the same depth as the lower end D12 of the emitter region 12 or shallower than the lower end D12 of the emitter region 12 in the depth direction of the semiconductor substrate 10. That is, the first plug region 19 does not have a protruding portion that protrudes to the base region 14. In this example, the lower end of the first plug region 19 is provided at the same depth as the lower end D12 of the emitter region 12. By making the lower end of the first plug region 19 at the same depth as the lower end D12 of the emitter region 12 or shallower than the lower end D12 of the emitter region 12, the doping concentration of the base region 14 is made uniform, the influence on the threshold value of the semiconductor device 100 is reduced, and the miniaturization of the semiconductor device 100 becomes easy.

[0087] The second plug region 29 is in contact with the front surface side electrode 53 at a position shallower than the first plug region 19 in the depth direction of the semiconductor substrate 10. In this example, the first plug region 19 is in contact with the front surface side electrode 53 on the side wall of the trench contact portion 60 that is below the front surface 21 of the semiconductor substrate 10, and the second plug region is in contact with the front surface side electrode 53 on the front surface 21 of the semiconductor substrate 10. Thereby, since the front surface side electrode 53 and the semiconductor substrate 10 can be connected in the vicinity of the front surface 21 where the doping concentration is high in the diode portion 80, the forward voltage Vf of the diode portion 80 can be reduced while suppressing an increase in the reverse recovery loss Err of the semiconductor device 100.

[0088] In this example, the trench contact portion 60 is provided in the main region 75, and the trench contact portion 60 is not provided in the diode portion 80, the first boundary portion 190, and the second boundary portion 290. Thereby, the amount of hole injection from the anode region 84 increases, and the forward voltage Vf of the diode portion 80 can be reduced.

[0089] FIG. 1C shows an example of the b-b' cross-section in FIG. 1A. The b-b' cross-section is an XZ plane that does not pass through the second plug region 29 in the diode portion 80. Using FIG. 1C, the differences from FIG. 1B will be described.

[0090] In the cross-section shown in FIG. 1C, the second plug region 29 is not provided in the diode portion 80 and the second boundary portion 290. By having a region where the second plug region 29 is not provided in this way, an increase in the reverse recovery loss Err can be suppressed.

[0091] In the cross-section shown in FIG. 1C, the contact region 15 is formed to the same depth as the emitter region 12. The contact region 15 may be formed to a position deeper than the emitter region 12. This facilitates the extraction of holes from the base region 14 and can suppress the latch-up of the semiconductor device 100.

[0092] FIG. 1D shows an example of the c-c' cross-section in FIG. 1A. The c-c' cross-section is a YZ cross-section that passes through the contact hole 54 in the transistor portion 70. The semiconductor device 100 of this example has, in the c-c' cross-section, the semiconductor substrate 10, the interlayer insulating film 38, the emitter electrode 52, the trench contact portion 60, and the collector electrode 24.

[0093] The first plug region 19 of this example is provided in the transistor portion 70 so as to entirely cover the bottom of the trench contact portion 60. This facilitates the extraction of holes from the first plug region 19 to the trench contact portion 60 and can suppress the latch-up of the semiconductor device 100. However, there may be a portion where the bottom of the trench contact portion 60 is not covered by the first plug region 19.

[0094] FIG. 1E shows an example of the d-d' cross-section in FIG. 1A. The d-d' cross-section is a YZ cross-section that passes through the contact hole 54 in the diode portion 80. Using FIG. 1E, the differences from FIG. 1D will be described.

[0095] In the diode section 80, the trench contact section 60 is not provided. The second plug region 29 is provided on the front surface 21 of the semiconductor substrate 10 in the diode section 80. As a result, the doping concentration on the front surface 21 where the emitter electrode 52 and the semiconductor substrate 10 are electrically connected increases, and the amount of hole injection increases, so that the forward voltage Vf of the diode section 80 can be reduced.

[0096] The second plug region 29 is provided alternately with the anode region 84 in the extending direction of the contact hole 54. That is, the second plug region 29 is selectively provided in the extending direction of the contact hole 54 (in this example, the Y-axis direction). Thereby, while reducing the forward voltage Vf of the diode section 80, an increase in the reverse recovery loss Err can be suppressed.

[0097] The cathode region 82 of this example has a first cathode section 181 and a second cathode section 182. The first cathode section 181 is a region of the first conductivity type having a higher doping concentration than the drift region 18. The doping concentration of the first cathode section 181 may be higher than the doping concentration of the buffer region 20. In one example, the first cathode section 181 is of N+ type.

[0098] The second cathode section 182 is a region of the second conductivity type provided adjacent to the first cathode section 181 on the back surface 23 of the semiconductor substrate 10. That is, the second cathode section 182 may be in direct contact with the first cathode section 181. In one example, the second cathode section 182 is of P+ type. The doping concentration of the second cathode section 182 may be the same as or different from the doping concentration of the collector region 22.

[0099] The first cathode section 181 may be formed by further injecting an N-type dopant after injecting a P-type dopant by an ion implantation process for forming the second cathode section 182. Conversely, the second cathode section 182 may be formed by further injecting a P-type dopant after injecting an N-type dopant by an ion implantation process for forming the first cathode section 181.

[0100] The first cathode portion 181 and the second cathode portion 182 are alternately and repeatedly arranged in a predetermined direction. The first cathode portion 181 and the second cathode portion 182 may be alternately arranged in the trench arrangement direction (in this example, the X-axis direction), and may be alternately arranged in the trench extension direction (in this example, the Y-axis direction). In this example, they are alternately arranged in the trench extension direction. The first cathode portion 181 and the second cathode portion 182 may be arranged in a stripe shape in a top view. Thereby, the trade-off between the forward voltage Vf of the diode portion 80 and the reverse recovery loss Err of the semiconductor device 100 can be adjusted.

[0101] FIG. 2 is a diagram showing a modified example of the a-a' cross section of the semiconductor device 100. The modified example in FIG. 2 is different from the example in FIG. 1B in that the trench contact portion 60 is provided at the diode portion 80, the first boundary portion 190, and the second boundary portion 290. The differences from FIG. 1B will be described with reference to FIG. 2.

[0102] In the example shown in FIG. 2, the lower end of the first plug region 19 is deeper than the lower end of the emitter region 12 in the depth direction of the semiconductor substrate 10. That is, the first plug region 19 is provided so as to protrude to the base region 14. Thereby, the extraction of holes from the base region 14 becomes easy, and the latch-up of the semiconductor device 100 can be suppressed.

[0103] The lower end D2 of the trench contact portion 60 provided in the diode portion 80 is shallower than the lower end D1 of the trench contact portion 60 provided in the transistor portion 70. In one example, the distance from the front surface 21 of the semiconductor substrate 10 to the lower end D2 of the trench contact portion 60 in the diode portion 80 is 0 μm or more and 0.1 μm or less. Thereby, since the front surface side electrode 53 and the semiconductor substrate 10 can be connected in the vicinity of the front surface 21 where the doping concentration is high in the diode portion 80, while reducing the forward voltage Vf of the diode portion 80, an increase in the reverse recovery loss Err of the semiconductor device 100 can be suppressed.

[0104] The trench contact portion 60 in the diode portion 80 may be formed by filling a region where the front surface 21 of the semiconductor substrate 10 is slightly etched during the operation of forming the contact hole 54 in the diode portion 80 with a conductive material. That is, it may be formed without requiring a separate step for forming the trench contact portion 60 in the diode portion 80.

[0105] FIG. 3 is a diagram showing a modification of the upper surface of the semiconductor device 100. Differences from FIG. 1A will be described with reference to FIG. 3.

[0106] The second plug region 29 may be provided along the shape of the contact hole 54 in a top view. In this specification, that the second plug region 29 is provided along the shape of the contact hole 54 means that dopant is implanted into the region of the semiconductor substrate 10 exposed through the opening of the contact hole 54 in the ion implantation step for forming the second plug region 29. Therefore, even when the dopant diffuses due to a thermal annealing step or the like after the ion implantation step and the region where the contact hole 54 is provided and the region where the second plug region 29 is provided do not completely coincide in a top view, it may be included in an embodiment where the second plug region 29 is provided along the shape of the contact hole 54.

[0107] In the modification of FIG. 3, in the main region 75, one contact hole 54 is provided extending in the trench extending direction, and in the second boundary portion 290 and the diode portion 80, a plurality of contact holes 54 are selectively provided in the trench extending direction. That is, in the trench extending direction, the length of the contact hole 54 in the second boundary portion 290 and the diode portion 80 is shorter than the length of the contact hole 54 in the main region 75.

[0108] By providing the second plug region 29 along the shape of the contact hole 54, when selectively forming the second plug region 29, an additional resist mask or the like can be made unnecessary. Thereby, the number of manufacturing steps when manufacturing the semiconductor device 100 is reduced, and the manufacturing cost of the semiconductor device 100 is reduced.

[0109] FIG. 4 is a diagram showing the Vf-If characteristics of the semiconductor device 100 of this example and the semiconductor device of the comparative example. The Vf-If characteristics of this example are shown by a solid line, and the Vf-If characteristics of the comparative example are shown by a dotted line. The horizontal axis represents the forward voltage Vf, and the vertical axis represents the forward current If. The numerical values on the vertical and horizontal axes are normalized.

[0110] In this specification, the semiconductor device of the comparative example means a semiconductor device in which the second plug region is in contact with the front-side electrode at the same depth as the first plug region or at a depth deeper than the first plug region in the depth direction of the semiconductor substrate. FIG. 4 shows the Vf-If characteristics of a comparative example in which the first plug region and the second plug region are in contact with the front-side electrode at the same depth. The semiconductor device 100 of this example is different from the semiconductor device of the comparative example in that the second plug region 29 is in contact with the front-side electrode 53 at a position shallower than the first plug region 19.

[0111] For the semiconductor device 100 of this example, the numerical value of the forward voltage Vf for the same forward current If to flow is smaller than that of the semiconductor device of the comparative example. That is, the forward voltage Vf of the semiconductor device 100 of this example is reduced compared to the semiconductor device of the comparative example. In the semiconductor device 100 of this example, since the second plug region 29 is in contact with the front-side electrode 53 at a position shallower than the first plug region 19, the front-side electrode 53 and the semiconductor substrate 10 are electrically connected near the front surface 21 where the doping concentration is higher than that of the comparative example, the hole injection from the anode region 84 can be improved, and the forward voltage Vf can be reduced.

[0112] FIG. 5 is a diagram showing the Vf-Err characteristics of the semiconductor device 100 of this example and the semiconductor device of the comparative example. The Vf-Err characteristics of this example are shown by a solid line, and the Vf-Err characteristics of the comparative example are shown by a dotted line. The horizontal axis represents the forward voltage Vf, and the vertical axis represents the reverse recovery loss Err. The numerical values on the vertical and horizontal axes are normalized.

[0113] The semiconductor devices of the comparative examples show four data points with different doping concentrations in the anode region as white circles. Qp1, Qp2, Qp3, and Qp4 represent the doping concentrations in the anode region respectively, where Qp1 has the lowest doping concentration, Qp2 and Qp3 have increasing doping concentrations in that order, and Qp4 has the highest doping concentration. From FIG. 5, it can be seen that in the semiconductor devices of the comparative examples, when the doping concentration in the anode region is increased, the forward voltage Vf decreases and the reverse recovery loss Err tends to increase.

[0114] In FIG. 5, the Vf-Err characteristics of the semiconductor device 100 of this example when the doping concentration of the anode region 84 is Qp3 are shown by crosses. In the semiconductor device of the comparative example, when the doping concentration in the anode region is increased from Qp3 to Qp4, the forward voltage Vf decreases by 13.8%. On the other hand, in the semiconductor device 100 of this example, even when the doping concentration of the anode region 84 is Qp3, the forward voltage Vf also decreases by 13.8%. Therefore, the semiconductor device 100 of this example can reduce the forward voltage Vf without increasing the doping concentration of the anode region 84.

[0115] Also, in the semiconductor device of the comparative example, when the doping concentration in the anode region is increased from Qp3 to Qp4, the reverse recovery loss Err increases by 12%. On the other hand, in the semiconductor device 100 of this example, the increase in the reverse recovery loss Err only remains at 6.9%. That is, compared with the case of increasing the doping concentration from Qp3 to Qp4, the increase in the reverse recovery loss Err can be reduced by 5.1%. Therefore, the semiconductor device 100 of this example can improve the Vf-Err characteristics compared with the case of increasing the doping concentration of the anode region 84.

[0116] As described above, the present invention has been explained using embodiments, but the technical scope of the present invention is not limited to the scope described in the above embodiments. It is obvious to those skilled in the art that various changes or improvements can be made to the above embodiments. It is clear from the description of the claims that forms with such changes or improvements can also be included in the technical scope of the present invention.

[0117] In the claims, the specification, and the drawings, the execution order of each process such as operations, procedures, steps, and stages in the devices, systems, programs, and methods shown is not explicitly indicated as "earlier than" or "preceding" etc. in particular, and it should be noted that it can be realized in any order as long as the output of the previous process is not used in the subsequent process. Regarding the operation flows in the claims, the specification, and the drawings, even if explanations are made using "first," "next," etc. for convenience, it does not mean that it is essential to implement in this order.

Explanation of Reference Numerals

[0118] 10 ··· semiconductor substrate, 12 ··· emitter region, 14 ··· base region, 15 ··· contact region, 16 ··· storage region, 17 ··· well region, 18 ··· drift region, 19 ··· first plug region, 20 ··· buffer region, 21 ··· front surface, 22 ··· collector region, 23 ··· back surface, 24 ··· collector electrode, 25 ··· connection portion, 29 ··· second plug region, 30 ··· dummy trench portion, 31 ··· extension portion, 32 ··· dummy insulating film, 33 ··· connection portion, 34 ··· dummy conductive portion, 38 ··· interlayer insulating film, 40 ··· gate trench portion, 41 ··· extension portion, 42 ··· gate insulating film, 43 ··· connection portion, 44 ··· gate conductive portion, 50 ··· gate metal layer, 52 ··· emitter electrode, 53 ··· front surface side electrode, 54 ··· contact hole, 55 ··· contact hole, 56 ··· contact hole, 60 ··· trench contact portion, 70 ··· transistor portion, 71 ··· mesa portion, 75 ··· main region, 80 ··· diode portion, 81 ··· mesa portion, 82 ··· cathode region, 84 ··· anode region, 90 ··· boundary region, 100 ··· semiconductor device, 181 ··· first cathode portion, 182 ··· second cathode portion, 190 ··· first boundary portion, 191 ··· mesa portion, 290 ··· second boundary portion, 291 ··· mesa portion

Claims

1. A semiconductor device including a transistor portion and a diode portion, a plurality of trench portions provided on the front surface of a semiconductor substrate, a drift region of a first conductivity type provided in the semiconductor substrate, a front surface side electrode provided above the semiconductor substrate, and comprising: The transistor portion includes: a base region of a second conductivity type provided above the drift region, an emitter region of a first conductivity type provided above the base region and having a higher doping concentration than the drift region, a contact region of a second conductivity type provided above the base region and having a higher doping concentration than the base region, a trench contact portion provided on the front surface of the semiconductor substrate, and a first plug region of a second conductivity type having a higher doping concentration than the base region and provided below the trench contact portion, and having: The diode portion includes: an anode region of a second conductivity type provided above the drift region, and a second plug region of a second conductivity type having a higher doping concentration than the anode region, and having: The second plug region is in contact with the front surface side electrode at a position shallower than the first plug region in the depth direction of the semiconductor substrate. Semiconductor device.

2. The semiconductor device according to claim 1, wherein the second plug region is in contact with the front surface side electrode on the front surface of the semiconductor substrate.

3. The semiconductor device according to claim 1, wherein the lower end of the trench contact portion provided in the diode portion is shallower than the lower end of the trench contact portion provided in the transistor portion.

4. The semiconductor device according to claim 1, wherein in the diode portion, the second plug region is provided alternately with the anode region in the trench extension direction of the plurality of trench portions.

5. The semiconductor device according to claim 4, wherein in the trench extension direction, the width of the first plug region provided in the transistor portion is larger than the width of the second plug region provided in the diode portion.

6. The semiconductor device according to claim 1, wherein the lower end of the first plug region is deeper than the lower end of the emitter region in the depth direction of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein the lower end of the first plug region is at the same depth as the lower end of the emitter region or shallower than the lower end of the emitter region in the depth direction of the semiconductor substrate.

8. The semiconductor device according to claim 1, wherein the doping concentration of the anode region is lower than the doping concentration of the base region.

9. The doping concentration of the anode region is 1E16 cm －３ Above, 1E18cm －３ 2. The semiconductor device according to claim 1, wherein:

10. The semiconductor device according to claim 1, wherein a lower end of the trench contact portion is shallower than a lower end of the emitter region in a depth direction of the semiconductor substrate.

11. The transistor portion has a main region having the emitter region, and has a boundary region provided closer to the diode portion than the main region, wherein the boundary region has a first boundary portion including the contact region on a front surface of the semiconductor substrate, and has a second boundary portion provided closer to the diode portion than the first boundary portion and including the anode region, The semiconductor device according to any one of claims 1 to 10.

12. The semiconductor device according to claim 11, wherein the trench contact portion is not provided in the boundary region.

13. The semiconductor device according to claim 11, wherein a width in a trench extending direction of the contact region provided in the first boundary portion is larger than a width in the trench extending direction of the contact region provided in the main region.

14. The semiconductor device according to claim 11, wherein the second boundary portion includes the second plug region.

15. The semiconductor device according to claim 14, wherein a width of the second plug region provided in the second boundary portion is smaller than a width of the first plug region in a trench extending direction of the plurality of trench portions.

16. The diode portion has a cathode region of a first conductivity type having a higher doping concentration than the drift region on a back surface of the semiconductor substrate, The semiconductor device according to any one of claims 1 to 10, wherein the cathode region includes a first cathode portion of a first conductivity type and a second cathode portion of a second conductivity type.

17. The semiconductor device according to claim 16, wherein the first cathode portion and the second cathode portion are alternately and repeatedly arranged in a predetermined direction.

18. The semiconductor device according to any one of claims 1 to 10, further comprising an accumulation region of a first conductivity type provided above the drift region in the transistor portion and having a higher doping concentration than the drift region.

19. A interlayer insulating film provided above the semiconductor substrate and having a contact hole for electrically connecting the front surface side electrode to the semiconductor substrate is provided. The semiconductor device according to any one of claims 1 to 10, wherein the second plug region is provided along the shape of the contact hole in a top view.

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