Transistor

Abstract

To provide a novel metal oxide.SOLUTION: A crystalline metal oxide includes a first layer and a second layer. The first layer has a wider bandgap than the second layer. By the first layer and the second layer, a crystal lattice is formed. When a carrier is excited in the metal oxide, carriers are transmitted through the second layer. The first layer includes an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, and the second layer includes In.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a metal oxide and a transistor having the metal oxide. Also one aspect of the present invention relates to a semiconductor device, a semiconductor wafer, a module, and an electronic device .

[0002] Note that, in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics . Semiconductor elements such as transistors, semiconductor circuits, arithmetic units, and storage devices are one aspect of semiconductor devices. Display devices (such as liquid crystal display devices and light-emitting display devices), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, imaging devices, electronic devices etc. may be said to have a semiconductor device in some cases

[0003] Note that one aspect of the present invention is not limited to the above technical field. One aspect of the invention disclosed in this specification and the like relates to an article, a method, or a manufacturing method. Or, one aspect of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter) .

Background Art

[0004] In oxide semiconductors, a CAAC (c-axis aligned crystalline) structure and an nc (nanocrystalline ) structure that are neither single crystal nor amorphous have been found (see Non-Patent Document 1 and Non-Patent Document 2).

[0005] In Non-Patent Document 1 and Non-Patent Document 2, techniques for fabricating transistors using oxide semiconductors having a CAAC structure are disclosed .

[0006] ​ Also, in the latter half of the 1980s, as the channel formation region of a transistor, a layer with a large energy bandwidth and a semiconductor layer with a small energy bandwidth interact quantum mechanically to form a multilayer structure (see Patent Document 1).

[0007] In Patent Document 1, a superlattice structure composed of a repeating multilayer structure of semiconductor layer - insulator layer - semiconductor layer is provided in the channel formation region of the transistor, and each layer is stacked such that the plane of the layer is along the carrier movement direction.

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Non-Patent Documents

[0009]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] One aspect of the present invention is to provide a novel metal oxide. Also, the present invention ​One aspect of the disclosure aims to provide a novel transistor. Another aspect of the present invention aims to provide a semiconductor device with a large on-current. Another aspect of the present invention aims to provide a semiconductor device having high frequency characteristics. Another aspect of the present invention aims to provide a semiconductor device with good reliability. Another aspect of the present invention aims to provide a semiconductor device capable of miniaturization or high integration. Another aspect of the present invention aims to provide a semiconductor device having good electrical characteristics.

[0011] Another aspect of the present invention aims to provide a semiconductor device capable of retaining data for a long period. Another aspect of the present invention aims to provide a semiconductor device with a high information writing speed. Another aspect of the present invention aims to provide a semiconductor device capable of suppressing power

[0012] consumption. It should be noted that the description of these problems does not preclude the existence of other problems. It should be noted that one aspect of the present invention does not necessarily need to solve all of these problems. Other problems will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other problems from the descriptions in the

[0013] specification, drawings, claims, etc. One aspect of the present invention is a crystalline metal oxide, which has a first layer And a second layer forms a crystal lattice and excites carriers in the crystalline metal oxide When this occurs, carriers are transmitted through the second layer.

[0014] Another aspect of the present invention is a crystalline metal oxide, the crystalline metal oxide having a first layer and a second layer, the first layer having a wider bandgap than the second layer, each of the first layer and the second layer being disposed substantially parallel to the surface to be formed of the crystalline metal oxide and forming a crystal lattice by the first layer and the second layer, and when carriers are excited in the crystalline metal oxide, the carriers are transmitted through the second layer.

[0015] Another aspect of the present invention is a crystalline metal oxide, the crystalline metal oxide having a first layer and a second layer, the first layer having a wider bandgap than the second layer, the first layer having one or more elements M (M is selected from one or more of Al, Ga, Y, and Sn) and Zn, the second layer having In, and each of the first layer and the second layer being disposed substantially parallel to the surface to be formed of the crystalline metal oxide, and forming a crystal lattice by the first layer and the second layer, and when carriers are excited in the crystalline metal oxide, the carriers are transmitted through the second layer.

[0016] Another aspect of the present invention is a crystalline metal oxide, the crystalline metal oxide having a first layer and a second layer, the first layer having a wider bandgap than the second layer, each of the first layer and the second layer being disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and forming a crystal lattice by the first layer and the second layer, and the crystalline metal oxide ​​​​When a carrier is excited in an object, the carrier is transmitted through the second layer.

[0017] Another aspect of the present invention is a crystalline metal oxide, and the crystalline metal oxide has a first layer and a second layer, the first layer has a wider band gap than the second layer, the first layer contains an element M (M is one or more selected from Al, Ga, Y, and Sn) and Zn, the second layer contains In, and each of the first layer and the second layer is disposed substantially perpendicular to the formation surface of the crystalline metal oxide, and the first layer and the second layer form a crystal lattice. When a carrier is excited in the crystalline metal oxide, the carrier is transmitted through the second layer.

[0018] In the above crystalline metal oxide, the distance between the first layer and the second layer is preferably 1 nm or less. Further, in the above crystalline metal oxide, when the crystalline metal oxide is observed by TEM from the c-axis direction, the crystalline metal oxide preferably has hexagonal lattice points.

[0019] Another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain. The crystalline metal oxide has a first layer and a second layer. The first layer has a wider band gap than the second layer. The first layer and the second layer are each disposed substantially parallel to the channel length direction of the transistor. The first layer and the second layer form a crystal lattice. When a voltage is applied to the gate and a carrier is excited in the crystalline metal oxide, the carrier is transmitted from the source to the drain through the second layer. ​​​​​​​​​​​

[0020] Also, another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially parallel to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer

[0021] Also, another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer wherein the crystalline metal oxide has a first layer and a second layer The first layer has a wider bandgap than the second layer, and each of the first layer and the second layer is disposed substantially perpendicular to the surface to be formed of the crystalline metal oxide, and a crystal lattice is formed by the first layer and the second layer. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer

[0022] Also, another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain wherein the crystalline metal oxide has a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide wherein the first metal oxide, the second metal oxide, and the third metal oxide each have a first layer wherein the first metal oxide, the second metal oxide, and the third metal oxide each have a first layer and a second layer, wherein the first layer has a wider bandgap than the second layer, and the first layer and the second layer are each arranged substantially parallel to the channel length direction of the transistor such that a crystal lattice is formed by the first layer and the second layer, and when a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer.

[0023] Another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain wherein the crystalline metal oxide has a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide, and the first metal oxide, the second metal oxide, and the third metal oxide each have a first layer and a second layer, the first layer having a wider bandgap than the second layer, and each of the first layer and the second layer of the second metal oxide is arranged substantially parallel to the surface to be formed of the second metal oxide, and a crystal lattice is formed by the first layer and the second layer, and when a voltage is applied to the gate to excite carriers in the crystalline metal oxide, carriers are transmitted from the source to the drain through the second layer.

[0024] In the above transistor, in the channel width direction of the transistor, the third metal oxide covers the upper surface and the side surface of the second metal oxide, the gate covers the upper surface and the side surface of the second metal oxide, and on the side surface of the second metal oxide, it is preferable that the c-axis direction of the third metal oxide is different from the c-axis direction of the second metal oxide.

[0025] In addition, another aspect of the present invention is a transistor having a crystalline metal oxide, a gate, a source, and a drain. The crystalline metal oxide includes a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide. The first metal oxide, the second metal oxide, and the third metal oxide each have a first layer and a second layer. The first layer has a wider bandgap than the second layer. Each of the first layer of the second metal oxide and the second layer of the second metal oxide is disposed substantially perpendicular to the formation surface of the second metal oxide. The first layer and the second layer form a crystal lattice. When a voltage is applied to the gate to excite carriers in the crystalline metal oxide, the carriers are transmitted from the source to the drain through the second layer. In the above transistor, at the gate, the bottom surface of the first region that does not overlap with the second metal oxide is lower than the bottom surface of the second metal oxide. At the gate, the bottom surface of the second region that is opposed to the first region with the second metal oxide interposed therebetween is preferably lower than the bottom surface of the second metal oxide. In the above transistor, it is preferable to have a second gate overlapping at least a part of the region where the second metal oxide and the gate overlap under the first metal oxide. In the above transistor, it is preferable that at least one or both of the channel length and the channel width of the transistor have a region of 100 nm or less.

[0026]

[0027]

[0028]

[0029] ​​​​​​​​In addition, in the above transistor, the first layer contains an element M (M is one or more selected from Al, Ga, Y, and S n) and Zn, and the second layer preferably contains In.

Advantages of the Invention

[0030] According to one aspect of the present invention, a novel metal oxide can be provided. Also, according to one aspect of the present invention, a novel transistor can be provided. Further, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. Additionally, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. Moreover, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. Furthermore, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. Also, according to one aspect of the present invention, a semiconductor

[0031] device having good electrical characteristics can be provided. In addition, according to one aspect of the present invention, a semiconductor device capable of holding data for a long period can be provided. Also, according to one aspect of the present invention, a semiconductor device with a high information writing speed can be provided. Moreover, according to one aspect of the present

[0032] invention, a semiconductor device capable of suppressing power consumption can be provided. Note that the description of these effects does not preclude the existence of other effects. Note that one aspect of the present invention does not necessarily have all of these effects. Note that other effects will become apparent from the descriptions in the specification, drawings, claims, etc., and it is possible to extract these other effects from the descriptions in the specification, drawings, claims, etc.​

[0033]

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Mode for Carrying Out the Invention

[0034] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different modes, and without departing from the spirit and its scope, the Those skilled in the art can easily understand that the form and details can be changed in various ways. Therefore, the present invention is not construed as being limited to the description of the following embodiments.

[0035] Also, in the drawings, the size, layer thickness, or area may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. Note that the drawings schematically show ideal examples and are not limited to the shapes or values shown in the drawings. For example, in an actual manufacturing process, layers, resist masks, etc. may unintentionally shrink due to processes such as etching, but this may not be reflected in the figures for ease of understanding. Also, in the drawings, the same reference numerals are commonly used for the same parts or parts having similar functions among different drawings, and repeated descriptions may be omitted. Also, in cases where similar functions are referred to, the hatch patterns may be the same and may not be particularly labeled.

[0036] Also, especially in top views (also referred to as "plan views") and perspective views, etc., for ease of understanding of the invention, the description of some components may be omitted. Also, the description of some hidden lines, etc. may be omitted.

[0037] Also, in this specification, etc., ordinal numbers such as first, second, etc. are used for convenience and do not indicate the process order or stacking order. Therefore, for example, "first" can be appropriately replaced with "second" or "third", etc. for explanation. Also, the ordinal numbers described in this specification, etc. and the ordinal numbers used to identify an aspect of the present invention may not match.

[0038] ​In addition, in this specification and the like, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components changes appropriately according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification, and can be appropriately rephrased according to the situation. For example, when it is explicitly described in this specification and the like that X and Y are connected, it is disclosed in this specification and the like that the case where X and Y are electrically connected, the case where X and Y are functionally connected, and the case where X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or the text, and those other than the connection relationship shown in the figure or the text are also considered to be disclosed in the figure or the text. Here, it is assumed that X and Y are objects (for example, devices, elements, circuits, wirings, electrodes, terminals, conductive films, layers, etc.).

[0039] In addition, in this specification and the like, a transistor is an element having at least three terminals including a gate, a drain, and a source. And there is a region (hereinafter also referred to as a channel formation region) in which a channel is formed between the drain (drain terminal, drain region, or drain electrode) and the source (source terminal, source region, or source electrode), and current can flow between the source and the drain through the channel formation region. Note that in this specification and the like, the channel formation region refers to the region where current mainly flows.

[0040]

[0041]

[0042] ​​​​​​​​​​​​Also, the functions of the source and drain may be interchanged when transistors of different polarities are employed or when the direction of the current changes during circuit operation. Therefore, in this specification and the like, the terms "source" and "drain" may be used interchangeably in some cases.

[0043] Note that the channel length refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the distance between the source (source region or source electrode) and the drain (drain region or drain electrode) in the channel formation region. Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be determined by a single value. Therefore, in this specification and the like, the channel length is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0044] Note that the channel width refers to, for example, in the top view of a transistor, the region where the semiconductor (or the portion where current flows in the semiconductor when the transistor is in the on state) and the gate electrode overlap each other, or the length of the channel formation region in the direction perpendicular to the channel length direction in the channel formation region. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is, the channel width of one transistor may not be determined by a single value. Therefore, in this specification and the like, the channel width is taken as any one value, the maximum value, the minimum value, or the average value in the channel formation region.

[0045] ​​​​​​​​​​​​​In addition, in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width") may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and there may be a case where the influence cannot be ignored. For example, in a fine transistor in which the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width becomes larger than the apparent channel width. In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. In this specification and the like, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification and the like, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration In addition, in this specification and the like, depending on the structure of the transistor, the channel width in the region where the channel is actually formed (hereinafter, also referred to as the "effective channel width") and the channel width shown in the top view of the transistor (hereinafter, also referred to as the "apparent channel width") may be different. For example, when the gate electrode covers the side surface of the semiconductor, the effective channel width may become larger than the apparent channel width, and there may be a case where the influence cannot be ignored. For example, in a fine transistor in which the gate electrode covers the side surface of the semiconductor, the ratio of the channel formation region formed on the side surface of the semiconductor may increase. In that case, the effective channel width becomes larger than the apparent channel width. In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. In this specification and the like, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification and the like, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration

[0046] In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width. In this specification and the like, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification and the like, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0047] In this specification and the like, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification and the like, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration In this specification and the like, when simply described as the channel width, it may refer to the apparent channel width. Or, in this specification and the like, when simply described as the channel width, it may refer to the effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, etc. can be determined by analyzing a cross-sectional TEM image or the like. In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, when the shape of the semiconductor is not accurately known, it is difficult to accurately measure the effective channel width.

[0048] In addition, the semiconductor impurities refer to, for example, components other than the main components constituting the semiconductor. For example, the concentration Elements with a degree of less than 0.1 atomic % can be regarded as impurities. When impurities are included, for example, the density of defect levels in the semiconductor may increase, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, examples of impurities that change the characteristics of the semiconductor include, for example Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main component of the oxide semiconductor. For example, there are hydrogen, lithium, sodium, silicon con, boron, phosphorus, carbon, nitrogen, etc. In the case of an oxide semiconductor, water may also function as an impurity In the case of an oxide semiconductor, for example, oxygen deficiency may be formed due to the incorporation of impurities In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include, for example Group 1 elements, Group 2 elements, Group 13 elements, Group 1 5 elements, etc., excluding oxygen and hydrogen.

[0049] In this specification, etc., silicon oxynitride means that, in terms of its composition, the oxygen content is higher than the nitrogen content. Also, silicon nitride oxide means that, in terms of its composition, the nitrogen content is higher than the oxygen content.

[0050] In this specification, etc., the term "insulator" can be replaced with an insulating film or an insulating layer Also, the term "conductor" can be replaced with a conductive film or a conductive layer Also, the term "semiconductor" can be replaced with a semiconductor film or a semiconductor layer can be done.

[0051] In this specification, etc., "parallel" means a state in which two straight lines are arranged at an angle of -10 degrees or more and 10 degrees or less Therefore, the case of -5 degrees or more and 5 degrees or less is also included. Also Here, "substantially parallel" means a state where two straight lines are arranged at an angle of -30 degrees or more and 30 degrees or less. Also, "perpendicular" means a state where two straight lines are arranged at an angle of 80 degrees or more and 100 degrees or less. Therefore, cases where the angle is 85 degrees or more and 95 degrees or less are also included. Also, "substantially perpendicular" means a state where two straight lines are arranged at an angle of 60 degrees or more and 120 degrees or less.

[0052] In this specification and the like, a barrier film is a film having a function of suppressing the permeation of impurities such as water and hydrogen and oxygen. When the barrier film has conductivity, it may be referred to as a conductive barrier film.

[0053] In this specification and the like, a metal oxide is an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as Oxide Semiconductor or simply OS). For example, when a metal oxide is used for the semiconductor layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when described as an OS transistor, it can be equivalently stated as a transistor having an oxide or an oxide semiconductor.

[0054] Also, in this specification and the like, normally-off means that when no potential is applied to the gate or when the gate is given a ground potential, the current per 1 μm of the channel width flowing through the transistor is 1 × 10 A or less at room temperature, 1 × 10 -20 A or less at 85 °C, or -18 1 × 10 A or less at 125 °C. -16

[0055] ​​​​​​ (Embodiment 1) In this embodiment, a metal oxide which is one aspect of the present invention, and a transistor having the metal oxide will be described with reference to FIGS. 1 to 10.

[0056] (Configuration Example of Transistor) FIG. 1(A) is a cross-sectional view of a transistor 10 in the channel length direction according to one aspect of the present invention.

[0057] As shown in FIG. 1(A), the transistor 10 includes an oxide 230 disposed on a substrate (not shown), an insulator 250 disposed on the oxide 230, and a conductor 260 disposed on the insulator 250. The oxide 230 has a region 234 that functions as a region where a channel of the transistor 10 is formed (hereinafter also referred to as a channel formation region), and regions 231 (regions 231a and 231b) that function as a source region or a drain region. The insulator 250 functions as a gate insulating film. The conductor 260 functions as a gate electrode.

[0058] Further, FIG. 1(B) is a model of a band diagram on a dotted line indicated by X1-X2 in the transistor shown in FIG. 1(A). In FIG. 1(B), the k space is ignored. Note that FIG. 1(B) shows a state where no voltage is applied between the gate and the source. The solid line located at the conductor 260 indicates the position of the Fermi surface of the conductor 260. The solid line located at the insulator 250 indicates the position of the lower end of the conduction band of the insulator 250. The solid line located at the oxide 230 indicates the position of the lower end of the conduction band of the oxide 230.

[0059] ​​​​​​​​​​​​Transistor 10 can control the resistance of the channel portion according to the potential applied to the gate. That is, conduction (when the transistor is in the on state) and non-conduction (when the transistor is in the off state) between the source and the drain can be controlled according to the potential applied to the gate. (The transistor is in the on state) It is possible.

[0060] For transistor 10, it is preferable to use a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor in the oxide 230 including the channel formation region. The oxide semiconductor has better switching characteristics of the transistor and can obtain an extremely small off-current compared with semiconductors made of silicon or the like, so it is preferable.

[0061] In addition, a transistor using an oxide semiconductor in the channel formation region has an extremely small leakage current (off-current) in the non-conducting state, so a semiconductor device with low power consumption can be provided. In addition, since the oxide semiconductor can be formed into a film by using a sputtering method or the like, it can be used for transistors constituting a highly integrated semiconductor device.

[0062] In addition, for a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. In addition, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor is likely to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the insulator 250 or the like to compensate for the oxygen deficiencies. This can suppress fluctuations in electrical characteristics and provide a transistor having stable electrical characteristics and improved reliability. ​ It is possible.

[0063] In addition, for the oxide 230, it is preferable to use a metal oxide with a low carrier density. High A metal oxide with a high-purity intrinsic or substantially high-purity intrinsic property has few carrier generation sources, so the carrier density can be lowered. Also, a metal oxide with a high-purity intrinsic or substantially high-purity intrinsic property may have a low trap level density because of its low defect level density.

[0064] For example, as the oxide 230, an In-M-Zn oxide (element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) and the like of a metal oxide may be used. In particular, as element M, it is preferable to use aluminum (Al), gallium (Ga), yttrium (Y), or tin (Sn). Also, as the oxide 230, an In-Ga oxide or an In-Zn oxide may be used. In addition, a conductive film that functions as a source electrode or a drain electrode may be provided so as to be in contact with the oxide 230. At this time, when the element contained in the conductive film has a function of absorbing the oxygen of the oxide 230,

[0065] a low-resistance region may be partially formed between the oxide 230 and the conductive film or near the surface of the oxide 230. In this case, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen deficiency in the low-resistance region function as donors, and the carrier density may increase. Also, at least a part of the low-resistance region is a source region or near the surface of the oxide 230. In this case, impurities (hydrogen, nitrogen, metal elements, etc.) that have entered the oxygen deficiency in the low-resistance region function as donors, and the carrier density may increase. Also, at least a part of the low-resistance region is a source region or a drain region. a drain region. It is included in the region 231 which functions as the drain region.

[0066] Oxide semiconductors (metal oxides) are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. As a non-single crystal oxide semiconductor, for example, CAAC-OS (c- axis aligned crystalline oxide semiconductor ctor), polycrystalline oxide semiconductor, nc-OS (nanocrystalline ox ide semiconductor), pseudo amorphous oxide semiconductor (a-like OS : amorphous-like oxide semiconductor) and non and amorphous oxide semiconductors.

[0067] The channel formation region of the transistor is provided with a metal oxide that increases the on-state current of the transistor. In order to increase the on-state current of the transistor, it is preferable to use a It is preferable to increase the mobility of the metal oxide used in the transistor. improves the transmission of carriers or reduces the sources of scattering that affect the transmission of carriers It is necessary to.

[0068] Therefore, it is possible to use a crystalline metal oxide for the oxide 230 including the channel formation region. It is preferable that the crystal of the metal oxide has a first layer and a second layer. It is preferable that the first layer and the second layer are alternately laminated to form a crystal structure. The first layer preferably has a wider band gap than the second layer. In the literature, the first layer is referred to as having a wider band gap than the second layer. The second layer has a gap smaller than the first layer. The second layer may be described as having a narrow gap when the gap is narrow. That is, the crystalline metal oxide preferably has a crystal in which a second layer having a narrow gap is sandwiched between a first layer having a wide gap.

[0069] The first layer and the second layer of the oxide 230 are each arranged substantially parallel to the channel length direction of the transistor 10. Also, it can be said that the extending directions of the first layer and the second layer of the oxide 230 are each substantially parallel to the channel length direction of the transistor 10. Further, each of the first layer and the second layer of the oxide 230 is preferably arranged substantially parallel to the formation surface of the oxide 230.

[0070] Examples of the crystalline metal oxide include a single crystal oxide semiconductor and CAAC-OS. The crystalline metal oxide can improve carrier transmission. Therefore, the mobility of the metal oxide is increased, the on-current of the transistor using the metal oxide is increased, and the electrical characteristics of the transistor can be improved.

[0071] [Carrier Transmission Model] Hereinafter, the carrier transmission model in the crystalline metal oxide will be described. Here, CAAC-OS is cited as an example of the crystalline metal oxide. Further, the metal oxide is a metal oxide composed of indium, element M, zinc, and oxygen (also referred to as In-M-Zn oxide).

[0072] CAAC-OS has c-axis orientation and a plurality of nanocrystals in the a-b plane direction (the most crystalline regions with a major axis of less than 10 nm) are connected to form a crystal structure with strain. Also, strain refers to a location where the orientation of the lattice arrangement changes between a region with an aligned lattice arrangement and another region with an aligned lattice arrangement in the region where a plurality of nanocrystals are connected.

[0073] When CAAC-OS is viewed from the c-axis direction, the nanocrystals are based on a hexagon, but they are not necessarily regular hexagons and may be non-regular hexagon shapes. Also, in the strain, there may be lattice arrangements such as pentagons and heptagons. In CAAC-OS, it is difficult to confirm a clear grain boundary (also referred to as a grain boundary) even in the vicinity of the strain. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS allows strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the interatomic bond distance changes due to the substitution of metal elements. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement. This is because CAAC-OS can allow strain due to the fact that the arrangement of oxygen atoms is not dense in the a-b plane direction, and the interatomic bond distance changes due to the substitution of metal elements. That is, it can be seen that the formation of grain boundaries is suppressed by the strain of the lattice arrangement.

[0074] The hexagonal shape in the crystalline metal oxide can be confirmed by an observation image obtained by a transmission electron microscope (TEM: Transmission Electron Microscope) from the c-axis direction of the metal oxide. ope). A magnified view of region 51 of oxide 230 shown in Fig. 1(A) is shown in Fig. 1(C). Here, the oxide 230 is an In-M-Zn oxide having a CAAC structure. Also, element M is set as G

[0075] a, and the composition of oxide 230 is set to In:M:Zn = 1:1:1 [atomic ratio]. Also in Fig. 1(C), the c-axis (c-axi s) of the In-M-Zn oxide having a CAAC structure is The (s) direction is the vertical direction of the paper surface, and the a-b plane direction is the left-right direction and the normal direction of the paper surface. In Fig. 1(C), as the oxide 230, an In-M-Zn oxide having a CAAC structure with a composition of In:M:Zn = 1:1:1 [atomic ratio] is shown, but it is not limited to this. The oxide 230 may be any crystalline metal oxide. For example, the composition formula is In M (1+ α) M (1-α) O3(ZnO) m (α is a real number from 0 to 1, and m is a non-negative real number) and may be an In-M-Zn oxide having a CAAC structure or a single crystal structure.

[0076] As shown in Fig. 1(C), the In-M-Zn oxide having a CAAC structure has a layered crystal structure (also referred to as a layered crystal or a layered structure) in which a layer containing indium , and oxygen (hereinafter, the InO layer) and a layer containing element M, zinc, and oxygen ( hereinafter, the (M,Zn)O layer) are laminated. In this specification, etc., the (M,Zn)O layer is located between the InO layer and the InO layer adjacent to the InO layer in the c-axis direction, and refers to a layer containing element M, zinc, and oxygen. .) tends to have. Also, since indium, element M, and zinc are mutually substitutable, a part of indium may be contained in the (M,Zn)O layer. Also, a part of element M or a part of zinc may be contained in the InO layer.

[0077] In this specification, etc., when a structure in which the first layer and the second layer are alternately laminated is regarded as a crystal structure and the unit cell of the crystal structure can be represented by a certain space group, the laminated structure may be referred to as a crystal lattice. For example, an In-M-Zn oxide having a CAAC structure In this case, the first layer is a (M,Zn)O layer, and the second layer is an InO layer. Also, the crystal lattice may not be formed by two layers, and may be formed by three or more layers.

[0078] Also, as the distance between the first layer and the second layer increases, the interaction between the first layer and the second layer becomes weaker, and the crystal lattice becomes structurally unstable. Therefore, it is preferable that the distance is close to the distance between the atoms constituting the crystal lattice. For example, the distance between the first layer and the second layer is preferably 1 nm or less, more preferably 0.7 nm or less, and even more preferably 0.5 nm or less. By doing so, the crystal lattice formed by the first layer and the second layer becomes structurally stable.

[0079] Also, as shown in FIG. 1(C), the c-axis of the crystal of CAAC-OS is oriented in the normal direction to the formation surface or the film surface of the oxide 230. Therefore, in the cross-sectional view of the transistor 10 the direction of the c-axis of the crystal of CAAC-OS is the vertical direction of the paper surface. Also, the a-b plane of the crystal of CAAC-OS is substantially parallel to the formation surface or the film surface of the oxide 230. That is, each of the InO layer and the (M,Zn)O layer is arranged substantially parallel to the formation surface of the oxide 2 30. Therefore, the a-b plane of the crystal of CAAC-OS is parallel to the left-right direction of the paper surface and the normal direction of the paper surface.

[0080] Here, an enlarged view of the region 52 at the lower end of the conduction band of the oxide 230 in the model of the band diagram shown in FIG. 1(B) is shown in FIG. 1(D). In FIG. 1(D), the k space is ignored . Note that the region 52 corresponds to the region 51 in real space.

[0081] ​​​​​The InO layer and the (M,Zn)O layer have different ratios of constituent elements in each layer. Thus, the InO layer and the (M,Zn)O layer have different band gaps. Or, the InO layer and the (M,Zn)O layer have different electron affinities. Or, the InO layer and the (M,Zn)O layer have different differences between the energy of the vacuum level and the energy Ec of the lower edge of the conduction band.

[0082] It is known that the oxide of gallium has a larger band gap than the oxide of indium. Thus, when element M is Ga, the band gap of the (M,Zn)O layer is presumed to be larger than the band gap of the InO layer. Also, the electron affinity of the (M,Zn)O layer is presumed to be smaller than the electron affinity of the InO layer. In other words, in the InO layer, the difference between the energy of the vacuum level and the energy of the lower edge of the conduction band is presumed to be larger than the difference between the energy of the vacuum level and the energy of the lower edge of the conduction band in the (M,Zn)O layer. Therefore, it is presumed that the lower edge of the conduction band of the InO layer is located at a lower position than the lower edge of the conduction band of the (M,Zn)O layer. Note that since the (M,Zn)O layer has a larger band gap than the InO layer, the (M,Zn)O layer may be expressed as having a wide band gap. Also, since the InO layer has a smaller band gap than the (M,Zn)O layer, the InO layer may be expressed as having a narrow band gap.

[0083] In addition, since the InO layer and the (M,Zn)O layer form a crystal lattice, the lower edge of the conduction band of the InO layer and the lower edge of the conduction band of the (M,Zn)O layer are presumed to change continuously at the boundary between the InO layer and the (M,Zn)O layer. Therefore, as shown in Fig. 1(D), , the lower end of the conduction band of the oxide 230 is presumed to be the levels that repeatedly appear at the lower end of the conduction band of the InO layer and the lower end of the conduction band of the (M,Zn)O layer. Therefore, in the band diagram shown in Fig. 1(D), the vicinity of the lower end of the conduction band of the (M,Zn)O layer becomes a convex part, and the vicinity of the lower end of the conduction band of the InO layer becomes a concave part. Since the InO layer and the (M,Zn)O layer are formed in the a-b plane direction, the lower end of the conduction band in the a-b plane direction is constant. Therefore, carriers are more likely to be transmitted along the a-b plane direction of the InO layer where the lower end of the conduction band is lower. Carriers injected from the source concentrate in the InO layer with a narrow bandgap, which is sandwiched by the (M,Zn)O layer with a wide bandgap. Furthermore, in Figs. 1(C) and 1(D), the carrier transmission direction, that is, the direction from the source to the drain, generally coincides with the a-b plane direction (the left-right direction and the normal direction of the paper surface) of the InO layer. From the above, the main carrier transmission path is the InO layer. That is, when carriers are excited in a crystalline metal oxide, the carriers are transmitted through the InO layer. Note that since the InO layer and the (M,Zn)O layer are formed in the a-b plane direction, the lower end of the conduction band in the a-b plane direction is constant. Therefore, carriers are more likely to be transmitted along the a-b plane direction of the InO layer where the lower end of the conduction band is lower.

[0084] Carriers injected from the source concentrate in the InO layer with a narrow bandgap, which is sandwiched by the (M,Zn)O layer with a wide bandgap. Furthermore, in Figs. 1(C) and 1(D), the carrier transmission direction, that is, the direction from the source to the drain, generally coincides with the a-b plane direction (the left-right direction and the normal direction of the paper surface) of the InO layer. From the above, the main carrier transmission path is the InO layer. That is, when carriers are excited in a crystalline metal oxide, the carriers are transmitted through the InO layer.

[0085] Note that carriers flow from the source to the drain through the channel formation region. To increase the transmission speed of carriers, it is preferable to provide a channel formation region where carriers can easily flow in the channel length direction. Also, as described above, in the crystal of the In-M-Zn oxide, carriers easily flow in the a-b plane direction. Therefore, it is preferable to align the a-b plane of the crystal of the In-M-Zn oxide in the direction of carrier flow.

[0086] In addition, the layered structure preferably extends to the region 231 of the oxide 230. ​​​​​​​​By doing so, the transmission of carriers between region 231a and region 231b through the channel formation region can be facilitated. The carriers can be easily transmitted.

[0087] It is estimated that electrons move in the a-b plane direction after being quantized. The electrons contained in the InO layer are blocked by the (M,Zn)O layer, and since there is no lattice scattering, these electrons tend to move in the a-b plane direction of the InO layer. That is, it is estimated that the mobility in the a-b plane direction is higher than that in the c-axis direction.

[0088] CAAC-OS is a highly crystalline metal oxide. On the other hand, since it is difficult to confirm distinct crystal grain boundaries in CAAC-OS, the conduction band bottom with a low trap level density due to crystal grain boundaries extends over the a-b plane direction (in this specification, etc., it is also said to be highly leveled). Therefore, it can be said that the decrease in electron mobility is unlikely to occur. Also, since the crystallinity of metal oxides may decrease due to the incorporation of impurities or the generation of defects, etc., CAAC-OS can also be said to be a metal oxide with few impurities and defects (such as oxygen deficiencies). Therefore, the physical properties of the metal oxide having CAAC-OS are stable. For this reason, the metal oxide having CAAC-OS is heat-resistant and highly reliable.

[0089] Also, metal oxides tend to have higher mobility as the temperature increases. This is presumably due to lattice scattering. The lattice vibration of atoms and the carrier transmission due to heat will be described with reference to FIGS. 2 and 3.

[0090] FIG. 2(A) shows the crystal structure of an In-M-Zn oxide having a CAAC structure. In FIG. 2(A), W_(M,Zn)O indicates the thickness of the (M,Zn)O layer in the c-axis direction. Also ​ , W_(M,Zn)O can also be referred to as the width of the convex portion at the lower end of the conduction band of the (M,Zn)O layer in the band diagram shown in Fig. 1(D). W_InO indicates the thickness of the InO layer in the c-axis direction. Also, W_InO can also be referred to as the width of the concave portion at the lower end of the conduction band of the InO layer in the band diagram shown in Fig. 1(D).

[0091] Also, Wa_(M,Zn)O shown in Fig. 2(B) indicates the thickness of the (M,Zn)O layer in the c-axis direction when the temperature T is approximately the same as the reference temperature (e.g., room temperature (R.T.)), and Wa_InO shown in Fig. 2(B) indicates the thickness of the InO layer in the c-axis direction when the temperature T is approximately the same as the reference temperature (e.g., room temperature (R.T.)). Also, Wb_(M,Zn)O shown in Fig. 2(C) indicates the thickness of the (M,Zn)O layer in the c-axis direction when the temperature T is higher than the reference temperature (e.g., room temperature (R.T.)), and Wb_InO shown in Fig. 2(C) indicates the thickness of the InO layer in the c-axis direction when the temperature T is higher than the reference temperature (e.g., room temperature (R.T.)). Also, in Fig. 2(B) and Fig. 2(C), the wavy line shown on the right side of the figure indicates the state of carriers transmitting through the InO layer.

[0092] The lattice vibration of atoms due to heat becomes smaller as the atomic mass number of the atoms increases. When the metal oxide is In-Ga-Zn oxide, the atomic mass number is the largest for In, followed by Ga and Zn, and the smallest for O. Therefore, the lattice vibration due to heat is larger for Ga and Zn than for In. From this, when the temperature increases, compared with the InO layer, (Ga,Zn ​​​​​​​​​​​​​​​)The vibration of the atoms constituting the O layer increases. Also, since the bond between the atoms in the (Ga,Zn)O layer is weaker than the bond between the atoms in the InO layer and the (Ga,Zn)O layer, the lattice vibration of Ga and Zn in the c-axis direction is larger than the lattice vibration in the a-b plane direction. From the above, Wb_(Ga,Zn) becomes larger than Wa_(Ga,Zn)O (see Fig. 2(C)). Note that assuming that the lattice constant in the c-axis direction of the layered crystal does not change with temperature, as the Wb_(Ga,Zn)O layer becomes larger, Wb_InO becomes relatively smaller (see Fig. 2(C)). That is, the higher the temperature, the smaller the thickness of the InO layer in the c-axis direction.

[0093] Figs. 3(A) to 3(C) are diagrams schematically showing the band diagram and the state of carriers transmitting through the InO layer in the crystal structure shown in Fig. 2(A). In Figs. 3(A) to 3(C), the back side of the paper corresponds to the source, the front side of the paper corresponds to the drain, the left-right direction of the paper corresponds to the c-axis direction of CAAC-OS, and the wavy curved surface in the figure indicates the lower end of the conduction band of CAAC-OS. Also, in Figs. 3(A) to 3(C), the black circles indicate carriers (e.g., electrons), and the dotted lines indicate the schematic trajectories of the carriers.

[0094] Fig. 3(A) shows a model at a temperature Ta that is approximately the same as the reference temperature (e.g., room temperature (R.T.)). Wa_(M,Zn) is the width of the convex part at the lower end of the conduction band of the (M,Zn)O layer, and Wa_InO is the width of the concave part at the lower end of the conduction band of the InO layer. Also, Fig. 3(B) shows a model at a temperature Tb higher than the reference temperature (e.g., room temperature (R.T.)). Wb_ ​​​​​​​​​​​​​​(M,Zn)O is the width of the convex portion at the lower end of the conduction band of the (M,Zn)O layer, and Wb_InO is In the width of the concave portion at the lower end of the conduction band of the O layer. Further, FIG. 3(C) shows the mode at a temperature Tc higher than the temperature Tb and Wc_(M,Zn)O is the width of the convex portion at the lower end of the conduction band of the (M,Zn)O layer and Wc_InO is the width of the concave portion at the lower end of the conduction band of the InO layer.

[0095] As described above, when the temperature increases, the vibration of the atoms constituting the (Ga,Zn)O layer becomes larger compared to the InO layer. Also, compared to the bond between the atoms in the (Ga,Zn)O layer, the bond between the InO layer and the (Ga,Zn)O layer is weak, so the lattice vibration of Ga and Zn in the c-axis direction is larger than the lattice vibration in the a-b plane direction. From the above, as shown in FIGS. 3(A) to (C), Wc_(Ga,Zn)O > Wb_(Ga,Zn)O > Wa_(Ga,Zn)O, and it becomes so. Assuming that the lattice constant in the c-axis direction of the layered crystal does not change with temperature, when W _(Ga,Zn)O becomes large, W_InO becomes relatively small. Therefore, as shown in FIGS. 3(A) to (C), Wa_InO > Wb_InO > Wc_InO, and it becomes so. That is, the higher the temperature, the smaller the thickness of the InO layer in the c-axis direction on the band diagram becomes.

[0096] As described above, the main carrier transmission path is the InO layer. The higher the temperature, the smaller the thickness of the InO layer in the c-axis direction on the band diagram, so the carriers are transmitted more planar ly on the a-b plane of the InO layer. From the above, as the carriers are transmitted more linearly from the source to the drain , the mobility of the metal oxide increases. Therefore, by using a metal oxide in the channel formation region of the transistor, the higher the temperature, the better the frequency characteristics become. ​​ will improve.

[0097] As mentioned above, the higher the temperature, the more planar the carriers propagate along the ab plane of the InO layer. In other words, in crystalline metal oxides, the carriers are scattered by lattice vibration (so-called It is assumed that the phonon scattering is difficult to occur. By narrowing the drain (also called shortening the channel), the drain electric field becomes stronger, and the carrier drift The improvement in drift velocity due to the shortened channel is due to phonon scattering. However, in crystalline metal oxides, phonon scattering is difficult to occur, The drift velocity increase due to the short channel is difficult to suppress. It is expected that metal oxides are less likely to exhibit short channel effects. It is possible to miniaturize a transistor using an oxide for a channel formation region. For example, Either or both of the channel length and the channel width of the transistor are set to 100n The area can be less than m.

[0098] In this specification, a narrow gap layer is sandwiched between a first layer having a wide gap. The transport of carriers along the ab plane in the second layer is called multi-atomic layer conduction (MALT). -Atomic Layers Transport). The material in which T occurs is a layer with a narrow gap between the first and second layers. The semiconductor material is not limited to the first and second layers. Even if the carrier is selectively or preferentially transferred to either the first layer or the second layer, Examples of materials in which MALT occurs include graphene stacks. Examples include graphite or the like that is.

[0099] <Modified Example 1 of Transistor> FIG. 4 is a perspective view of a transistor 10a according to one aspect of the present invention. In the perspective view of FIG. 4, some elements are omitted for clarity of the drawing. Also, FIGS. 5(A) and 5(B ) are cross-sectional views of the transistor 10a according to one aspect of the present invention. FIG. 5(A) is a cross-sectional view of the transistor 10a in the direction indicated by A1 - A2 in FIG. 4, and is also a cross-sectional view of the transistor 10a in the channel length direction. Further, FIG. 5(B) is a cross-sectional view of the transistor 10a in the direction indicated by A3 - A4 in FIG. 4, and is also a cross-sectional view of the transistor 10a in the channel width direction of the transistor 10a. in the channel width direction.

[0100] As shown in FIG. 5(A), the transistor 10a has an insulator 224 disposed on a substrate (not shown), an oxide 230b disposed on the insulator 224, an oxide 230c disposed on the oxide 230b, an insulator 250 disposed on the oxide 230c, and a conductor 260 disposed on the insulator 250.

[0101] Also, as shown in FIG. 5(B), in the channel width direction of the transistor 10a, the oxide 230c is provided so as to cover the upper surface and side surfaces of the oxide 230b. Further, the insulator 250 is provided so as to cover the upper surface and side surfaces of the oxide 230b via the oxide 230c. Also, the conductor 260 is provided so as to cover the upper surface and side surfaces of the oxide 230b via the oxide 230c and the insulator 250.

[0102]

[0102] The insulator 250 functions as a gate insulating film. Also, the conductor 260 functions as a gate electrode It functions. Further, the oxide 230b functions as a channel formation region of the transistor 10a a region 234 that functions as, and a region 231 (region 23 1a and region 231b) that functions as a source region or a drain region. Further, the channel formation region may be formed in the oxide 230c .

[0103] As shown in FIG. 5(B), the transistor 10a is different from the transistor 10 in that the first layer and the second layer of the oxide 230b are each disposed substantially perpendicular to the formation surface (the upper surface of the insulator 224) of the oxide 230b. Further, it can also be said that the arrangement direction of the first layer and the second layer of the oxide 230b of the transistor 10a is different from that of the transistor 10 in that it is parallel to the formation surface of the oxide 230b. However, also in the transistor 10a, the first layer and the second layer of the oxide 230b are each disposed substantially parallel to the channel length direction of the transistor 10. Note that the oxide 230b of the transistor 10a has the same configuration as the oxide 230 of the transistor 10 except that the first layer and the second layer are each disposed substantially perpendicular to the formation surface of the oxide 230b . . . . . . . . .

[0104] Here, an enlarged view of the region 53 of the oxide 230b shown in FIG. 5(B) is shown in FIG. 5(C). As shown in FIG. 5(C), the oxide 230b is an In-M-Zn oxide having a CAAC structure .

[0105] As shown in FIG. 5(C), in the oxide 230b of the transistor 10a, the c-axis of the crystal of the CAAC- OS is the formation surface or the film surface of the oxide 230b and They are oriented in a substantially parallel direction. Therefore, in FIG. 5(B), the direction of the c-axis of the crystal included in CAAC-OS is the horizontal direction of the paper surface. Also, the a- b plane of the crystal included in CAAC-OS is substantially parallel to the normal direction with respect to the formation surface or the film surface of the oxide 230b. That is to say, the InO layer and the (M,Zn)O layer are each arranged substantially perpendicular to the formation surface. Therefore, in FIG. 5(B), the a-b plane of the crystal included in CAAC-OS is parallel to the vertical direction of the paper surface and the normal direction of the paper surface.

[0106] When providing such an oxide 230b, for example, a structure is formed on the insulator 224, the oxide 230b is formed using the side surface of the structure as the formation surface, and then the structure may be removed. Here, it is preferable that the side surface of the structure is substantially perpendicular to the upper surface of the insulator 224.

[0107] Also, in the channel width direction of the transistor 10a, when the bottom surface of the insulator 224 is used as a reference the bottom surface of the conductor 260 in the region that does not overlap with the oxide 230b is preferably lower than the bottom surface of the oxide 230b. In particular, in the conductor 260, the bottom surface of the first region (which can also be referred to as the bottom surface on the A3 side) that does not overlap with the oxide 230b, and the bottom surface of the second region (which can also be referred to as the bottom surface on the A4 side) that is located opposite to the first region with the oxide 230b interposed therebetween are preferably lower than the bottom surface of the oxide 230b. Here, the difference between the height of the bottom surface of the conductor 260 in the region where the oxide 230b and the conductor 260 do not overlap and the height of the bottom surface of the oxide 230b is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less. ​ Let it be so.

[0108] A conductor 260 that functions as a gate electrode covers the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250. As a result, as shown in Fig. 5( B), the electric field of the conductor 260 acts on the entire region 234 of the oxide 230b, becoming less. In particular, by positioning the bottom surface of the conductor 260 below the bottom surface of the oxide 230b, the electric field of the conductor 260 can also act on the bottom surface of the oxide 230b.

[0109] In this way, in the cross-section of the transistor 10a in the channel width direction, a gate electric field can be applied to the region 234 of the oxide 230b from substantially the entire circumference. As a result, a channel can be formed throughout the region 234 of the oxide 2 30b. Therefore, the on-current of the transistor 10a can be increased and the frequency characteristics can be improved. Also, by forming a channel throughout the region 234 of the oxide 2 in this way, it is also possible to reduce the off-current of the transistor 10a. 30b, it is possible to reduce the off-current of the transistor 10a.

[0110] Here, the oxide 230b is preferably formed in an elongated wire shape with a film thickness and a length in the channel width direction of several nm to several tens of nm. Such an oxide 230b can be referred to as a nanowire. Also, as shown in Figs. 4 and 5, an elongated wire-shaped structure can be formed including the oxide 230b, the oxide 2 30c, the insulator 250, and the conductor 260. Collectively, these can also be referred to as nanowires. Also, as described above, since the transistor 10a can cause the electric field of the conductor 260 to act on the entire region 234 of the oxide 230b, it can also be referred to as a nanowire transistor. as described above, the electric field of the conductor 260 can act on the entire region 234 of the oxide 230b, it can also be called a nanowire transistor.

[0111] The oxide 230b of the transistor 10a is as follows compared to the oxide 230 of the transistor 10: In this case, the metal oxide layer is rotated by 90 degrees around the axis of the channel length. The transistor 10a is nanowire-like, i.e., conductive across the region 234 of the oxide 230b. By applying an electric field to the conductive body 260, the metal oxide layer is Therefore, the metal oxide 230b is formed on the surface on which the oxide 230b is formed. Even if the angles of the layers of the oxide are different, the transistors 10a and 10 have the same characteristics. Then it can be regarded as.

[0112] In addition, the oxide 230c contains a metal oxide having a larger band gap than the oxide 230b. Alternatively, a metal oxide having a small electron affinity may be used. Metal oxides having a small difference between the energy of the vacant level and the energy of the conduction band minimum may be used. In this way, the probability that carriers can move to the gate electrode and the gate insulating film is can be reduced.

[0113] In addition, when the oxide 230c has a function of suppressing the diffusion of oxygen, the oxide 230b The oxide 230 can be prevented from diffusing into the gate insulating film or the gate electrode. When the oxide 230c has a function of suppressing the diffusion of impurities, the oxide 230c is formed above the oxide 230c. This can suppress the diffusion of impurities from the structure into the oxide 230b.

[0114] In addition, although the oxide 230c is illustrated as a single layer in FIG. 4 and FIG. 5, the oxide 230c is A laminated structure may also be used.

[0115] <Modification Example 2 of Transistor> Fig. 6 shows a modified transistor 10b as a modified example of the transistor 10a. Fig. 6(A) and Fig. 6(B) are cross-sectional views of the transistor 10b according to one aspect of the present invention. Fig. 6( A) is a cross-sectional view of the transistor 10b in the channel length direction. Also, Fig. 6(B) is a cross-sectional view of the transistor 10b in the channel width direction.

[0116] In the transistor 10b, structures having the same functions as those constituting the transistor 10 and the transistor 10a are denoted by the same reference numerals. In this item, regarding the constituent materials of the transistor 10b, the materials described in detail for the transistor 10 and the transistor 10a can be used.

[0117] The transistor 10b is different from the transistor 10a in that the conductor 205 overlaps at least a part of the region where the oxide 230b and the conductor 260 overlap under the insulator 224. In the transistor 10b, the oxide 230c provided in the transistor 10a is not provided.

[0118] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 205 may function as a second gate (also referred to as a back gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 10b can be controlled. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 10b and reduce the off-current. ​​​​​​​​​​Therefore, applying a negative potential to the conductor 205 can reduce the drain current when the potential applied to the conductor 260 is 0 V compared to the case where no potential is applied. The drain current when the potential applied to the conductor 260 is 0 V can be reduced.

[0119] Note that the conductor 205 may be provided larger than the channel formation region in the oxide 230b. In particular, as shown in FIG. 6(B), the conductor 205 preferably extends also in a region outside the end portion intersecting the channel width direction of the oxide 230b. That is, it is preferable that the conductor 205 and the conductor 260 overlap via the insulator 224 outside the side surface in the channel width direction of the oxide 230. By having the above configuration, as shown in FIG. 6(B), the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the oxide 230b. In particular, the electric field of the conductor 205 can strengthen the electric field acting on the bottom surface of the oxide 230b. In this way, in the cross section in the channel width direction of the transistor 10b, a gate electric field can be applied to the region 234 of the oxide 230b from substantially the entire circumference. Thereby, since a channel can be formed in the entire region 234 of the oxide 230b, the on-current of the transistor 10b can be increased and the frequency characteristics can be improved. Also, by forming a channel in the entire region 234 of the oxide 230b in this way, the off-current of the transistor 10b can be reduced.

[0120] By having the above configuration, as shown in FIG. 6(B), the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the oxide 230b. In particular, the electric field of the conductor 205 can strengthen the electric field acting on the bottom surface of the oxide 230b. By having the above configuration, as shown in FIG. 6(B), the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the oxide 230b. In particular, the electric field of the conductor 205 can strengthen the electric field acting on the bottom surface of the oxide 230b. The channel formation region of the oxide 230b can be electrically surrounded. In particular, the electric field of the conductor 205 can strengthen the electric field acting on the bottom surface of the oxide 230b. The electric field acting on the bottom surface of the oxide 230b can be made stronger by the electric field of the conductor 205.

[0121] In this way, in the cross section in the channel width direction of the transistor 10b, a gate electric field can be applied to the region 234 of the oxide 230b from substantially the entire circumference. Thereby, a channel can be formed in the entire region 234 of the oxide 230b, so that the on-current of the transistor 10b can be increased and the frequency characteristics can be improved. Also, by forming a channel in the entire region 234 of the oxide 230b in this way, the off-current of the transistor 10b can be reduced. The on-current of the transistor 10b can be increased, and the frequency characteristics can be improved. Also, by forming a channel in the entire region 234 of the oxide 230b in this way, the off-current of the transistor 10b can be reduced. The on-current of the transistor 10b can be increased, and the frequency characteristics can be improved. Also, by forming a channel in the entire region 234 of the oxide 230b in this way, the off-current of the transistor 10b can be reduced. The off-current of the transistor 10b can also be reduced.

[0122] Also, similar to the transistor 10a, the transistor 10b can apply the electric fields of the conductor 260 and the conductor 205 to the entire region 234 of the oxide 230b, so it can be called a nanowire or nanowire transistor. In addition, in this specification and the like, the structure of the transistor in which the channel formation region is electrically surrounded by the electric fields of the first gate electrode and the second gate electrode can also be called a surrounded channel (S-channel) structure.

[0123] channel(S-channel) structure. channel(S-channel) structure. channel(S-channel) structure.

[0124] <Modified Example 3 of Transistor> Figs. 7 and 8 show a transistor 10c as a modified example of the transistor 10a. Fig. 7 is a perspective view of the transistor 10c according to an aspect of the present invention. Note that in the perspective view of Fig. 7, some elements are omitted for clarity of the drawing. Also, Figs. 8(A) and 8(B) are cross-sectional views of the transistor 10c according to an aspect of the present invention. Fig. 8(A) is a cross-sectional view of the transistor 10c in the direction indicated by A 1-A2 in Fig. 7, and is also a cross-sectional view of the transistor 10c in the channel length direction. Also, Fig. 8(B) is a cross-sectional view of the transistor 10c in the direction indicated by A3-A4 in Fig. 7, and is also a cross-sectional view of the transistor 10c in the channel width direction. cross-sectional view. cross-sectional view.

[0125] In the transistor 10c, structures having the same functions as the structures constituting the transistor 10, the transistor 10a, and the transistor 10b are denoted by the same reference numerals. Note that in this item, for the constituent materials of the transistor 10c, the materials described in detail for the transistor 10, the transistor 10a, and the transistor 10b can be used.

[0126] Transistor 10c has an oxide 230a between the insulator 224 and the oxide 230b. At this point, it is different from the transistor 10a. That is, the oxide 230 is on the insulator 224 oxide 230a, oxide 230b on oxide 230a, and oxide 2 on oxide 230b 30c.

[0127] It is preferable to use an oxide similar to the oxide 230c for the oxide 230a. For example, for the oxide 230a, a metal oxide having a larger band gap than the oxide 230b may be used or a metal oxide having a small electron affinity may be used. Or, the energy of the vacuum level The difference between the energy of the conduction band bottom and the energy of the conduction band bottom may be small, and a metal oxide may be used. In this way By doing so, the probability that carriers can move to the insulator 224 can be reduced.

[0128] The oxide 230a preferably has an upper surface in contact with the oxide 230b and a side surface in contact with the oxide 230c as shown in FIG. 8(B) at least in the region 234. With such a configuration In the region 234, the oxide 230b can be covered by the oxide 230a and the oxide 230 c. Therefore, in the region 234, the oxide 230b can be isolated from the insulator 224 and the insulator 250. Thereby, the probability that carriers can move to the outside in the oxide 230b can be reduced, and the diffusion of oxygen to the outside and the diffusion of impurities from the outside can be suppressed.

[0129] <Modified Example 4 of Transistor> FIG. 9 is a perspective view of a transistor 10d according to an aspect of the present invention. Note that the perspective view of FIG. 9 In the figure, some elements are omitted for clarity of the figure. Also, FIGS. 10(A) and 10 (B) are cross-sectional views of the transistor 10d according to one aspect of the present invention. FIG. 10(A) is a cross-sectional view of the transistor 10d in the direction indicated by A1 - A2 in FIG. 9, and is also a cross-sectional view of the transistor 10d in the channel length direction. Further, FIG. 10(B) is a cross-sectional view of the transistor 10d in the direction indicated by A3 - A4 in FIG. 9, and is also a cross-sectional view of the transistor 10d in the channel width direction.

[0130] Note that in the transistor 10d, structures having the same functions as the structures constituting the transistors 10, 10a, 10b, and 10c are given the same reference numerals. In this item, regarding the constituent materials of the transistor 10d, the materials described in detail for the transistors 10, 10a, 10b, and 10c can be used.

[0131] As shown in FIG. 10(A), the transistor 10d has an insulator 224 disposed on a substrate (not shown), an oxide 230b disposed on the insulator 224, an oxide 230c disposed on the oxide 230b, an insulator 250 disposed on the oxide 230c, and a conductor 260 disposed on the insulator 250.

[0132] Also, as shown in FIG. 10(B), in the channel width direction of the transistor 10d, the oxide 230c is provided so as to cover the upper surface and the side surface of the oxide 230b. Further, the insulator 250 covers the upper surface and the side surface of the oxide 230b via the oxide 230c. The conductor 260 is provided through the oxide 230c and the insulator 250. , which is provided to cover the top and side surfaces of oxide 230b.

[0133] The insulator 250 functions as a gate insulating film. The conductor 260 functions as a gate electrode. The oxide 230b also functions as a channel forming region of the transistor 10d. and a region 231 (region 232) that functions as a source region or a drain region. 1a, and region 231b). The channel forming region has oxide 230c. The second insulating layer 21 may be formed as follows.

[0134] In addition, in the channel width direction of the transistor 10d, At this time, the bottom surface of the conductor 260 in the region not overlapping with the oxide 230b is The conductor 260, which functions as a gate electrode, is preferably located at a position lower than the bottom surface of the channel 260. The side and top surfaces of the oxide 230b in the hole formation region are covered with the oxide 230c and the insulator 250. By covering the oxide 230b, the electric field of the conductor 260 is generated in the entire region 234 of the oxide 230b. This increases the on-state current of the transistor 10d and improves the frequency characteristics. In the region where the oxide 230b and the conductor 260 do not overlap, The difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b is 0 nm or more and 10 0 nm or less, preferably 3 nm to 50 nm, more preferably 5 nm to 20 nm m or less.

[0135] At least one of the oxide 230b and the oxide 230c is made of a crystalline metal oxide. Specifically, it is preferable that at least the oxide 230b and the oxide 230c are One party is preferably a single crystal oxide semiconductor or CAAC-OS.

[0136] Also, although the oxide 230b is illustrated as a single layer, it may have a laminated structure. For example, when the oxide 2 30b has a two-layer laminated structure, the lower layer of the oxide 230b is in contact with the insulator 224, and the upper layer of the oxide 230b is in contact with the oxide 230c. By having such a configuration, diffusion of impurities from the structure formed below the lower layer of the oxide 230b into the oxide 230b can be suppressed.

[0137] Here, an enlarged view of the region 54 of the oxide 230b shown in FIG. 10(B) is shown in FIG. 10(D). Also, the region 55 of the oxide 230c shown in FIG. 10(B) is shown in FIG. 10(E). Note that the oxide 230b and the oxide 230c are In-M-Zn oxides having a CAAC structure.

[0138] As described above, when the oxide 230b is CAAC-OS, the c-axis of the crystal of the oxide 230b is oriented in the normal direction with respect to the formation surface or the film surface of the oxide 230b, and the a-b plane is substantially parallel to the formation surface or the film surface of the oxide 230b. Therefore, in the region 54 of the oxide 230b shown in FIG. 1 0(D), the direction of the c-axis (c-axis) of the crystal of the oxide 230b is the vertical direction of the paper surface. Also, the a-b plane of the crystal of the oxide 230b is parallel to the left-right direction of the paper surface and the normal direction of the paper surface. Also, the c-axis of the crystal of CAAC-OS is oriented substantially perpendicular to the formation surface of CAAC-OS, and the a-b plane is substantially parallel to the formation surface of CAAC-OS. Therefore,

[0139] When a crystalline metal oxide is used for the oxide 230c, in the region 55 of the oxide 23 0c, the direction of the c-axis of the crystal possessed by the oxide 230c is , which is the left-right direction of the paper surface. Also, the a-b plane of the crystal possessed by the oxide 230c is parallel to the up-down direction of the paper surface and the normal direction of the paper surface.

[0140] From the above, on the dashed-dotted line shown as X5-X6 in Fig. 10(B), the c-axis direction of the crystal possessed by the oxide 230b and the c-axis direction of the crystal possessed by the oxide 230c are different.

[0141] [Carrier Transmission Model 2] Here, the carrier transmission in the transistor in which the oxide 230b and the oxide 230c are stacked will be described using the carrier transmission model described above.

[0142] Fig. 10(C) shows the model of the band diagram on the dashed-dotted line shown as X5-X6 in the transistor 10d shown in Figs. 10(A) and 10(B). Note that Fig. 1 0(C) shows the state where a positive potential is applied to the gate electrode. Also, in Fig. 10(C), an example is shown in which the oxide 230b and the oxide 230c use metal oxides having the same energy at the lower end of the conduction band.

[0143] On the dashed-dotted line of X5-X6 shown in Fig. 10(B), inside the oxide 230b, the a-b plane of the crystal possessed by the oxide 230b is substantially parallel to the substrate surface. Therefore, the energy at the lower end of the conduction band of the oxide 230b on the dashed-dotted line shown as X5- X6 is constant. Also, inside the oxide 230b, an electric field is generated in the a-b plane direction of the crystal possessed by the oxide 230b. Also, inside the oxide 230b, compared with the electric field applied to the surface of the oxide 230b, the electric field generated in the a-b plane direction of the crystal possessed by the oxide 230b is . Also, inside the oxide 230b, the electric field generated in the a-b plane direction of the crystal possessed by the oxide 230b is greater than the electric field applied to the surface of the oxide 230b. It is small. Therefore, the curvature of the lower end of the conduction band inside the oxide 230b is small.

[0144] On the other hand, in the oxide 230c, an electric field is generated in the c-axis direction of the crystal that the oxide 230c has. Also, the electric field generated in the oxide 230c is larger than the electric field applied inside the oxide 230b. Therefore, the band curvature in the oxide 230c is large (see the dotted line in Fig. 10(C)). . Also, on the dashed-dotted line indicated by X5-X6, the a-b plane of the crystal that the oxide 230c has is substantially perpendicular to the substrate surface. Therefore, as shown in Fig. 10(C), on the dashed-dotted line indicated by X5-X6 the lower end of the conduction band of the oxide 230c alternates with the lower end of the conduction band derived from the InO layer and the lower end of the conduction band derived from the ( M,Zn)O layer.

[0145] At this time, the carriers injected from the source concentrate in the InO layer of the oxide 230c where the lower end of the conduction band is lower. Furthermore, the carriers are transmitted between the source and the drain, that is, transmitted in the a-b plane direction. From the above, on the dashed-dotted line indicated by X5-X6, the main carrier transmission path is the InO layer of the oxide 230b or the InO layer of the oxide 230c and. becomes.

[0146] If the carriers concentrate too much, repulsion due to the Coulomb force occurs between the carriers, and the carrier transmission is suppressed. In a metal oxide having a layered crystal, as shown in Fig. 10(C) since there are a plurality of InO layers that are the main carrier transmission paths, the carriers are dispersed in the plurality of existing InO layers. Therefore, the concentration of carriers is alleviated, and it is difficult for repulsion due to the Coulomb force to occur between the carriers, and the carrier transmission is not suppressed.

[0147] Note that, for the oxide 230c, a metal oxide having a larger band gap than the oxide 230b may be used. Alternatively, a metal oxide having a small electron affinity may be used. Alternatively, a metal oxide having a small difference between the energy of the vacuum level and the energy of the lower end of the conduction band may be used. By doing so, the probability that carriers can move to the gate electrode and the gate insulating film can be reduced. In FIGS. 9 and 10, the oxide 230c is illustrated as a single layer, but it may have a stacked structure. For example, when the oxide 230c has a two-layer stacked structure, assume that the lower layer of the oxide 230c is in contact with the oxide 230b, and the upper layer of the oxide 230c is in contact with the insulator 250. At this time, for the lower layer of the oxide 230c, a metal oxide having the same composition as the oxide 230b is used, and for the upper layer of the oxide 230c, a metal oxide having a larger band gap than the oxide 230b is preferably used. With such a configuration, the probability that carriers can move to the gate electrode and the gate insulating film can be reduced. Alternatively, when the upper layer of the oxide 230c has a function of suppressing oxygen diffusion, oxygen in the oxide 230b and the lower layer of the oxide 230c can be suppressed from diffusing into the gate insulating film or the gate electrode. Alternatively, when the upper layer of the oxide 230c has a function of suppressing impurity diffusion, impurity diffusion from a structure formed above the upper layer of the oxide 230c to the lower layer of the oxide 230c and the oxide 230b can be suppressed. As described above, the configuration examples of the transistor and the configurations of the modified examples can be used in appropriate combinations with each other.

[0148]

[0149]

[0150] As described above, a semiconductor device having a transistor with a large on-current can be provided. In addition, a semiconductor device having a transistor with high frequency characteristics can be provided. In addition, a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability can be provided. In addition, a semiconductor device having a transistor with a small off-current can be provided.

[0151] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and examples.

[0152] (Embodiment 2) Hereinafter, an example of a specific configuration of the semiconductor device shown in the previous embodiment will be described with reference to FIGS. 11 to 17.

[0153] <Example Configuration 1 of Semiconductor Device> FIGS. 11(A) to 11(C) are a top view and a cross-sectional view of the transistor 200 according to one aspect of the present invention and the periphery of the transistor 200.

[0154] FIG. 11(A) is a top view of a semiconductor device having the transistor 200. FIGS. 11(B) and 11(C) are cross-sectional views of the semiconductor device. Here, FIG. 11(B) is a cross-sectional view of the portion indicated by the dashed line A1 - A2 in FIG. 11(A), and is also a cross-sectional view in the channel length direction of the transistor 200. FIG. 11(C) is a cross-sectional view of the portion indicated by the dashed line A3 - A4 in FIG. 11(A), and is also a cross-sectional view in the channel width direction of the transistor 200. In the top view of FIG. 11(A), some elements are omitted for clarity of the drawing. 0.

[0155] A semiconductor device according to one aspect of the present invention includes a transistor 200, an insulator 214 that functions as an interlayer film, an insulator 280, an insulator 274, and an insulator 281. It also has a conductor 240 (conductor 240a and conductor 240b) that is electrically connected to the transistor 200 and functions as a plug. Note that an insulator 241 (insulator 241a and insulator 241b) is provided in contact with the side surface of the conductor 240 that functions as a plug.

[0156] In addition, an insulator 241 is provided in contact with the side walls of the openings of the insulator 254, the insulator 280, the insulator 274, and the insulator 281. A first conductor of the conductor 240 is provided in contact with the side surface thereof, and a second conductor of the conductor 240 is provided further inside. Here, the height of the upper surface of the conductor 240 and the height of the upper surface of the insulator 281 can be made approximately the same. Note that in the transistor 200, although the structure in which the first conductor of the conductor 240 and the second conductor of the conductor 240 are stacked is shown, the present invention is not limited to this. For example, the conductor 240 may be provided as a single layer or a stacked structure of three or more layers. When the structure has a stacked structure, ordinal numbers may be assigned in the formation order for distinction.

[0157] [Transistor 200] As shown in FIG. 11, the transistor 200 includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a, Oxide 230b and oxide 230c), and insulator 25 disposed on oxide 230 0, and conductor 260 (conductor 260a and conductor 260 b) disposed on insulator 250, and conductor 242a and conductor 242b in contact with a part of the upper surface of oxide 230b A part of the upper surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, oxide 230 The side surface of b, the side surface of conductor 242a, the upper surface of conductor 242a, the side surface of conductor 242b, and Insulator 254 disposed in contact with the upper surface of conductor 242b.

[0158] Conductor 260 functions as the gate electrode of the transistor, and conductor 242a and conductor 242b each function as a source electrode or a drain electrode. In transistor 2 00, conductor 260 functioning as the gate electrode is self-alignedly formed so as to fill an opening formed in insulator 280 or the like. By forming conductor 260 in this way, it is possible to surely dispose conductor 260 in the region between conductor 242a and conductor 242b without alignment.

[0159] Note that conductor 260 preferably has conductor 260a and conductor 2 60b disposed on conductor 260a. For example, conductor 260a is preferably disposed so as to surround the bottom surface and side surface of conductor 260b. Further, as shown in FIG. 11(B), the upper surface of conductor 260 substantially coincides with the upper surface of insulator 250 and the upper surface of oxide 230c. Note that in transistor 200, conductor 260 is shown as having a two-layer stacked structure, but the present invention is not limited thereto. For example, conductor 260 may have a single-layer structure or a stacked structure of three or more layers. ​

[0160] The insulators 222, 254, and 274 are made of hydrogen (e.g., hydrogen atoms, hydrogen It is preferable that the insulating material has a function of suppressing the diffusion of at least one of the molecules. 222, insulator 254, and insulator 274 are oxygen (e.g., oxygen atoms, oxygen molecules, etc.) For example, the insulator 222 has a function of suppressing the diffusion of at least one of the above. , insulator 254, and insulator 274 have higher hydrogen and oxygen concentrations than insulator 224, respectively. It is preferable that one or both of the insulators have low permeability. The insulator 274 is more permeable to hydrogen and / or oxygen than the insulator 250. The insulators 222, 254, and 274 are preferably insulators having a low It is preferable that the permeability to one or both of hydrogen and oxygen is lower than that of the edge 280 .

[0161] The oxide 230 is made up of an oxide 230a disposed on the insulator 224 and an oxide 230b. and a second oxide layer 230b disposed on the second oxide layer 230b, the second oxide layer 230b being at least partially oxide-coated. It is preferable that the oxide 230c is in contact with the upper surface of the oxide 230b. As shown in FIG. 1C, in the channel width direction of the transistor 200, the oxide 230c It is preferable that the oxide 230b is provided so as to cover the top and side surfaces of the oxide 230b.

[0162] Here, the oxide 230, the insulator 250, the conductor 260, the insulator 224, and the conductor 2 05 is a transistor 10 or transistors 10a to 10c shown in the above embodiment. This corresponds to the configuration of the transistor 10d.

[0163] Note that in the transistor 200, the region where the channel is formed (hereinafter also referred to as the channel formation region ).) and in its vicinity, a structure in which three layers of the oxide 230a, the oxide 230b, and the oxide 2 30c are laminated is shown, but the present invention is not limited to this . For example, a single layer of the oxide 230b, a two-layer structure of the oxide 230a and the oxide 230b, an oxide A two-layer structure of 230b and the oxide 230c, or a laminated structure of four or more layers may be provided . Further, each of the oxide 230a, the oxide 230b, and the oxide 230c may have a laminated structure of two layers or more.

[0164] For example, when the oxide 230c has a laminated structure composed of a first oxide and a second oxide on the first oxide , the first oxide may have the same composition as the oxide 230b, and the second oxide may have the same composition as the oxide 230a.

[0165] Further, in the transistor 200, a metal oxide (hereinafter also referred to as an oxide semiconductor) that functions as a semiconductor is preferably used for the oxide 230 (the oxide 230a , the oxide 230b, and the oxide 230c) including the channel formation region.

[0166] The transistor 200 using an oxide semiconductor in the channel formation region has an extremely small leakage current (off current) in the non-conducting state , so that a low-power semiconductor device can be provided. Also , since the oxide semiconductor can be formed by a sputtering method or the like, it can be used for the transistor 200 constituting a highly integrated semiconductor device.

[0167] For example, as the oxide 230, an In-M-Zn oxide (element M is aluminum, gallium Umm, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel , germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium One or more selected from metals such as tantalum, tungsten, magnesium, etc.) It is preferable to use a metal oxide. In particular, as the element M, aluminum, gallium, yttrium, or tin may be used. Further, as the oxide 230, an In-Ga oxide, an In-Zn oxide oxide, or a Ga-Zn oxide may be used.

[0168] As described above, the oxide 230 corresponds to the oxide 230 shown in the previous embodiment. Therefore , for the oxide 230 including the channel formation region of the transistor 200, a crystalline metal oxide is preferably used. Further, the crystal of the metal oxide has a first layer and a second layer and preferably has a crystal structure in which the first layer and the second layer are alternately laminated . Further, it is preferable that the first layer has a wider band gap than the second layer . Examples of the crystalline metal oxide include a single crystal oxide semiconductor and CAAC-OS . The crystalline metal oxide can improve the carrier transmission. Therefore, the mobility of the metal oxide becomes high, the on-current of the transistor using the metal oxide becomes high and the electrical characteristics of the transistor can be improved.

[0169] Furthermore, as described above, at least one of the oxide 230b and the oxide 230c is preferably a crystalline metal oxide . Specifically, at least one of the oxide 230b and the oxide 230c is preferably a single crystal oxide semiconductor or CAAC-OS This is preferable. Here, FIG. 11(C) is a cross-sectional view in the channel width direction of the transistor 200, similar to FIG. 10(B). Therefore, the region corresponding to the region 54 of the oxide 230b shown in FIG. 10(B) has the crystal structure shown in FIG. 10(D), and the region corresponding to the region 55 of the oxide 230c shown in FIG. 10(B) has the crystal structure shown in FIG. 10(E). Thus, since the transistor 200 satisfies the model of the schematic band diagram shown in FIG. 10(C), it is possible to prevent the suppression of carrier transmission. Also, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. In addition, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Also, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability.

[0170] Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability. Moreover, as shown in FIG. 11(B), it is preferable that the region located near the interface between the oxide 230c and the insulator 274 is physically separated from the channel formation region of the oxide 230. Near the interface between the oxide 230c and the insulator 274, the trap level density may be high. Therefore, by separating the physical distance between the region located near the interface between the oxide 230c and the insulator 274 and the channel formation region of the oxide 230, it is possible to suppress fluctuations in the electrical characteristics of the transistor 200 and improve the reliability.

[0171] Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity Moreover, in a transistor using an oxide semiconductor, if impurities and oxygen deficiencies exist in the channel formation region in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may deteriorate. Also, if the channel formation region in the oxide semiconductor contains oxygen deficiencies, the transistor tends to have normally-on characteristics. Therefore, it is preferable that the oxygen deficiencies in the channel formation region are reduced as much as possible. For example, oxygen may be supplied to the oxide 230 through the oxide 230c or the insulator 250 to compensate for the oxygen deficiencies. Thereby, the electricity It is possible to provide a transistor that suppresses fluctuations in characteristics, has stable electrical characteristics, and has improved reliability.

[0172] Further, when the elements contained in the conductor 242 (conductor 242a and conductor 242b) that is provided so as to be in contact with the oxide 230 and functions as a source electrode or a drain electrode have a function of absorbing oxygen in the oxide 230, a low-resistance region may be partially formed between the oxide 230 and the conductor 242 or near the surface of the oxide 230. In this case, impurities (such as hydrogen, nitrogen, and metal elements) that have entered the oxygen deficiency function as donors in the low-resistance region, and the carrier density may increase.

[0173] Further, an enlarged view of a part of the region of the transistor 200 shown in FIG. 11(B) is shown in FIG. 12(A). As shown in FIG. 12(A), the conductor 242 is provided so as to be in contact with the oxide 230, and regions 243 (regions 243a and regions 243b) may be formed as low-resistance regions at the interface between the oxide 230 and the conductor 242 and in the vicinity thereof. The oxide 230 includes at least a part of the region 234 that functions as a channel formation region of the transistor 200 and the region 243, and has a region 231 (regions 231a and regions 231b) that functions as a source region or a drain region. In the following drawings, even when the region 243 is not shown in an enlarged view or the like, a similar region 243 may be formed.

[0174] Note that the regions 243a and 243b are shown as an example provided so as to diffuse in the depth direction near the conductor 242 of the oxide 230b, but the present invention is not limited to this. ​​​​​​​​​​​​​​Regions 243a and 243b may be formed appropriately according to the required electrical characteristics of the transistor. Also, in the oxide 230, it may be difficult to clearly detect the boundary between each region. The concentration of the element detected within each region is not limited to a stepwise change for each region, and may also change continuously (also referred to as gradation) within each region. Also, as shown in FIG. 11(B), the insulator 254 preferably contacts the upper surfaces of the conductors 242a and 242b, the side surfaces of the conductors 242a and 242b other than the opposing side surfaces, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and a part of the upper surface of the insulator 222. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, impurities such as hydrogen contained in the insulator 280 or the like can be suppressed from mixing into the insulator 224, the oxide 230a, and the oxide 230b. The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other.

[0175] By having such a structure, impurities such as hydrogen contained in the insulator 281 or the like can be suppressed from mixing into the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed. The insulator 254 preferably contacts the upper surfaces of the conductors 242a and 242b, the side surfaces of the conductors 242a and 242b other than the opposing side surfaces, the side surfaces of the oxides 230a and 230b, the side surface of the insulator 224, and a part of the upper surface of the insulator 222. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, impurities such as hydrogen contained in the insulator 280 or the like can be suppressed from mixing into the insulator 224, the oxide 230a, and the oxide 230b. The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, impurities such as hydrogen contained in the insulator 280 or the like can be suppressed from mixing into the insulator 224, the oxide 230a, and the oxide 230b. The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other. Thereby, the insulator 280 is separated from the insulator 224, the oxide 230a, and the oxide 230b by the insulator 254. Therefore, impurities such as hydrogen contained in the insulator 280 or the like can be suppressed from mixing into the insulator 224, the oxide 230a, and the oxide 230b. The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other.

[0176] The insulator 274 contacts the upper surfaces of the conductor 260, the insulator 250, and the oxide 230c, respectively. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other. Also, as shown in FIG. 12(A), the transistor 200, which is one aspect of the present invention, has a structure in which the insulator 274 and the insulator 250 are in contact with each other. By having such a structure, impurities such as hydrogen contained in the insulator 281 or the like can be suppressed from mixing into the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed. By having such a structure, impurities such as hydrogen contained in the insulator 281 or the like can be suppressed from mixing into the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed. By having such a structure, impurities such as hydrogen contained in the insulator 281 or the like can be suppressed from mixing into the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed. By having such a structure, impurities such as hydrogen contained in the insulator 281 or the like can be suppressed from mixing into the insulator 250. Therefore, adverse effects on the electrical characteristics and reliability of the transistor can be suppressed.

[0177] Further, as shown in FIG. 12(A), with reference to the bottom surface of the insulator 224, the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 may be lower than the heights of the upper surfaces of the conductors 242a and 242b, respectively. For example, the difference between the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 and the heights of the upper surfaces of the conductors 242a and 242b, respectively, is set to be 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less. In the region where the bottom surface of the conductor 260 overlaps with the region 234, the height of the bottom surface of the conductor 260 may be lower than the heights of the upper surfaces of the conductors 242a and 242b, respectively. For example, the difference between the height of the bottom surface of the conductor 260 in the region overlapping with the region 234 and the heights of the upper surfaces of the conductors 242a and 242b, respectively, is set to be 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less. In the region where the bottom surface of the conductor 260 overlaps with the region 234, the height of the bottom surface of the conductor 260 and the heights of the upper surfaces of the conductors 242a and 242b, respectively, The difference is set to be 0 nm or more and 30 nm or less, or 0 nm or more and 15 nm or less.

[0178] Further, an enlarged view of a partial region of the transistor 200 shown in FIG. 11(C) is shown in FIG. 12(B). Similar to the previous embodiment, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, in the region where the conductor 260 and the oxide 230b do not overlap, it is preferable that the height of the bottom surface of the conductor 260 is lower than the height of the bottom surface of the oxide 230b. Similar to the previous embodiment, in the channel width direction of the transistor 200, with reference to the bottom surface of the insulator 222, in the region where the conductor 260 and the oxide 230b do not overlap, it is preferable that the height of the bottom surface of the conductor 260 is lower than the height of the bottom surface of the oxide 230b. In the region where the conductor 260 and the oxide 230b do not overlap, with reference to the bottom surface of the insulator 222, in the channel width direction of the transistor 200, it is preferable that the height of the bottom surface of the conductor 260 is lower than the height of the bottom surface of the oxide 230b. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, the electric field of the conductor 260 can be easily applied to the entire region 234 of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. When the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap is defined as T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, the electric field of the conductor 260 can be easily applied to the entire region 234 of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. By configuring the conductor 260 that functions as a gate electrode to cover the side surface and the upper surface of the oxide 230b in the channel formation region via the oxide 230c and the insulator 250, the electric field of the conductor 260 can be easily applied to the entire region 234 of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved. The oxide 230 a and the oxide 230b and the conductor 260, in the region where they do not overlap, the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b, When the difference is defined as T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less. When the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap is defined as T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less. When the difference between the height of the bottom surface of the conductor 260 and the height of the bottom surface of the oxide 230b in the region where the oxide 230a and the oxide 230b and the conductor 260 do not overlap is defined as T2, T2 is 0 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less, more preferably 5 nm or more and 20 nm or less.

[0179] Further, as shown in FIG. 12(B), in the channel width direction of the transistor 200, the acid The oxide 230c in the region that does not overlap the insulator 224 is the oxide 230b, the oxide 230a, and the insulator 224. At least a part of the insulating material 222 is preferably in contact with the insulating material 222. The oxygen contained in the oxide 230c flows through the insulator 224 to the outside of the transistor 200. In addition, the oxide 230b and the oxide 230a can be prevented from diffusing. Preventing oxygen from diffusing through the insulator 224 to the outside of the transistor 200 In addition, the area of ​​the insulator 224 is reduced, so that the amount of oxygen taken in by the insulator 224 is reduced. The amount of oxygen supplied to the oxide 230 can be reduced. The oxygen contained in the oxide 230c is efficiently converted into the oxide 230b and the oxide 230a. Therefore, the decrease in the resistance of the oxide 230 in the region 234 can be suppressed. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the transistor has stable electrical characteristics. At the same time, reliability can be improved.

[0180] In addition, by adopting the above-mentioned configuration, impurities such as hydrogen contained in the insulator 224 are oxidized. In other words, the oxide 230 is prevented from being mixed with the oxide 230. Therefore, the fluctuation of the electrical characteristics of the transistor can be suppressed, and the electrical characteristics can be stabilized. In addition, the oxide 230 can be formed on the surface of the insulating film 230. b, and removing the insulator 224 in the areas not overlapping the oxide 230a to form It is possible.

[0181] Also, the oxide 230b and the insulator 224 in the area not overlapping the oxide 230a are removed. As a result, as shown in FIG. 12B, in the channel width direction of the transistor 200, 、With reference to the bottom surface of the insulator 222, the oxides 230a and 230b and the conductor 2 60 are arranged such that in a region where they do not overlap, the height of the bottom surface of the conductor 260 is likely to be lower than the height of the bottom surface of the oxide 230b. Therefore, the on-current of the transistor 200 can be increased and the frequency characteristics can be improved.

[0182] From the above, a semiconductor device having a transistor with a large on-current can be provided. Also, a semiconductor device having a transistor with high frequency characteristics can be provided. Also, a semiconductor device that suppresses fluctuations in electrical characteristics, has stable electrical characteristics, and has improved reliability can be provided. Also, a semiconductor device having a transistor with a small off-current can be provided.

[0183] Hereinafter, the detailed configuration of the semiconductor device having the transistor 200 according to one aspect of the present invention will be described.

[0184] The conductor 205 is arranged to overlap with the oxide 230 and the conductor 260. Also, the conductor 205 is preferably provided by being embedded in the insulators 214 and 216. Here, it is preferable to improve the flatness of the upper surface of the conductor 205. For example, the average surface roughness (Ra) of the upper surface of the conductor 205 may be 1 nm or less, preferably 0.5 nm or less, and more preferably 0.3 nm or less. Thereby, the flatness of the insulator 224 formed on the conductor 205 can be improved, and the crystallinity of the oxides 230a, 230b, and 230c can be improved.

[0185] Here, the conductor 260 may function as a first gate (also referred to as a top gate) electrode. Also, the conductor 205 may function as a second gate (also referred to as a back gate) electrode. In that case, by changing the potential applied to the conductor 205 independently without linking it to the potential applied to the conductor 260, the threshold voltage (Vth) of the transistor 200 can be controlled. In particular, by applying a negative potential to the conductor 205, it is possible to increase the Vth of the transistor 200 and reduce the off - current. Therefore, applying a negative potential to the conductor 205 can make the drain current smaller when the potential applied to the conductor 260 is 0V than when no negative potential is applied.

[0186] Note that as shown in Fig. 11(A), the conductor 205 may be provided larger than the channel formation region in the oxide 230. In particular, as shown in Fig. 11(C), the conductor 205 preferably extends also in a region outside the end portion intersecting the channel width direction of the oxide 230. That is, it is preferable that the conductor 205 and the conductor 260 overlap via an insulator outside the side surface in the channel width direction of the oxide 230.

[0187] By having the above - described configuration, the electric field of the conductor 260 functioning as the first gate electrode and the electric field of the conductor 205 functioning as the second gate electrode can electrically surround the channel formation region of the oxide 230.

[0188] Also, as shown in Fig. 11(C), the conductor 205 is extended to also function as a wiring. However, it is not limited to this, and a conductor functioning as a wiring may be provided under the conductor 205.​​​​​​​ It may be configured to provide a conductor. Also, the conductor 205 does not necessarily need to be provided one by one for each transistor. For example, it may be configured to share the conductor 205 among a plurality of transistors.

[0189] Also, the conductor 205 preferably uses a conductive material mainly composed of tungsten, copper, or aluminum. Although the conductor 205 is illustrated as a single layer, it may have a laminated structure. For example, it may be a laminate of titanium, titanium nitride, and the above conductive material.

[0190] Also, a conductor having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms may be provided under the conductor 205 (the above impurities are difficult to permeate). Or, it is preferable to provide a conductor having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.) (the above oxygen is difficult to permeate). In this specification, etc., the function of suppressing the diffusion of impurities or oxygen means the function of suppressing the diffusion of any one or all of the above impurities or the above oxygen.

[0191] By using a conductor having a function of suppressing the diffusion of oxygen under the conductor 205, it is possible to suppress the oxidation of the conductor 205 and the decrease in conductivity. As the conductor having a function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, or ruthenium oxide. Therefore, the lower layer conductor of the conductor 205 may be the above conductive material in a single layer or a laminate.

[0192] Note that the film formation of the conductor 205 can be performed using a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method. cal Vapor Deposition) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, or an atomic layer deposition (ALD) method. For example, in this embodiment, a stacked film in which conductive films are formed in the order of tantalum nitride, titanium nitride, and tungsten can be used as the conductor 205.

[0193] The insulator 214 disposed on the substrate (not shown) preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. Therefore, it is preferable to use an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, and NO2), and copper atoms (the above impurities are difficult to permeate).

[0194] In addition, it is preferable to use an insulating material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is difficult to permeate). Preferably, for example, aluminum oxide, silicon nitride, or the like is used as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side through the insulator 214 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side from the insulator 214. Preferably, for example, aluminum oxide, silicon nitride, or the like is used as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side through the insulator 214 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side from the insulator 214.

[0195] Preferably, for example, aluminum oxide, silicon nitride, or the like is used as the insulator 214. Thereby, it is possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side through the insulator 214 to the transistor 200 side. Alternatively, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side from the insulator 214. Thereby, it is possible to suppress the diffusion of oxygen contained in the insulator 224 or the like to the substrate side from the insulator 214.

[0196] Note that the film formation of the insulator 214 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A LD method, etc. In this embodiment, as the insulator 214, for example, aluminum oxide formed by a sputtering method can be used.

[0197] The insulator 216 disposed on the insulator 214 functions as an interlayer film. Also, the insulators 2 80 and 281 disposed on the insulator 254 also function as interlayer films in the same manner. Here, the insulators 216, 280, and 281 that function as interlayer films preferably have a lower dielectric constant than the insulator 214. By using a material with a low dielectric constant as the interlayer film , the parasitic capacitance generated between the wirings can be reduced. For example, as the insulators 216, 2 80, and 281, silicon oxide, silicon oxynitride, silicon nitride oxide , silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with both carbon and nitrogen added, silicon oxide with pores, etc. can be appropriately used.

[0198] Also, the insulator 216 may have a laminated structure. For example, in the insulator 216, at least a part in contact with the side surface of the conductor 205 is configured to be provided with an insulator similar to the insulator 214 . By adopting such a configuration, oxidation of the conductor 205 by oxygen contained in the insulator 216 can be suppressed. Or, oxidation of the insulator 21 6 by oxygen contained therein can be suppressed by the conductor 205.

[0199] Note that the film formation of the insulator 216 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A It can be carried out using the LD method or the like. In this embodiment, as the insulator 216, for example, , silicon oxynitride formed by the CVD method can be used.

[0200] The insulator 222 and the insulator 224 have the function as a gate insulator.

[0201] Here, the insulator 224 in contact with the oxide 230 preferably desorbs oxygen by heating. In this specification and the like, the oxygen desorbed by heating may be referred to as excess oxygen. For example, the insulator 224 may be appropriately silicon oxide, silicon oxynitride, or the like. By providing an oxygen-containing insulator in contact with the oxide 230, the oxygen deficiency in the oxide 230 can be reduced, and the reliability of the transistor 200 can be improved.

[0202] Specifically, as the insulator 224, it is preferable to use an oxide film in which some oxygen desorbs by heating. The oxide film that desorbs oxygen by heating is an oxide film in which the desorption amount of oxygen in terms of oxygen atoms is 1.0×10 or more, preferably 1.0×10 or more, more preferably 2.0×10 18 atoms / cm 3 or more, or 3 19 3 19 3 20 3 atoms / cm 13 or more, as determined by TDS (Thermal Desorption Spectroscopy) analysis. Note that the surface temperature of the film during the above TDS analysis is preferably in the range of 100°C or higher and 700°C or lower, or 100°C or higher and 400°C or lower.

[0203] ​​​​​​​​Note that the film formation of the insulator 224 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, as the insulator 224, for example, silicon oxynitride formed by a CVD method can be used. In the transistor 200 shown in FIG. 11, the insulator 224 is formed in an island shape, but the present embodiment is not limited to this. For example, the insulator 224 can also be configured to cover the entire surface of the insulator 222.

[0204] The insulator 222 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side into the transistor 200. For example, the insulator 222 preferably has lower hydrogen permeability than the insulator 224. By the insulator 222 and the insulator 254, surrounding the insulator 224, the oxide 230, etc., it is possible to suppress the diffusion of impurities such as water and hydrogen from the outside into the insulator 224 and the oxide 230.

[0205] Furthermore, the insulator 222 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 222 preferably has lower oxygen permeability than the insulator 224. Since the insulator 222 has a function of suppressing the diffusion of oxygen and impurities, the oxygen contained in the oxide 230 can be reduced from diffusing to the substrate side, which is preferable. Also, it is possible to suppress the reaction of the conductor 205 with the oxygen contained in the insulator 224 and the oxide 230.

[0206] The insulator 222 is an insulating material of one or both of aluminum and hafnium It is preferable to use an insulator containing an oxide. One or both of aluminum and hafnium As the insulator containing an oxide, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the oxide 230 and the diffusion of impurities such as hydrogen from the peripheral portion of the transistor 200 to the oxide 230. Note that, among the materials described above, it is particularly preferable to use hafnium oxide as the insulator 222. For example, when the insulator 222 is used as a gate insulating film, using hafnium oxide for the insulator 222 may reduce the interface state density as compared with aluminum oxide.

[0207] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, zirconium oxide may be added to these insulators. Or these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may be laminated and used on the above-mentioned insulators.

[0208] Also, the insulator 222 may be a single layer or a laminate of an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST). As the transistor is miniaturized and highly integrated, problems such as leakage current may occur due to the thinning of the gate insulator. Gate By using a high-k material for the insulator that functions as an insulator, while maintaining the physical film thickness it becomes possible to reduce the gate potential during transistor operation.

[0209] Note that the film formation of the insulator 222 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A LD method, etc. In the present embodiment, as the insulator 222, for example hafnium oxide formed by an ALD method can be used.

[0210] Also, as shown in FIG. 11(C), the film thickness of the region where the insulator 222 does not overlap with the oxide 230b may be thinner than the film thickness of the other regions. In the insulator 222, when forming an opening provided in the insulator 280 or the like the film thickness of the region that does not overlap with the oxide 230b is a film thickness that can function as an etching stopper film, or is preferably a film thickness sufficient to prevent the surface of the insulator 216 or the conductor 205 from being exposed.

[0211] Note that the insulator 222 and the insulator 224 may have a laminated structure of two or more layers . In that case, it is not limited to a laminated structure made of the same material, and a laminated structure made of different materials may also be used. For example, a configuration in which an insulator similar to the insulator 224 is provided under the insulator 222 may also be used.

[0212] The oxide 230 has an oxide 230a, an oxide 230b on the oxide 230a, and an oxide 2 30c on the oxide 230b. By having the oxide 230a under the oxide 230b it is possible to suppress the diffusion of impurities from the structure formed below the oxide 230a to the oxide 230b. Also, by having the oxide 230c on the oxide 230b ​​Diffusion of impurities from the structure formed above the oxide 230c to the oxide 230b can be suppressed.

[0213] Note that the oxide 230 preferably has a stacked structure with oxides having different atomic ratios of each metal atom. Specifically, in the metal oxide used for the oxide 230a, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230a, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. In the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230a. Also, the metal oxide that can be used for the oxide 230c can be the metal oxide that can be used for the oxide 230a or the oxide 230b. In addition, the oxides 230b and 230c preferably have crystallinity. For example, it is preferable to use CAAC-OS described later. Oxides having crystallinity such as CAAC-OS have a small amount of impurities and defects (such as oxygen deficiency) and have a highly crystalline and dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed.

[0214] As a result, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable with respect to a high temperature (so-called thermal budget) in the manufacturing process. For example, it is preferable to use CAAC-OS. Oxides having crystallinity such as CAAC-OS have few impurities and defects (such as oxygen deficiency) and have a highly crystalline and dense structure. Therefore, extraction of oxygen from the oxide 230b by the source electrode or the drain electrode can be suppressed. As a result, even when heat treatment is performed, extraction of oxygen from the oxide 230b can be reduced, so that the transistor 200 is stable with respect to a high temperature (so-called thermal budget) in the manufacturing process. This reduces the possibility that oxygen is extracted from the oxide 230b, so that the transistor 200 is stable at a high temperature (so-called thermal budget) in the manufacturing process. is stable.

[0215] Further, it is preferable that the lower end of the conduction band of the oxide 230a and the oxide 230c is closer to the vacuum level than the lower end of the conduction band of the oxide 230b. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c is smaller than the electron affinity of the oxide 230b. In this case, it is preferable that the oxide 230c uses a metal oxide that can be used for the oxide 230a. Specifically, in the metal oxide used for the oxide 230c, the atomic ratio of the element M in the constituent elements is preferably larger than the atomic ratio of the element M in the constituent elements in the metal oxide used for the oxide 230b. Also, in the metal oxide used for the oxide 230c, the atomic ratio of the element M to In is preferably larger than the atomic ratio of the element M to In in the metal oxide used for the oxide 230b. Further, in the metal oxide used for the oxide 230b, the atomic ratio of In to the element M is preferably larger than the atomic ratio of In to the element M in the metal oxide used for the oxide 230c.

[0216] Also, when the oxide 230c has a laminated structure including the oxide 230c1 and the oxide 230c2 on the oxide 230c1, it is preferable that the lower end of the conduction band of the oxide 230a and the oxide 230c2 is closer to the vacuum level than the lower end of the conduction band of the oxide 230b and the oxide 230c1. In other words, it is preferable that the electron affinity of the oxide 230a and the oxide 230c2 is smaller than the electron affinity of the oxide 230b and the oxide 230c1. In this case, it is preferable that the oxide 230c2 uses a metal oxide that can be used for the oxide 230a, and the oxide 230c1 uses a metal oxide that can be used for the oxide 230b.

[0217] Here, at the junctions of oxide 230a, oxide 230b, and oxide 230c, In other words, the oxide 230a, the oxide 230b, and The conduction band edge at the junction of the oxide 230c and the junction of the oxide 230c changes continuously or is called a continuous junction. In order to achieve this, the interface between the oxide 230a and the oxide 230b must be , and the defect levels of the mixed layer formed at the interface between oxide 230b and oxide 230c. It is better to reduce the density.

[0218] Specifically, oxide 230a and oxide 230b, and oxide 230b and oxide 230c, By having a common element other than oxygen (as the main component), a mixed layer with a low defect level density is formed. For example, when the oxide 230b is an In-Ga-Zn oxide, the oxide The material 230a and the oxide 230c are In-Ga-Zn oxide, Ga-Zn oxide, Gallium oxide may be used. In addition, the oxide 230c may be a mixture of the oxide 230c1 and the oxide In the case of forming a laminated structure with 230c2, for example, In-Ga-Zn oxide and the In-G A laminated structure of Ga-Zn oxide on a-Zn oxide, or In-Ga-Zn oxide and A laminated structure of gallium oxide on the In-Ga-Zn oxide can be used. Then, the laminated structure of the In-Ga-Zn oxide and the oxide not containing In was formed by the oxide 23 It may also be used as 0c.

[0219] Specifically, the oxide 230a is In:Ga:Zn=1:3:4 [atomic ratio], Alternatively, a metal oxide having an atomic ratio of In:Ga:Zn=1:1:0.5 may be used. , as the oxide 230b, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] or In:G a:Zn = 3:1:2 [atomic ratio] may be used. Also, as the oxide 230c , a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio], In:Ga:Zn = 4:2:3 [atomic ratio], Ga:Zn = 2:1 [atomic ratio], or Ga:Zn = 2:5 [atomic ratio] may be used. Also, as a specific example when the oxide 230c has a laminated structure , examples include a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and In:Ga:Zn = 1:3:4 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga:Zn = 2:1 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and Ga :Zn = 2:5 [atomic ratio], a laminated structure of In:Ga:Zn = 4:2:3 [atomic ratio] and gallium oxide, etc.

[0220] At this time, the main path of carriers becomes the oxide 230b or the oxide 230c. Or when the oxide 230c has a laminated structure including the oxide 230c1 and the oxide 230c2 , not only the oxide 230b but also the oxide 230c1 may become the main path of carriers . By configuring the oxide 230a and the oxide 230c as described above, at the interface between the oxide 23 0a and the oxide 230b, and at the interface between the oxide 230b and the oxide 230c , the density of defect energy levels can be reduced. Therefore, the influence of interface scattering on carrier conduction becomes small, and the transistor 200 can obtain a high on-current and high frequency characteristics . Note that when the oxide 230c has a laminated structure, the above-mentioned oxide 230b and gallium oxide . In addition to the effect of reducing the density of defect levels at the interface with the object 230c, it is expected that the constituent elements of the oxide 230c are suppressed from diffusing toward the insulator 250 side. More specifically, since the oxide 230c has a laminated structure and an oxide containing no In is positioned above the laminated structure, it is possible to suppress the diffusion of In toward the insulator 250 side. Since the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250 or the like, the characteristics of the transistor will deteriorate. Therefore, by forming the oxide 230c into a laminated structure, it becomes possible to provide a highly reliable semiconductor device.

[0221] As the oxide 230, it is preferable to use a metal oxide that functions as a semiconductor. For example, as the metal oxide that becomes the region 234, those having a band gap of 2 eV or more, preferably 2.5 eV or more are preferably used. By using such a metal oxide having a large band gap, the off-current of the transistor can be reduced. By using such a transistor, a semiconductor device with low power consumption can be provided.

[0222] Note that the films of the oxide 230a, the oxide 230b, and the oxide 230c can be formed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. Note that when forming a film using the sputtering method, it is preferable to use oxygen or a mixed gas of oxygen and a rare gas as the sputtering gas. Also, by performing film formation while heating the substrate, the crystallinity of the oxide film can be improved.

[0223] In this embodiment, as the oxide 230a, for example, In:Ga:Zn = 1:3:4 ​​​​​​​A film is formed by sputtering using an In-Ga-Zn oxide target with an atomic ratio. The resulting metal oxide can be used. Also, as the oxide 230b, for example, In: Ga:Zn = 4:2:4.1 [atomic ratio] of an In-Ga-Zn oxide target can be used to form a film by sputtering. Also, as the oxide 2 30c1, for example, In:Ga:Zn = 4:2:4.1 [atomic ratio] of an In-Ga -Zn oxide target can be used to form a film by sputtering and the resulting metal oxide can be used. Also, as the oxide 230c2, for example, In:Ga:Zn = 1:3: 4 [atomic ratio] of an In-Ga-Zn oxide target can be used to form a film by sputtering and the resulting metal oxide can be used.

[0224] On the oxide 230b, conductors 242 (conductor 242a and conductor 242b) that function as source electrodes and drain electrodes are provided. The film thickness of the conductor 242 is, for example, 1 nm or more and 50 nm or less, preferably 2 nm or more and 25 nm or less.

[0225] As the conductor 242, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, or an alloy containing the above-described metal elements as components, or an alloy combining the above-described metal elements, etc. is preferably used. For example, titanium nitride, tantalum nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum Nitrides containing minium, ruthenium oxide, ruthenium nitride, strontium and ruthenium It is preferable to use oxides containing , oxides containing lanthanum and nickel, etc. Also, nit Tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum Nitrides, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium Oxides, oxides containing lanthanum and nickel are preferable because they are conductive materials that are difficult to oxidize or materials that maintain conductivity even when they absorb oxygen

[0226] Note that the film formation of the conductor 242 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A LD method, etc. In the present embodiment, for example, Tantalum nitride formed by a sputtering method can be used as the conductor 242.

[0227] The insulator 254 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side into the transistor 200, similar to the insulator 214 etc. For example, it is preferable that the insulator 254 has lower hydrogen permeability than the insulator 224. Furthermore, as shown in FIG. 11(B), the insulator 254 preferably contacts the upper surface and side surfaces of the conductor 242a, the upper surface and side surfaces of the conductor 242b, the side surfaces of the oxides 230a and 230b, and also the side surface of the insulator 224. With such a configuration, the insulator 280 is separated from the insulator 224 and the oxides 230 by the insulator 254 . Thereby, the hydrogen contained in the insulator 280 diffuses from the upper surface or side surfaces of the conductor 242a, the conductor 242b, the oxides 230a, the oxides 230b, and the insulator 224 to the oxides 230 ​​​​Since diffusion can be suppressed, good electrical characteristics and reliability can be imparted to the transistor 200. Sex can be given.

[0228] Furthermore, the insulator 254 preferably has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (The above oxygen is difficult to permeate.) For example, the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224. Diffusion suppression function (the above oxygen is difficult to permeate). For example, the insulator 254 preferably has lower oxygen permeability than the insulator 280 or the insulator 224. Insulator 254 preferably has lower oxygen permeability than insulator 280 or insulator 224.

[0229] The insulator 254 is preferably formed by a sputtering method. By forming the insulator 254 by using the sputtering method in an atmosphere containing oxygen, oxygen can be added in the vicinity of the region where the insulator 254 is in contact with the insulator 224. Thereby, oxygen can be supplied from the said area | region into the oxide 230 through the insulator 224. Here, since the insulator 254 has a function of suppressing the upward diffusion of oxygen, oxygen can be prevented from diffusing from the oxide 230 to the insulator 280. In addition, since the insulator 222 has a function of suppressing the downward diffusion of oxygen, oxygen can be prevented from diffusing from the oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the oxide 230. Thereby, the oxygen deficiency of the oxide 230 can be reduced, and the normal ionization of the transistor can be suppressed. Insulator 254 is formed by sputtering in an oxygen-containing atmosphere, and oxygen can be added in the vicinity of the region where insulator 254 contacts insulator 224. Thereby, oxygen can be supplied from the said area | region into the oxide 230 through the insulator 224. In this way, oxygen can be supplied from the said area | region into the oxide 230 through the insulator 224. Here, since the insulator 254 has a function of suppressing the upward diffusion of oxygen, oxygen can be prevented from diffusing from the oxide 230 to the insulator 280. Insulator 254 has a function of suppressing the upward diffusion of oxygen, preventing oxygen from diffusing from oxide 230 to insulator 280. In addition, since the insulator 222 has a function of suppressing the downward diffusion of oxygen, oxygen can be prevented from diffusing from the oxide 230 to the substrate side. Insulator 222 has a function of suppressing the downward diffusion of oxygen, preventing oxygen from diffusing from oxide 230 to the substrate side. In this way, oxygen is supplied to the channel formation region of the oxide 230. Thereby, the oxygen deficiency of the oxide 230 can be reduced, and the normal ionization of the transistor can be suppressed. Suppression can be achieved.

[0230] As the insulator 254, for example, an insulator containing one or both of aluminum oxide and hafnium oxide may be formed. Note that, as the insulator containing one or both of aluminum oxide and hafnium oxide, aluminum oxide, hafnium oxide, aluminum and One or both of hafnium oxides may be used. As the insulator containing one or both of aluminum oxide and hafnium oxide, aluminum oxide, hafnium oxide, aluminum and It is preferable to use an oxide containing yttrium and hafnium (hafnium aluminate), etc. In this case, the insulator 254 is preferably formed by ALD method. The ALD method is a film forming method with good coverage, so steps or the like are not formed due to the unevenness of the insulator 254. This can be prevented.

[0231] In this way, by covering the insulator 224 and the oxide 230 with the insulator 254 having a barrier property against hydrogen, the insulator 280 is separated from the insulator 224 and the oxide 230. As a result, the entry of impurities such as hydrogen from the outside of the transistor 200 can be suppressed, so that good electrical characteristics and reliability can be given to the transistor 200.

[0232] Further, as the insulator 254, for example, an insulator containing aluminum nitride may be used. As the insulator 254, it is preferable to use a nitride insulator whose composition formula satisfies AlNx (x is a real number greater than 0 and less than or equal to 2, preferably x is a real number greater than 0.5 and less than or equal to 1.5). Thereby, a film excellent in insulation and heat conductivity can be obtained, so that the heat dissipation property of the heat generated when the transistor 200 is driven can be improved. Further, as the insulator 254, aluminum titanium nitride, titanium nitride, etc. can also be used. In this case, by forming a film using a sputtering method, a film can be formed without using a gas having strong oxidizing properties such as oxygen or ozone in the film forming gas, so it is preferable. Also, silicon nitride or nitrided silicon oxide, etc. can also be used.

[0233] Further, the insulator 254 can have a multilayer structure of two or more layers. For example, the insulator 25 ​​​​​​​As 4, the first layer is formed by sputtering in an oxygen-containing atmosphere, and then the second layer is formed using the ALD method It may have a two-layer structure. Since the ALD method is a film-forming method with good coverage , it is possible to prevent the formation of steps or the like due to the unevenness of the first layer. When the insulator 254 has a multi-layer structure of two or more layers, it may have a multi-layer structure made of different materials . For example, a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride and an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen may be used . Further, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, for example, an insulator containing an oxide of one or both of aluminum and hafnium may be used . The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c . The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. In particular, silicon oxide and silicon oxynitride are preferred because they are stable to heat .

[0234] The insulator 250 functions as a gate insulator. The insulator 250 is preferably disposed in contact with the upper surface of the oxide 230c . The insulator 250 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, etc. In particular, silicon oxide and silicon oxynitride are preferred because they are stable to heat . . . .

[0235] Similar to the insulator 224, the insulator 250 is preferably formed using an insulator that releases oxygen upon heating . By providing an insulator that releases oxygen upon heating as the insulator 250 in contact with the upper surface of the oxide 230c, oxygen can be effectively supplied to the region 234 of the oxide 230b . Also, similar to the insulator 224, water and water in the insulator 250 . It is preferable that the impurity concentration such as the substrate is reduced. The film thickness of the insulator 250 is preferably 1 nm or more and 20 nm or less.

[0236] Note that the film formation of the insulator 250 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. In the present embodiment, as the insulator 250, for example, silicon oxynitride formed by a CVD method can be used.

[0237] Further, a metal oxide may be provided between the insulator 250 and the conductor 260. The metal oxide preferably suppresses the diffusion of oxygen from the insulator 250 to the conductor 260. By providing a metal oxide that suppresses the diffusion of oxygen, the diffusion of oxygen from the insulator 250 to the conductor 260 is suppressed. That is, it is possible to suppress a decrease in the amount of oxygen supplied to the oxide 230. Further, oxidation of the conductor 260 by oxygen in the insulator 250 can be suppressed.

[0238] Note that the metal oxide may have a function as a part of the gate insulator. Therefore, when silicon oxide, silicon oxynitride, or the like is used for the insulator 250, it is preferable to use a metal oxide which is a high-k material having a high relative dielectric constant as the metal oxide. By forming the gate insulator into a laminated structure of the insulator 250 and the metal oxide, a laminated structure that is stable against heat and has a high relative dielectric constant can be obtained. Therefore, it is possible to reduce the gate potential applied during transistor operation while maintaining the physical film thickness of the gate insulator. Further, it is possible to reduce the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator.

[0239] ​​​​​​​​​​​​In addition, the metal oxide may function as part of the first gate. For example, An oxide semiconductor that can be used as the oxide 230 can be used as the metal oxide. In that case, by forming the conductor 260 by sputtering, the electrical resistance value of the metal oxide can be reduced to make it a conductor. This can be called an OC (Oxide Conductor) electrode.

[0240] By having the metal oxide, it is possible to improve the on-current of the transistor 200 without weakening the influence of the electric field from the conductor 260. Also, by maintaining the distance between the conductor 260 and the oxide 230 based on the physical thickness of the insulator 250 and the metal oxide, the leakage current between the conductor 260 and the oxide 230 can be suppressed. Further, by providing a laminated structure of the insulator 250 and the metal oxide, the physical distance between the conductor 260 and the oxide 230 and the electric field strength applied from the conductor 260 to the oxide 230 can be easily adjusted as appropriate.

[0241] Specifically, a metal oxide containing one or more selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, magnesium, etc. can be used. In particular, it is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., which are insulators containing one or both of aluminum and hafnium oxides. Also, by reducing the resistance of the oxide semiconductor that can be used for the oxide 230, it can be used as the metal oxide. ​

[0242] Although the conductor 260 is shown as a two-layer structure in FIG. 11, it may be a single-layer structure or a laminated structure of three or more layers. It may be a laminated structure of five or more layers.

[0243] The conductor 260a preferably uses a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as N2O, NO, NO2), and copper atoms. Or, it is preferable to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.). (N2O, NO, NO2, etc.), copper atoms, etc. In addition, by having the function of suppressing the diffusion of oxygen, the conductor 260a can suppress the oxidation of the conductor 260b by oxygen contained in the insulator 250 and the decrease in conductivity. As the conductive material having the function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. It can be done.

[0244] In addition, since the conductor 260a has the function of suppressing the diffusion of oxygen, it is possible to suppress the oxidation of the conductor 260b by oxygen contained in the insulator 250 and the decrease in conductivity. As the conductive material having the function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. It can be suppressed that the conductor 260b is oxidized by oxygen contained in the insulator 250 and the conductivity decreases. As the conductive material having the function of suppressing the diffusion of oxygen, for example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. For example, it is preferable to use tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. It can be done.

[0245] In addition, since the conductor 260 also functions as a wiring, it is preferable to use a conductor having high conductivity. For example, the conductor 260b can use a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material may be used. For example, the conductor 260b can use a conductive material mainly composed of tungsten, copper, or aluminum. It can be done. In addition, the conductor 260b may have a laminated structure, for example, a laminated structure of titanium, titanium nitride, and the above conductive material may be used.

[0246] Note that the film formation of the conductor 260 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In this embodiment, for example, titanium nitride formed by a CVD method is used as the conductor 260a, and for example, C In this embodiment, for example, titanium nitride formed by a CVD method is used as the conductor 260a, and for example, C For example, titanium nitride formed by a CVD method is used as the conductor 260a, and for example, C Titanium nitride formed by the VD method can be used.

[0247] The insulator 280 is provided on the insulator 222, the insulator 224, the oxide 230, and the conductor 242 via the insulator 254. For example, as the insulator 280, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, etc. are preferably used. In particular, silicon oxide and silicon oxynitride are preferable because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferable because they can easily form a region containing oxygen that desorbs by heating.

[0248] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. Also, the upper surface of the insulator 280 may be planarized.

[0249] Note that the film formation of the insulator 280 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. In the present embodiment, as the insulator 280, for example, silicon oxynitride formed by the CVD method can be used.

[0250] The insulator 274 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from above to the insulator 280, similar to the insulator 214. As the insulator 274, for example, an insulator that can be used for the insulator 214, the insulator 254, etc. can be used.

[0251] Note that the film formation of the insulator 274 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A LD method, etc. In this embodiment, as the insulator 274, for example, , aluminum oxide formed by a sputtering method can be used.

[0252] Also, it is preferable to provide an insulator 281 that functions as an interlayer film on the insulator 274. Similar to the insulator 224, etc., the insulator 281 preferably has a reduced concentration of impurities such as water and hydrogen in the film.

[0253] Note that the film formation of the insulator 281 can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an A LD method, etc. In this embodiment, as the insulator 281, for example, , silicon nitride formed by a CVD method can be used.

[0254] Also, conductors 240a and 240b are arranged in the openings formed in the insulator 281, the insulator 274, the insulator 280, and the insulator 254. The conductors 240a and the conductors 240b are provided to face each other with the conductor 260 interposed therebetween. Note that the height of the upper surfaces of the conductors 240a and the conductors 240b may be on the same plane as the upper surface of the insulator 281.

[0255] Note that an insulator 241a is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a first conductor of the conductor 240a is formed in contact with the side surface thereof. At least a part of the bottom of the opening has the conductor 242a located therein , and the conductor 240a is in contact with the conductor 242a. Similarly, an insulator 241b is provided in contact with the side walls of the openings of the insulator 281, the insulator 274, the insulator 280, and the insulator 254, and a second conductor of the conductor 240b is formed in contact with the side surface thereof. At least a part of the bottom of the opening has the conductor 242b located therein , and the conductor 240b is in contact with the conductor 242b. ​ A first conductor of the conductor 240b is formed in contact with the side surface of it. At least a part of the bottom of the opening has the conductor 242b located therein, and the conductor 240b is in contact with the conductor 242b.

[0256] The conductor 240a and the conductor 240b are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum. Also, the conductor 240a and the conductor 240b may have a laminated

[0257] structure. When the conductor 240 has a laminated structure, the conductor in contact with the oxide 230a, the oxide 230b, the conductor 242, the insulator 254, the insulator 280, the insulator 274, and the insulator 281 is preferably made of a conductive material having a function of suppressing the permeation of impurities such as water and hydrogen. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, etc. Also, the conductive material having a function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or

[0258] laminated. By using such a conductive material, it is possible to prevent oxygen added to the insulator 280 from being absorbed by the conductor 240a and the conductor 240b. Also, it is possible to Diffusion through the 240a and the conductor 240b into the oxide 230 can be suppressed. In addition, oxygen contained in the insulator 280 can be prevented from being absorbed by the conductor 240a and the conductor 240b. Note that, for the formation of the insulator 241a and the insulator 241b, ALD method or CVD method can be used.

[0259] Although not shown, conductors functioning as wirings may be arranged in contact with the upper surface of the conductor 240a and the upper surface of the conductor 240b. As the conductor functioning as a wiring, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. Further, the conductor may have a laminated structure, for example, a laminate of titanium, titanium nitride, and the above conductive material. Note that the conductor may be formed so as to be embedded in an opening provided in an insulator.

[0260] Although not shown, an insulator having a resistivity of 1.0×10 13 Ωcm or more 1.0×10 15 Ωcm or less, preferably 5.0×10 13 Ωcm or more and 5.0×10 14 Ωcm or less is preferably provided so as to cover the above conductor. By providing an insulator having the above resistivity on the above conductor, while maintaining the insulation property, the insulator can disperse charges accumulated between wirings such as the transistor 200 and the above conductor, and suppress characteristic deterioration and electrostatic breakdown of the transistor and an electronic device having the transistor, which is preferable.

[0261] As described above, according to one aspect of the present invention, a semiconductor device with a large on-current can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device having high frequency characteristics can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device with good reliability can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device with a small off-current can be provided. It is possible. Further, according to one aspect of the present invention, a semiconductor device with reduced power consumption can be provided. It is possible. Further, according to one aspect of the present invention, a highly productive semiconductor device can be provided. It is possible.

[0262] <Constituent Materials of Semiconductor Device> Hereinafter, the constituent materials that can be used in the semiconductor device will be described.

[0263] The film formation of the constituent materials shown below can be performed using a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, etc. It can be performed using methods such as a sputtering method, a CVD method, an MBE method, a PLD method, and an ALD method.

[0264] Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, etc. Further, depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method. Note that the CVD method can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, etc. Further, depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method. It can be classified into a plasma CVD (PECVD: Plasma Enhanced CVD) method that uses plasma, a thermal CVD (TCVD: Thermal CVD) method that uses heat, a photo CVD method that uses light, etc. Further, depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method. Depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method. Depending on the raw material gas used, it can be divided into a metal CVD (MCVD: Metal CVD) method and a metal organic CVD (MOCVD: Metal Organic CVD) method.

[0265] The plasma CVD method can obtain a high-quality film at a relatively low temperature. Also, the thermal CVD method, the plasma Since it does not use plasma, it is a film-forming method capable of suppressing plasma damage to the object to be processed. For example, wirings, electrodes, elements (such as transistors and capacitor elements) included in a semiconductor device may be charged up by receiving charges from plasma. At this time, the wirings, electrodes, elements, etc. included in the semiconductor device may be damaged by the accumulated charges. On the other hand, in the case of the thermal CVD method that does not use plasma, such plasma damage does not occur. Therefore, the yield of the semiconductor device can be increased. Also, in the thermal CVD method, since plasma damage does not occur during film formation, a film with few defects can be obtained.

[0266] Also, the ALD method is a film-forming method capable of suppressing plasma damage to the object to be processed. Therefore, a film with few defects can be obtained. Note that some of the precursors used in the ALD method contain impurities such as carbon. For this reason, the film formed by the ALD method may contain more impurities such as carbon compared to the film formed by other film-forming methods. Note that the quantification of impurities can be performed using X-ray photoelectron spectroscopy (XPS). ectroscopy)

[0267] The CVD method and the ALD method are different from film-forming methods in which particles emitted from a target or the like are deposited, and are film-forming methods in which a film is formed by a reaction on the surface of the object to be processed. Therefore, it is less affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and is suitable for covering the surface of an opening with a high aspect ratio, for example. However, the ALD method has a relatively low film formation rate. ​​Because of the slow speed, it may be preferable to use it in combination with other film-forming methods such as CVD method with a high film-forming speed. There are also cases where it is preferable.

[0268] The CVD method and the ALD method can control the composition of the obtained film by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film with an arbitrary composition can be formed by the flow rate ratio of the source gases. Also, for example, in the CVD method and the ALD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required. Therefore, there are cases where the productivity of semiconductor devices can be increased. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required. Therefore, there are cases where the productivity of semiconductor devices can be increased. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required. Therefore, there are cases where the productivity of semiconductor devices can be increased. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required. Therefore, there are cases where the productivity of semiconductor devices can be increased. When forming a film while changing the flow rate ratio of the source gases, compared with the case of forming a film using a plurality of film-forming chambers, the time required for film formation can be shortened because the time required for transfer and pressure adjustment is not required. Therefore, there are cases where the productivity of semiconductor devices can be increased. There are also cases where it is preferable.

[0269] Also, the processing of the constituent material may be performed using a lithography method. Also, dry etching method or wet etching method can be used for the processing. The processing by the dry etching method is suitable for microfabrication. Also, the processing of the constituent material may be performed using a lithography method. Also, dry etching method or wet etching method can be used for the processing. The processing by the dry etching method is suitable for microfabrication. Also, the processing of the constituent material may be performed using a lithography method. Also, dry etching method or wet etching method can be used for the processing. The processing by the dry etching method is suitable for microfabrication.

[0270] In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. In the lithography method, first, the resist is exposed through a mask. Next, the exposed area is removed or left using a developer to form a resist mask. Next, by performing an etching process through the resist mask, conductors, semiconductors, insulators, etc. can be processed into a desired shape. For example, a resist mask may be formed by exposing the resist using KrF excimer laser light, ArF excimer laser light, EUV (Extreme Ultraviolet) light, etc. Also, a liquid may be placed between the substrate and the projection lens. It may be possible to use immersion technology, such as filling with (for example, water) and then performing exposure. Also, instead of the light described above, , an electron beam or an ion beam may be used. When using an electron beam or an ion beam, since direct drawing is performed on the resist, the above-mentioned mask for resist exposure becomes unnecessary. The resist mask can be removed by, for example, performing dry etching such as ashing, performing wet etching, performing wet etching after dry etching, or performing dry etching after wet etching.

[0271] Alternatively, a hard mask made of an insulator or a conductor may be used instead of the resist mask. When using a hard mask, an insulating film or a conductive film serving as the hard mask material is formed on the said constituent material, a resist mask is formed thereon, and a hard mask having a desired shape can be formed by etching the hard mask material. Etching of the said constituent material may be performed after removing the resist mask, or may be performed with the resist mask remaining. In the latter case, the resist mask may disappear during etching. The hard mask may be removed by etching after etching of the said constituent material. On the other hand, when the material of the hard mask has no influence on the subsequent process or can be used in the subsequent process, it is not always necessary to remove the hard mask.

[0272] As the dry etching apparatus, a capacitively coupled plasma (CCP : Capacitively Coupled Plasma) etching apparatus having parallel plate electrodes can be used. A capacitively coupled plasma etching apparatus having parallel plate electrodes is a parallel plate A configuration in which a high-frequency power source is applied to one of the electrodes of the type electrode may also be used. Or one of the parallel plate electrodes A configuration in which a plurality of different high-frequency power sources are applied to the electrode may also be used. Or the parallel plate electrodes themselves A configuration in which high-frequency power sources of the same frequency are applied to each of them may also be used. Or each of the parallel plate electrodes A configuration in which high-frequency power sources of different frequencies are applied may also be used. Or a dry etching apparatus having a high-density plasma source can be used. A dry etching apparatus having a high-density plasma source For example, an inductively coupled plasma (ICP) etching apparatus or the like can be used.

[0273] <<Substrate>> As the substrate on which the transistor 200 is formed, for example, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used. Examples of the insulator substrate include a glass substrate, a quartz substrate, a s apphire substrate, a stabilized zirconia substrate (such as yttria-stabilized zirconia substrate), a resin substrate and the like. Examples of the semiconductor substrate include semiconductor substrates such as silicon and germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide , zinc oxide, and gallium oxide. Further, semiconductor substrates having an insulator region inside the aforementioned semiconductor substrates, for example, SOI (Silicon On Insulator) substrates and the like. Examples of the conductor substrate include a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate. Or a substrate having a metal nitride, a substrate having a metal oxide and the like. Further, a substrate in which a conductor or a semiconductor is provided on an insulator substrate, a substrate in which a conductor or an insulator is provided on a semiconductor substrate, a substrate in which a semiconductor or an insulator is provided on a conductor substrate ​​There is a provided substrate or the like. Alternatively, those in which elements are provided on these substrates may also be used. Examples of the elements provided on the substrate include a capacitive element, a resistive element, a switching element, a light-emitting element, a memory element, etc.

[0274] <<Insulator>> Examples of the insulator include oxides, nitrides, oxynitrides, nitroxides, metal oxides, metal oxynitrides, metal nitroxides, etc. having insulating properties.

[0275] For example, as the miniaturization and high integration of transistors progress, problems such as leakage current may occur due to the thinning of the gate insulator. By using a high-k material for the insulator that functions as the gate insulator, it becomes possible to reduce the operating voltage of the transistor while maintaining the physical film thickness. On the other hand, for the insulator that functions as the interlayer film, by using a material with a low relative permittivity, the parasitic capacitance generated between the wirings can be reduced. Therefore, it is advisable to select the material according to the function of the insulator.

[0276] Examples of the insulator with a high relative permittivity include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium, etc.

[0277] Examples of the insulator with a low relative permittivity include silicon oxide, silicon oxynitride, silicon nitroxide, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, or resin, etc. ​​​​​​​​​​​​be.

[0278] In addition, a transistor using an oxide semiconductor can suppress the permeation of impurities such as hydrogen and oxygen. Insulators having a function of controlling the temperature (insulator 214, insulator 222, insulator 254, and insulator By surrounding the transistor with a metal (such as 274), the electrical characteristics of the transistor can be stabilized. Examples of insulators that have the function of suppressing the permeation of impurities such as hydrogen and oxygen include HO. Uranium, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium Insulators including titanium, hafnium, or tantalum may be used in single or multilayer configurations. Specifically, the following insulators have the function of suppressing the permeation of impurities such as hydrogen and oxygen: Aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide tungsten oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, or thorium oxide Metal oxides such as tantalum, aluminum nitride, aluminum titanium nitride, titanium nitride, and nitrogen Metal nitrides such as silicon oxide or silicon nitride can be used.

[0279] In addition, the insulator that functions as the gate insulator has a region that contains oxygen that is desorbed by heating. For example, it is preferable that the insulating material has a region containing oxygen that is desorbed by heating. By forming a structure in which silicon oxide or silicon oxynitride is in contact with the oxide 230, The oxygen deficiency of 230 can be compensated for.

[0280] <<Conductors>> Conductive materials include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, and titanium. Tantalum, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium Sodium, zirconium, beryllium, indium, ruthenium, iridium, strontium A metal element selected from the above, or an alloy containing the above metal element as a component , or an alloy combining the above metal elements is preferably used. For example, tantalum nitride , titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium , an oxide containing lanthanum and nickel, etc. are preferably used. Also, tantalum nitride , titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum , ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium , an oxide containing lanthanum and nickel are preferred because they are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when absorbing oxygen . Also, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus , or a silicide such as nickel silicide may be used.

[0281] Also, a plurality of conductive layers formed of the above materials may be laminated and used. For example, a laminated structure combining the above material containing a metal element and a conductive material containing oxygen may be used . Also, a laminated structure combining the above material containing a metal element and a conductive material containing nitrogen may be used . Also, a laminated structure combining the above material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used . Also, a laminated structure combining the above material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used .

[0282] ​In the case of using an oxide in the channel formation region of a transistor, between the gate electrode and the conductor functioning as [the gate electrode], it is preferable to use a laminated structure formed by combining the material containing the above-described metal element and a conductive material containing oxygen. In this case, the conductive material containing oxygen may be provided on the channel formation region side. By providing the

[0283] conductive material containing oxygen on the channel formation region side, oxygen detached from the conductive material is easily supplied to the channel formation region. Particularly, as the conductor functioning as the gate electrode, it is preferable to use a conductive material containing the metal element and oxygen contained in the metal oxide in which the channel is formed. Further, the conductive material containing the above-described metal element and nitrogen may be used. For example, a conductive material containing nitrogen such as titanium nitride or tantalum nitride may be used. Further, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing

[0284] <<Metal Oxide>> As the oxide 230, it is preferable to use a metal oxide functioning as an oxide semiconductor. Hereinafter, the metal oxide applicable to the oxide 230

[0285] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition to these, it is preferable that aluminum, gallium, yttrium, tin, etc. are included. Further, one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. may be included. Here, consider the case where the metal oxide is an In-M-Zn oxide having indium, element M, and zinc. Note that element M is aluminum, gallium, yttrium, or tin, etc. Elements applicable to other element Ms include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc. However, as element M, there may be cases where a plurality of the aforementioned elements may be combined. In addition, in this specification, etc., a metal oxide having nitrogen may also be collectively referred to as a metal oxide. Further, a metal oxide having nitrogen may be referred to as a metal oxynitride. [Structure of Metal Oxide] The oxide semiconductor (metal oxide) is divided into a single crystal oxide semiconductor and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS, polycrystalline oxide semiconductor, nc-OS, a-like OS, and amorphous oxide semiconductor.

[0286]

[0287]

[0288] ​

[0289] CAAC-OS has a c-axis orientation and multiple nanocrystals are connected in the ab-plane direction. The nanocrystals are connected together to form a distorted crystal structure. In a region, a lattice arrangement is formed between a region having a uniform lattice arrangement and another region having a uniform lattice arrangement. This refers to the point where the direction of the

[0290] Nanocrystals are basically hexagonal, but are not limited to regular hexagons and may have non-regular hexagonal shapes. In addition, the distortion may have lattice arrangements such as pentagons and heptagons. In addition, in the CAAC-OS, clear grain boundaries (grain bows) were observed even in the vicinity of the strain. It is difficult to confirm the presence of the lattice distortion. This is because the CAAC-OS has ab-plane orientation. In the case of the SiO2, the arrangement of oxygen atoms is not dense, and the bond distance between atoms is reduced by the substitution of metal elements. This is because distortion can be tolerated due to changes in the distance, etc.

[0291] CAAC-OS is a highly crystalline metal oxide. Since it is difficult to confirm the grain boundaries, the decrease in electron mobility caused by the grain boundaries is unlikely to occur. In addition, the crystallinity of metal oxides is reduced by the incorporation of impurities and the generation of defects. Therefore, CAAC-OS is designed to prevent impurities and defects (oxygen vacancies (V O :oxygen v It can also be said to be a metal oxide with low acancy. Metal oxides with CAAC-OS have stable physical properties. The metal oxides used are heat resistant and highly reliable.

[0292] Here, FIG. 13(A) shows a high-resolution TEM image of the cross-section of C AAC-OS observed by TEM from a direction approximately parallel to the sample surface. For the observation of the high-resolution TEM image, a spherical aberration correction function was used. The high-resolution TEM image of the cross-section of C AAC-OS is shown. For the observation of the high-resolution TEM image, a spherical aberration correction (Spherical Aberration Corrector) function was used. The high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be observed, for example, with a JEOL JEM-ARM200F atomic-resolution analytical electron microscope.

[0293] From FIG. 13(A), nanocrystals, which are regions where metal atoms are arranged in layers, can be confirmed. It can be seen that the size of one nanocrystal is 1 nm or more, or 3 nm or more. The nanocrystals reflect the unevenness of the formed surface or the upper surface of CAAC-OS and are parallel to the formed surface or the upper surface of CAAC-OS.

[0294] Also, FIGS. 13(B) and 13(C) show Cs-corrected high-resolution TEM images of the plane of CAAC-OS observed from a direction approximately perpendicular to the sample surface. FIGS. 13(D) and 13(E) are images obtained by image processing of FIGS. 13(B) and 13(C), respectively. Hereinafter, the method of image processing will be described. First, FIG. 13(B) is subjected to fast Fourier transform (FFT) processing to obtain an FFT image. Next, in the obtained FFT image, a masking process is performed to leave the range between 2.8 nm and 5.0 nm with the origin as a reference. Next, the masked FFT image is subjected to inverse fast Fourier transform (IFF -1 -1 ​​​​​​​​​​​obtained by performing an inverse fast Fourier transform (IFFT) process An image obtained by image processing is acquired. The image thus obtained is referred to as an FFT filtering image. FF The FFT filtering image is an image obtained by extracting periodic components from a Cs-corrected high-resolution TEM image and shows a lattice array.

[0295] In FIG. 13(D), the disrupted portions of the lattice array are indicated by broken lines. The region surrounded by the broken lines is a single nanocrystal. And the portions indicated by the broken lines are the connection parts between the nanocrystals There is. Since the broken line is hexagonal, it can be seen that the nanocrystal is hexagonal. In this way CAAC-OS shows hexagonal lattice points when observed by TEM in the c-axis direction. Therefore, CAAC-OS has the layered crystal structure shown in FIG. 1(C) in the previous embodiment. Note that the shape of the nanocrystal is not necessarily a regular hexagon and may be a non- regular hexagon.

[0296] In FIG. 13(E), the locations where the orientation of the lattice array changes between a region with an aligned lattice array and another region with an aligned lattice array are indicated by dotted lines, and the change in the orientation of the lattice array is indicated by broken lines . Even in the vicinity of the dotted line, no clear grain boundary can be confirmed. Connecting the surrounding lattice points centered on the lattice points near the dotted line can form distorted hexagons, pentagons, heptagons, etc . That is, it can be seen that the formation of grain boundaries is suppressed by distorting the lattice array. This is considered to be because CAAC-OS can tolerate strain due to the non-dense arrangement of oxygen atoms in the a-b plane direction and the change in the interatomic bond distance due to the substitution of metal elements .

[0297] ​​​​ In addition, FIG. 14(A) shows a high-resolution TEM image of the cross section of CAAC-OS different from that in FIG. 13. FIG. 14(B) is a high-resolution TEM image of the cross section obtained by further magnifying FIG. 14(A), and the atomic arrangement is highlighted for easy understanding.

[0298] FIG. 14(C) is a local Fourier transform image of the region (diameter: about 4 nm) surrounded by a circle between A-O-A' in FIG. 14(A). From FIG. 14(C), c-axis orientation can be confirmed in each region. Also, since the directions of the c-axis are different between A-O and O-A', it is suggested that they are different grains. Also, between A-O, the angle of the c-axis is 14.3°, 16. 6°, 26.4°, etc., and it can be seen that they change continuously little by little. Similarly, between O-A ', the angles of the c-axis are -18.3°, -17.6°, -15.9°, etc., and it can be seen that they change continuously little by little.

[0299] From the high-resolution TEM images of the cross section and the high-resolution TEM images of the plane, it can be seen that the nanocrystals of CAAC-OS have orientation.

[0300] From the above, as shown in the previous embodiments, CAAC-OS has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the surface to be formed of CAAC-OS or the film surface of CAAC-OS. Therefore, each layer of the metal atoms arranged in a layered manner confirmed by the above-described high-resolution TEM observation of the cross section is a plane parallel to the a-b plane of the nanocrystal.

[0301] nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, nc-OS has different nano No regularity is observed in the crystal orientation between the nano crystals. Therefore, no orientation is observed in the entire film. Thus, depending on the analysis method, nc-OS may not be distinguishable from a-like OS or amorphous oxide semiconductors in some cases.

[0302] Incidentally, indium-gallium-zinc oxide (hereinafter referred to as IGZO), which is a kind of metal oxide having indium, gallium, and zinc, may have a stable structure by forming the above-described nano crystals. In particular, since IGZO tends to be difficult to grow crystals in the air, a crystal smaller than a large crystal (here, a crystal of several mm or several cm), for example, the above-described nano crystal, may be structurally more stable.

[0303] a-like OS is a metal oxide having a structure between nc-OS and amorphous oxide semiconductors. a-like OS has a loose or low-density region. That is, a-like OS has lower crystallinity than nc-OS and CAAC-OS.

[0304] Oxide semiconductors (metal oxides) have various structures, each having different characteristics. The oxide semiconductor according to one embodiment of the present invention may have two or more of amorphous oxide semiconductors, polycrystalline oxide semiconductors, a-like OS, nc-OS, and CAAC-OS.

[0305] [Impurities] Here, the influence of each impurity in the metal oxide will be described.

[0306] When an alkali metal or an alkaline earth metal is contained in the metal oxide, defect levels may be formed and carriers may be generated. Therefore, when an alkali metal or an alkaline earth metal is contained, A transistor using a metal oxide in the channel formation region has normal-on characteristics and is likely to occur. Therefore, it is preferable to reduce the concentration of alkali metals or alkaline earth metals in the metal oxide . Specifically, the concentration of alkali metals or alkaline earth metals in the metal oxide obtained by secondary ion mass spectrometry (SIMS: Secondary y Ion Mass Spectrometry) (the concentration obtained by SIMS) is 1×10 or less, preferably 2×10 1 8 atoms / cm 3 or less. 16 atoms / cm 3

[0307] In addition, hydrogen contained in the metal oxide reacts with oxygen bonded to metal atoms to form water , and oxygen vacancies may be formed. When hydrogen enters the oxygen vacancies, carriers such as electrons may be generated. In addition, a part of hydrogen may bond with oxygen bonded to metal atoms to generate carriers such as electrons . Therefore, a transistor using a metal oxide containing hydrogen is likely to have normal-on characteristics .

[0308] Therefore, it is preferable that the hydrogen in the metal oxide is reduced as much as possible. Specifically , in the metal oxide, the hydrogen concentration obtained by SIMS is 1×10 20 atoms / cm 3 less than, preferably 1×10 19 atoms / cm 3 less than, more preferably 5×1 0 18 atoms / cm 3 less than, even more preferably 1×10 18 atoms / cm 3 less than ​Let it be. By using a metal oxide with sufficiently reduced impurities in the channel formation region of the transistor stable electrical characteristics can be imparted.

[0309] <Configuration Example 2 of Semiconductor Device> FIG. 15 is a top view and a cross-sectional view of the transistor 200A according to one aspect of the present invention, and the periphery of the transistor 200A is shown.

[0310] FIG. 15(A) is a top view of a semiconductor device having the transistor 200A. Also, FIGS. 15(B) and 15(C) are cross-sectional views of the semiconductor device. Here, FIG. 15(B) is a cross-sectional view of the part indicated by the dashed line A1 - A2 in FIG. 15(A), and is also a cross-sectional view in the channel length direction of the transistor 20 0A. Further, FIG. 15(C) is a cross-sectional view of the part indicated by the dashed line A3 - A4 in FIG. 15(A), and is also a cross-sectional view in the channel width direction of the transistor 200A sectional view. Note that in the top view of FIG. 15(A), some elements are omitted for clarity of the figure is shown.

[0311] Note that in the semiconductor device shown in FIG. 15, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> are marked with the same reference numerals. is shown.

[0312] Hereinafter, the configuration of the semiconductor device will be described with reference to FIG. 15. Note that in this section, as the constituent materials of the semiconductor device, the materials described in detail in <Configuration Example 1 of Semiconductor Device> can be used is shown.

[0313] [Transistor 200A] As shown in FIG. 15, the transistor 200A includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, and an insulator is shown. Insulator 222 disposed above 216 and above conductor 205, and disposed above insulator 222 Insulator 224, oxide 230 (oxide 230a , oxide 230b, oxide 230c1, and oxide 230c2) disposed above insulator 224, and above oxide 230 250 disposed thereon, conductor 260 (conductor 260a, and conductor 260b) disposed above insulator 250, conductors 242a and con ductor 242b in contact with a part of the upper surface of oxide 230b, barrier film 244a disposed above conductor 242a, and barrier film 244b disposed above conductor 242b, a part of the upper surface of insulator 222, the side surface of insulator 224 , the side surface of oxide 230a, the side surface of oxide 230b, the side surface of conductor 242a, the upper surface of barrier film 24 4a, the side surface of conductor 242b, and insulator 254 (insulator 254a, and insulator 254b) disposed in contact with the upper surface of barrier film 244b.

[0314] Insulator 254 has a structure in which two layers of insulator 254a and insulator 254b are laminated, and also, oxide 230 has a structure in which two layers of oxide 230c1 and oxide 230c2 are laminated, which is different from the aforementioned transistor 200. Hereinafter, the differences from transistor 200 will be described.

[0315] As shown in FIG. 15, insulator 254 has insulator 254a and insulator 254b disposed above insulator 254a. For example, insulator 254a preferably functions as a barrier film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side into transistor 200A. Further, for example, insulator 254b prevents oxygen in oxide 230 from diffusing into the insulator 280 side of transistor 200A. It is preferable to suppress the diffusion of the fluorine-containing gas toward the side of the insulating layer 280. This can prevent hydrogen from being mixed into the channel formation region of the oxide 230. In addition, it is possible to prevent oxygen from being released from the channel formation region of the oxide 230. The insulator 254a is made of silicon nitride formed by sputtering. The insulator 254b may be an aluminum oxide film formed by ALD.

[0316] For example, the insulator 254a may be an insulating material having an excess oxygen region or An insulating material that is prone to forming an excess oxygen region is used as the insulator 254b. It is preferable to use an insulating material that easily forms an oxygen region. The insulator 254a is a silicon oxide film formed by a sputtering method, and the insulator 254b is a In this case, an aluminum oxide film formed by sputtering may be used. By laminating two layers, the excess oxygen in the insulator 254a is converted into the oxide 230. can be efficiently supplied to

[0317] In addition, when the insulator 254a contains excess oxygen, a barrier layer is formed on the upper surface of the conductor 242a. A film 244a is provided on the upper surface of the conductor 242b, and a barrier film 244b is provided in contact with the upper surface of the conductor 242b. The barrier film 244a and the barrier film 244b are preferably formed to prevent impurities such as water and hydrogen, and The oxide 230c and the insulator 250 have a function of suppressing the permeation of oxygen. Prevent excess oxygen in the conductive material from diffusing into the conductive material 242a and the conductive material 242b. In other words, the excess oxygen in the surroundings is used to oxidize the conductors 242a and 242b. It can be prevented from occurring. Further, oxidation of the conductor 242a and the conductor 242b can prevent the increase in the electrical resistance values of the conductor 242a and the conductor 242b . The measurement of the electrical resistance value of the conductor can be performed using a two-terminal method or the like .

[0318] As the barrier films 244a and 244b, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, silicon oxynitride, silicon nitride, etc. may be used .

[0319] Also, a conductive material through which impurities hardly permeate may be used as the barrier films 244a and 244b. When using a conductive material for the barrier films 244a and 244b , it is preferable to use a conductive material in which oxygen is hardly released or hardly absorbed . Note that a configuration in which the barrier films 244a and 244b are not provided may also be adopted .

[0320] Note that the insulator 254 is not limited to a configuration in which the insulator 254a and the insulator 254b are laminated, and may be a single layer, or may have a configuration in which three layers of the insulator 254a, the insulator 254b, and the insulator 254c are laminated . When adopting a configuration in which three layers are laminated, for example, as the insulator 254a , an insulating material having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen may be used, as the insulator 254b , an insulating material having an excess oxygen region may be used, and as the insulator 254c , an insulating material having a function of suppressing the diffusion of oxygen may be used . In this way ​​By adopting a structure in which three layers are stacked, it is possible to suppress the diffusion of the excess oxygen in the insulator 254b to the outside of the insulator 254a and the insulator 254c. Therefore, the excess oxygen in the insulator 254b can be efficiently supplied to the oxide 230.

[0321] In addition, when the insulator 254 is configured to be stacked in two or more layers, the combination of insulating materials used for the insulator 254 and the stacking order may be appropriately designed according to the required transistor characteristics.

[0322] Also, as shown in FIG. 15, the oxide 230c includes an oxide 230c1 and an oxide 230c2 disposed on the oxide 230c1. The oxide 230c1 preferably contains at least one of the metal elements constituting the metal oxide used for the oxide 230b, and more preferably contains all of the metal elements. Thereby, the density of defect energy levels at the interface between the oxide 230b and the oxide 230c1 can be lowered. Further, the oxide 230c2 is preferably a metal oxide that suppresses the diffusion or permeation of oxygen more than the oxide 230c1. By providing the oxide 230c2 between the insulator 250 and the oxide 230c1, it is possible to suppress the diffusion of the oxygen contained in the insulator 280 to the insulator 250. Therefore, the oxygen is more likely to be supplied to the oxide 230 through the oxide 230c1.

[0323] In addition, the oxide 230c1 and the oxide 230c2 preferably have crystallinity, and more preferably, the oxide 230c2 has higher crystallinity than the oxide 230c1. In particular, it is preferable to use CAAC-OS as the oxide 230c1 and the oxide 230c2. ​​​​​​​​​​​​Preferably, the c-axis of the crystal of the oxide 230c1 and the oxide 230c2 is oriented in a direction substantially perpendicular to the formed surface or the upper surface of the oxide 23 0c1 and the oxide 230c2. CAAC-OS has the property of being difficult to move oxygen in the c-axis direction. Therefore, by providing the oxide 230c2 between the oxide 230c1 and the insulator 250, the oxygen of the oxide 230c1 can be prevented from diffusing into the insulator 250, and the oxygen can be efficiently supplied to the oxide 230.

[0324] Specifically, as the oxide 230c1, a metal oxide with In:Ga:Zn = 4:2:3 [atomic ratio] can be used, and as the oxide 230c2, a metal oxide with In:Ga:Zn = 1:3:4 [atomic ratio can be used. In the metal oxide used for the oxide 230c2, by making the atomic ratio of In in the constituent elements smaller than the atomic ratio of In in the constituent elements in the metal oxide used for the oxide 230c1, the diffusion of In to the insulator 250 side can be suppressed. Since the insulator 250 functions as a gate insulator, if In is mixed into the insulator 250 anywhere, the characteristics of the transistor will deteriorate. Therefore, by forming the oxide 230c into a stacked structure, it becomes possible to provide a highly reliable semiconductor device.

[0325] Also, the insulator 280 may be configured to have a two-layer stacked structure. As shown in FIG. 15, when the insulator 280 has the insulator 280a and the insulator 280b disposed on the insulator 280a, the insulator 280a preferably has an excess oxygen region. The insulator 280a is physically closer to the channel formation region of the oxide 230 than the insulator 280b. 80b, the insulator 280a preferably has an excess oxygen region. The insulator 280a is physically closer to the channel formation region of the oxide 230 than the insulator 280b. distance than the insulator 280b. Since the distance is short, oxygen contained in the insulator 280 can be efficiently supplied to the channel formation region of the oxide 230. It can be efficiently supplied.

[0326] Specifically, as the insulator 280a, silicon oxide formed by a sputtering method may be used, and as the insulator 280b, silicon oxynitride formed by a CVD method may be used. In the transistor 200A, a configuration in which the insulator 280 is laminated is shown, but the present invention is not limited to this. For example, the insulator 280 may be provided as a single layer or a laminated structure of three or more layers. It may also be provided in a laminated structure of three or more layers.

[0327] Also, as shown in FIG. 15, an insulator 282 may be provided between the insulator 274 and the insulator 281. The insulator 282 is preferably an insulating film having a function of suppressing diffusion of impurities such as hydrogen and oxygen. For example, it is preferable to form silicon nitride, aluminum oxide, etc. by a sputtering method or an ALD method. By providing the insulator 282, it is possible to suppress diffusion of oxygen contained in the insulator 280, the insulator 250, etc. to the insulator 281 side. It can be suppressed from diffusing to the insulator 281 side. It can be suppressed.

[0328] <Configuration Example 3 of Semiconductor Device> FIG. 16 is a top view and a cross-sectional view of the transistor 200B and the periphery thereof according to one aspect of the present invention. It is a top view and a cross-sectional view.

[0329] FIG. 16(A) is a top view of a semiconductor device having the transistor 200B. Also, FIGS. 16(B) to 16(D) are cross-sectional views of the semiconductor device. Here, FIG. 16(B) is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 16(A), and is the transistor 200 It is a cross-sectional view of the portion indicated by the one-dot chain line A1 - A2 in FIG. 16(A), and is the transistor 200 It is also a cross-sectional view in the channel length direction of B. Further, Fig. 16(C) is a cross-sectional view of the part indicated by the dashed-dotted line A3-A 4 in Fig. 16(A), and it is also a cross-sectional view in the channel width direction of the transistor 200B Fig. Also, Fig. 16(D) is a cross-sectional view of the part indicated by the dashed-dotted line A5-A6 in Fig. 16(A) and it is also a cross-sectional view near the region 243b that functions as a low-resistance region of the transistor 200B Fig. Note that in the top view of Fig. 16(A), some elements are omitted for clarity of the figure

[0330] Note that in the semiconductor device shown in Fig. 16, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device> are marked with the same reference numerals as appended

[0331] Hereinafter, the configuration of the semiconductor device will be described with reference to Fig. 16. Note that in this section as the constituent materials of the semiconductor device, the materials described in detail in <Configuration Example 1 of Semiconductor Device> or <Configuration Example 2 of Semiconductor Device> can be used

[0332] [Transistor 200B] As shown in Fig. 16, the transistor 200B includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, an oxide 230 (oxide 230a , oxide 230b, oxide 230c1, and oxide 230c2) disposed on the insulator 224, an insulator 250 disposed on the oxide 230, and a conductor 260 (conductor 260 disposed on the insulator 250 and disposed on the insulator 224), an insulator 250 disposed on the oxide 230, and a conductor 260 (conductor 260 disposed on the insulator 250), and a conductor 260 (conductor 260 disposed on the oxide 230), and an insulator 250 disposed on the oxide 230, and a conductor 260 (conductor 260 a, and a conductor 260b), a part of the upper surface of the insulator 222, the side surface of the insulator 224, oxidation placed in contact with the side surface of the object 230a, the side surface of the oxide 230b, and the upper surface of the oxide 230b insulators 254 (insulator 254a and insulator 254b). Here, on the upper surface of the oxide 230b, regions 243a and 243b are formed separated from each other.

[0333] The transistor 200B is different from the aforementioned transistor 200 etc. in that it does not provide a conductor 242. Below, the differences from the aforementioned transistor 200 etc. will be described.

[0334] As shown in FIG. 16(B), the regions 243a and 243b are formed to face each other with the conductor 260 interposed therebetween, and it is preferable that their upper surfaces are in contact with the insulator 254. In a top view, the side surfaces of the regions 243a and 243b on the side of the conductor 260 coincide with the side surfaces of the conductor 260, or a part of the regions 243a and 243b overlaps with the conductor 260.

[0335] In the transistor 200B shown in FIG. 16, for example, by adding an element that can increase the carrier density of the oxide 230 and lower its resistance as a dopant, the regions 243 (regions 243a and 243b) can be formed.

[0336] As the dopant, an element that forms oxygen vacancies or an element that binds to oxygen vacancies etc. can be used. Typically, such elements include boron or phosphorus. Also, hydrogen, carbon, nitrogen, fluorine, sulfur, chlorine, titanium, noble gases, etc. can be used. Representative examples of rare gases include helium, neon, argon, krypton, and xenon. Also, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, etc. Zn, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium nium, zirconium, beryllium, indium, ruthenium, iridium, strontium Add one or more metal elements selected from the group consisting of lanthanum, lanthanum, etc. Among the above, boron and phosphorus are preferable as the dopant. , when phosphorus is used as a dopant, amorphous silicon, or low-temperature polysilicon This allows the use of existing production line equipment, which reduces capital investment. The concentration of the above elements may be measured using SIMS or the like.

[0337] In particular, it is preferable to use an element that easily forms an oxide as the element to be added to the region 243. Representative examples of such elements include boron, phosphorus, aluminum, magnesium, and the like. The element added to the region 243 takes away oxygen from the oxide 230 to form the oxide. As a result, many oxygen vacancies are formed in the region 243. When the hydrogen in the oxide 230 is bonded to the SiO 2 , carriers are generated, resulting in an extremely low resistance region. Furthermore, since the element added to the region 243 exists in the region 243 in the form of a stable oxide, Even if a subsequent process requiring high temperatures is performed, the metal is unlikely to be desorbed from the region 243. That is, the element to be added to the region 243 is an element that easily forms an oxide. This allows the formation of a region in the oxide 230 that is resistant to high resistance even when subjected to high-temperature processes.

[0338] Here, the concentration of the above elements in the region 243 is the same as that in the region 243 where the oxide 230 is not formed. It is preferable that the concentration of the above elements in the region 2 is equal to or higher than that in the region 3. The amount of oxygen vacancies in 43 is determined by the amount of oxygen vacancies in the portion of the oxide 230 where the region 243 is not formed. It is preferable that the amount of the defect is equal to or greater than the amount of the defect. The carrier density is higher than that of the area 243 of the oxide 230 where the oxide 230 is not formed. , the resistance becomes lower.

[0339] Forming regions 243 in the oxide 230 to function as source or drain regions. Thus, the region 243 is provided without providing a source electrode and a drain electrode made of a metal. A conductor 240 can be connected which acts as a plug.

[0340] Furthermore, when the region 243 is formed by adding the dopant in this manner, the insulators 254a and The oxide 230b, the insulator 254b are also doped with dopants. 4a, and insulator 254b have an element contained in the dopant. When the insulator 254a and the insulator 254b have excess oxygen, the excess oxygen is transferred to the outside by the dopant. By forming such a region 243, the diffusion of the element can be suppressed. The on-current of the 200B is increased, and the S value (Subthreshold Swing, SS This improves the frequency characteristics.

[0341] When the region 243 is formed by adding a dopant, for example, the oxide 230c1, the oxide A dummy gate is formed at a position where the oxide 230c2, the insulator 250, and the conductor 260 are to be provided. It is only necessary to form the dummy gate and use the dummy gate as a mask to add a dopant. Thus, in the oxide 230, a region 243 containing the above elements can be formed in a region where the dummy gate does not overlap.

[0342] As a method for adding a dopant, an ion implantation method in which an ionized source gas is mass-separated and added, an ion doping method in which an ionized source gas is added without mass separation, a plasma immersion ion implantation method, etc. can be used. When mass separation is performed, the ion species to be added and its concentration can be strictly controlled. On the other hand, when mass separation is not performed, ions with a high concentration can be added in a short time. Also, an ion doping method that generates clusters of atoms or molecules and ionizes them may be used. Note that the dopant may be rephrased as an ion, donor, acceptor, impurity, or element, etc.

[0343] In addition, by adding an element that forms an oxygen deficiency in the region 243 and performing heat treatment, hydrogen contained in the region 234 that functions as a channel formation region may be captured by the oxygen deficiency contained in the region 243. Thereby, stable electrical characteristics can be given to the transistor 200B, and the reliability can be improved.

[0344] Note that in FIG. 16, similar to the transistor 200A, the oxide 230c is shown as a laminate of the oxide 230c1 and the oxide 230c2, and the insulator 254 is shown as a laminate of the insulator 254a and the insulator 254b, but it is not limited thereto. The oxide 230c and the insulator 254 may be single layers or may have a laminate structure of three or more layers.

[0345] ​​​​​​​​​​ <Configuration Example 4 of Semiconductor Device> FIG. 17 is a top view and a cross-sectional view of the transistor 200C and the periphery thereof according to one aspect of the present invention. It is a top view and a cross-sectional view of the periphery.

[0346] FIG. 17(A) is a top view of a semiconductor device having the transistor 200C. Also, FIG. 17(B) and FIG. 17(C) are cross-sectional views of the semiconductor device. Here, FIG. 17(B) is a cross-sectional view of the portion indicated by the dashed line A1-A2 in FIG. 17(A), and is also a cross-sectional view in the channel length direction of the transistor 20 0C. Further, FIG. 17(C) is a cross-sectional view of the portion indicated by the dashed line A3- A4 in FIG. 17(A), and is also a cross-sectional view in the channel width direction of the transistor 200C. Note that in the top view of FIG. 17(A), some elements are omitted for clarity of the figure. For clarity of the figure, some elements are omitted. are omitted.

[0347] In the semiconductor device shown in FIG. 17, structures having the same functions as the structures constituting the semiconductor device shown in <Configuration Example 1 of Semiconductor Device> are denoted by the same reference numerals. are denoted by the same reference numerals.

[0348] Hereinafter, the configuration of the semiconductor device will be described with reference to FIG. 17. In this section, as the constituent materials of the semiconductor device, the materials described in detail in <Configuration Example 1 of Semiconductor Device> can be used. can be used.

[0349] [Transistor 200C] As shown in FIG. 17, the transistor 200C includes an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a) disposed on the insulator 224. an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a) disposed on the insulator 224. an insulator 216 disposed on a substrate (not shown), a conductor 205 disposed so as to be embedded in the insulator 216, an insulator 222 disposed on the insulator 216 and on the conductor 205, an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a) disposed on the insulator 224. an insulator 224 disposed on the insulator 222, and an oxide 230 (oxide 230a) disposed on the insulator 224. ), oxide 230b, and oxide 230c), and insulator 2 disposed on oxide 230 50, and conductor 260 (conductor 260a and conductor 26 0b) disposed on insulator 250, and conductor 242a and conductor 242b in contact with a part of the upper surface of oxide 230b , a part of the upper surface of insulator 222, the side surface of insulator 224, the side surface of oxide 230a, oxide 23 0b side surface, conductor 242a side surface, conductor 242a upper surface, conductor 242b side surface, guide electric body 242b upper surface, and insulator 254 disposed in contact with a part of oxide 230c, and insulator 273 disposed covering conductor 260.

[0350] Having insulator 273, a part of oxide 230c, insulator 250, and conductor 260 is conductive The body 242 is superimposed, and the point that the insulator 280 is provided on the oxide 230c, the insulator 250, and the conductor 26 0 is different from the aforementioned transistor 200. Hereinafter, the differences from the transistor 200 will be described.

[0351] In transistor 200C, conductor 260 has a region overlapping conductor 242 a via insulator 250 and a region overlapping conductor 242b via insulator 250. Conductor By forming 260 in such a shape, a margin for alignment can be provided for conductor 260 Therefore, conductor 260 can be surely superimposed on the region between conductor 242a and conductor 242b of oxide 230, and the formation of an offset region can be prevented.

[0352] Insulator 273, like insulator 254, etc., has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc. One) (it is difficult for the above oxygen to permeate.) This is preferable. Preferably. For example, the insulator 273 has lower oxygen permeability than the insulator 280 or the insulator 224. Preferably. By covering the conductor 260 with such an insulator 273, oxidation of the conductor 2 60 can be suppressed.

[0353] Also, similar to the insulator 254, the insulator 273 preferably functions as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the insulator 280 side to the conductor 260. Preferably. For example, the insulator 273 preferably has lower hydrogen permeability than the insulator 224.

[0354] In FIG. 17, the insulator 273 covers the conductor 260 and is in contact with the upper surface of the insulator 250, but it is not limited to this. For example, the insulator 273 may be configured to cover the conductor 260, the insulator 250, and the oxide 230c and be in contact with the insulator 254. That is also acceptable.

[0355] As described above, the configurations, methods, etc. shown in the present embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments and examples. That is also acceptable.

[0356] (Embodiment 3) In this embodiment, one form of the semiconductor device will be described with reference to FIGS. 18 and 19.

[0357] [Memory device 1] An example of a semiconductor device (memory device) using a capacitive element, which is one aspect of the present invention, is shown in FIG. 18. In the semiconductor device of one aspect of the present invention, the transistor 200 is provided above the transistor 300, and the capacitive element 100 is provided above the transistor 300 and the transistor 200. Note that, as the transistor 200, the transistor described in the previous embodiment Sta200 etc. can be used.

[0358] The transistor 200 is a transistor in which a channel is formed in a semiconductor layer having an oxide semiconductor. The transistor 200 is used in a memory device because its off-state current is small. This makes it possible to retain the memory contents for a long period of time. Since no refresh operation is required or the frequency of refresh operations is extremely low, Power consumption can be reduced sufficiently.

[0359] In the semiconductor device shown in FIG. 18, a wiring 1001 is electrically connected to the source of a transistor 300. The wiring 1002 is electrically connected to the drain of the transistor 300. The wiring 1003 is electrically connected to one of the source and drain of the transistor 200. The wiring 1004 is electrically connected to the first gate of the transistor 200. 006 is electrically connected to the second gate of the transistor 200. The gate of the transistor 300 and the other of the source and drain of the transistor 200 are connected to a capacitor. The wiring 1005 is electrically connected to one of the electrodes of the capacitor 100. It is electrically connected to the other.

[0360] In addition, the memory device shown in FIG. 18 has a memory cell array arranged in a matrix. It can be configured.

[0361] <Transistor 300> The transistor 300 is provided on a substrate 311 and has a conductor 312 functioning as a gate electrode. 16, an insulator 315 acting as a gate insulator, a semiconductor region consisting of a portion of a substrate 311 313, and a low-resistance region 314a that functions as a source region or a drain region, and a low-resistance region 314b. The transistor 300 can be either p-channel or n-channel .

[0362] Here, in the transistor 300 shown in FIG. 18, the semiconductor region 313 ( a part of the substrate 311) where the channel is formed has a convex shape. Also, the side and upper surfaces of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. Note that the conductor 316 may be made of a material that adjusts the work function. Since such a transistor 300 utilizes the convex portion of the semiconductor substrate, it is also called a FIN-type transistor. Note that an insulator that functions as a mask for forming the convex portion may be provided in contact with the upper part of the convex portion. Also, although the case of forming a convex portion by processing a part of the semiconductor substrate is shown here, an SOI substrate may be processed to form a semiconductor film having a convex shape. Here, the case of forming a convex portion by processing a part of the semiconductor substrate is shown, but an SOI substrate may be processed to form a semiconductor film having a convex shape.

[0363] Note that the transistor 300 shown in FIG. 18 is an example and is not limited to its structure, and an appropriate transistor may be used according to the circuit configuration and the driving method.

[0364] <Capacitor element 100> The capacitor element 100 is provided above the transistor 200. The capacitor element 100 has a conductor 110 that functions as a first electrode, a conductor 120 that functions as a second electrode, and an insulator 130 that functions as a dielectric.

[0365] Also, for example, the conductor 110 and the conductor 112 provided on the conductor 240 can be formed simultaneously. Note that the conductor 112 is for the capacitor element 100, the transistor 200, or ​​​​​​It has the function as a plug that is electrically connected to the transistor 300, or as wiring.

[0366] In FIG. 18, the conductor 112 and the conductor 110 are shown in a single-layer structure, but the configuration is not limited to this, and a laminated structure of two or more layers may be used. For example, a conductor having a barrier property and a conductor having high conductivity may be formed between a conductor having a barrier property and a conductor having high adhesion to the conductor having high conductivity. Also, the insulator 130 may be made of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, etc., and can be provided in a laminated or single-layer form. For example, it is preferable to use a laminated structure of a material having a large dielectric breakdown strength such as silicon oxynitride and a high dielectric constant (high-k) material for the insulator 130. With this configuration, the capacitor 100 can secure a sufficient capacitance by having a high dielectric constant (high-k) insulator, and the dielectric breakdown strength is improved by having an insulator having a large dielectric breakdown strength, so that the electrostatic breakdown of the capacitor 100 can be suppressed.

[0367]

[0368]

[0369] There are nitrides containing um, etc.

[0370] On the other hand, materials with high dielectric strength (materials with low relative permittivity) include silicon oxide, silicon nitride, silicon oxynitride, silicon nitride, silicon oxide with fluorine added, silicon oxide with carbon added, silicon oxide with carbon and nitrogen added, silicon oxide with pores, resins, etc.

[0371] <Wiring layer> A wiring layer provided with an interlayer film, wiring, plugs, etc. may be provided between each structure. Also, multiple wiring layers can be provided according to the design. Here, conductors having the function of plugs or wiring may be given the same reference numeral collectively for a plurality of structures. Also, in this specification, etc., a wiring and a plug electrically connected to the wiring may be integrated. That is, a part of the conductor may function as wiring, and a part of the conductor may function as a plug.

[0372] For example, on the substrate 311, as an interlayer film, insulators 320, 322, 32 4, and insulator 326 are laminated in order. Note that insulators 315 and conductor 316 are provided so as to be embedded in insulator 320. Also, conductors 328 and 330 that are electrically connected to capacitor element 100 or transistor 200 are embedded in insulators 320, 322, 324, and insulator 326. Note that conductors 328 and 330 function as plugs or wiring.

[0373] Also, the insulator functioning as an interlayer film serves as a planarization film covering the uneven shape below it. ​​​​It may function. For example, the upper surface of the insulator 322 may be planarized by a planarization process such as chemical mechanical polishing ( CMP).

[0374] A wiring layer may be provided on the insulator 326 and the conductor 330. For example, in FIG. 18, the insulators 350, 352, and 354 are sequentially stacked and provided. Also, a conductor 356 is formed in the insulators 350, 352, and 354. The conductor 356 functions as a plug or wiring.

[0375] On the insulator 354 and the conductor 356, the insulators 210, 212, 21 4, and 216 are sequentially stacked and provided. Also, in the insulators 210, 2 12, 214, and 216, conductors 218 and conductors (conductors 205) constituting the transistor 200 etc. are embedded. Note that the conductor 218 functions as a plug or wiring that is electrically connected to the capacitor element 100 or the transistor 300. Further, an insulator 150 is provided on the conductor 120 and the insulator 130.

[0376] Examples of insulators that can be used as interlayer dielectrics include oxides, nitrides, oxynitrides, nitride oxides, metal oxides, metal oxynitrides, metal nitride oxides, etc. having insulating properties.

[0377] For example, by using a material with a low relative permittivity for the insulator that functions as an interlayer dielectric, the parasitic capacitance generated between the wirings can be reduced. Therefore, the material may be selected according to the function of the insulator.

[0378] ​​​​For example, the insulators 212, 352, 354, etc. preferably have an insulator with a low relative permittivity. For example, the insulator preferably includes silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, silicon oxide with pores, resin, etc. Or, the insulator preferably has a laminated structure of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen or silicon oxide with pores, and resin. Since silicon oxide and silicon oxynitride are thermally stable, a laminated structure that is thermally stable and has a low relative permittivity can be obtained by combining them with resin. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc. Preferably, it has. For example, the insulator is silicon oxide, silicon oxynitride, nitride Silicon oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon Con, silicon oxide with added carbon and nitrogen, silicon oxide with pores, resin, etc. Preferably, it has. Or, the insulator is silicon oxide, silicon oxynitride, nitride Silicon oxide, silicon nitride, silicon oxide with added fluorine, silicon oxide with added carbon Con, silicon oxide with added carbon and nitrogen or silicon oxide with pores, and resin Preferably, it has a laminated structure with. Silicon oxide and silicon oxynitride are thermally Stable, so by combining with resin, a thermally stable and low relative permittivity laminated structure Can be obtained. Examples of the resin include polyester, polyolefin, polyamide (Nylon, aramid, etc.), polyimide, polycarbonate, acrylic, etc.

[0379] Also, one or both of the insulator 130 provided on the conductor 112 or the conductor 120, and the insulator 150 have a resistivity of 1.0×10 12 Ωcm or more and 1.0×10 15 Ωc m or less, preferably 5.0×10 12 Ωcm or more and 1.0×10 14 Ωcm or less, more preferably Preferably 1.0×10 13 Ωcm or more and 5.0×10 13 Ωcm or less. Preferably, one or both of the insulator 130 and the insulator 150 have an insulator with the above resistivity. By making the insulator an insulator with the above resistivity, the insulator can maintain its insulating property while the transistor 200, (Omitted content) Between the transistor 300, the capacitive element 100, and wirings such as the conductor 112 and the conductor 120 The charge accumulated is dispersed, and characteristic defects and electrostatic breakdown of the transistor and the memory device having the transistor can be suppressed, which is preferable. As such an insulator, silicon nitride , or silicon oxynitride can be used.

[0380] Also, as the insulator having the resistivity as described above, the insulator 140 may be provided under the conductor 112 . In this case, the insulator 140 is formed on the insulator 281, and openings are formed in the insulator 140, the insulator 281, the insulator 274, the insulator 280, the insulator 254, etc., and the insulator 241 is formed in the opening, or the conductor 240 electrically connected to the transistor 200, the conductor 218, etc. may be formed. The insulator 140 can use the same material as the insulator 130 or the insulator 1 50.

[0381] Also, a transistor using an oxide semiconductor can have its electrical characteristics stabilized by surrounding it with an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen. Therefore, for the insulator 210, the insulator 350, etc., an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen may be used.

[0382] As an insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen and oxygen, for example, an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine , argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium , hafnium or tantalum may be used in a single layer or in a laminate. Specifically, as the insulator having a function of suppressing the permeation of impurities such as hydrogen and oxygen, aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide and other metal oxides, silicon oxynitride, silicon nitride, etc. can be used.

[0383] As the conductor that can be used for wiring and plugs, aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vana dium, niobium, manganese, magnesium, zirconium, beryllium, indium, ru tenium and other materials containing one or more metal elements selected therefrom can be used. Also, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing impurity elements such as phosphorus, silicide such as nickel silicide may be used.

[0384] For example, as the conductors 328, 330, 356, 218, 110, 112, 120, etc., conductive materials such as metal materials, alloy materials, metal nitride materials, and metal oxide materials formed of the above materials can be used singly or in a stacked manner. It is preferable to use a high melting point material such as tungsten or molybdenum that achieves both heat resistance and conductivity, and it is preferable to use tungsten. Or, it is preferable to form with a low resistance conductive material such as aluminum or copper. By using a low resistance conductive material, the wiring resistance can be lowered.

[0385] <<Wiring or plug of the layer provided with the oxide semiconductor>> ​In addition, when an oxide semiconductor is used for the transistor 200, an insulator having an excessive oxygen region may be provided in the vicinity of the oxide semiconductor. In this case, it is preferable to provide an insulator having a barrier property between the insulator having the excessive oxygen region and a conductor provided on the insulator having the excessive oxygen region. For example, in FIG. 18, an insulator 241 may be provided between the insulators 280 and 281 and the conductor 240. By the insulator 241 existing between the insulators 280 and 281 and the conductor 240, absorption of oxygen contained in the insulators 280 and 281 by the conductor 240, that is, oxidation of the conductor 240 can be suppressed. That is, by providing the insulator 241, absorption of the excessive oxygen possessed by the insulator 280 by the conductor 240 can be suppressed. Further, by having the insulator 241, diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240 can be suppressed. Note that, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used.

[0386] For example, in FIG. 18, an insulator 241 may be provided between the insulators 280 and 281 and the conductor 240. When the insulator 241 exists between the insulators 280 and 281 and the conductor 240, absorption of oxygen contained in the insulators 280 and 281 by the conductor 240, that is, oxidation of the conductor 240 can be suppressed. That is, by providing the insulator 241, absorption of the excessive oxygen possessed by the insulator 280 by the conductor 240 can be suppressed. In addition, by having the insulator 241, diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240 can be suppressed.

[0387] That is, by providing the insulator 241, absorption of the excessive oxygen possessed by the insulator 280 by the conductor 240 can be suppressed. In addition, by having the insulator 241, diffusion of hydrogen, which is an impurity, to the transistor 200 through the conductor 240 can be suppressed. Note that, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like.

[0388] Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used. Note that, as the insulator 241, an insulating material having a function of suppressing diffusion of impurities such as water and hydrogen and oxygen may be used. For example, it is preferable to use aluminum oxide, hafnium oxide, or the like. Alternatively, for example, metal oxides such as magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, and tantalum oxide, silicon oxynitride, silicon nitride, or the like can be used.

[0389] The above is the description of the configuration example. By using this configuration, for a transistor having an oxide semiconductor, In a semiconductor device using a transistor, fluctuations in electrical characteristics can be suppressed and the reliability can be improved. In addition, a transistor having an oxide semiconductor with a large on-current can be provided. In addition, a transistor having an oxide semiconductor with a small off-current can be provided. In addition, a semiconductor device with reduced power consumption can be provided.

[0390] [Memory device 2] An example of a memory device using the semiconductor device according to one aspect of the present invention is shown in FIG. 19. The memory device shown in FIG. 19 has a transistor 400 in addition to the semiconductor device having the transistor 200, the transistor 300, and the capacitive element 100 shown in FIG. 18.

[0391] The transistor 400 can control the second gate voltage of the transistor 200. For example, the first gate and the second gate of the transistor 400 are diode-connected to the source, and the source of the transistor 400 is connected to the second gate of the transistor 200. When the negative potential of the second gate of the transistor 200 is held in this configuration, the voltage between the first gate and the source of the transistor 400 and the voltage between the second gate and the source of the transistor 400 become 0V. In the transistor 400, since the drain current when the second gate voltage and the first gate voltage are 0V is very small, the negative potential of the second gate of the transistor 200 can be maintained for a long time without supplying power to the transistor 200 and the transistor 400. As a result, the memory device having the transistor 200 and the transistor 400 can retain the stored content for a long time.

[0392] Therefore, in FIG. 19, wiring 1001 is electrically connected to the source of transistor 300 and wiring 1002 is electrically connected to the drain of transistor 300. Also, wiring 1003 is electrically connected to one of the source and drain of transistor 200, wiring 1004 is electrically connected to the first gate of transistor 200, and wiring 1006 is electrically connected to the second gate of transistor 200. Then, the gate of transistor 3 00, and the other of the source and drain of transistor 200 are electrically connected to one of the electrodes of capacitor element 1 00, and wiring 1005 is electrically connected to the other electrode of capacitor element 100. Wiring 1007 is electrically connected to the source of transistor 400 and wiring 1008 is electrically connected to the first gate of transistor 400, wiring 1009 is electrically connected to the second gate of transistor 400, and wiring 1010 is electrically connected to the drain of transistor 400. Here, wiring 1006, wiring 1007, wiring 1008, and wiring 1009 are electrically connected.

[0393] Also, the memory device shown in FIG. 19 can form a memory cell array by being arranged in a matrix shape, similar to the memory device shown in FIG. 18. Note that one transistor 40 0 can control the second gate voltages of a plurality of transistors 200. Therefore , transistor 400 may be provided in a smaller number than transistor 200.

[0394] <Transistor 400> Transistor 400 is a transistor formed in the same layer as transistor 200 and can be manufactured in parallel. Transistor 400 has a first gate electrode as ​ A conductor 460 (conductor 460a and conductor 460b) that functions as such, a conductor 405 that functions as a second gate electrode, an insulator 222 that functions as a gate insulator, an insulator 4 24a, an insulator 424b, and an insulator 450, an oxide 430c having a region where a channel is formed, a conductor 442a that functions as one of a source or a drain, an oxide 4 31a, and an oxide 431b, a conductor 4 that functions as the other of the source or the drain 42b, an oxide 432a, and an oxide 432b, and a conductor 440 (conductor 440a, and conductor 440b). In the transistor 400, the conductor 405 is formed in the same layer as the conductor 205. The insulator 424a and the insulator 424b are formed in the same layer as the insulator 224. The oxide 4 31a and the oxide 432a are formed in the same layer as the oxide 230a, and the oxide

[0395] 431b and the oxide 432b are formed in the same layer as the oxide 230b. The conductor 4 42 is formed in the same layer as the conductor 242. The oxide 430c is formed in the same layer as the oxide 230c. The insulator 450 is formed in the same layer as the insulator 250. The conductor 4 60 is formed in the same layer as the conductor 260. It should be noted that the structures formed in the same layer can be formed simultaneously. For example, the oxide 4 30c can be formed by processing an oxide film that becomes the oxide 230c. The oxide 430c that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as water and hydrogen, similar to the oxide 230 and the like. As a result, the transistor 400...

[0396] Note that the structures formed in the same layer can be formed simultaneously. For example, the oxide 4 30c can be formed by processing an oxide film that becomes the oxide 230c.

[0397] The oxide 430c that functions as the active layer of the transistor 400 has reduced oxygen deficiency and reduced impurities such as water and hydrogen, similar to the oxide 230 and the like. As a result, the transistor 400... Increase the threshold voltage of the transistor 400, reduce the off-current, and make the drain current very small when the second gate voltage and the first gate voltage are 0V.

[0398] <<Dicing line>> In the following, a dicing line (which may be called a scribing line, a dividing line, or a cutting line) provided when a plurality of semiconductor devices are taken out in chip form by dividing a large-area substrate for each semiconductor element will be described. As a dividing method, for example, first, after forming a groove (dicing line) for dividing the semiconductor element in the substrate, it may be cut at the dicing line and divided (split) into a plurality of semiconductor devices. First, a groove (dicing line) for dividing the semiconductor element is formed in the substrate, and then it is cut at the dicing line and divided (split) into a plurality of semiconductor devices.

[0399] At the outer edges of the transistor 200 described in the previous embodiment and the transistor 400 shown in this embodiment, as shown in FIG. 19, the insulator 254 and the insulator 222 are in contact. Therefore, when designing the region where the insulator 254 and the insulator 222 are in contact to be a dicing line, the degree of freedom in designing the dicing line can be increased. At this time, the insulator 2 22 and the insulator 254 may be formed using the same material and the same method. By providing the insulator 222 and the insulator 254 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide. By providing the insulator 222 and the insulator 254 using the same material and the same method, the adhesion can be enhanced. For example, it is preferable to use aluminum oxide.

[0400] With this structure, the insulator 222 and the insulator 254 can wrap the insulator 224, the transistor 200, and the transistor 400. Since the insulator 222 and the insulator 254 have the function of suppressing the diffusion of oxygen, hydrogen, and water, in this embodiment they have the function of suppressing the diffusion of oxygen, hydrogen, and water. By dividing the substrate for each circuit region in which the semiconductor element shown in the figure is formed, a plurality of chips Even if processed into a plurality, impurities such as water and hydrogen can be prevented from mixing in from the side direction of the divided substrate and diffusing into the transistor 200 and the transistor 400.

[0401] Also, with this structure, it is possible to prevent the excess oxygen in the insulator 224 from diffusing to the outside of the insulator 254 and the insulator 222. Therefore, the excess oxygen in the insulator 224 is efficiently supplied to the oxide in which the channel in the transistor 200 or the transistor 400 is formed. With this oxygen, it is possible to reduce the oxygen deficiency in the oxide in which the channel in the transistor 200 or the transistor 400 is formed. As a result, the oxide in which the channel in the transistor 200 or the transistor 400 is formed can be made into an oxide semiconductor having stable characteristics with a low defect level density. That is, the variation in the electrical characteristics of the transistor 200 or the transistor 400 can be suppressed, and the reliability can be improved.

[0402] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments and examples, etc.

[0403] (Embodiment 4) In this embodiment, using FIGS. 20 and 21, a transistor using an oxide as a semiconductor (hereinafter sometimes referred to as an OS transistor) according to an aspect of the present invention, and a storage device to which a capacitive element is applied (hereinafter sometimes referred to as an OS memory device) will be described. The OS memory device includes at least a capacitive element and an OS transistor that controls the charging and discharging of the capacitive element. ​​​​​​​​​It is a memory device having transistors. Since the off-current of the OS transistor is extremely small, the OS memory device has excellent holding characteristics and can function as a non-volatile memory .

[0404] <Configuration example of the memory device> Fig. 20(A) shows an example of the configuration of the OS memory device. The memory device 1400 has a peripheral circuit 1 411 and a memory cell array 1470. The peripheral circuit 1411 has a row circuit 142 0, a column circuit 1430, an output circuit 1440, and a control logic circuit 1460 .

[0405] The column circuit 1430 has, for example, a column decoder, a precharge circuit, a sense amplifier, a write circuit, etc. The precharge circuit has a function of precharging the wiring. The sense a mplifier has a function of amplifying the data signal read from the memory cell. Note that the above-mentioned wir ing is the wiring connected to the memory cells included in the memory cell array 1470, which will be described in detail later. The amplified data signal is output to the outside of the memory device 1400 as a data signal RDA TA via the output circuit 1440. Also, the row circuit 1420 has, for example, a row decoder, a word line driver circuit, etc., and can select the row to be accessed.

[0406] The memory device 1400 is supplied with a low power supply voltage (VSS) as a power supply voltage from the outside, a high power supply voltage (VDD) for the peripheral circuit 14 11, and a high power supply voltage (VIL) for the memory cell array 1470. Also, control signals (CE, WE, RE), an address sig nal ADDR, and a data signal WDATA are input to the memory device 1400 from the outside. The address signal ADDR is a row signal, and... It is input to the decoder and the column decoder, and the data signal WDATA is input to the write circuit .

[0407] The control logic circuit 1460 processes control signals (CE, WE, R E) input from the outside to generate control signals for the row decoder and the column decoder. The control signal CE is a chip enable signal, the control signal WE is a write enable signal, and the control signal R E is a read enable signal. The signals processed by the control logic circuit 1460 are not limited to this, and other control signals may be input as necessary.

[0408] The memory cell array 1470 has a plurality of memory cells MC arranged in a matrix and a plurality of wirings. Note that the number of wirings connecting the memory cell array 1470 and the row circuit 1420 is determined by the configuration of the memory cell MC, the number of memory cells MC in a column, etc. . Also, the number of wirings connecting the memory cell array 1470 and the column circuit 1430 is determined by the configuration of the memory cell MC, the number of memory cells MC in a row, etc.

[0409] In FIG. 20(A), an example in which the peripheral circuit 1411 and the memory cell array 1470 are formed on the same plane is shown, but the present embodiment is not limited to this. For example , as shown in FIG. 20(B), the memory cell array 14 70 may be provided so as to overlap a part of the peripheral circuit 1411. For example, a configuration in which a sense amplifier is provided so as to overlap under the memory cell array 1470 may be adopted.

[0410] A configuration example of a memory cell applicable to the above-described memory cell MC will be described with reference to FIG. 21. ​​​​

[0411] [DOSRAM] FIG. 21(A) through (C) show circuit configuration examples of DRAM memory cells. In this specification, etc. A DRAM using a 1OS transistor 1 capacitor type memory cell is sometimes referred to as DOSRA M (registered trademark) (Dynamic Oxide Semiconductor Rand om Access Memory). The memory cell 1471 shown in FIG. 21(A) has a transistor M1 and a capacitor element CA. Note that the transistor M 1 has a gate (which may be called a top gate) and a back gate.

[0412] The first terminal of transistor M1 is connected to the first terminal of capacitor element CA, and the second terminal of transistor M 1 is connected to wiring BIL, the gate of transistor M1 is connected to wiring WOL, and the back gate of transistor M1 is connected to wiring BGL. The second terminal of capacitor element C A is connected to wiring CAL. A is connected to wiring CAL.

[0413] Wiring BIL functions as a bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitor element CA. During data writing and reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M1. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M1 can be increased or decreased. M1 can be increased or decreased. M1 can be increased or decreased.

[0414] Also, the memory cell MC is not limited to the memory cell 1471, and changes can be made to the circuit configuration. It is possible. For example, the memory cell MC may be configured such that, as in the memory cell 1472 shown in FIG. 21(B), the back gate of the transistor M1 is connected to the wiring WOL instead of the wiring BGL. Also, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 21(C). For example, the back gate of the transistor M1 may be connected to the wiring WOL instead of the wiring BGL as in the memory cell 1472 shown in FIG. 21(B). Also, for example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 21(C). For example, the memory cell MC may be a memory cell composed of a transistor having a single gate structure, that is, a transistor M1 without a back gate, as in the memory cell 1473 shown in FIG. 21(C). It may be a memory cell composed of a transistor M1 without a back gate, that is, a transistor having a single gate structure, as in the memory cell 1473 shown in FIG. 21(C).

[0415] When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor element 100 can be used as the capacitor element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Also, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very small, multi-valued data or analog data can be held for the memory cell 1471, the memory cell 1472, and the memory cell 1473. When the semiconductor device shown in the above embodiment is used for the memory cell 1471 or the like, the transistor 200 can be used as the transistor M1, and the capacitor element 100 can be used as the capacitor element CA. By using an OS transistor as the transistor M1, the leakage current of the transistor M1 can be made very small. That is, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. That is, since the written data can be held by the transistor M1 for a long time, the refresh frequency of the memory cell can be reduced. Also, the refresh operation of the memory cell can be made unnecessary. Also, since the leakage current is very small, multi-valued data or analog data can be held for the memory cell 1471, the memory cell 1472, and the memory cell 1473. Also, since the leakage current is very small, multi-valued data or analog data can be held for the memory cell 1471, the memory cell 1472, and the memory cell 1473. It can hold multi-valued data or analog data for the memory cell 1471, the memory cell 1472, and the memory cell 1473.

[0416] Also, in the DOSRAM, if the sense amplifier is provided as shown above so as to overlap below the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacitance becomes small, and the holding capacitance of the memory cell can be reduced. Also, in the DOSRAM, if the sense amplifier is provided as shown above so as to overlap below the memory cell array 1470, the bit line can be shortened. As a result, the bit line capacitance becomes small, and the holding capacitance of the memory cell can be reduced.

[0417] [NOSRAM] In FIGS. 21(D) to (G), a gain cell type memory cell of a two-transistor one-capacitor element is shown. Shows a circuit configuration example. The memory cell 1474 shown in FIG. 21(D) includes transistor M2 and transistor M3, and capacitance element CB. Note that transistor M2 has a top gate (which may simply be referred to as a gate), and a back gate. In this specification etc., a memory device having a gain cell type memory cell using transistor M2 as an OS transistor may be referred to as NOSRAM (registered trademark) (Nonvolatile Oxide Semi conductor RAM).

[0418] The first terminal of transistor M2 is connected to the first terminal of capacitance element CB, the second terminal of transistor M 2 is connected to wiring WBL, the gate of transistor M2 is connected to wiring WOL, and the back gate of transistor M2 is connected to wiring BGL. The second terminal of capacitance element C B is connected to wiring CAL. The first terminal of transistor M3 is connected to wiring R BL, the second terminal of transistor M3 is connected to wiring SL, and the gate of transistor M 3 is connected to the first terminal of capacitance element CB.

[0419] Wiring WBL functions as a write bit line, wiring RBL functions as a read bit line, and wiring WOL functions as a word line. Wiring CAL functions as a wiring for applying a predetermined potential to the second terminal of capacitance element CB. During data writing, during data retention, and during data reading, it is preferable to apply a low-level potential to wiring CAL. Wiring BGL functions as a wiring for applying a potential to the back gate of transistor M2. By applying an arbitrary potential to wiring BGL, the threshold voltage of transistor M2 can be increased or decreased. ​

[0420] In addition, the memory cell MC is not limited to the memory cell 1474, and the circuit configuration may be appropriately changed. For example, the memory cell MC can be the memory cell 1475 shown in FIG. In this way, the back gate of the transistor M2 is connected to the wiring WOL instead of the wiring BGL. For example, the memory cell MC may be a memory cell shown in FIG. Like the 1476, it has a single-gate transistor, i.e. no back gate. The memory cell may be configured with a transistor M2. For example, the memory cell MC As shown in FIG. 21G, a memory cell 1477 is formed by connecting a wiring WBL and a wiring RBL together. The wiring BIL may be integrated.

[0421] When the semiconductor device described in the above embodiment is used for the memory cell 1474 or the like, The transistor 200 is used as M2, and the transistor 300 is used as M3. The capacitance element CB can be a capacitance element 100. By using an OS transistor, the leakage current of transistor M2 is made very small. This allows the written data to be stored for a long time by the transistor M2. Since the memory cells can be maintained at a constant level, the frequency of refreshing the memory cells can be reduced. In addition, the refresh operation of the memory cells can be eliminated. Since the memory cell 1474 is always small, it is possible to store multi-value data or analog data. The same can be said for memory cells 1475 to 1477.

[0422] The transistor M3 is a transistor having silicon in the channel formation region (hereinafter (which may be referred to as an Si transistor). The conductivity type of the Si transistor may be either n-channel type or p-channel type. The Si transistor may have a higher field-effect mobility than the OS transistor. Therefore, an Si transistor may be used as the transistor M3 that functions as a read transistor. Also, by using an Si transistor for the transistor M3, a transistor M2 can be provided laminated on the transistor M3, so that the occupied area of the memory cell can be reduced and the high integration of the storage device can be achieved.

[0423] Also, the transistor M3 may be an OS transistor. When OS transistors are used for the transistor M2 and the transistor M3, the memory cell array 1470 can be configured with a circuit using only n-type transistors.

[0424] Also, an example of a gain cell type memory cell of a three-transistor one-capacitor element is shown in FIG. 21(H). The memory cell 1478 shown in FIG. 21(H) has transistors M4 to M 6, and a capacitor element CC. The capacitor element CC is provided as appropriate. The memory cell 1478 is electrically connected to wiring BIL, wiring RWL, wiring WWL, wiring BGL, and wiring GNDL. Wiring GNDL is a wiring that gives a low-level potential. Note that the memory cell 1 478 may be electrically connected to wiring RBL and wiring WBL instead of wiring BIL.

[0425] The transistor M4 is an OS transistor having a back gate, and the back gate is electrically connected to wiring BGL. Note that the back gate and the gate of the transistor M4 They may be electrically connected to each other. Alternatively, the transistor M4 may not have a back gate. It may not have.

[0426] Note that the transistor M5 and the transistor M6 may each be an n-channel Si transistor or a p-channel Si transistor. Alternatively, the transistors M4 to M6 may be OS transistors. In this case, the memory cell array 1470 can be configured with only n-type transistors. When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor element 100 can be used as the capacitor element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small. When using the semiconductor device shown in the above embodiment for the memory cell 1478, the transistor 200 can be used as the transistor M4, the transistor 300 can be used as the transistors M5 and M6, and the capacitor element 100 can be used as the capacitor element CC. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small. It can be configured.

[0427] When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 is used as the transistor M4, the transistors 300 are used as the transistors M5 and M6, and the capacitor element 100 is used as the capacitor element CC. When the semiconductor device shown in the above embodiment is used for the memory cell 1478, the transistor 200 is used as the transistor M4, the transistors 300 are used as the transistors M5 and M6, and the capacitor element 100 is used as the capacitor element CC. It can be used. By using an OS transistor as the transistor M4, the leakage current of the transistor M4 can be made very small. It can be made very small.

[0428] Note that the configurations of the peripheral circuit 1411, the memory cell array 1470, etc. shown in this embodiment are not limited to the above. The arrangements or functions of these circuits, the wirings connected to the circuits, circuit elements, etc. may be changed, deleted, or added as necessary. The configurations shown in this embodiment are not limited to the above. The arrangements or functions of these circuits, the wirings connected to the circuits, circuit elements, etc. may be changed, deleted, or added as necessary. It may be changed, deleted, or added.

[0429] The configuration shown in this embodiment can be used in appropriate combination with the configurations shown in other embodiments, examples, etc. It can be used in appropriate combination with the configurations shown in other embodiments, examples, etc.

[0430] (Embodiment 5) In this embodiment, an example of the chip 1200 on which the semiconductor device of the present invention is mounted is shown using FIG. 22. A plurality of circuits (systems) are mounted on the chip 1200. In this way, a plurality of circuits (systems) are mounted on the chip 1200. The technology of integrating multiple circuits (systems) onto one chip is sometimes called System on Chip: SoC. System on Chip:SoC

[0431] As shown in FIG. 22(A), chip 1200 includes a CPU (Central Processing Unit) 1211, a GPU (Graphics Processing Unit) 1212, one or more analog arithmetic units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, etc. ssing Unit Unit rollers works

[0432] Bumps (not shown) are provided on chip 1200 and are connected to the first surface of a Printed Circuit Board (PCB) 1201 as shown in FIG. 22(B). Also, a plurality of bumps 1202 are provided on the back surface of the first surface of PCB 1201 and are connected to a motherboard 1203. Printed Circuit Board:PCB The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for flash memory 1222. connected

[0433] The motherboard 1203 may be provided with storage devices such as a DRAM 1221 and a flash memory 1222. For example, the DOSRAM shown in the previous embodiment can be used for DRAM 1221. Also, for example, the NOSRAM shown in the previous embodiment can be used for flash memory 1222. devices AM NOSRAM

[0434] The CPU 1211 preferably has a plurality of CPU cores. Also, the GPU 1212 preferably has a plurality of GPU cores. Also, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Or, CP cores 212 A memory common to the CPU 1211 and the GPU 1212 may be provided in the chip 1200. The NOSRAM or DOSRAM described above can be used for this memory. Also, the GPU 1212 is suitable for parallel calculation of a large number of data and can be used for image processing and multiplication-accumulation operations. By providing an image processing circuit or a multiplication-accumulation operation circuit using the oxide semiconductor of the present invention in the GPU 1212, it becomes possible to execute image processing and multiplication-accumulation operations with low power consumption. In addition, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and the GPU 1212, and after the operation in the GPU 1212, the transfer of the operation result from the GPU 1212 to the CPU 1211 can be performed at high speed. The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The multiplication-accumulation operation circuit may be provided in the analog operation unit 1213. The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222. The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller is a micro...

[0435] Also, since the CPU 1211 and the GPU 1212 are provided on the same chip, the wiring between the CPU 1211 and the GPU 1212 can be shortened, and the data transfer from the CPU 1211 to the GPU 1212, the data transfer between the memories of the CPU 1211 and the GPU 1212, and after the operation in the GPU 1212, the transfer of the operation result from the GPU 1212 to the CPU 1211 can be performed at high speed. The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. The multiplication-accumulation operation circuit may be provided in the analog operation unit 1213.

[0436] The analog operation unit 1213 has one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. Also, the multiplication-accumulation operation circuit may be provided in the analog operation unit 1213. The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222. The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller is a micro...

[0437] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222. The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller is a micro...

[0438] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller is a micro... The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, and a controller. The controller is a micro... Including a mouse, keyboard, game controller, etc. Such an interface can use USB (Universal Serial Bus), HDMI (registered trademark) (H igh-Definition Multimedia Interface), etc.

[0439] The network circuit 1216 has a network circuit such as a LAN (Local Area Network). Also, it may have a circuit for network security

[0440] The above circuits (systems) can be formed on the chip 1200 in the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at low cost.

[0441] A PCB 1201 provided with a chip 1200 having a GPU 1212, a DRAM 122 1, and a motherboard 1203 provided with a flash memory 1222 can be called a GPU module 1204.

[0442] Since the GPU module 1204 has a chip 1200 using SoC technology, its size can be reduced. Also, since it is excellent in image processing, it is suitable for use i...

Claims

1. A transistor having a crystalline metal oxide, a gate, a source, and a drain, wherein the crystalline metal oxide has a first layer and a second layer, the first layer has a wider bandgap than the second layer, a crystal lattice is formed by the first layer and the second layer, when the temperature rises, the thickness of the first layer of the crystalline metal oxide in the c-axis direction increases, and when the temperature rises, the thickness of the second layer of the crystalline metal oxide in the c-axis direction decreases.

2. The transistor according to claim 1, wherein the crystalline metal oxide has a first metal oxide, a second metal oxide on the first metal oxide, and a third metal oxide on the second metal oxide, and the first metal oxide, the second metal oxide, and the third metal oxide each have the first layer and the second layer.

3. The transistor according to claim 2, wherein each of the first layer of the second metal oxide and the second layer of the second metal oxide is disposed substantially parallel to the surface of the second metal oxide on which it is formed. ​

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