Semiconductor device

Abstract

To provide a semiconductor device including a transistor having excellent electrical characteristics (e.g., on-state current, field-effect mobility, or frequency characteristics), and also to provide the semiconductor device including the transistor with high reliability.SOLUTION: A semiconductor device includes a dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a channel width direction of the transistor, a side surface of each of the first and second gate electrodes is at an outer side of a side surface of the oxide semiconductor film. The first or second gate electrode faces the side surface of the oxide semiconductor film via a gate insulating film provided between the first or second gate electrode and the oxide semiconductor film.SELECTED DRAWING: Figure 1

Description

[Technical field]

[0001] The present invention relates to a semiconductor device including a transistor having an oxide semiconductor film and a manufacturing method thereof. [Background technology]

[0002] A transistor (thin film transistor (TFT)) is made by using a semiconductor thin film formed on a substrate. The technology of constructing a transistor is attracting attention. It is widely used in electronic devices such as image display devices (display devices). Silicon-based semiconductor materials are widely known as semiconductor thin films that can be used, but other materials and Oxide semiconductors have been attracting attention as a new type of semiconductor.

[0003] For example, indium (In), gallium (Ga) and nickel are used as the active layer of a transistor. A transistor using an oxide semiconductor containing lead (Zn) has been disclosed (see Patent Document 1). .).

[0004] In addition, a technique for improving carrier mobility by forming an oxide semiconductor layer into a stacked structure is also known. are disclosed (see Patent Documents 2 and 3). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] JP 2006-165528 A [Patent Document 2] JP 2011-138934 A [Patent Document 3] JP 2011-124360 A Summary of the Invention [Problem to be solved by the invention]

[0006] One aspect of the present invention provides a semiconductor device having excellent transistors in terms of electrical characteristics (e.g., on-current, field-effect mobility, frequency characteristics, etc.). Or, it provides a semiconductor device having highly reliable transistors. Means for Solving the Problems One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor.

[0007] One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film.

[0008] One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor.

[0009] One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each located outside the side surface of the oxide semiconductor film. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. One aspect of the present invention is a transistor having a dual-gate structure in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode. In a double logarithmic graph showing the amount of change in the threshold voltage of the transistor with respect to the stress time, the intervals of the logarithmic scales on the horizontal axis and the vertical axis are equal, and the angle formed by the power approximation line of the amount of change in the threshold voltage with respect to the stress time and the line where the amount of change in the threshold voltage is 0 V is less than 30°, and the amount of change in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. Here, the stress time refers to the time when a load such as voltage and temperature is applied to the transistor. The slope of the power approximation line of the threshold voltage variation is equal to or less than 0.5, and the stress time is The semiconductor device has a threshold voltage variation of less than 0.2 V in 0.1 hour.

[0010] The first gate electrode or the second gate electrode is The gate electrode and the oxide semiconductor film are connected to each other through a gate insulating film provided between the gate electrode and the oxide semiconductor film. It may be opposite the side surface.

[0011] The first gate electrode and the second gate electrode are disposed outside the oxide semiconductor film with an insulating film interposed therebetween. It is also acceptable to have them face to face in this manner.

[0012] The transistor may have a channel etch structure. In addition, the distance between the pair of electrodes on the oxide semiconductor film is set to 1 μm or more and less than 4 μm. can be done.

[0013] The oxide semiconductor film is In, M (M is Al, Ga, Y, Zr, La, Ce, or Nd ) and Zn, and the atomic ratio of In is equal to or greater than the atomic ratio of M. It can be formed with a tapping target. Effect of the Invention

[0014] According to one embodiment of the present invention, the electrical characteristics (e.g., on-current, field effect mobility, frequency characteristics, etc.) It is possible to provide a semiconductor device having a transistor having excellent characteristics. According to one embodiment, a semiconductor device including a highly reliable transistor can be provided. [Brief description of the drawings]

[0015]

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Mode for Carrying Out the Invention

[0016] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments and examples shown below. Also in the embodiments and examples described below, the same parts or parts having the same functions are commonly used with the same reference numerals or the same hatching patterns between different drawings, and the repeated description thereof will be omitted.

[0017] In each figure described in this specification, the size, thickness, or area of ​​each component is indicated by the following formula: The figures may be exaggerated for clarity and are not necessarily limited to scale. stomach.

[0018] In addition, the terms "first," "second," "third," etc., used in this specification are used interchangeably to avoid confusion of components. The number is added for convenience and is not intended to be a numerical limit. The terms can be replaced with "second" or "third" as appropriate for explanation.

[0019] The function of the "source" and "drain" is to change the direction of the current during circuit operation. For this reason, in this specification, the terms "sauce" and "dressing" are used interchangeably. The terms "in" and "in" may be used interchangeably.

[0020] Voltage is the potential difference between two points, and potential is the electrostatic field at a certain point. This refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in a particle. Generally, the potential difference between a potential at a certain point and a reference potential (for example, ground potential) This is simply called potential or voltage, and potential and voltage are often used synonymously. Therefore, in this specification, unless otherwise specified, potential may be read as voltage. In this specification, voltage may be read as potential.

[0021] In this specification, when an etching process is performed after a photolithography process, The mask formed in the photolithography process is removed.

[0022] (Embodiment 1) In this embodiment, a semiconductor device which is an aspect of the present invention and a method for manufacturing the same will be described with reference to the drawings. Reference will be made to FIGS.

[0023] 2(A) to 2(C) show a top view and a cross-sectional view of a transistor 50 included in the semiconductor device. The transistor 50 shown in FIG. 2 is a channel etch type transistor. FIG. 2(A) is a top view of the transistor 50, FIG. 2(B) is a cross-sectional view taken along the dashed-dotted line A- B in FIG. 2(A), and FIG. 2(C) is a cross-sectional view taken along the dashed-dotted line C-D in FIG. 2(A). In addition, in FIG. 2(A), for clarity, the substrate 11, the gate insulating film 17, the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, etc. are omitted. The transistor 50 shown in FIGS. 2(B) and 2(C) includes a gate electrode 15 provided on the substrate 11, a gate insulating film 17 formed on the substrate 11 and the gate electrode 15, an oxide semiconductor film 18 overlapping the gate electrode 15 with the gate insulating film 17 therebetween, a pair of electrodes 21 and 22 in contact with the oxide semiconductor film 18, a protective film 26 on the gate insulating film 17, the oxide semiconductor film 18, and the pair of electrodes 21 and 22, and a gate electrode 29 overlapping the oxide semiconductor film 18 with the protective film 26 therebetween. Note that the protective film 26 includes the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25.

[0024] The transistor 50 shown in this embodiment has a plurality of gate electrodes and is a dual-gate structure transistor having an oxide semiconductor film 18 between the gate electrodes. In the channel width direction shown in FIG. 2(C), the end portion of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 overlaps the oxide through the protective film 26. semiconductor film 18 through the protective film 26. The transistor 50 shown in this embodiment has a plurality of gate electrodes and is a dual-gate structure transistor having an oxide semiconductor film 18 between the gate electrodes. In the channel width direction shown in FIG. 2(C), the end portion of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 overlaps the oxide semiconductor film 18 through the protective film 26. The transistor 50 shown in this embodiment has a plurality of gate electrodes and is a dual-gate structure transistor having an oxide semiconductor film 18 between the gate electrodes. In the channel width direction shown in FIG. 2(C), the end portion of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 overlaps the oxide semiconductor film 18 through the protective film 26.

[0025] The transistor 50 shown in this embodiment has a plurality of gate electrodes and is a dual-gate structure transistor having an oxide semiconductor film 18 between the gate electrodes. In the channel width direction shown in FIG. 2(C), the end portion of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 overlaps the oxide semiconductor film 18 through the protective film 26. In the channel width direction shown in FIG. 2(C), the end portion of the gate electrode 29 is located outside the oxide semiconductor film 18. Alternatively, in the channel width direction, the gate electrode 29 overlaps the oxide semiconductor film 18 through the protective film 26. It faces the side surface of the semiconductor film 18. Or, in the channel width direction, on the outside of the oxide semiconductor film 18, the gate electrode 15 and the gate electrode 29 face each other with the gate insulating film 17 and the protective film 26 therebetween.

[0026] FIG. 2(D) is an enlarged view of the broken line 30 in FIG. 2(C). Using FIG. 2(D), the positions of the ends of the gate electrode 15, the oxide semiconductor film 18, and the gate electrode 29 will be described.

[0027] Here, as shown in FIG. 2(D), assuming that the distance between the end of the oxide semiconductor film 18 and the end of the gate electrode 29 is d and the thickness of the protective film 26 is t, the distance d between the end of the oxide semiconductor film 18 and the end of the gate electrode 29 is preferably equal to or less than the thickness t of the protective film 26. By making the distance d between the end of the oxide semiconductor film 18 and the end of the gate electrode 29 equal to or less than the thickness t of the protective film 26, it is possible to affect the electric field of the gate electrode 29 at the end of the oxide semiconductor film 18, and the entire region including the end of the oxide semiconductor film 18 can function as a channel.

[0028] At the end of the oxide semiconductor film processed by etching or the like, defects are formed due to damage during processing, and contamination occurs due to impurity adhesion or the like. For this reason, when stress such as an electric field is applied, the end of the oxide semiconductor film becomes easily activated and tends to become n-type (low resistance). Therefore, in this embodiment, at the end of the oxide semiconductor film 18 overlapping with the gate electrode 15, n-type formation becomes easy. When the n-type formed end is provided between the pair of electrodes 21 and 22, this region becomes a carrier path, and a parasitic channel is formed. However, as shown in FIG. 2(C), outside the oxide semiconductor film 18, the gate Since the end of the gate electrode 29 is positioned, generation of a parasitic channel in or near the side surface of the oxide semiconductor film 18 is suppressed by the influence of the electric field of the gate electrode 29. As a result, a transistor with excellent electrical characteristics is obtained, in which the increase in the drain current at the threshold voltage is steep.

[0029] In addition, by providing the gate electrode 15 and the gate electrode 29, and further by setting the gate electrode 15 and the gate electrode 29 to the same potential, the region where carriers flow in the oxide semiconductor film 18 becomes larger in the film thickness direction, so that the amount of movement of carriers increases. As a result, the on-current of the transistor 50 increases and the field-effect mobility becomes higher.

[0030] Further, by having the gate electrode 15 and the gate electrode 29, each has a function of shielding an external electric field, so that charges such as charged particles provided between the substrate 11 and the gate electrode 15 and on the gate electrode 29 do not affect the oxide semiconductor film 18. As a result, deterioration in a stress test (for example, a -GBT (Gate Bias-Temperature) stress test in which a negative charge is applied to the gate) is suppressed, and fluctuations in the turn-on voltage of the on-current at different drain voltages can be suppressed. Note that this effect occurs when the gate electrode 15 and the gate electrode 29 are at the same potential or different potentials. (For example, a -GBT (Gate Bias-Temperature) stress test in which a negative charge is applied to the gate)

[0031] Note that the BT stress test is a type of acceleration test, and changes in the characteristics of a transistor (that is, secular changes) that occur due to long-term use can be evaluated in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is used to examine reliability. This becomes an important indicator. Before and after the BT stress test, the smaller the variation in the threshold voltage, , the more reliable the transistor can be said to be.

[0032] Also, by having the gate electrode 15 and the gate electrode 29 and setting the gate electrode 15 and the gate electrode 29 to the same potential, the variation in the threshold voltage is reduced. Therefore, the variation in the electrical characteristics among a plurality of transistors is also reduced at the same time.

[0033] Also, for the transistor 50, the variation in the threshold voltage before and after the +GBT stress test in which a positive charge is applied to the gate is small.

[0034] In the transistor 50 shown in this embodiment, a power approximation line L1 representing the variation in the threshold voltage (ΔVth ) with respect to the stress time is shown in FIG. 1 before and after the gate BT stress test in which a positive charge is applied to the gate. Note that when the test time (stress time) and the variation in the threshold voltage are plotted on a graph, the plotted values can be approximated by a power approximation line, and the power approximation line becomes a straight line on a log-log graph. In FIG. 1, FIG. 1 is a log-log graph, the horizontal axis represents the logarithm of the stress time, and the vertical axis represents the logarithm of the variation in the threshold voltage. . Also, as the conditions of the stress test, the substrate temperature is set to 60° C., the measurement environment is under a dark room (dark environment), and +30 V is applied to the gate voltage to apply stress to the transistor for an arbitrary time, for example, 1 hour.

[0035] In FIG. 1, since the power approximation line L1 is a straight line on the log-log graph, when the interval of the logarithmic scales on the horizontal axis and the vertical axis is equal, the power approximation line L in the transistor 50 shown in this embodiment 1 and the straight line when there is no variation in the threshold voltage with respect to the stress time (ΔVth is 0 V) , that is, the angle θ formed with the straight line L2 with a slope of 0 shown by the broken line in FIG. 1 is less than 30 degrees, or less than 25 degrees. Note that the equal intervals of the logarithmic scales on the horizontal and vertical axes means that, for example, on the horizontal axis the interval from 0.01 hour to 0.1 hour when the stress time becomes 10 times, and on the vertical axis, the interval from 0.01 V to 0.1 V when ΔV th becomes 10 times is equal.

[0036] Note that the smaller the magnitude of the angle θ, the smaller the variation in the threshold voltage due to aging, and it is a highly reliable transistor.

[0037] Also, in FIG. 1, when the horizontal axis is x and the vertical axis is y, the power approximation line can be expressed by Equation 1 . Note that b and C are constants, and b corresponds to the slope of the power approximation line.

[0038]

Equation

[0039] The slope b of the power approximation line L1 in the transistor 50 shown in this embodiment is 0.5 V / hr or less, or 0.4 V / hr or less, and Δ Vth when the stress time is 0.1 hour is less than 0.2 V, or less than 0.5 V.

[0040] The smaller the slope b of the power approximation line L1, the smaller the variation in the threshold voltage due to aging, and it is a highly reliable transistor. Also, the smaller ΔVth is when the stress time is 0.1 hour, the higher the reliability of the transistor at the initial stage of operation. As a result, the slope b of the power approximation line L1 is 0.5 V / hr or less, or 0.4 V / hr or less, and the stress When the time is 0.1 hour, ΔVth is less than 0.2 V or less than 0.5 V, and the transistor has high reliability.

[0041] In FIG. 2(A), the width of the oxide semiconductor film 18 is larger than the width of the gate electrode 15 per channel length direction. However, as in the transistor 51 shown in FIG. 3(A), the width of the gate electrode 15 can be made larger than the width of the oxide semiconductor film 18 per channel length direction. As a result, since it is possible to shield the irradiation of light from the substrate 11 side with the gate electrode 15, fluctuations in the electrical characteristics of the transistor 51 can be suppressed. Note that FIG. 3(A) is a top view of the transistor 51, FIG. 3(B) is a cross-sectional view taken along the dashed line A - B in FIG. 3(A), and FIG. 3(C) is a cross-sectional view taken along the dashed line C - D in FIG. 3(A).

[0042] In the present embodiment, the gate electrode 15 and the gate electrode 29 are connected and at the same potential. However, the gate electrode 15 and the gate electrode 29 may not be connected and different potentials may be applied thereto.

[0043] Details of other configurations of the transistor 50 will be described below.

[0044] There is no significant limitation on the material of the substrate 11, etc., but it is necessary to have at least heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 11. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI substrates, etc. can be applied, and those in which semiconductor elements are provided on these substrates ​​​​​​​​​​​, it may be used as the substrate 11. When using a glass substrate as the substrate 11, the 6th generation (1500mm×1850mm), 7th generation (1870mm×2200mm), 8th generation (2200mm×2400mm), 9th generation (2400mm×2800mm), 10th generation (2950mm×3400mm), etc. By using a large - area substrate, a large - sized display device can be manufactured.

[0045] Further, as the substrate 11, a flexible substrate may be used, and the transistor 50 may be directly formed on the flexible substrate. Alternatively, a release layer may be provided between the substrate 11 and the transistor 50. After partially or completely completing a semiconductor device on the release layer, it can be separated from the substrate 11 and used for transfer to another substrate. At this time, the transistor 50 can also be transferred to a substrate with poor heat resistance or a flexible substrate.

[0046] The gate electrode 15 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above - mentioned metal elements as components, or an alloy combining the above - mentioned metal elements. Further, a metal element selected from any one or more of manganese and zirconium may be used. Also, the gate electrode 15 may have a single - layer structure or a laminated structure of two or more layers. For example, a single - layer structure of an aluminum film containing silicon, a two - layer structure in which an aluminum film is laminated on a titanium film, a two - layer structure in which a titanium film is laminated on a titanium nitride film, a two - layer structure in which a tungsten film is laminated on a titanium nitride film, a two - layer structure in which a tungsten film is laminated on a tantalum nitride film or a tungsten nitride film, a two - layer structure in which a copper film is laminated on a titanium film, a titanium film, and an aluminum film laminated on the titanium film ​ There is a three-layer structure or the like in which layers are stacked and a titanium film is further formed thereon. Also, on aluminum, a film of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium, or an alloy film or a nitride film formed by combining a plurality thereof may be used.

[0047] Further, the gate electrode 15 can also be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide added with silicon oxide, etc. Also, a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element can also be adopted.

[0048] The gate insulating film 17 may be formed of, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide or a Ga-Zn based metal oxide, silicon nitride, etc., and may be provided in a laminated or single layer form.

[0049] Also, as the gate insulating film 17, hafnium silicate (HfSiO x ), hafnium silicate added with nitrogen (HfSi O x y N z ), hafnium aluminate added with nitrogen (HfAl O x y N z ), hafnium oxide, yttrium oxide, etc., which are high- k materials, can be used to reduce the gate leakage of the transistor.

[0050] The thickness of the gate insulating film 17 is 5 nm or more and 400 nm or less, 10 nm or more and 300 nm or less or 50 nm or more and 250 nm or less.

[0051] The oxide semiconductor film 18 typically includes an In-Ga oxide film, an In-Zn oxide film, In -M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd).

[0052] When the oxide semiconductor film 18 is an In-M-Zn oxide film, when the sum of In and M is 100 atomic%, the atomic ratio of In to M is such that In is 25 atomic% or more and M is less than 75 atomic%, or In is 34 atomic% or more and M is 6 less than 66 atomic%.

[0053] The oxide semiconductor film 18 has an energy gap of 2 eV or more, 2.5 eV or more, or 3 eV or more. Thus, by using an oxide semiconductor with a wide energy gap, the off-current of the transistor 50 can be reduced.

[0054] The thickness of the oxide semiconductor film 18 is 3 nm or more and 200 nm or less, 3 nm or more and 100 nm or less or 3 nm or more and 50 nm or less.

[0055] When the oxide semiconductor film 18 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, C e, or Nd), the atomic ratio of the metal elements of the sputtering target used to form the In-M-Zn oxide preferably satisfies In ≥ M and Zn ≥ M. With such an atomic ratio of the metal elements of the sputtering target, In:M:Zn = 1:1 :1 and In:M:Zn = 3:1:2 are preferred. Note that for the formed oxide semiconductor film 18 The atomic ratio includes, as an error, plus or minus 40% variation in the atomic ratio of the metal elements contained in the above sputtering target. In addition, when the content of In in the oxide semiconductor film 18 is high, the on-current of the transistor increases and the field-effect mobility increases. For this reason, by forming the oxide semiconductor film 18 using a sputtering target of In-M-Zn oxide with an atomic ratio of metal elements of In:M:Zn = 3:1:2, a transistor with excellent electrical characteristics can be fabricated. As the oxide semiconductor film 18, an oxide semiconductor film with a low carrier density is used. For example, the oxide semiconductor film 18 has a carrier density of 1×10 per cm or less, 1×10

[0056] per cm or less, or 1×10 17 per cm 3 or less, and an oxide semiconductor film with such a carrier density is used. 15 It should be noted that the present invention is not limited to these, and an oxide semiconductor film with an appropriate composition may be used according to the required semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. Also, in order to obtain the required semiconductor characteristics of the transistor, it is preferable that the carrier density, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. of the oxide semiconductor film 18 are appropriate. In addition, by using an oxide semiconductor film with a low impurity concentration and a low defect level density as the oxide semiconductor film 18, a transistor with even more excellent electrical characteristics can be fabricated. 3 13 3 11 3

[0057]

[0058] ​​​​​​​​​​​​​It is preferable. Here, the impurity concentration is low and the density of defect levels is low (with few oxygen deficiencies). This is called high-purity intrinsic or substantially high-purity intrinsic. With high-purity intrinsic or substantially high-purity intrinsic a certain oxide semiconductor may have few carrier generation sources, so the carrier density can be lowered In some cases. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film is less likely to have an electrical characteristic (also called normally-on) in which the threshold voltage becomes negative In addition, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has a low density of defect levels so the trap level density may also be low. Also, an oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has an extremely small off-current. Even for an element with a channel width of 1×10 6 μm and a channel length L of 10 μm, when the voltage between the source electrode and the drain electrode (drain voltage) is in the range of 1 V to 10 V, the off-current can be below the measurement limit of a semiconductor parameter analyzer that is, 1×10 -13 A or less. Therefore, a transistor in which a channel region is formed in the oxide semiconductor film may have small electrical characteristic variations and become a highly reliable transistor. Note that the charge trapped in the trap levels of the oxide semiconductor film takes a long time to disappear and may behave like a fixed charge. Therefore, a transistor in which a channel region is formed in an oxide semiconductor film with a high trap level density may have unstable electrical characteristics. Examples of impurities include hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc. The hydrogen contained in the oxide semiconductor film reacts with the oxygen bonded to the metal atoms to form water, and at the same time

[0059] ​An oxygen vacancy is formed in the lattice from which oxygen has desorbed (or the portion from which oxygen has desorbed). When hydrogen enters into the oxygen vacancy electrons may be generated as carriers. In addition, when a part of hydrogen binds to oxygen that binds to a metal atom, electrons may be generated as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. become.

[0060] For this reason, it is preferable that the hydrogen in the oxide semiconductor film 18 is reduced as much as possible. Specifically in the oxide semiconductor film 18, the hydrogen concentration obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry) is 5×10 19 atoms / cm 3 or less, 1×10 19 atoms / cm 3 or less, 5×10 18 atoms / cm 3 or less, 1×10 18 atoms / cm 3 or less, 5×10 17 at oms / cm 3 or less, or 1×10 16 atoms / cm 3 or less.

[0061] When silicon or carbon, which is one of the group 14 elements, is contained in the oxide semiconductor film 18 the oxygen vacancies in the oxide semiconductor film 18 increase and it becomes n-type. For this reason, the concentration of silicon or carbon (the concentration obtained by secondary ion mass spectrometry ) in the oxide semiconductor film 18 is 2×10 18 atoms / cm 3 or less, or 2×10 17 atoms / cm 3 or less. down.

[0062] In the oxide semiconductor film 18, the concentration of an alkali metal or an alkaline earth metal obtained by secondary ion mass spectrometry is set to 1×10 atoms / cm 18 or less, or 2× 3 10 atoms / cm 16 or less. When an alkali metal and an alkaline earth metal are combined with an oxide semiconductor, carriers may be generated, and the off-current of the transistor may increase. Therefore, it is preferable to reduce the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor film 18. 3 When nitrogen is contained in the oxide semiconductor film 18, electrons as carriers are generated, the carrier density increases, and it tends to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen tends to have normally-on characteristics. Therefore, in the oxide semiconductor film, it is preferable that nitrogen is reduced as much as possible. For example, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5×10 atoms / cm or less. The oxide semiconductor film 18 may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example,

[0063] CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect energy levels, and CAAC-OS has the lowest density of defect energy levels. In the non-single crystal structure, the amorphous structure has the highest density of defect energy levels, and CAAC-OS has the lowest density of defect energy levels. In the oxide semiconductor film 18, the nitrogen concentration obtained by secondary ion mass spectrometry is preferably 5×10 18 atoms / cm 3 or less.

[0064] The oxide semiconductor film 18 may have, for example, a non-single crystal structure. The non-single crystal structure includes, for example, CAAC-OS (C Axis Aligned Crystalline Oxide Semiconductor) described later, a polycrystalline structure, a microcrystalline structure described later, or an amorphous structure. In the non-single crystal structure, the amorphous structure has the highest density of defect energy levels, and CAAC-OS has the lowest density of defect energy levels. In the non-single crystal structure, the amorphous structure has the highest density of defect energy levels, and CAAC-OS has the lowest density of defect energy levels.

[0065] The oxide semiconductor film 18 may have, for example, an amorphous structure. The oxide semiconductor film having an amorphous structure has, for example, a disordered atomic arrangement and no crystal component. Or, the oxide film having an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0066] Note that the oxide semiconductor film 18 may be a mixed film having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region . The mixed film may have, for example, any two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Also , the mixed film may have, for example, a laminated structure of any two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region . In some cases, there is such a situation. Also , the mixed film may have, for example, a laminated structure of any two or more regions of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region . In some cases, there is such a situation.

[0067] The pair of electrodes 21 and 22 are used as a single-layer structure or a laminated structure of a simple metal made of aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy having this as a main component. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which an aluminum film is laminated on a titanium film, a two-layer structure in which an aluminum film is laminated on a tungsten film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a titanium film, a two-layer structure in which a copper film is laminated on a tungsten film, a titanium film or a titanium nitride film and, on the titanium film or the titanium nitride film, an aluminum film or a copper film is laminated, and further on that, a titanium film or a titanium nitride film is formed, a three-layer structure, a molybdenum film or a molybdenum nitride film and, on that molybdenum film or molybdenum nitride film, an aluminum film or a copper film is laminated, and further on that, a titanium film or a titanium nitride film is formed, a three-layer structure, a molybdenum film or a molybdenum nitride film and, on that molybdenum film or molybdenum nitride film, an aluminum film or a copper film is laminated, and further on that, a titanium film or a titanium nitride film is formed, a three-layer structure, a molybdenum film or a molybdenum nitride film and, An aluminum film or a copper film is laminated on a molybdenum film or a molybdenum nitride film, and a three-layer structure or the like is formed by further forming a molybdenum film or a molybdenum nitride film thereon. In addition, a transparent conductive material containing indium oxide, tin oxide, or zinc oxide may be used. The oxide insulating film 23 is an oxide insulating film that permeates oxygen. The oxide insulating film 23

[0068] also functions as a damage relaxation film for the oxide semiconductor film 18 when forming the oxide insulating film 24 formed later.

[0069] As the oxide insulating film 23, a silicon oxide film, a silicon oxynitride film, etc. with a thickness of 5 nm or more and 150 nm or less, or 5 nm or more and 50 nm or less can be used. In this specification, the silicon oxynitride film refers to a film having a higher oxygen content than nitrogen in its composition, and the silicon nitride oxide film refers to a film having a higher nitrogen content than oxygen in its composition.

[0070] In addition, the oxide insulating film 23 preferably has a small amount of defects. Typically, by ESR measurement, the spin density of the signal appearing at g = 2.001 derived from the dangling bonds of silicon is 3×10 17 spins / cm 3 or less. This is because if the defect density in the oxide insulating film 23 is high, oxygen will bind to the defects, resulting in a decrease in the oxygen permeation amount in the oxide insulating film 2 3.

[0071] In addition, it is preferable that the amount of defects at the interface between the oxide insulating film 23 and the oxide semiconductor film 18 is small. Typically, by ESR measurement, g = 1 derived from the defects of the oxide semiconductor film 18 The spin density of the signal appearing at 0.93 is 1×10 17 spins / cm 3 Hereinafter, it is preferably further detected to be below the lower limit.

[0072] In the oxide insulating film 23, all the oxygen that has entered the oxide insulating film 23 from the outside does not move to the outside of the oxide insulating film 23 and some oxygen remains in the oxide insulating film 23. Also, when oxygen enters the oxide insulating film 23 and the oxygen contained in the oxide insulating film 23 moves to the outside of the oxide insulating film 23, oxygen movement may occur in the oxide insulating film 23. When an oxide insulating film that permeates oxygen is formed as the oxide insulating film 23, the oxygen desorbed from the oxide insulating film 24 provided on the oxide insulating film 23 can be moved to the oxide semiconductor film 18 through the oxide insulating film 23. The oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23. The oxide insulating film 24 is formed using an oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition desorbs a part of the oxygen by heating. The oxide insulating film containing more oxygen than oxygen that satisfies the stoichiometric composition has an oxygen desorption amount in terms of oxygen atoms of 1.0×10 or more, or 3.0×10

[0073] The oxide insulating film 24 is an oxide insulating film having a thickness of 30 nm or more and 500 nm or less, or 50 nm or more

[0074]

[0075] atoms 18 / cm / cm 3 or more, or 3.0×10 20 atoms / cm 3 or more.

[0075] The oxide insulating film 24 has a thickness of 30 nm or more and 500 nm or less, or 50 nm or more ​Silicon oxide films, silicon oxynitride films, etc. with a thickness of 400 nm or less can be used.

[0076] In addition, the oxide insulating film 24 preferably has a small amount of defects. Typically, by ESR measurement the spin density of the signal appearing at g = 2.001 derived from the dangling bonds of silicon is 1.5×10 18 spins / cm 3 less than, and more preferably 1×10 18 spins / cm 3 or less. Note that since the oxide insulating film 24 is separated from the oxide semiconductor film 18, it may have a higher defect density than the oxide insulating film 23. That's okay.

[0077] Furthermore, by providing a nitride insulating film 25 having a blocking effect for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc. on the oxide insulating film 24, it is possible to prevent the diffusion of oxygen from the oxide semiconductor film 18 to the outside and the intrusion of hydrogen, water, etc. from the outside into the oxide semiconductor film 18. Examples of the nitride insulating film include a silicon nitride film, a silicon oxynitride film, an aluminum nitride film, an aluminum oxynitride film, etc. Instead of the nitride insulating film having a blocking effect for oxygen, hydrogen, water, alkali metals, alkaline earth metals, etc., an oxide insulating film having a blocking effect for oxygen, hydrogen, water, etc. may be provided. Examples of the oxide insulating film having a blocking effect for oxygen, hydrogen, water, etc. include an aluminum oxide film, an aluminum oxynitride film, a gallium oxide film, a gallium oxynitride film, a yttrium oxide film, a yttrium oxynitride film, a hafnium oxide film, a hafnium oxynitride film, etc.

[0078] Note that the configuration of the protective film 26 is not limited to the above configuration, and may be appropriately a single layer or a laminate of an oxide insulating film or a nitride insulating film, or a laminate structure such as two layers or four layers may be appropriately used.

[0079] Next, the manufacturing method of the transistor 50 shown in FIG. 2 will be described with reference to FIG. 4.

[0080] As shown in FIG. 4(A), a gate electrode 15 is formed on a substrate 11, and a gate insulating film 17 is formed on the gate electrode 15.

[0081] Here, a glass substrate is used as the substrate 11.

[0082] The method for forming the gate electrode 15 is shown below. First, a conductive film is formed by a sputtering method, a CVD method, an evaporation method, etc., and a mask is formed by a photolithography process using a first photomask on the conductive film. Next, a part of the conductive film is etched using the mask to form the gate electrode 15. After that, the mask is removed.

[0083] Note that the gate electrode 15 may be formed by an electroplating method, a printing method, an inkjet method, etc. instead of the above formation method.

[0084] Here, a tungsten film with a thickness of 200 nm is formed by a sputtering method. Next, a mask is formed by a photolithography process, and the tungsten film is dry-etched using the mask to form the gate electrode 15.

[0085] The gate insulating film 17 is formed by a sputtering method, a CVD method, an evaporation method, etc.

[0086] ​​​​​​​​When forming the gate insulating film 17 as a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film, it is preferable to use a depositable gas containing silicon and an oxidizing gas as raw material gases. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, and the like. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, and the like.

[0087] When forming the gate insulating film 17 as a gallium oxide film, it can be formed by using the MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0088] Here, as the gate insulating film 17, a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm are laminated and formed. The silicon nitride film is formed by a plasma CVD method using silane, nitrogen, and ammonia as raw material gases. The silicon oxynitride film is formed by a plasma CVD method using silane and nitrous oxide as raw material gases.

[0089] Next, as shown in FIG. 4(B), an oxide semiconductor film 18 is formed on the gate insulating film 17.

[0090] The method for forming the oxide semiconductor film 18 will be described below. An oxide semiconductor film that will become the oxide semiconductor film 18 is formed on the gate insulating film 17. Next, after forming a mask by a photolithography process using a second photomask on the oxide semiconductor film, a part of the oxide semiconductor film is etched using the mask to form the element-separated oxide semiconductor film 18 as shown in FIG. 4(B). After that, the mask is removed.

[0091] The oxide semiconductor film that will later become the oxide semiconductor film 18 can be formed using a sputtering method, a coating method, a pulsed laser deposition method, a laser ablation method, or the like.

[0092] When forming an oxide semiconductor film by a sputtering method, a power supply device for generating plasma can appropriately use an RF power supply device, an AC power supply device, a DC power supply device, or the like.

[0093] The sputtering gas can appropriately use a mixed gas of a noble gas and oxygen, a noble gas (typically argon), oxygen, or the like. In the case of a mixed gas of a noble gas and oxygen, it is preferable to increase the gas ratio of oxygen with respect to the noble gas.

[0094] Also, the target can be appropriately selected according to the composition of the oxide semiconductor film to be formed .

[0095] In order to obtain an oxide semiconductor film that is highly pure intrinsic or substantially highly pure intrinsic, not only is it necessary to evacuate the chamber to a high vacuum, but also to purify the sputtering gas to a high purity. The oxygen gas or argon gas used as the sputtering gas should be a gas purified to a dew point of -40°C or lower, -80°C or lower, -100°C or lower, or -120°C or lower, so as to prevent as much as possible the incorporation of moisture and the like into the oxide semiconductor film. Here, an In-Ga-Zn oxide film with a thickness of 35 nm is formed as an oxide semiconductor film by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 3:1:2) and

[0096] oxygen as the sputtering gas. Next, a mask is placed on the oxide semiconductor film Form it, and by selectively etching a part of the oxide semiconductor film, the oxide semiconductor film 18 is formed.

[0097] Next, as shown in FIG. 4(C), a pair of electrodes 21 and 22 are formed.

[0098] The method for forming the pair of electrodes 21 and 22 is shown below. First, a conductive film is formed by a sputtering method, CVD method, evaporation method, or the like. Next, a mask is formed on the conductive film by a photolithography process using a third photomask. Next, the conductive film is etched using the mask to form a pair of electrodes 21 and 22. After that, the mask is removed. using the mask to etch the conductive film to form a pair of electrodes 21 and 22. After that, the mask is removed. Here, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm are sequentially laminated by a sputtering method. Next, a mask is formed on the titanium film by a photolithography process, and the tungsten film, aluminum film, and titanium film are dry-etched using the mask to form a pair of electrodes 21 and 22.

[0099] Here, a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm are sequentially laminated by a sputtering method. Next, a mask is formed on the titanium film by a photolithography process, and the tungsten film, aluminum film, and titanium film are dry-etched using the mask to form a pair of electrodes 21 and 22. Next, as shown in FIG. 4(D), an oxide insulating film 23 is formed on the oxide semiconductor film 18 and the pair of electrodes 21 and 22. Next, an oxide insulating film 24 is formed on the oxide insulating film 23. Next, as shown in FIG. 4(D), an oxide insulating film 23 is formed on the oxide semiconductor film 18 and the pair of electrodes 21 and 22. Next, an oxide insulating film 24 is formed on the oxide insulating film 23. Next, as shown in FIG. 4(D), an oxide insulating film 23 is formed on the oxide semiconductor film 18 and the pair of electrodes 21 and 22. Next, an oxide insulating film 24 is formed on the oxide insulating film 23.

[0100] Next, as shown in FIG. 4(D), an oxide insulating film 23 is formed on the oxide semiconductor film 18 and the pair of electrodes 21 and 22. Next, an oxide insulating film 24 is formed on the oxide insulating film 23. Next, as shown in FIG. 4(D), an oxide insulating film 23 is formed on the oxide semiconductor film 18 and the pair of electrodes 21 and 22. Next, an oxide insulating film 24 is formed on the oxide insulating film 23. is formed.

[0101] Note that after forming the oxide insulating film 23, it is preferable to continuously form the oxide insulating film 24 without exposing it to the atmosphere. After forming the oxide insulating film 23, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, the oxide insulating film 24 is continuously formed, so that the oxide insulating film 23 and the oxide insulating film 24 are formed. Note that after forming the oxide insulating film 23, it is preferable to continuously form the oxide insulating film 24 without exposing it to the atmosphere. After forming the oxide insulating film 23, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, the oxide insulating film 24 is continuously formed, so that the oxide insulating film 23 and the oxide insulating film 24 are formed. Note that after forming the oxide insulating film 23, it is preferable to continuously form the oxide insulating film 24 without exposing it to the atmosphere. After forming the oxide insulating film 23, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, the oxide insulating film 24 is continuously formed, so that the oxide insulating film 23 and the oxide insulating film 24 are formed. Note that after forming the oxide insulating film 23, it is preferable to continuously form the oxide insulating film 24 without exposing it to the atmosphere. After forming the oxide insulating film 23, without opening to the atmosphere, by adjusting one or more of the flow rate, pressure, high-frequency power, and substrate temperature of the source gas, the oxide insulating film 24 is continuously formed, so that the oxide insulating film 23 and the oxide insulating film 24 are formed. It is possible to reduce the impurity concentration and move the oxygen contained in the oxide insulating film 24 to the oxide semiconductor film 18, and it is possible to reduce the oxygen deficiency amount of the oxide semiconductor film 18.

[0102] A substrate placed in the evacuated processing chamber of a plasma CVD apparatus is held at 280°C or higher and 400 °C or lower, a source gas is introduced into the processing chamber to set the pressure in the processing chamber to 20 Pa or higher and 25 0 Pa or lower, or 100 Pa or higher and 250 Pa or lower, and high-frequency power is supplied to the electrode provided in the processing chamber. Under these conditions, a silicon oxide film or a silicon oxynitride film can be formed as the oxide insulating film 23.

[0103] As the source gas for the oxide insulating film 23, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Typical examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0104] By using the above conditions, an oxide insulating film that permeates oxygen can be formed as the oxide insulating film 23. In addition, by providing the oxide insulating film 23, it is possible to reduce the damage to the oxide semiconductor film 18 in the formation process of the subsequently formed oxide insulating film 24.

[0105] Note that the oxide insulating film 23 is formed by holding a substrate placed in the evacuated processing chamber of a plasma CVD apparatus at 280°C or higher and 400°C or lower, introducing a source gas into the processing chamber, and setting the pressure in the processing chamber to 100 Pa or higher and 250 Pa or lower, and supplying high-frequency power to the electrode provided in the processing chamber. ​​​​Under the condition of supply, as the oxide insulating film 23, a silicon oxide film or a silicon oxynitride film can be formed. film can be formed.

[0106] Under the film formation conditions, by setting the substrate temperature to the above temperature, the bonding force between silicon and oxygen becomes stronger. As a result, as the oxide insulating film 23, an oxide insulating film through which oxygen permeates, is dense, and is hard, typically, a silicon oxide film or a silicon oxynitride film having an etching rate of 10 nm / min or less, or 8 nm / min or less with respect to 0.5 wt% hydrofluoric acid at 25°C can be formed. oxide insulating film, typically, an etching rate with respect to 0.5 wt% hydrofluoric acid at 25°C is 10 nm / min or less, or 8 nm / min or less silicon oxide film or silicon oxynitride film can be formed. film can be formed.

[0107] Also, since the oxide insulating film 23 is formed while heating, hydrogen, water, etc. contained in the oxide semiconductor film 18 can be desorbed in this process. The hydrogen contained in the oxide semiconductor film 18 combines with oxygen radicals generated in the plasma to become water. Since the substrate is heated in the film formation process of the oxide insulating film 23, the water generated by the combination of oxygen and hydrogen desorbs from the oxide semiconductor film. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. oxide semiconductor film 18 can be desorbed. The hydrogen contained in the oxide semiconductor film 18 combines with oxygen radicals generated in the plasma to become water. Since the substrate is heated in the film formation process of the oxide insulating film 23, the water generated by the combination of oxygen and hydrogen desorbs from the oxide semiconductor film. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. hydrogen contained in the oxide semiconductor film 18 combines with oxygen radicals generated in the plasma to become water. Since the substrate is heated in the film formation process of the oxide insulating film 23, the water generated by the combination of oxygen and hydrogen desorbs from the oxide semiconductor film. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. oxide insulating film 23, the water generated by the combination of oxygen and hydrogen desorbs from the oxide semiconductor film. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. oxide semiconductor film 18 can be reduced. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. oxide semiconductor film 18 can be reduced. That is, by forming the oxide insulating film 23 by the plasma CVD method, the contents of water and hydrogen contained in the oxide semiconductor film 18 can be reduced. can be.

[0108] Also, since heating is performed in the process of forming the oxide insulating film 23, the heating time in the state where the oxide semiconductor film 18 is exposed is short, and the amount of oxygen desorbed from the oxide semiconductor film due to the heat treatment can be reduced. That is, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced. oxide semiconductor film 18 is short, and the amount of oxygen desorbed from the oxide semiconductor film due to the heat treatment can be reduced. That is, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced. oxide semiconductor film can be reduced. That is, the amount of oxygen vacancies contained in the oxide semiconductor film can be reduced. can be reduced.

[0109] Furthermore, by setting the pressure in the processing chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film The water content in the 23 is reduced, which reduces the variation in the electrical characteristics of the transistor 50. It is possible to reduce the threshold voltage and suppress the fluctuation of the threshold voltage.

[0110] In addition, by setting the pressure in the treatment chamber to 100 Pa or more and 250 Pa or less, the oxide insulating film 23 When forming the oxide semiconductor film 18, damage to the oxide semiconductor film 18 can be reduced. In particular, the amount of oxygen vacancies in the oxide insulating film 23 can be reduced. Alternatively, the deposition temperature of the oxide insulating film 24 to be formed later is increased, typically to 220° C. or higher. By setting the temperature at a low level, part of oxygen contained in the oxide semiconductor film 18 is released, and oxygen vacancies are formed. In addition, in order to improve the reliability of the transistor, the oxide insulating film 2 to be formed later is By using the film formation conditions for reducing the amount of defects in 4, the amount of oxygen desorption is easily reduced. As a result, it may be difficult to reduce oxygen vacancies in the oxide semiconductor film 18. The pressure in the processing chamber is set to 100 Pa or more and 250 Pa or less during the formation of the oxide insulating film 23. By reducing damage to the oxide semiconductor film 18 caused by the oxidation of the oxide insulating film 24, the oxide semiconductor film 18 can be prevented from being damaged. The oxygen vacancies in the oxide semiconductor film 18 can be reduced by the amount of oxygen desorption.

[0111] In addition, by increasing the amount of oxidizing gas to 100 times or more the amount of deposition gas containing silicon, The hydrogen content in the oxide insulating film 23 can be reduced. Since the amount of hydrogen mixed into the semiconductor film 18 can be reduced, the threshold voltage of the transistor can be reduced. The shift can be suppressed.

[0112] Here, the oxide insulating film 23 is formed by plasma deposition using silane and dinitrogen monoxide as raw material gases. A silicon oxynitride film with a thickness of 50 nm is formed by the plasma CVD method. Under these conditions, a silicon oxynitride film through which oxygen can permeate can be formed.

[0113] As the oxide insulating film 24, the substrate placed in the evacuated processing chamber of the plasma CVD apparatus is held at 180°C or higher and 280°C or lower, or 200°C or higher and 240°C or lower, and a raw material gas is introduced into the processing chamber so that the pressure in the processing chamber is 100 Pa or higher and 250 Pa or lower, or 100 Pa or higher and 200 Pa or lower, and a high-frequency power of 0.17 W / cm or higher and 0.5 W / cm or lower, or 0.25 W / cm or higher and 0.35 W / cm or lower is supplied to the electrode provided in the processing chamber, and a silicon oxide film or a silicon oxynitride film is formed under these conditions. 2 2 2 2

[0114] As the raw material gas for the oxide insulating film 24, it is preferable to use a depositable gas containing silicon and an oxidizing gas. Representative examples of the depositable gas containing silicon include silane, disilane, trisilane, silane fluoride, etc. Examples of the oxidizing gas include oxygen, ozone, nitrous oxide, nitrogen dioxide, etc.

[0115] As the film formation conditions for the oxide insulating film 24, by supplying the high-frequency power of the above power density in the processing chamber of the above pressure, the decomposition efficiency of the raw material gas in the plasma increases, the oxygen radicals increase, and the oxidation of the raw material gas proceeds, so the oxygen content in the oxide insulating film 24 becomes more than the stoichiometric composition. On the other hand, in the film formed at the above temperature, since the binding force between silicon and oxygen is weak, a part of the oxygen in the film desorbs due to the heat treatment in the subsequent process. As a result , contains more oxygen than oxygen that satisfies the stoichiometric composition, and a part of the oxygen is desorbed by heating An oxide insulating film can be formed. Further, an oxide insulating film 2 3 is provided on the oxide semiconductor film 18. Therefore, in the step of forming the oxide insulating film 24, the oxide insulating film 2 3 serves as a protective film for the oxide semiconductor film 18. As a result, while reducing damage to the oxide semiconductor film 18, it is possible to form the oxide insulating film 24 using high-frequency power with a high power density.

[0116] In addition, in the film formation conditions of the oxide insulating film 24, by increasing the flow rate of the deposition gas containing silicon with respect to the oxidizing gas, it is possible to reduce the amount of defects in the oxide insulating film 24 . Typically, by ESR measurement, the spin density of the signal appearing at g = 2.0 01 derived from the dangling bond of silicon is less than 6 × 10 spins / cm 17 spins / cm 3 , less than 3 × 10 17 s pins / cm 3 or less, or less than 1.5 × 10 17 spins / cm 3 An oxide insulating film with a small amount of defects can be formed. As a result, the reliability of the transistor can be improved .

[0117] Here, as the oxide insulating film 24, a silicon oxynitride film with a thickness of 400 nm is formed by plasma CVD method using silane and dinitrogen monoxide as raw material gases.

[0118] Next, a heat treatment is performed. The temperature of the heat treatment is typically 150°C or higher and 400°C or lower , 300°C or higher and 400°C or lower, or 320°C or higher and 370°C or lower.

[0119] ​​​The heat treatment can be carried out using an electric furnace, an RTA apparatus, etc. By using an RTA apparatus, it is possible to perform the heat treatment at a temperature equal to or higher than the distortion point of the substrate for a limited short time. Therefore, the heat treatment time can be shortened.

[0120] The heat treatment may be carried out in an atmosphere of nitrogen, oxygen, ultra-dry air (air with a water content of 20 ppm or less, 1 ppm or less, or 10 ppb or less), or a noble gas (argon, helium, etc.). It should be noted that it is preferable that the above nitrogen, oxygen, ultra-dry air, or noble gas does not contain hydrogen, water, etc.

[0121] By the heat treatment, a part of the oxygen contained in the oxide insulating film 24 can be moved to the oxide semiconductor film 18, and the oxygen deficiency amount contained in the oxide semiconductor film 18 can be further reduced.

[0122] Further, when the oxide insulating film 23 and the oxide insulating film 24 contain water, hydrogen, etc., if a nitride insulating film 25 having a function of blocking water, hydrogen, etc. is formed later and the heat treatment is carried out, the water, hydrogen, etc. contained in the oxide insulating film 23 and the oxide insulating film 24 will move to the oxide semiconductor film 18, and defects will occur in the oxide semiconductor film 18. However, by the heating, it is possible to desorb the water, hydrogen, etc. contained in the oxide insulating film 23 and the oxide insulating film 24, reduce the variation in the electrical characteristics of the transistor 50, and suppress the fluctuation of the threshold voltage.

[0123] In addition, by forming the oxide insulating film 24 on the oxide insulating film 23 while heating, it is possible to move oxygen to the oxide semiconductor film 18 and reduce the oxygen deficiency contained in the oxide semiconductor film 18. Therefore, it is not necessary to perform the heat treatment.​​​​​​​​​

[0124] Here, a heat treatment is performed at 350°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen.

[0125] Also, when forming a pair of electrodes 21 and 22, the oxide semiconductor film 18 is damaged by etching the conductive film, and oxygen deficiency occurs on the back channel (the side of the oxide semiconductor film 18 opposite to the surface facing the gate electrode 15) side of the oxide semiconductor film 18. However, by applying an oxide insulating film containing more oxygen than the stoichiometric composition to the oxide insulating film 24, it is possible to repair the oxygen deficiency generated on the back channel side by the heat treatment. As a result, the defects contained in the oxide semiconductor film 18 can be reduced, so that the reliability of the transistor 50 can be improved. Next, a nitride insulating film 25 is formed by a sputtering method, a CVD method, or the like.

[0126] When forming the nitride insulating film 25 by the plasma CVD method, it is preferable to set the substrate placed in the vacuum-exhausted processing chamber of the plasma CVD apparatus to 300°C or higher and 400°C or lower, or 320°C or higher and 370°C or lower, so that a dense nitride insulating film can be formed.

[0127] When forming a silicon nitride film as the nitride insulating film 25 by the plasma CVD method, it is preferable to use a depositable gas containing silicon, nitrogen, and ammonia as the source gases. By using a small amount of ammonia compared to nitrogen as the source gas, ammonia dissociates in the plasma and active species are generated. The active species are contained in the depositable gas containing silicon.

[0128] By using a small amount of ammonia compared to nitrogen as the source gas, ammonia dissociates in the plasma and active species are generated. The active species are contained in the depositable gas containing silicon. Break the bonds between silicon and hydrogen and the triple bond of nitrogen. As a result, the bond between silicon and nitrogen is promoted, the bond between silicon and hydrogen is reduced, the defects are reduced, and a dense silicon nitride film can be formed. On the other hand, in the source gas, if the amount of ammonia relative to nitrogen is large, the decomposition of each of the depositable gas containing silicon and nitrogen does not proceed, and the bond between silicon and hydrogen remains, the defects increase, and a rough silicon nitride film is formed. Therefore, in the source gas, it is preferable that the flow rate ratio of nitrogen to ammonia is 5 or more and 50 or less, or 10 or more and 50 or less.

[0129] Here, a silicon nitride film with a thickness of 100 nm is formed by plasma CVD method using silane, nitrogen, and ammonia as source gases.

[0130] Through the above steps, a protective film 26 composed of an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 can be formed.

[0131] Next, heat treatment may be performed. The temperature of the heat treatment is typically 150 °C or more and 40 0 °C or less, 300 °C or more and 400 °C or less, or 320 °C or more and 370 °C or less.

[0132] When connecting the gate electrode 15 and the gate electrode 29 to be formed later, here, openings are formed in the gate insulating film 17, the oxide insulating film 23, the oxide insulating film 24, and the nitride insulating film 25.

[0133] Next, as shown in FIG. 4(E), the gate electrode 29 is formed. The formation method of the gate electrode 29 is shown below. First, a conductive film is formed by sputtering method, CVD method, evaporation method, etc. ​​​​Next, a mask is formed by a photolithography process using a fourth photomask on the conductive film. Next, a part of the conductive film is etched using the mask to form the gate electrode 29. After that, the mask is removed.

[0134] Note that as shown in Fig. 3(C), the gate electrode 29 is formed such that the end portion thereof is positioned outside the oxide semiconductor film 18 in the channel width direction. Here, an indium tin oxide (hereinafter referred to as ITO) film having a 100 nm thick silicon oxide is formed by a sputtering method. Next, a mask is formed by a photolithography process, and the ITO film having silicon oxide is wet-etched using the mask to form the gate electrode 29. After that, heat treatment may be performed.

[0135] Through the above steps, the transistor 50 can be manufactured. Next, a mask is formed by a photolithography process, and the ITO film having silicon oxide is wet-etched using the mask to form the gate electrode 29. After that, heat treatment may be performed. Next, a mask is formed by a photolithography process, and the ITO film having silicon oxide is wet-etched using the mask to form the gate electrode 29. After that, heat treatment may be performed. Through the above steps, the transistor 50 can be manufactured.

[0136] Through the above steps, the transistor 50 can be manufactured.

[0137] A dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each positioned outside the side surface of the oxide semiconductor film, so that the electric field of the gate electrode 29 can affect the end portion of the oxide semiconductor film 18, and the entire portion including the end portion of the oxide semiconductor film 18 can function as a channel. A dual-gate transistor in which an oxide semiconductor film is provided between a first gate electrode and a second gate electrode, and in the channel width direction of the transistor, the side surfaces of the first gate electrode and the second gate electrode are each positioned outside the side surface of the oxide semiconductor film, so that the electric field of the gate electrode 29 can affect the end portion of the oxide semiconductor film 18, and the entire portion including the end portion of the oxide semiconductor film 18 can function as a channel. As a result, it is possible to increase the on-current of the transistor and enhance the field-effect mobility. As a result, it is possible to increase the on-current of the transistor and enhance the field-effect mobility. As a result, it is possible to increase the on-current of the transistor and enhance the field-effect mobility. As a result, it is possible to increase the on-current of the transistor and enhance the field-effect mobility. As a result, it is possible to increase the on-current of the transistor and enhance the field-effect mobility.

[0138] Also, the transistor shown in this embodiment has a first gate electrode and a second gate electrode. Since the gate electrodes have a gate insulating layer, each gate electrode can block an electric field from the outside. As a result, the deterioration of the stress test is suppressed and the on-current at different drain voltages is improved. This makes it possible to suppress fluctuations in the start-up voltage, resulting in a transistor with excellent electrical characteristics. In addition, a semiconductor device having high reliability can be obtained. can.

[0139] <Modification 1, Regarding the Undercoat Insulating Film> In the transistor 50 of this embodiment, the substrate 11 and the gate electrode A base insulating film can be provided between the electrodes 15. The base insulating film can be made of silicon oxide. Silicon oxide nitride, silicon nitride, silicon oxide nitride, gallium oxide, hafnium oxide Examples of the oxides include aluminum oxide, yttrium oxide, aluminum oxide nitride, etc. The insulating film materials are silicon nitride, gallium oxide, hafnium oxide, and yttrium oxide. By using aluminum oxide or the like, impurities, typically alkali metals, The diffusion of water, hydrogen, and the like into the oxide semiconductor film 18 can be suppressed.

[0140] The base insulating film can be formed by a sputtering method, a CVD method, or the like.

[0141] <Modification 2: Gate insulating film> In the transistor 50 according to this embodiment, a gate insulating film 17 may be stacked as necessary. The gate insulating film 17 may have a layer structure. explain.

[0142] As shown in FIG. 5A, the gate insulating film 17 is made of a nitride insulating film 17a and an oxide insulating film. 17b can have a stacked structure that is stacked in order from the gate electrode 15 side. By providing the nitride insulating film 17a on the gate electrode 15 side, impurities from the gate electrode 15, typically hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc., can be prevented from moving to the oxide semiconductor film 18.

[0143] Also, by providing the oxide insulating film 17b on the oxide semiconductor film 18 side, it is possible to reduce the density of defect energy levels at the interface between the gate insulating film 17 and the oxide semiconductor film 18. As a result, a transistor with less degradation of electrical characteristics can be obtained. Note that as the oxide insulating film 17 b, similar to the oxide insulating film 24, if it is formed using an oxide insulating film containing more oxygen than the stoichiometric composition, it is possible to further reduce the density of defect energy levels at the interface between the gate insulating film 17 and the oxide semiconductor film 18, which is more preferable.

[0144] As shown in FIG. 5(B), the gate insulating film 17 can have a stacked structure in which a nitride insulating film 17c with few defects, a nitride insulating film 17d with high hydrogen blocking property, and an oxide insulating film 17b are stacked in order from the gate electrode 15 side. By providing the nitride insulating film 17c with few defects as the gate insulating film 17, the breakdown voltage of the gate insulating film 17 can be improved. Also, by providing the nitride insulating film 17d with high hydrogen blocking property, hydrogen from the gate electrode 15 and the nitride insulating film 17c can be prevented from moving to the oxide semiconductor film 18.

[0145] An example of the manufacturing method of the nitride insulating films 17c and 17d shown in FIG. 5(B) is shown below. First ​​​​​​​A plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a source gas is used to form a silicon nitride film with few defects as the nitride insulating film 17c. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a silicon nitride film with a low hydrogen concentration and capable of blocking hydrogen is formed as the nitride insulating film 17d. By such a formation method, a nitride insulating film with few defects and having hydrogen blocking properties can be deposited to form the gate insulating film 17.

[0146] As shown in FIG. 5(C), the gate insulating film 17 has a stacked structure in which a nitride insulating film 17e with high impurity blocking properties, a nitride insulating film 17c with few defects, a nitride insulating film 17d with high hydrogen blocking properties, and an oxide insulating film 17b are stacked in this order from the gate electrode 15 side. By providing a nitride insulating film 17e with high impurity blocking properties as the gate insulating film 17, impurities from the gate electrode 15, typically hydrogen, nitrogen, alkali metals, or alkaline earth metals, etc., can be prevented from moving to the oxide semiconductor film 18.

[0147] An example of the manufacturing method of the nitride insulating films 17e, 17c, and 17d shown in FIG. 5(C) is shown below. First, a silicon nitride film with high impurity blocking properties is formed as the nitride insulating film 17e by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia as a source gas. Next, by increasing the flow rate of ammonia, a silicon nitride film with few defects is formed as the nitride insulating film 17c. Next, the source gas is switched to a mixed gas of silane and nitrogen, and a silicon nitride film with a low hydrogen concentration and capable of blocking hydrogen The SiN film is formed as the nitride insulating film 17d. By such a forming method, a gate insulating film 17 in which a nitride insulating film having few defects and having impurity blocking properties is laminated can be formed.

[0148] <Modification Example 3, Regarding a Pair of Electrodes> As the pair of electrodes 21 and 22 provided in the transistor 50 shown in this embodiment, a conductive material that easily binds to oxygen, such as tungsten, titanium, aluminum, copper, molybdenum, chromium, or tantalum, or an alloy, can be used. As a result, oxygen contained in the oxide semiconductor film 18 binds to the conductive material contained in the pair of electrodes 21 and 22, and an oxygen-deficient region is formed in the oxide semiconductor film 18. Also, in some cases, a part of the constituent elements of the conductive material forming the pair of electrodes 21 and 22 may be mixed into the oxide semiconductor film 18. As a result, as shown in FIG. 6, in the oxide semiconductor film 18, low-resistance regions 20a and 20b are formed in the vicinity of the region in contact with the pair of electrodes 21 and 22. The low-resistance regions 20a and 20b are in contact with the pair of electrodes 21 and 22 and are formed between the gate insulating film 17 and the pair of electrodes 21 and 22. Since the low-resistance regions 20a and 20b have high conductivity, it is possible to reduce the contact resistance between the oxide semiconductor film 18 and the pair of electrodes 21 and 22, and it is possible to increase the on-current of the transistor.

[0149] Alternatively, the pair of electrodes 21 and 22 may have a laminated structure of a conductive material that easily binds to the above oxygen and a conductive material that hardly binds to oxygen, such as titanium nitride, tantalum nitride, and ruthenium. By having such a laminated structure, at the interface between the pair of electrodes 21 and 22 and the oxide insulating film 23, ​​​​​​​​​​​​​​​It is possible to prevent oxidation of the pair of electrodes 21 and 22 and suppress an increase in the resistance of the pair of electrodes 21 and 22. It is possible to suppress an increase in resistance.

[0150] <Modification Example 4, Oxide Semiconductor Film> In the method for manufacturing the transistor 50 shown in this embodiment, after forming the pair of electrodes 21 and 22, the oxide semiconductor film 18 is exposed to plasma generated in an oxygen atmosphere, and oxygen can be supplied to the oxide semiconductor film 18. As the oxidation atmosphere, there are atmospheres such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. Further, in the plasma treatment, it is preferable to expose the oxide semiconductor film 18 to the plasma generated without applying a bias to the substrate 11 side. As a result, it is possible to supply oxygen without damaging the oxide semiconductor film 18 and reduce the amount of oxygen vacancies contained in the oxide semiconductor film 18. In addition, impurities remaining on the surface of the oxide semiconductor film 18, such as halogens such as fluorine and chlorine, can be removed by an etching process. Further, it is preferable to perform the plasma treatment while heating at 300°C or higher. Oxygen in the plasma combines with hydrogen contained in the oxide semiconductor film 18 to form water. Since the substrate is heated, the water desorbs from the oxide semiconductor film 18. As a result, the contents of hydrogen and water contained in the oxide semiconductor film 18 can be reduced. After forming the pair of electrodes 21 and 22, the oxide semiconductor film 18 is exposed to plasma generated in an oxygen atmosphere, and oxygen can be supplied to the oxide semiconductor film 18. As the oxidation atmosphere, there are atmospheres such as oxygen, ozone, nitrous oxide, and nitrogen dioxide. Further, in the plasma treatment, it is preferable to expose the oxide semiconductor film 18 to the plasma generated without applying a bias to the substrate 11 side. As a result, it is possible to supply oxygen without damaging the oxide semiconductor film 18 and reduce the amount of oxygen vacancies contained in the oxide semiconductor film 18. In addition, impurities remaining on the surface of the oxide semiconductor film 18, such as halogens such as fluorine and chlorine, can be removed by an etching process. Further, it is preferable to perform the plasma treatment while heating at 300°C or higher. Oxygen in the plasma combines with hydrogen contained in the oxide semiconductor film 18 to form water. Since the substrate is heated, the water desorbs from the oxide semiconductor film 18. As a result, the contents of hydrogen and water contained in the oxide semiconductor film 18 can be reduced. Oxygen in the plasma combines with hydrogen contained in the oxide semiconductor film 18 to form water. Since the substrate is heated, the water desorbs from the oxide semiconductor film 18. As a result, the contents of hydrogen and water contained in the oxide semiconductor film 18 can be reduced.

[0151] <Modification Example 5> The transistor 50 shown in this embodiment can desorb hydrogen, water, etc. contained in the oxide semiconductor film 18 by forming the oxide insulating film 23 while maintaining the substrate at 280°C or higher and 400°C or lower. On the other hand, after forming the oxide semiconductor film 18 shown in Fig. 4(B), 15 It is possible to desorb hydrogen, water, etc. contained in the oxide semiconductor film 18 by forming the oxide insulating film 23 while maintaining the substrate at 280°C or higher and 400°C or lower. On the other hand, after forming the oxide semiconductor film 18 shown in Fig. 4(B), 15 Above 0°C and less than the substrate warping point, 200°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower After performing the heat treatment, while maintaining the substrate at 180°C or higher and 260°C or lower, an oxide insulating film 23 may be formed. As a result, it is possible to further reduce the content of hydrogen, water, etc. contained in the oxide semiconductor film 18, and to fabricate a transistor with even better electrical characteristics can be achieved.

[0152] Note that the configurations and methods shown in this embodiment can be used in appropriate combination with the configurations and methods shown in other embodiments and examples

[0153] (Embodiment 2) In this embodiment, a semiconductor device having a transistor capable of further reducing the defect amount of the oxide semiconductor film will be described with reference to the drawings as compared with Embodiment 1. The transistor described in this embodiment is different in that it has a multilayer film in which an oxide semiconductor film is laminated as compared with Embodiment 1

[0154] FIG. 7 shows a top view and a cross-sectional view of a transistor 60 included in a semiconductor device. FIG. 7(A) is a top view of the transistor 60, FIG. 7(B) is a cross-sectional view taken along the dashed line A - B in FIG. 7(A), and FIG. 7(C) is a cross-sectional view taken along the dashed line C - D in FIG. 7(A). Note that in FIG. 7 (A), for clarity, the substrate 11, the gate insulating film 17, the oxide insulating film 23, the oxide insulating film 24, the nitride insulating film 25, etc. are omitted

[0155] The transistor 60 shown in FIGS. 7(A) to 7(C) includes a gate electrode 15 provided on a substrate 11, a gate insulating film 17, and, via the gate insulating film 17, overlaps with the gate electrode 15 ​​​​​​​​The multilayer film 20, a pair of electrodes 21 and 22 in contact with the multilayer film 20, the gate insulating film 17, the multilayer film 20, and the protective film 26 on the pair of electrodes 21 and 22, and the gate electrode 29 on the protective film 26, are included. The protective film 26 includes an oxide insulating film 23, an oxide insulating film 24, and a nitride insulating film 25 and functions as a gate insulating film.

[0156] In the transistor 60 shown in this embodiment, the multilayer film 20 includes an oxide semiconductor film 18 and an oxide semiconductor film 19. That is, the multilayer film 20 has a two-layer structure. Also, a part of the oxide semiconductor film 18 functions as a channel region. Further, an oxide insulating film 23 is formed so as to be in contact with the multilayer film 20. An oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Also, an oxide insulating film 24 is formed so as to be in contact with the oxide insulating film 23.

[0157] The oxide semiconductor film 19 is an oxide film composed of one or more of the elements constituting the oxide semiconductor film 18. Therefore, interface scattering hardly occurs at the interface between the oxide semiconductor film 18 and the oxide semiconductor film 19. Accordingly, carrier movement is not inhibited at the interface, so that the field-effect mobility of the transistor is increased.

[0158] Typically, the oxide semiconductor film 19 is an In-Ga oxide film, an In-Zn oxide film, an In -M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), and the energy of the lower end of the conduction band is closer to the vacuum level than that of the oxide semiconductor film 18. Typically, the energy of the lower end of the conduction band of the oxide semiconductor film 19 and the energy of the lower end of the conduction band of the oxide semiconductor film 18 ​​​​​​​The difference from the energy is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less. That is, the difference between the electron affinity of the oxide semiconductor film 19 and the electron affinity of the oxide semiconductor film 18 is 0.05 eV or more, 0.07 eV or more, 0.1 eV or more, or 0.15 eV or more and 2 eV or less, 1 eV or less, 0.5 eV or less, or 0.4 eV or less.

[0159] The oxide semiconductor film 19 preferably contains In because the carrier mobility (electron mobility) is increased. For this reason, it is preferable.

[0160] When the oxide semiconductor film 19 has Al, Ga, Y, Zr, La, Ce, or Nd at an atomic ratio higher than that of In, the following effects may be obtained. (1) The energy gap of the oxide semiconductor film 19 is increased. (2) The electron affinity of the oxide semiconductor film 19 is decreased. (3) Impurities from the outside are shielded. (4) Compared with the oxide semiconductor film 18, the insulation property is increased. (5) Since Al, Ga, Y, Zr, La, Ce, or Nd is a metal element having a strong binding force with oxygen, oxygen deficiency is less likely to occur.

[0161] When the oxide semiconductor film 19 is an In-M-Zn oxide film, when the sum of In and M is 100 atomic%, the atomic ratio of In and M is such that In is less than 50 atomic% and M is 50 atomic% or more, or In is less than 25 atomic% and M is 75 a tomic% or more.

[0162] In addition, when the oxide semiconductor film 18 and the oxide semiconductor film 19 are In-M-Zn oxide films (M is ​​​In the case of (Al, Ga, Y, Zr, La, Ce, or Nd), compared with the oxide semiconductor film 18 the number of atoms of M (Al, Ga, Y, Zr, La, Ce, or Nd) contained in the oxide semiconductor film 19 is large, and typically, compared with the above atoms contained in the oxide semiconductor film 18 it is 1.5 times or more, 2 times or more, or 3 times or more higher in atomic ratio.

[0163] In addition, when the oxide semiconductor films 18 and 19 are In-M-Zn oxide films (M is Al, Ga, Y, Zr, La, Ce, or Nd), for the oxide semiconductor film 19, In: M:Zn = x1:y1:z1 [atomic ratio], and for the oxide semiconductor film 18, In:M:Zn = x2 :y2:z2 [atomic ratio], then y1 / x1 is larger than y2 / x2, or y 1 / x1 is 1.5 times or more than y2 / x2. Or y1 / x1 is more than 2 times larger than y2 / x2, or y1 / x1 is more than 3 times larger than y2 / x2. At this time, in the oxide semiconductor film, when y2 is equal to or more than x2, it is preferable because stable electrical characteristics can be imparted to the transistor using the oxide semiconductor film.

[0164] When the oxide semiconductor film 18 is an In-M-Zn oxide film (M is Al, Ga, Y, Zr, La, Ce, or Nd), in the target used for forming the oxide semiconductor film 18 if the atomic ratio of the metal elements is In:M:Zn = x1:y1:z1 、 x1 / y1 is 1 / 3 or more and 6 or less, and further preferably 1 or more and 6 or less, and z1 / y1 is 1 / 3 or more and 6 or less and further preferably 1 or more and 6 or less. By setting z1 / y1 to 1 or more and 6 or less it becomes easier to form a CAAC-OS film as the oxide semiconductor film 18. Target Representative examples of atomic ratios of metal elements are In:M:Zn=1:1:1, In:M:Zn =1:1:1.2, In:M:Zn=3:1:2, etc.

[0165] The oxide semiconductor film 19 is an In-M-Zn oxide film (wherein M is Al, Ga, Y, Zr, La, In the case of Ce or Nd), the target used for depositing the oxide semiconductor film 19 In this case, the atomic ratio of metal elements is In:M:Zn=x2:y2:z2. 、 x2 / y2< x1 / y1, z2 / y2 is 1 / 3 or more and 6 or less, and more preferably 1 or more and 6 or less. Note that when z2 / y2 is greater than or equal to 1 and less than or equal to 6, the oxide semiconductor film 19 can be formed with a thickness of 100 nm. The CAAC-OS film is easily formed by the above. For example, In:M:Zn=1:3:2, In:M:Zn=1:3:4, In:M:Zn= 1:3:6, In:M:Zn=1:3:8, etc.

[0166] Note that the atomic ratios of the oxide semiconductor film 18 and the oxide semiconductor film 19 are each calculated using an error. The atomic ratios listed above may vary by ±40%.

[0167] The oxide semiconductor film 19 is a film formed by forming an oxide insulating film 24 later. It also functions as a film for reducing damage to the film 18 .

[0168] The thickness of the oxide semiconductor film 19 is 3 nm or more and 100 nm or less, or 3 nm or more and 50 nm or less. Let us assume that.

[0169] In addition, like the oxide semiconductor film 18, the oxide semiconductor film 19 may have a non-single crystal structure. The non-single crystal structure may be, for example, a CAAC-OS, a polycrystalline structure, or a microcrystalline structure. It includes a crystalline structure or an amorphous structure.

[0170] The oxide semiconductor film 19 may be, for example, an amorphous structure. The oxide semiconductor film with an amorphous structure For example, has a disordered atomic arrangement and no crystal component. Or, the oxide film with an amorphous structure is, for example, a completely amorphous structure and has no crystal part.

[0171] Note that in each of the oxide semiconductor film 18 and the oxide semiconductor film 19, an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region may form a mixed film having two or more of these regions. The mixed film may be, for example, a single-layer structure having two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Further, the mixed film may be, for example, a single-layer structure having two or more of any of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region. Also, the mixed film may be, for example, a laminated structure in which two or more of an amorphous structure region, a microcrystalline structure region, a polycrystalline structure region, a CAAC-OS region, and a single crystal structure region are laminated.

[0172] Here, the oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, even if trap levels are formed due to impurities and defects between the oxide semiconductor film 19 and the oxide insulating film 23, there is a gap between the trap levels and the oxide semiconductor film 18. As a result, electrons flowing through the oxide semiconductor film 18 are less likely to be trapped by the trap levels, and it is possible to increase the on-current of the transistor and increase the field-effect mobility. Also, when electrons are trapped by the trap levels, the electrons become the fixed charges of the transistors. As a result, the threshold voltage of the transistor fluctuates. ​​​However, since there is a gap between the oxide semiconductor film 18 and the trap level, it is possible to reduce the capture of electrons at the trap level and reduce the fluctuation of the threshold voltage.

[0173] In addition, since the oxide semiconductor film 19 can shield impurities from the outside, it is possible to reduce the amount of impurities moving from the outside to the oxide semiconductor film 18. Further, the oxide semiconductor film 19 is less likely to form oxygen vacancies. For these reasons, it is possible to reduce the impurity concentration and the amount of oxygen vacancies in the oxide semiconductor film 18.

[0174] Note that the oxide semiconductor film 18 and the oxide semiconductor film 19 are not simply laminated, but are formed so that a continuous junction (here, a structure in which the energy at the lower end of the conduction band continuously changes between the films) is formed. That is, a laminated structure is formed in which there are no impurities that form defect levels such as trap centers and recombination centers at the interface of each film. If impurities are mixed between the laminated oxide semiconductor film 18 and the oxide semiconductor film 19, the continuity of the energy band is lost, carriers are trapped at the interface, or recombine and disappear.

[0175] To form a continuous junction, it is necessary to continuously laminate each film without exposing it to the atmosphere using a multi-chamber type film forming apparatus (sputtering apparatus) equipped with a load lock chamber. Each chamber in the sputtering apparatus uses an adsorption type vacuum exhaust pump such as a cryopump to remove water and the like that become impurities for the oxide semiconductor film as much as possible, and exhausts to a high vacuum (5×10 -7 -4It is preferable to (up to the Pa level). Or, by combining a turbo molecular pump and a cold trap, it is preferable to prevent gas, particularly gas containing carbon or hydrogen, from flowing back into the chamber from the exhaust system. Further, instead of the multilayer film 20, like the transistor 65 shown in Fig. 7(D), it may have a multilayer film 3 4. The multilayer film 34 has an oxide semiconductor film 31, an oxide semiconductor film 18, and an oxide semiconductor film 19. That is, the multilayer film 34 has a three-layer structure. Also, the oxide semiconductor film 18 functions as a channel region.

[0176] In addition, the gate insulating film 17 and the oxide semiconductor film 31 are in contact. That is, the oxide semiconductor film 31 is provided between the gate insulating film 17 and the oxide semiconductor film 18.

[0177] Also, the multilayer film 34 and the oxide insulating film 23 are in contact. Also, the oxide semiconductor film 19 and the oxide insulating film 23 are in contact. That is, the oxide semiconductor film 19 is provided between the oxide semiconductor film 18 and the oxide insulating film 23.

[0178] The oxide semiconductor film 31 can appropriately use the same materials and formation methods as the oxide semiconductor film 19.

[0179] It is preferable that the oxide semiconductor film 31 has a smaller film thickness than the oxide semiconductor film 18. By setting the thickness of the oxide semiconductor film 31 to 1 nm or more and 5 nm or less, or 1 nm or more and 3 nm or less, it is possible to reduce the variation amount of the threshold voltage of the transistor.

[0180]

[0181]

[0182] ​​​​​​​​​​​The transistor shown in this embodiment has an oxide semiconductor film 19 provided between the oxide semiconductor film 18 and the oxide insulating film 23. Therefore, even if trap levels are formed due to impurities and defects between the oxide semiconductor film 19 and the oxide insulating film 23, there is a gap between the trap levels and the oxide semiconductor film 18. As a result, electrons flowing through the oxide semiconductor film 18 are less likely to be trapped by the trap levels, and it is possible to increase the on-current of the transistor and increase the field-effect mobility. Also, when electrons are trapped in the trap levels, these electrons become negative fixed charges. As a result, the threshold voltage of the transistor fluctuates. However, since there is a gap between the oxide semiconductor film 18 and the trap levels, it is possible to reduce the trapping of electrons in the trap levels and reduce the fluctuation of the threshold voltage.

[0183]

[0184] ​​​​​​​​​​​​​​​​The concentration of silicon or carbon in the vicinity of the interface between the oxide semiconductor film 19 and the oxide semiconductor film 18 is reduced. As a result, the absorption coefficient of the multilayer film 34, which is derived by the constant photocurrent measurement method, The number is 1 × 10 -3 / cm or less than 1×10 -4 / cm, and the localized level is extremely There are very few.

[0185] The transistor 65 having such a structure is formed by a multilayer film 34 including an oxide semiconductor film 18. Since there are very few defects in the Typically, it is possible to increase the on-current and improve the field effect mobility. Threshold voltage fluctuations during BT stress testing and optical BT stress testing, which are examples of testing Small quantity and high reliability.

[0186] <Band structure of transistor> Next, the multilayer film 20 provided in the transistor 60 shown in FIG. 7(A) and the multilayer film 20 in FIG. The band structure of the multilayer film 34 provided in the transistor 65 shown in FIG. do.

[0187] Here, as an example, the oxide semiconductor film 18 has an energy gap of 3.15 eV. The oxide semiconductor film 19 is made of In-Ga-Zn oxide, which has an energy gap of 3 The energy gap of the In-Ga-Zn oxide is 0.5 eV. Measure using a meter (HORIBA JOBIN YVON UT-300) can be done.

[0188] Energy difference between the vacuum level and the top of the valence band of the oxide semiconductor film 18 and the oxide semiconductor film 19 (Also referred to as ionization potential.) was 8 eV and 8.2 eV, respectively. Note that , the energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS: Ultr aviolet Photoelectron Spectroscopy) apparatus (PH I VersaProbe).

[0189] Therefore, the energy differences between the vacuum levels and the lower ends of the conduction bands of the oxide semiconductor film 18 and the oxide semiconductor film 19 (also referred to as electron affinity) are 4.85 eV and 4.7 eV, respectively.

[0190] Figure 8(A) schematically shows a part of the band structure of the multilayer film 20. Here, the case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. Note that EcI1 shown in Figure 8(A) represents the energy of the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy of the lower end of the conduction band of the oxide semiconductor film 18, EcS2 represents the energy of the lower end of the conduction band of the oxide semiconductor film 19, and EcI2 represents the energy of the lower end of the conduction band of the silicon oxide film. Also, E cI1 corresponds to the gate insulating film 17 in Figure 7(B), and EcI2 corresponds to the oxide insulating film 23 in Figure 7(B).

[0191] As shown in Figure 8(A), in the oxide semiconductor film 18 and the oxide semiconductor film 19, the energy of the lower end of the conduction band changes smoothly without a barrier. In other words, it can also be said that it changes continuously. This is because the multilayer film 20 contains elements common to the oxide semiconductor film 18, and a mixed layer is formed by the mutual movement of oxygen between the oxide semiconductor film 18 and the oxide semiconductor film 19.

[0192] As shown in Fig. 8(A), the oxide semiconductor film 18 of the multilayer film 20 serves as a well, and in the transistor using the multilayer film 2 0, it can be seen that the channel region is formed in the oxide semiconductor film 18. Since the energy at the lower end of the conduction band of the multilayer film 20 changes continuously, it can also be said that the oxide semiconductor film 18 and the oxide semiconductor film 19 are continuously joined.

[0193] As shown in Fig. 8(A), although trap levels may be formed near the interface between the oxide semiconductor film 19 and the oxide insulating film 23 due to impurities and defects, by providing the oxide semiconductor film 1 9, the oxide semiconductor film 18 and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 is small, electrons in the oxide semiconductor film 18 may reach the trap levels across the energy difference. When electrons are trapped at the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, when the energy difference between EcS1 and EcS2 is 0.1 eV or more, or 0.15 eV or more, fluctuations in the threshold voltage of the transistor are reduced, resulting in stable electrical characteristics, which is preferable.

[0194] Fig. 8(B) schematically shows a part of the band structure of the multilayer film 20, which is a modified example of the band structure shown in Fig. 8(A). Here, the case where a silicon oxide film is provided in contact with the multilayer film 20 will be described. EcI1 shown in Fig. 8(B) represents the energy at the lower end of the conduction band of the silicon oxide film, EcS1 represents the energy at the lower end of the conduction band of the oxide semiconductor film 18, and E cI2 represents the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 is as shown in Fig. 7(B 7B), EcI2 corresponds to the gate insulating film 17, and EcI3 corresponds to the oxide insulating film 17 in FIG. It corresponds to the membrane 23 .

[0195] In the transistor shown in FIG. 7B, the multilayer film 20 is formed when the pair of electrodes 21 and 22 are formed. In some cases, the upper part of the oxide semiconductor film 19 is etched. The upper surface of the oxide semiconductor film 18 is in contact with the oxide semiconductor film 18 during the formation of the oxide semiconductor film 19. 19 mixed layers may form.

[0196] For example, the oxide semiconductor film 18 is an In- Ga-Zn oxide, or In-Ga-Z with In:Ga:Zn=3:1:2 [atomic ratio] n oxide as a sputtering target, and The semiconductor film 19 is an In-Ga-Zn oxide having an atomic ratio of In:Ga:Zn=1:3:2. , In-Ga-Zn oxide with In:Ga:Zn=1:3:4 [atomic ratio], or In: In-Ga-Zn oxide with an atomic ratio of Ga:Zn=1:3:6 was used as a sputtering target. In the case where the oxide semiconductor film is formed using the above-mentioned method, the oxide semiconductor film is formed to have a larger thickness than the oxide semiconductor film 18. Since the conductor film 19 contains a large amount of Ga, a GaOx layer or a In this case, a mixed layer containing more Ga than the oxide semiconductor film 18 can be formed.

[0197] Therefore, even when the oxide semiconductor film 19 is etched, the Ec The energy at the bottom of the conduction band on the I2 side becomes higher, resulting in the band structure shown in Figure 8(B). There are cases.

[0198] In the case where the band structure is as shown in FIG. 8(B), when observing the cross section of the channel region, The multilayer film 20 may appear to be only the oxide semiconductor film 18 when observed superficially. However , substantially, a mixed layer containing more Ga than the oxide semiconductor film 18 is formed on the oxide semiconductor film 18, so that the mixed layer can be regarded as 1.5 layers. Incidentally , when measuring the elements contained in the multilayer film 20 by, for example, EDX analysis or the like , the mixed layer can be confirmed by analyzing the composition above the oxide semiconductor film 18. For example , it can be confirmed by the composition above the oxide semiconductor film 18 having a higher Ga content than the composition in the oxide semiconductor film 18 constituting it.

[0199] Fig. 8(C) schematically shows a part of the band structure of the multilayer film 34. Here, the case where a silicon oxide film is provided in contact with the multilayer film 34 will be described. Incidentally , EcI1 shown in Fig. 8(C) indicates the energy at the lower end of the conduction band of the silicon oxide film, EcS1 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 18, EcS2 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 19, EcS3 indicates the energy at the lower end of the conduction band of the oxide semiconductor film 31, and Ec I2 indicates the energy at the lower end of the conduction band of the silicon oxide film. Also, EcI1 corresponds to the gate insulating film 17 in Fig. 7(D) , and EcI2 corresponds to the oxide insulating film 23 in Fig. 7(D).

[0200] As shown in Fig. 8(C), in the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19, the energy at the lower end of the conduction band changes smoothly without a barrier. In other words , it can be said that it changes continuously. This is because the multilayer film 34 is the oxide semiconductor film 1 It can be said that this is because a mixed layer is formed by the mutual movement of oxygen between the oxide semiconductor film 18 and the oxide semiconductor film 31, which contain elements common to 8, and between the oxide semiconductor film 18 and the oxide semiconductor film 19. It can be seen from FIG. 8(C) that the oxide semiconductor film 18 of the multilayer film 34 becomes a well, and in the transistor using the multilayer film 34, the channel region is formed in the oxide semiconductor film 18. Since the energy at the lower end of the conduction band of the multilayer film 34 changes continuously, it can also be said that the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously joined.

[0201] It can be seen from FIG. 8(C) that the oxide semiconductor film 18 of the multilayer film 34 becomes a well, and in the transistor using the multilayer film 34, the channel region is formed in the oxide semiconductor film 18. It can be seen from FIG. 8(C) that the oxide semiconductor film 18 of the multilayer film 34 becomes a well, and in the transistor using the multilayer film 34, the channel region is formed in the oxide semiconductor film 18. Since the energy at the lower end of the conduction band of the multilayer film 34 changes continuously, it can also be said that the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously joined. Since the energy at the lower end of the conduction band of the multilayer film 34 changes continuously, it can also be said that the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously joined. Since the energy at the lower end of the conduction band of the multilayer film 34 changes continuously, it can also be said that the oxide semiconductor film 31, the oxide semiconductor film 18, and the oxide semiconductor film 19 are continuously joined.

[0202] Although trap levels due to impurities and defects may be formed near the interfaces between the oxide semiconductor film 18 and the oxide insulating film 23 and between the oxide semiconductor film 18 and the gate insulating film 17, as shown in FIG. 8(C), the oxide semiconductor films 19 and 31 are provided, so that the oxide semiconductor film 18 and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are small, Although trap levels due to impurities and defects may be formed near the interfaces between the oxide semiconductor film 18 and the oxide insulating film 23 and between the oxide semiconductor film 18 and the gate insulating film 17, as shown in FIG. 8(C), the oxide semiconductor films 19 and 31 are provided, so that the oxide semiconductor film 18 and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are small, Although trap levels due to impurities and defects may be formed near the interfaces between the oxide semiconductor film 18 and the oxide insulating film 23 and between the oxide semiconductor film 18 and the gate insulating film 17, as shown in FIG. 8(C), the oxide semiconductor films 19 and 31 are provided, so that the oxide semiconductor film 18 and the trap levels can be separated. However, when the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are small, the electrons in the oxide semiconductor film 18 may reach the trap levels by exceeding the energy difference. When electrons are captured by the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more When electrons are captured by the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more When electrons are captured by the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more When electrons are captured by the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more When electrons are captured by the trap levels, negative charges are generated at the oxide insulating film interface, and the threshold voltage of the transistor shifts in the positive direction. Therefore, it is preferable that the energy difference between EcS1 and EcS2 and the energy difference between EcS1 and EcS3 are 0.1 eV or more or 0.15 eV or more, so that the variation in the threshold voltage of the transistor is reduced and stable electrical characteristics are obtained, which is preferable. or 0.15 eV or more, so that the variation in the threshold voltage of the transistor is reduced and stable electrical characteristics are obtained, which is preferable.

[0203] Note that the configurations and methods shown in this embodiment, etc., can be appropriately combined and used with the configurations and methods shown in other embodiments.

[0204] (Embodiment 3) In this embodiment, in the transistor having the dual gate structure shown in Embodiment 2, the electrical characteristics of the transistor when different gate electrodes are connected and set to the same potential will be described with reference to FIGS. 7 , and FIGS. 26 to 31.

[0205] Here, a driving method in which the gate electrode 15 and the gate electrode 29 shown in FIG. 7 are electrically short-circuited and a gate voltage is applied is referred to as Dual Gate driving. That is, in Dual Gate driving, the voltage of the gate electrode 15 and the voltage of the gate electrode 29 are always equal.

[0206] Here, the electrical characteristics of the transistor were calculated. FIG. 26 shows the structure of the transistor used in the calculation. Note that the device simulation software Atlas (manufactured by Silvaco) was used for the calculation.

[0207] The transistor of Structure 1 shown in FIG. 26(A) is a transistor having a dual gate structure.

[0208] In the transistor of Structure 1, an insulating film 203 is formed on the gate electrode 201, and an oxide semiconductor film 205 is formed on the insulating film 20 3. A pair of electrodes 207 and 208 are formed on the insulating film 203 and the oxide semiconductor film 205, and an insulating film 209 is formed on the oxide semiconductor film 205 and the pair of electrodes 207 and 2 08. A gate electrode 213 is formed on the insulating film 209. Further, the gate electrode 201 and the gate electrode 213 are connected at an opening (not shown) formed in the insulating film 203 and the insulating film 209.

[0209] The transistor of Structure 2 shown in FIG. 26(B) is a single-gate structure transistor.

[0210] In the transistor of Structure 2, an insulating film 203 is formed over the gate electrode 201, and an oxide semiconductor film 205 is formed over the insulating film 203. Over the insulating film 203 and the oxide semiconductor film 205, a pair of electrodes 207 and 208 are formed, and an insulating film 209 is formed over the oxide semiconductor film 205 and the pair of electrodes 207 and 208.

[0211] In calculations, the work function φ of the gate electrode 201 was set to 5.0 eV. M The insulating film 203 was set to a film with a thickness of 100 nm and a relative permittivity of 4.1. As the oxide semiconductor film 205, a single layer of an In-Ga-Zn oxide film (In:Ga:Zn = 1:1:1) was assumed. The band gap E of the In-Ga-Zn oxide film g was set to 3.15 eV, the electron affinity χ was set to 4.6 eV, the relative permittivity was set to 15, the electron mobility was set to 10 cm 2 / Vs, and the donor density N d was set to 3×10 17 atoms / cm 3 The work function φ of the pair of electrodes 207 and 208 was set to 4. sd 6 eV, and an ohmic contact was assumed between the oxide semiconductor film 205 and the pair of electrodes 207 and 208. The relative permittivity of the insulating film 209 was set to 4.1, and the thickness was set to 100 nm. Note that models such as defect levels and surface scattering in the oxide semiconductor film 205 were not taken into consideration. Also, the channel length and The channel widths were set to 10 μm and 100 μm, respectively.

[0212] <Reduction of Initial Characteristic Variation> By using Dual Gate driving as in the transistor shown in Structure 1, the variation in the initial characteristics can be reduced. This is because, by using Dual Gate driving, the variation amount of the threshold voltage V th in the Id-Vg characteristic is smaller than that of the transistor shown in Structure 2.

[0213] Here, as an example, the negative shift in the Id-Vg characteristic due to the n-type conversion of the semiconductor film will be described.

[0214] Let the total charge amount of the donor ions be Q (C), and the capacitance formed by the gate electrode 201, the insulating film 203, and the Bottom oxide semiconductor film 205 be C and the capacitance formed by the oxide semiconductor film 205, Top the insulating film 209, and the gate electrode 213 be C At this time, the variation amount ΔV of V th of the transistor shown in Structure 1 is shown in Equation (2). Also, the variation amount ΔV of V th of the transistor shown in Structure 2 is shown in Equation (3).

[0215]

Equation

[0216]

Equation

[0217] As shown in Equation (2), in Dual Gate driving as in the transistor shown in Structure 1, the capacitance between the donor ions and the gate Bottom、and C Top is the sum of Therefore, the variation amount of the threshold voltage becomes small.

[0218] Also, in each of the transistors of Structure 1 and Structure 2, the current-voltage curves when the drain voltage is 0.1 V and 1 V are calculated, and the results are shown in FIG. 27. Note that FIG. 27(A) is the current-voltage curve of the transistor shown in Structure 1, and FIG. 27(B) is the current-voltage curve of the transistor shown in Structure 2. When the drain voltage Vd is 0.1 V, the threshold voltage of the transistor shown in Structure 1 is -2.26 V, and the threshold voltage of the transistor shown in Structure 2 is -4.73 V.

[0219] When Dual Gate drive is adopted as in the transistor shown in Structure 1, the variation amount of the threshold voltage is reduced. Therefore, the variation in electrical characteristics among a plurality of transistors is also reduced at the same time.

[0220] Here, although the negative shift of the threshold voltage due to donor ions is considered, the positive shift of the threshold voltage due to fixed charges, mobile charges, or negative charges (such as electrons trapped at acceptor-like levels) in the insulating film 203 and the insulating film 209 is similarly suppressed Therefore, it is considered that the variation is reduced.

[0221] <-Suppression of degradation in the -GBT stress test> Also, by adopting Dual Gate drive as in the transistor shown in Structure 1, the degradation in the -GBT stress test can be reduced. Hereinafter, the reason why the degradation in the -GBT stress test can be reduced will be explained.

[0222] As the first reason, there is a point that no electrostatic stress occurs by adopting Dual Gate driving. In Fig. 28(A), the contour map of the potential when -30V is applied to each of the gate electrode 201 and the gate electrode 213 in the transistor of Structure 1 is plotted. Also, in Fig. 28(B), the potential in the A-B cross section of Fig. 28(A) is shown. The oxide semiconductor film 205 is an intrinsic semiconductor. When a negative voltage is applied to the gate electrodes 201 and 213 and it is completely depleted, there are no charges between the gate electrodes 201 and 213. In this state, when the gate electrode 201 and the gate electrode 213 are set to the same potential, as shown in Fig. 28(B), the potential between the gate electrode 201 and the gate electrode 213 becomes completely equal. Since the potentials are equal, no electrostatic stress occurs in the insulating film 203, the oxide semiconductor film 205, and the insulating film 209. As a result, phenomena that cause deterioration in the -GBT stress test, such as mobile ions and trap-detrapping of carriers in the insulating film 203 and the insulating film 209, do not occur. As shown in Fig. 28(A), when -30V is applied to each of the gate electrode 201 and the gate electrode 213 in the transistor of Structure 1, the contour map of the potential is plotted. Also, in Fig. 28(B), the potential in the A-B cross section of Fig. 28(A) is shown.

[0223] The oxide semiconductor film 205 is an intrinsic semiconductor. When a negative voltage is applied to the gate electrodes 201 and 213 and it is completely depleted, there are no charges between the gate electrodes 201 and 213. In this state, when the gate electrode 201 and the gate electrode 213 are set to the same potential, as shown in Fig. 28(B), the potential between the gate electrode 201 and the gate electrode 213 becomes completely equal. Since the potentials are equal, no electrostatic stress occurs in the insulating film 203, the oxide semiconductor film 205, and the insulating film 209. As a result, phenomena that cause deterioration in the -GBT stress test, such as mobile ions and trap-detrapping of carriers in the insulating film 203 and the insulating film 209, do not occur. Since the potentials are equal, no electrostatic stress occurs in the insulating film 203, the oxide semiconductor film 205, and the insulating film 209. As a result, phenomena that cause deterioration in the -GBT stress test, such as mobile ions and trap-detrapping of carriers in the insulating film 203 and the insulating film 209, do not occur. As a result, phenomena that cause deterioration in the -GBT stress test, such as mobile ions and trap-detrapping of carriers in the insulating film 203 and the insulating film 209, do not occur.

[0224] As the second reason, the electric field from the outside of the FET is shielded by adopting Dual Gate driving. Here, in the transistor of Structure 1 shown in Fig. 26(A) and the transistor of Structure 2 shown in Fig. 26(B), the model in which charged particles in the air are adsorbed on the insulating film 209 or the gate electrode 213 is shown in Fig. 29. As shown in Fig. 29(B), in the transistor shown in Structure 2, positive charged particles in the air are adsorbed on the surface of the insulating film 209. When a negative voltage is applied to the gate electrode 201, the positive In the transistor shown in Structure 2, as shown in Fig. 29(B), positive charged particles in the air are adsorbed on the surface of the insulating film 209. When a negative voltage is applied to the gate electrode 201, the positive

[0225] In the transistor shown in Structure 2, as shown in Fig. 29(B), positive charged particles in the air are adsorbed on the surface of the insulating film 209. When a negative voltage is applied to the gate electrode 201, the positive ​​Charged particles are adsorbed on the insulating film 209. As a result, as indicated by the arrow in Fig. 29(B), the electric field of the positively charged particles affects up to the interface between the insulating film 209 of the oxide semiconductor film 205, and a state where a substantially positive bias is applied is obtained. As a result, it is considered that the threshold voltage shifts negatively.

[0226] On the other hand, as shown in Fig. 29(A), in the transistor shown in Structure 1, even if positively charged particles adhere to the surface of the gate electrode 213, as indicated by the arrow in Fig. 29(A), since the gate electrode 213 shields the electric field of the positively charged particles, the positively charged particles do not affect the electrical characteristics of the transistor. That is, having the gate electrode 213 makes it possible to electrically protect the transistor from external charges, and the deterioration in the -GBT stress test is suppressed.

[0227] For the above two reasons, in the transistor with Dual Gate drive, the deterioration in the -GBT stress test is suppressed.

[0228] <Suppression of Variation in Rise Voltage of On-Current at Different Drain Voltages> Here, the variation in the rise voltage of the on-current at different drain voltages in the case of Structure 2, and the cause thereof will be described.

[0229] In the transistor shown in Fig. 30, a gate insulating film 233 is provided on the gate electrode 231, and an oxide semiconductor film 235 is provided on the gate insulating film 233. On the oxide semiconductor film 235, a pair of electrodes 237 and 238 are provided, and an insulating film 239 is provided on the gate insulating film 233, the oxide semiconductor film 235, and the pair of electrodes 237 and 238.

[0230] ​​​​​In the calculation, the work function φ of the gate electrode 231 M was set to 5.0 eV. The gate insulating film 233 was set to a laminated structure of a 400-nm-thick film with a dielectric constant of 7.5 and a 50-nm-thick film with a dielectric constant of 4.1. As the oxide semiconductor film 235, a single layer of In-Ga-Z n oxide film (In:Ga:Zn = 1:1:1) was assumed, and the band gap E of the In-Ga-Zn oxide film g was 3.15 eV, the electron affinity χ was 4.6 eV, the relative dielectric constant was 15, and the electron mobility was 10 cm / Vs. The donor density N 2 was set to 1×10 d / cm 13 . 3 The work function φ of the pair of electrodes 237 and 238 sd was 4.6 eV, and an ohmic junction was set with the oxide semiconductor film 235. The relative dielectric constant of the insulating film 239 was 3.9, and the thickness was set to 550 nm . Note that models such as defect levels and surface scattering in the oxide semiconductor film 235 were not considered. Also, the channel length and channel width of the transistor were 3 μm and 50 μm, respectively.

[0231] Next, in the transistor shown in Fig. 30(A), models of the transistor with positive charged particles adsorbed on the surface of the insulating film 239 are shown in Figs. 30(B) and 30(C). Note that in Fig. 30( B), it is a structure assuming uniformly positive fixed charges on the surface of the insulating film 239, and in Fig. 3 0(C), it is a structure assuming partially positive fixed charges on the surface of the insulating film 239 .

[0232] The results of calculating the electrical characteristics of the transistors shown in Figs. 30(A) to 30(C) are shown in Figs. 31 (A) to 31(C).

[0233] ​​​​ As shown in Fig. 31(A), when no positive fixed charge is assumed in the insulating film 239 of the transistor shown in Fig. 30(A), the drain voltages (Vd) of 1V and 10V have substantially the same rising voltages.

[0234] On the other hand, as shown in Fig. 31(B), when a positive fixed charge is uniformly assumed in the insulating film 239 of the transistor shown in Fig. 30(B), the threshold voltage is negatively shifted. On the other hand, the drain voltages (Vd) of 1V and 10V have substantially the same rising voltages.

[0235] Also, as shown in Fig. 31(C), when a positive fixed charge is partially assumed in the insulating film 239 of the transistor shown in Fig. 30(C), the drain voltages (Vd) of 1V and 10V have different rising voltages.

[0236] On the other hand, in the transistor shown in Structure 1, since the gate electrode 213 is provided, as described in <Suppression of Degradation in the -GBT Stress Test>, the gate electrode 213 shields the electric field of external charged particles, so that the charged particles do not affect the electrical characteristics of the transistor. That is, when having the gate electrode 213, it is possible to electrically protect the transistor from external charges, and suppress the variation in the rising voltage of the on-current at different drain voltages.

[0237] From the above, by adopting a dual-gate structure and applying an arbitrary voltage to each gate electrode, it is possible to suppress the degradation in the -GBT stress test and the variation in the rising voltage of the on-current at different drain voltages. Also, by adopting a dual-gate structure and applying ​​​​​​​​​​​By applying a voltage of the same potential, it is possible to reduce the initial characteristic variations, suppress the deterioration in the GBT stress test, and suppress the variation in the rise voltage of the on-current at different drain voltages. It is possible to do so.

[0238] <Regarding the distance between the end of the gate electrode and the end of the oxide semiconductor film in the channel width direction and the variation amount of the threshold voltage> Fig. 32 shows a schematic cross-sectional view in the channel width direction of the transistor shown in Structure 1. Note that each configuration in the schematic cross-sectional view of the transistor shown in Fig. 32 has a different scale from each configuration of Structure 1 shown in Fig. 26(A).

[0239] Here, in the channel width direction of the transistor shown in Structure 1, although the gate electrode 201 and the gate electrode 213 protrude by t2 in the channel width direction from the oxide semiconductor film 205, a structure without a gate electrode facing the side surface of the oxide semiconductor film 205 is defined as Structure 3 (see Fig. 32(A)).

[0240] At this time, when the transistor shown in Structure 3 is driven by Dual Gate, the variation amount ΔV4 of V due to the charge amount Q (C / m) is as shown in Equation (4). (C / m 2 ) th

[0241]

Equation

[0242] Note that the situation where the variation amount of V in the transistor can be expressed by Equation (4) is limited to the case where the charge on the side surface of the oxide semiconductor film 205 is the main factor causing the shift of V. th th For example, when the gate electrode 201 or the gate electrode 213 protrudes from the oxide semiconductor film 205 in the channel When not protruding in the channel width direction, a parasitic channel may be formed by the charge of donor ions on the side surface of the oxide semiconductor film 205. In contrast, in the case of Structure 3, according to Equation ( 4), the influence of the charge is suppressed.

[0243] As described above, as the origin of the charge, donor ions on the side surface of the oxide semiconductor film 205 are assumed. However, even if it is a fixed charge in the insulating film, the insulating film interface, or the oxide semiconductor film, or electrons or holes trapped in the trap level, if they are the main factors causing the shift of V th , the same discussion holds.

[0244] As a more generalized case of Structure 3, consider Structure 4 in which the gate electrode 201 and the gate electrode 213 each protrude by X and X B in the channel width direction more than the oxide semiconductor film 205. (See FIG. 32(B).) At this time, C T and C can be rewritten as in Equation Bottom (5) and Equation (6), respectively. Top (5) and Equation (6) are rewritten as follows.

[0245]

Equation

[0246]

Equation

[0247] X B and X T When changed, Equation (5) and Equation (6) are X B = t1 + t os and X T = t3 + t os ​​and the maximum value C shown in Equation (7) Bottom Max and Equation (8) the C shown in Top Max is taken.

[0248]

Mathematics

[0249]

Mathematics

[0250] Therefore, to minimize the variation of V based on Equation (4), th X B = t1 + t os X T = t3 + t os is sufficient.

[0251] Note that the configurations and methods shown in this embodiment, etc., can be used in appropriate combination with the configurations and methods shown in other embodiments.

[0252] (Embodiment 4) In this embodiment, a semiconductor device, which is an aspect of the present invention, will be described with reference to the drawings. In this embodiment, a semiconductor device, which is an aspect of the present invention, will be described by taking a display device as an example.

[0253] Fig. 9(A) shows an example of a semiconductor device. The semiconductor device shown in Fig. 9(A) includes a pixel portion 10 1, a scanning line driving circuit 104, a signal line driving circuit 106, m scanning lines 107 that are each arranged in parallel or substantially parallel and whose potential is controlled by the scanning line driving circuit 104, and each is arranged in parallel or substantially parallel and whose potential is controlled by the signal line driving circuit 106 ​​​It has n signal lines 109. Further, the pixel portion 101 has a plurality of pixels 100 arranged in a matrix. Also, along the signal line 109, there are capacitance lines 115 arranged parallel or substantially parallel to each other. Note that the capacitance lines 115 may be arranged parallel or substantially parallel along the scanning line 107. Also, the scanning line driving circuit

[0254] 104 and the signal line driving circuit 106 may be collectively referred to as a driving circuit portion. Each scanning line 107 is electrically connected to n pixels 100 arranged in any one row among the pixels 100 arranged in m rows and n columns in the pixel portion 101. Also, each signal line 109 is electrically connected to m pixels 100 arranged in any one column among the pixels 100 arranged in m rows and n columns. m and n are both integers of 1 or more. Also, each capacitance line 115 is electrically connected to n pixels 100 arranged in

[0255] any one row among the pixels 100 arranged in m rows and n columns. Note that when the capacitance lines 115 are arranged parallel or substantially

[0256] parallel along the signal line 109, they are electrically connected to m pixels 100 arranged in any one column among the pixels 100 arranged in m

[0257] rows and n columns. The liquid crystal element 121 has its alignment state set according to the data to be written. Also, a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 121 included in each of the plurality of pixel 100. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal element 121 for each pixel 100 in each row.

[0258] Note that the liquid crystal element 121 is an element that controls the transmission or non-transmission of light by the optical modulation action of the liquid crystal. Note that the optical modulation action of the liquid crystal is controlled by an electric field applied to the liquid crystal (including a horizontal electric field, a vertical electric field, or an oblique electric field). Note that examples of the liquid crystal element 121 include nematic liquid crystal, cholesteric liquid crystal, smectic liquid crystal, thermotropic liquid crystal, lyotropic liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, and the like.

[0259] As a driving method for a display device having the liquid crystal element 121, for example, a TN mode, a VA mode, an ASM (Axially Symmetric Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode may be used. However, the present invention is not limited to this, and various liquid crystal elements and driving methods thereof can be used.

[0260] Further, a liquid crystal element may be configured by a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal exhibiting a blue phase has a response speed of 1 msec or less. ​​​​​​​​​​​​​It is short and optically isotropic, so no alignment treatment is required and the viewing angle dependence is small.

[0261] In the configuration of the pixel 100 shown in FIG. 9(B), one of the source electrode and the drain electrode of the transistor 103 is electrically connected to the signal line 109, and the other is one of the pair of electrodes of the liquid crystal element 121. It is electrically connected to the other of the electrodes. Also, the gate electrode of the transistor 103 is electrically connected to the scanning line 1 07. The transistor 103 has a function of controlling the writing of data of the data signal by being turned on or off.

[0262] In the configuration of the pixel 100 shown in FIG. 9(B), one of the pair of electrodes of the capacitor element 105 is electrically connected to the capacitor line 115 to which a potential is supplied, and the other is one of the pair of electrodes of the liquid crystal element 121. It is electrically connected to the other of the electrodes. Note that the value of the potential of the capacitor line 115 is appropriately set according to the specifications of the pixel 100. The capacitor element 105 has a function as a holding capacitor for holding the written data.

[0263] For example, in a display device having the pixel 100 of FIG. 9(B), the scanning line driving circuit 104 sequentially selects the pixels 100 of each row and turns on the transistor 103 to write the data of the data signal.

[0264] The pixel 100 in which data is written enters a holding state when the transistor 103 is turned off. By sequentially performing this for each row, an image can be displayed.

[0265] Also, the pixel 100 shown in FIG. 9(C) includes a transistor 1 33 that performs switching of the display element, a transistor 103 that controls the driving of the pixel, a transistor 135, and a capacitor element It has 105 and the light-emitting element 131.

[0266] One of the source electrode and the drain electrode of the transistor 133 is electrically connected to the signal line 109 to which a data signal is supplied. Furthermore, the gate electrode of the transistor 103 is electrically connected to the scanning line 107 to which a gate signal is supplied.

[0267] The transistor 133 has a function of controlling the writing of data of the data signal by being turned on or off.

[0268] One of the source electrode and the drain electrode of the transistor 103 is electrically connected to the wiring 137 that functions as an anode line, and the other of the source electrode and the drain electrode of the transistor 103 is electrically connected to one electrode of the light-emitting element 131. Furthermore, the gate electrode of the transistor 103 is electrically connected to the other of the source electrode and the drain electrode of the transistor 133, and one electrode of the capacitor element 105.

[0269] The transistor 103 has a function of controlling the current flowing through the light-emitting element 131 by being turned on or off.

[0270] One of the source electrode and the drain electrode of the transistor 135 is connected to the wiring 139 to which the reference potential of the data is supplied, and the other of the source electrode and the drain electrode of the transistor 135 is electrically connected to one electrode of the light-emitting element 131 and the other electrode of the capacitor element 105. Furthermore, the gate electrode of the transistor 135 is electrically connected to the scanning line 107 to which a gate signal is supplied.

[0271] Transistor 135 has a function of adjusting the current flowing through the light-emitting element 131. For example , when the internal resistance of the light-emitting element 131 increases due to deterioration or the like of the light-emitting element 131, the current flowing through the wiring 139 to which one of the source electrode and the drain electrode of the transistor 135 is connected is monitored, and the current flowing through the light-emitting element 131 can be corrected. As the potential applied to the wiring 139, for example, 0V can be used.

[0272] One of the pair of electrodes of the capacitor element 105 is electrically connected to the other of the source electrode and the drain electrode of the transistor 103, and the gate electrode of the transistor 133. The other of the pair of electrodes of the capacitor element 105 is electrically connected to the other of the source electrode and the drain electrode of the transistor 135, and one of the electrodes of the light-emitting element 131.

[0273] In the configuration of the pixel 100 shown in FIG. 9(C), the capacitor element 105 has a function as a holding capacitor for holding the written data.

[0274] One of the pair of electrodes of the light-emitting element 131 is electrically connected to the other of the source electrode and the drain electrode of the transistor 135, the other electrode of the capacitor element 105, and the other of the source electrode and the drain electrode of the transistor 103. Also, the other of the pair of electrodes of the light-emitting element 131 is electrically connected to the wiring 141 that functions as a cathode.

[0275] As the light-emitting element 131, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the light-emitting element 131 is not limited to this , and an inorganic EL element made of an inorganic material may be used.

[0276] Note that a high power supply potential VDD is applied to one of the wirings 137 and 141, and a low power supply potential VSS is applied to the other. In the configuration shown in Fig. 9(C), a configuration is adopted in which the high power supply potential VDD is applied to the wiring 137

[0277] and the low power supply potential VSS is applied to the wiring 141, respectively. In the display device having the pixel 100 of Fig. 9(C), the scanning line driving circuit 104 sequentially selects the pixels 100 of each row, turns on the transistor 102, and writes the data

[0278] of the data signal. The pixel 100 in which the data has been written enters a holding state when the transistor 103 is turned off. Further, since the transistor 103 is connected to the capacitive element 105, it is possible to hold the written data for a long time. Also, the transistor 133 controls the amount of current flowing between the source electrode and the drain electrode, and the light-emitting

[0279] element 131 emits light with a luminance corresponding to the amount of current flowing. By sequentially performing this for each row, an image can be displayed. Next, a specific example of a liquid crystal display device using a liquid crystal element

[0280] in the pixel 100 will be described. Here, a top view of the pixel 100 shown in Fig. 9(B) is shown in Fig. 10. Note that in Fig. 10, the counter electrode and the liquid crystal element are omitted. In Fig. 10, the conductive film 304c functioning as a scanning line extends in a direction The functional conductive film 304c is electrically connected to the scanning line driving circuit 104 (see Fig. 9(A)). The conductive film 310d that functions as a signal line and the conductive film 3 10f that functions as a capacitance line are electrically connected to the signal line driving circuit 106 (see Fig. 9(A)).

[0281] The transistor 103 is provided in a region where the scanning line and the signal line intersect. The transistor 103 is composed of a conductive film 304c that functions as a gate electrode, a gate insulating film (not shown in Fig. 10), an oxide semiconductor film 308 b in which a channel region is formed on the gate insulating film, conductive films 310d and 310e that function as source and drain electrodes, a protective film (not shown in Fig. 10) formed on the oxide semiconductor film 308b, and a conductive film 316c that functions as a gate electrode. Note that the conductive film 304c also functions as a scanning line, and the region overlapping with the oxide semiconductor film 308b functions as the gate electrode of the transistor 102 Also, the conductive film 310d also functions as a signal line, and the region overlapping with the oxide semiconductor film 308b functions as the source electrode or the drain electrode of the transistor 102. In Fig. 10, the scanning line has an end portion located outside the end portion of the oxide semiconductor film 308b in terms of the upper surface shape. Therefore, the scanning line functions as a light-shielding film that blocks light from a light source such as a backlight As a result, the oxide semiconductor film 308b included in the transistor is not irradiated with light, and fluctuations in the electrical characteristics of the transistor can be suppressed. Also, the conductive film 304c that functions as a gate electrode and the conductive film 316c that functions as a gate electrode are connected at the opening 364c

[0282] ​​​​​​​​​​In addition, the conductive film 310e is electrically connected to the conductive film 316b having translucency that functions as a pixel electrode at the opening 364c.

[0283] The capacitor element 105 is connected to the conductive film 310f that functions as a capacitor line at the opening 362. In addition, the capacitor element 105 is composed of a conductive film 308c formed on the gate insulating film, a dielectric film formed of a nitride insulating film provided on the transistor 103, and a conductive film 316c having translucency that functions as a pixel electrode. Since the conductive film 308c has translucency, the capacitor element 105 has translucency.

[0284] Since the capacitor element 105 has translucency in this way, the capacitor element 105 can be formed large (with a large area) within the pixel 100. Therefore, while increasing the aperture ratio, typically 50% or more, 55% or more, or 60% or more is possible, and a semiconductor device with an increased charge capacity can be obtained. For example, in a semiconductor device with high resolution, such as a liquid crystal display device, the area of the pixel becomes small and the area of the capacitor element also becomes small. For this reason, in a semiconductor device with high resolution, the charge capacity stored in the capacitor element becomes small. However, since the capacitor element 105 shown in this embodiment has translucency, by providing the capacitor element in the pixel, it is possible to increase the aperture ratio while obtaining a sufficient charge capacity in each pixel. Typically, it can be suitably used for a high-resolution semiconductor device with a pixel density of 200 ppi or more, further 300 ppi or more, and even more 500 ppi or more.

[0285] In addition, the pixel 100 shown in FIG. 10 has a side parallel to the conductive film 310d that functions as a signal line. The side parallel to the conductive film 304c that functions as a scanning line is longer in shape compared to it, and the capacitance conductive film 310f that functions as a capacitance line extends in a direction parallel to the conductive film 310d that functions as a signal line. As a result, since it is possible to reduce the area of the conductive film 310f in the pixel 100, the aperture ratio can be increased. Also, since the conductive film 310f that functions as a capacitance line contacts the film 308c having direct conductivity without using a connection electrode, the aperture ratio can be further increased. Moreover, since the conductive film 310f that functions as a capacitance line contacts the film 308c having direct conductivity without using a connection electrode, the aperture ratio can be further increased.

[0286] Also, in one aspect of the present invention, even in a high-resolution display device, since the aperture ratio can be increased, the light of a light source such as a backlight can be efficiently utilized, and the power consumption of the display device can be reduced.

[0287] Next, a cross-sectional view between the dashed-dotted line C-D in FIG. 10 is shown in FIG. 11. In FIG. 11, a cross-sectional view of the drive circuit section (the top view is omitted) including the scanning line drive circuit 104 and the signal line drive circuit 106 is shown at A-B. In the present embodiment, a vertical electric field type liquid crystal display device will be described.

[0288] The display device shown in the present embodiment has a liquid crystal element 322 sandwiched between a pair of substrates (substrate 302 and substrate 342).

[0289] The liquid crystal element 322 has a conductive film 316b having translucency above the substrate 302, a film for controlling alignment (hereinafter referred to as alignment films 318 and 352), a liquid crystal layer 320, and a conductive film 350. Note that the conductive film 316b having translucency functions as one electrode of the liquid crystal element 322, and the conductive film 350 functions as the other electrode of the liquid crystal element 322.

[0290] ​​​​ As described above, a liquid crystal display device refers to a device having liquid crystal elements. Note that the liquid crystal display device includes a drive circuit that drives a plurality of pixels and the like. Also, the liquid crystal display device includes a control circuit, a power supply circuit, a signal generation circuit, a backlight module, etc. arranged on another substrate, and may also be referred to as a liquid crystal module.

[0291] In the drive circuit section, a transistor 102 is constituted by a conductive film 304a that functions as a gate electrode, insulating films 305 and 306 that function as a gate insulating film, an oxide semiconductor film 30 8a in which a channel region is formed, and conductive films 310a and 310b that function as a source electrode and a drain electrode. The oxide semiconductor film 308a is provided on the gate insulating film.

[0292] In the pixel section, a transistor 103 is constituted by a conductive film 304c that functions as a gate electrode, insulating films 305 and 306 that function as a gate insulating film, an oxide semiconductor film 308b in which a channel region formed on the gate insulating film is formed, conductive films 310 d and 310e that function as a source electrode and a drain electrode, insulating films 312 and 314, and a conductive film 31 6c that functions as a gate electrode. The oxide semiconductor film 308b is provided on the gate insulating film. Also, insulating films 312 and 314 are provided as protective films on the conductive films 310d and 310e.

[0293] Also, a light-transmissive conductive film 316b that functions as a pixel electrode is connected to the conductive film 310e at an opening provided in the insulating films 312 and 314.

[0294] Also, a conductive film 308c that functions as one electrode and a dielectric film that functions as​​​​​​​​ The insulating film 314 and the light-transmitting conductive film 316b functioning as the other electrode form a capacitor. 105. The conductive film 308c is provided on the gate insulating film.

[0295] In the driving circuit section, the conductive film 304a and the conductive film 304c are formed at the same time. 4b and the conductive film 31 The light-transmitting conductive film 310c is formed at the same time as the light-transmitting conductive film 316b. Connected via 6a.

[0296] The conductive film 304b and the light-transmitting conductive film 316a are The conductive film 310c and the light-transmitting conductive film 310b are connected to each other through an opening provided in the conductive film 310c. The insulating film 312 and the insulating film 314 are connected to each other through an opening provided therein.

[0297] Here, the components of the display device shown in FIG. 11 will be described below.

[0298] Conductive films 304a, 304b, and 304c are formed on the substrate 302. The conductive film 04a functions as a gate electrode of a transistor in the driver circuit portion. 304c is formed in the pixel portion 101 and functions as a gate electrode of a transistor in the pixel portion. The conductive film 304b is formed in the scanning line driver circuit 104 and is connected to the conductive film 310c. do.

[0299] For the substrate 302, the material of the substrate 11 shown in Embodiment 1 can be used as appropriate.

[0300] The conductive films 304a, 304b, and 304c may be the same as those of the gate electrode 15 shown in the first embodiment. Materials and manufacturing methods can be used as appropriate.

[0301] On the substrate 302 and the conductive films 304a, 304c, 304b, an insulating film 305 and an insulating film 306 are formed. The insulating film 305 and the insulating film 306 function as a gate insulating film of a transistor in the drive circuit section and a gate insulating film of a transistor in the pixel section 101. As the insulating film 305, it is preferable to form it using the nitride insulating film described in the gate insulating film 17 shown in Embodiment 1.

[0302] As the insulating film 306, it is preferable to form it using the oxide insulating film described in the gate insulating film 17 shown in Embodiment 1. On the insulating film 306, an oxide semiconductor film 308a, 308b, and a conductive film 308c are formed. The oxide semiconductor film 308a is formed at a position overlapping with the conductive film 304a and functions as a channel region of a transistor in the drive circuit section. Also, the oxide semiconductor film 3

[0303] 08b is formed at a position overlapping with the conductive film 304c and functions as a channel region of a transistor in the pixel section. The conductive film 308c functions as one electrode of the capacitor element 105. region. The conductive film 308c functions as one electrode of the capacitor element 105. For the oxide semiconductor films 308a, 308b, and the conductive film 308c, the materials and manufacturing methods of the oxide semiconductor film 18 shown in Embodiment 1 can be appropriately used.

[0304] The oxide semiconductor films 308a, 308b, and the conductive film 308c can appropriately use the materials and manufacturing methods of the oxide semiconductor film 18 shown in Embodiment 1.

[0305] The conductive film 308c is an oxide semiconductor film, similar to the oxide semiconductor films 308a, 308b, and is characterized by containing impurities. As the impurities, there is hydrogen. In addition, instead of hydrogen, as impurities, boron, phosphorus, tin, antimony, noble gas elements ​​​​, it may contain an alkali metal, an alkaline earth metal, etc.

[0306] The oxide semiconductor films 308a and 308b and the conductive film 308c are both formed on the gate insulating film, but have different impurity concentrations. Specifically, the impurity concentration of the conductive film 308c is higher than that of the oxide semiconductor films 308a and 308b. For example, the hydrogen concentration contained in the oxide semiconductor films 308a and 308b is 5×10 atoms / cm or less, 19 5×10 3 atoms / cm or less, 1×10 18 atoms / cm 3 or less, 5×10 18 atoms / cm 3 or less, or 1×10 17 atoms / cm 3 or less, and the hydrogen concentration contained in the conductive film 308c is 16 8×10 3 atoms / cm or more, 1 19 ×10 3 atoms / cm or more, or 5×10 20 atoms / cm 3 or more. 20 3 Also, the hydrogen concentration contained in the conductive film 308c is twice or 10 times or more that of the oxide semiconductor films 308a and 308b. In addition, the resistivity of the conductive film 308c is lower than that of the oxide semiconductor films 308a and 308b. It is preferable that the resistivity of the conductive film 308c is 1×10

[0307] times or more and 1×10 times or less that of the oxide semiconductor films 308a and 308b. Typically, it is 1×10 Ωcm or more and 1×10 -8 times or more and 1×10 -1 times or less. Typically, it is 1×10 -3 Ωcm or more and 1×10​​4 less than Ωcm, or the resistivity is 1×10 -3 Ωcm or more and 1×1 0 -1 It may be less than Ωcm.

[0308] The oxide semiconductor films 308a and 308b are in contact with a film formed of a material capable of improving the interface characteristics with oxide semiconductor films such as the insulating film 306 and the insulating film 312. Therefore, the oxide semiconductor films 308a and 308b function as semiconductors, and a transistor having the oxide semiconductor films 308a and 3 08b has excellent electrical characteristics. On the other hand, the conductive film 308c is in contact with the insulating film 314 at the opening 362 (see FIG. 14(A)). The insulating film 314 is a film formed of a material that prevents impurities from the outside, such as water, alkali metals,

[0309] alkaline earth metals, etc., from diffusing into the oxide semiconductor film, and further contains hydrogen. For this reason, when hydrogen in the insulating film 314 diffuses into the oxide semiconductor film formed simultaneously with the oxide semiconductor films 308a and 308b, hydrogen combines with oxygen in the oxide semiconductor film, and carriers, electrons, are generated. Further, when the insulating film 314 is formed by plasma CVD method or sputtering method, the oxide semiconductor film is exposed to plasma, and oxygen deficiency is generated. When hydrogen contained in the insulating film 314 enters the oxygen deficiency, carriers, electrons, are generated. As a result, the oxide semiconductor film becomes highly conductive and functions as a conductor. That is, it can be said to be a highly conductive oxide semiconductor film. Here, a metal oxide having the same material as the oxide semiconductor films 308a and 308b as the main component and having a higher hydrogen concentration than the oxide semiconductor films 308a and 30 8b is referred to as the conductive film 308c. 8b, and having a higher hydrogen concentration than the oxide semiconductor films 308a and 30 8b, is referred to as the conductive film 308c. ​​​

[0310] However, one aspect of the embodiment of the present invention is not limited thereto, and the conductive film 308c may not be in contact with the insulating film 314 in some cases.

[0311] Also, one aspect of the embodiment of the present invention is not limited thereto, and the conductive film 308c may be formed in a separate process from the oxide semiconductor films 308a or 308b in some cases. In that case, the conductive film 308c may have a different material from the oxide semiconductor films 308a and 30 8b. For example, the conductive film 308c may be formed using ITO or indium zinc oxide or the like.

[0312] The semiconductor device shown in this embodiment forms an electrode that becomes one of the capacitor elements simultaneously with the oxide semiconductor film of the transistor. Also, a conductive film having translucency that functions as a pixel electrode is used as the other electrode of the capacitor element. For these reasons, in order to form the capacitor element, a process of newly forming a conductive film is unnecessary, and the manufacturing process of the semiconductor device can be reduced. Also, since the capacitor element has a pair of electrodes formed of a conductive film having translucency, it has translucency. As a result, while increasing the occupied area of the capacitor element, the aperture ratio of the pixel can be increased. The conductive films 310a, 310b, 310c, 310d, 310e can appropriately use the materials and manufacturing methods of the pair of electrodes 21, 22 shown in Embodiment 1. On the insulating film 306, oxide semiconductor films 308a, 308b, conductive film 308c having conductivity, and On the conductive films 310a, 310b, 310c, 310d, 310e, an insulating film 312, an insulating film are provided. Since the pair of electrodes of the capacitor element are formed of a conductive film having translucency, it has translucency. As a result, while increasing the occupied area of the capacitor element, the aperture ratio of the pixel can be increased. As a result, while increasing the occupied area of the capacitor element, the aperture ratio of the pixel can be increased.

[0313] The conductive films 310a, 310b, 310c, 310d, 310e can appropriately use the materials and manufacturing methods of the pair of electrodes 21, 22 shown in Embodiment 1. On the insulating film 306, oxide semiconductor films 308a, 308b, conductive film 308c having conductivity, and

[0314] On the insulating film 306, oxide semiconductor films 308a, 308b, conductive film 308c having conductivity, and On the conductive films 310a, 310b, 310c, 310d, 310e, an insulating film 312, an insulating The film 314 is formed. The insulating film 312, similar to the insulating film 306, preferably uses a material capable of improving the interface characteristics with the oxide semiconductor film, and at least the material and manufacturing method similar to those of the oxide insulating film 24 shown in Embodiment 1 can be appropriately used. Also, as shown in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be laminated and formed. It is preferable to use a material capable of improving the interface characteristics with the oxide semiconductor film, and at least the material and manufacturing method similar to those of the oxide insulating film 24 shown in Embodiment 1 can be appropriately used. It is possible to appropriately use the same materials and manufacturing methods as those of the oxide insulating film 24 shown in Embodiment 1. Also, as shown in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be laminated and formed. As shown in Embodiment 1, the oxide insulating film 23 and the oxide insulating film may be laminated and formed. Okay.

[0315] The insulating film 314, similar to the insulating film 305, preferably uses a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film, and the material and manufacturing method of the nitride insulating film 25 shown in Embodiment 1 can be appropriately used. Preferably, a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc., from diffusing into the oxide semiconductor film is used, and the material and manufacturing method of the nitride insulating film 25 shown in Embodiment 1 can be appropriately used. The material and manufacturing method of the nitride insulating film 25 shown in Embodiment 1 can be appropriately used. It can be used.

[0316] Also, on the insulating film 314, conductive films 316a, 316b having translucency, and a conductive film 316c functioning as a gate electrode are formed. The conductive film 316a having translucency is electrically connected to the conductive film 304b at the opening 364a (see Fig. 14(C)), and is electrically connected to the conductive film 310c at the opening 364b (see Fig. 14(C)). That is, it functions as a connection electrode connecting the conductive film 304b and the conductive film 310c. The conductive film 316b having translucency is electrically connected to the conductive film 310e at the opening 364c (see Fig. 14(C)) and functions as a pixel electrode of the pixel. Also, the conductive film 316b having translucency can function as one of the pair of electrodes of the capacitive element. The conductive film 316c is electrically connected to the conductive film 304c at the opening 364c (see Fig. 10). The conductive film 316a having translucency is electrically connected to the conductive film 304b at the opening 364a (see Fig. 14(C)), and is electrically connected to the conductive film 310c at the opening 364b (see Fig. 14(C)). (See Fig. 14(C).) and is electrically connected to the conductive film 310c at the opening 364b (see Fig. 14(C)). That is, it functions as a connection electrode connecting the conductive film 304b and the conductive film 310c. That is, it functions as a connection electrode connecting the conductive film 304b and the conductive film 310c. The conductive film 316b having translucency is electrically connected to the conductive film 310e at the opening 364c (see Fig. 14(C)) and functions as a pixel electrode of the pixel. The conductive film 316b having translucency is electrically connected to the conductive film 310e at the opening 364c (see Fig. 14(C)) and functions as a pixel electrode of the pixel. (See Fig. 14(C)) and functions as a pixel electrode of the pixel. Also, the conductive film 316b having translucency can function as one of the pair of electrodes of the capacitive element. Also, the conductive film 316b having translucency can function as one of the pair of electrodes of the capacitive element. The conductive film 316c is electrically connected to the conductive film 304c at the opening 364c (see Fig. 10). The conductive film 316c is electrically connected to the conductive film 304c at the opening 364c (see Fig. 10).

[0317] To have a connection structure where the conductive film 304b and the conductive film 310c are in direct contact, for the conductive film 3 Before forming 10c, patterning is required to form openings in the insulating films 305 and 306, and a mask needs to be formed. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device. ring is performed, and it is necessary to form a mask. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device. ring is performed, and it is necessary to form a mask. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device. ring is performed, and it is necessary to form a mask. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device. ring is performed, and it is necessary to form a mask. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device. ring is performed, and it is necessary to form a mask. However, in the connection structure of FIG. 11, such a photomask is unnecessary. However, as shown in FIG. 11, by connecting the conductive film 316b having translucency, the conductive film 304b and the conductive film 310c, there is no need to fabricate a connection portion where the conductive film 304b and the conductive film 310c are in direct contact, and one less photomask can be used. That is, it is possible to reduce the manufacturing process of the semiconductor device.

[0318] As the conductive films 316a, 316b, and 316c having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used. As the conductive films 316a, 316b, and 316c having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used. As the conductive films 316a, 316b, and 316c having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used. As the conductive films 316a, 316b, and 316c having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used. As the conductive films 316a, 316b, and 316c having translucency, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, ITO, indium zinc oxide, indium tin oxide added with silicon oxide, and other conductive materials having translucency can be used.

[0319] Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, a light-shielding film 344 adjacent to the colored film 346 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 is not necessarily provided, and for example, when the display device is black and white, etc., the colored film 346 may not be provided. Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, a light-shielding film 344 adjacent to the colored film 346 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 is not necessarily provided, and for example, when the display device is black and white, etc., the colored film 346 may not be provided. Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, a light-shielding film 344 adjacent to the colored film 346 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 is not necessarily provided, and for example, when the display device is black and white, etc., the colored film 346 may not be provided. Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, a light-shielding film 344 adjacent to the colored film 346 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 is not necessarily provided, and for example, when the display device is black and white, etc., the colored film 346 may not be provided. Also, a film having colorability (hereinafter referred to as a colored film 346) is formed on the substrate 342. The colored film 346 has a function as a color filter. Also, a light-shielding film 344 adjacent to the colored film 346 is formed on the substrate 342. The light-shielding film 344 functions as a black matrix. Also, the colored film 346 is not necessarily provided, and for example, when the display device is black and white, etc., the colored film 346 may not be provided.

[0320] The colored film 346 may be a colored film that transmits light in a specific wavelength band. For example, a red (R) color filter that transmits light in the red wavelength band, a green color filter that transmits light in the green wavelength band A green (G) color filter, a blue (B) color filter that transmits light in the blue wavelength band, etc. can be used. can be used.

[0321] As the light-shielding film 344, it only needs to have a function of shielding light in a specific wavelength band, and a metal film or an organic insulating film containing a black pigment or the like can be used.

[0322] Also, an insulating film 348 is formed on the colored film 346. The insulating film 348 has a function as a planarizing layer or a function of suppressing the diffusion of impurities that the colored film 346 may contain to the liquid crystal element side. has a function of suppressing the diffusion of impurities that the colored film 346 may contain to the liquid crystal element side.

[0323] Also, a conductive film 350 is formed on the insulating film 348. The conductive film 350 has a function as the other of a pair of electrodes of the liquid crystal element in the pixel portion. Note that, on the transparent conductive films 316a, 316b, and the conductive film 350, an insulating film having a function as an alignment film may be formed separately. formed separately.

[0324] Also, between the transparent conductive films 316a, 316b, the conductive film 316c and the conductive film 350, a liquid crystal layer 320 is formed. Also, the liquid crystal layer 320 is sealed between the substrate 302 and the substrate 342 using a sealing material (not shown). Note that the sealing material preferably has a configuration that contacts an inorganic material in order to suppress the entry of moisture from the outside. a liquid crystal layer 320 is formed. Also, the liquid crystal layer 320 is sealed between the substrate 302 and the substrate 342 using a sealing material (not shown). Note that the sealing material preferably has a configuration that contacts an inorganic material in order to suppress the entry of moisture from the outside. entering.

[0325] Also, between the transparent conductive films 316a, 316b, the conductive film 316c and the conductive film 350, a spacer for maintaining the thickness of the liquid crystal layer 320 (also referred to as a cell gap) may be provided.

[0326] Regarding the manufacturing method of the element portion provided on the substrate 302 shown in the semiconductor device shown in FIG. 11, This will be explained with reference to FIG. 12 to FIG.

[0327] First, prepare a substrate 302. Here, a glass substrate is used as the substrate 302.

[0328] Next, a conductive film is formed on the substrate 302, and the conductive film is processed into a desired region. The conductive films 304a, 304b, and 304c are formed. The formation of c is performed by forming a mask by a first patterning in a desired region, and then covering the mask. It can be formed by etching the uncut areas (see FIG. 12(A)). .

[0329] The conductive films 304a, 304b, and 304c are typically formed by deposition or CVD. The insulating film can be formed by a method such as sputtering or spin coating.

[0330] Next, an insulating film 305 is formed on the substrate 302 and the conductive films 304a, 304b, and 304c. Then, an insulating film 306 is formed over the insulating film 305 (see FIG. 12A).

[0331] The insulating film 305 and the insulating film 306 are formed by a sputtering method, a CVD method, or the like. When the insulating film 305 and the insulating film 306 are successively formed in a vacuum, impurities are easily removed. This is preferable because it suppresses the inclusion of

[0332] Next, an oxide semiconductor film 307 is formed over the insulating film 306 (see FIG. 12B).

[0333] The oxide semiconductor film 307 can be formed by a sputtering method, a coating method, a pulsed laser deposition method, a laser deposition method, or the like. The thin film can be formed by using a method such as ablation.

[0334] Next, by processing the oxide semiconductor film 307 into a desired region, island-shaped oxide semiconductor films 3 08a, 308b, and 308d are formed. Note that the formation of the oxide semiconductor films 308a, 308b, and 3 08d can be achieved by forming a mask by a second patterning in a desired region and etching the region not covered by the mask. As the etching, dry etching, wet etching, or etching that combines both can be used (see Fig. 12(C)).

[0335] Next, a conductive film 3 09 is formed on the insulating film 306 and the oxide semiconductor films 308a, 308b, and 308d (see Fig. 13(A)).

[0336] As the conductive film 309, for example, it can be formed using a sputtering method.

[0337] Next, by processing the conductive film 309 into a desired region, conductive films 310a, 310b, 31 0c, 310d, and 310e are formed. Note that the formation of the conductive films 310a, 310b, 310c, 3 10d, and 310e can be achieved by forming a mask by a third patterning in a desired region and etching the region not covered by the mask (see Fig. 1 3(B)).

[0338] Next, an insulating film 311 is formed so as to cover the insulating film 306, the oxide semiconductor films 308a, 308b, 308d, and the conductive films 31 0a, 310b, 310c, 310d, and 310e (see Fig. 13(C)).

[0339] As the insulating film 311, the oxide insulating films 23 and 24 shown in Embodiment 1 can be used, and ​​​​It can be formed by laminating using the same conditions. As shown in Embodiment 1, an oxide By forming the insulating film 23 while heating, hydrogen, water, etc. contained in the oxide semiconductor films 308a, 308b, 308 d can be desorbed to form a highly purified oxide semiconductor film. It can be done.

[0340] Next, by processing the insulating film 311 in a desired region, the insulating film 312 and the opening 362 are formed. Note that the formation of the insulating film 311 and the opening 362 is performed by forming a mask by fourth patterning in a desired region, and etching the region not covered by the mask. This can be done. (See FIG. 14(A)). Note that the opening 362 is formed so that the surface of the oxide semiconductor film 308d is exposed. As a method for forming the opening 362, for example, a dry etching method can be used.

[0341] However, the method for forming the opening 362 is not limited to this, and a wet etching method, or a formation method combining a dry etching method and a wet etching method may be used. However, the method for forming the opening 362 is not limited thereto, and a wet etching method, or a formation method combining a dry etching method and a wet etching method may be used.

[0342] After this, in the same manner as in Embodiment 1, a heat treatment is performed to move a part of the oxygen contained in the insulating film 311 to the oxide semiconductor films 308a and 308b, and the oxygen deficiency amount contained in the oxide semiconductor films 308a and 308b can be reduced. 308b can be reduced.

[0343] Next, an insulating film 313 is formed on the insulating film 312 and the oxide semiconductor film 308d (see FIG. 14 (B)).

[0344] As the insulating film 313, impurities from the outside, for example, oxygen, hydrogen, water, alkali metals, It is preferable to use a material that prevents alkaline earth metals and the like from diffusing into the oxide semiconductor film. Furthermore, it preferably contains hydrogen, and typically an inorganic insulating material containing nitrogen, such as a nitride insulating film can be used. As the insulating film 313, for example, it can be formed using the CVD method. It can be formed.

[0345] The insulating film 314 is a film formed of a material that prevents impurities from the outside, such as water, alkali metals, alkaline earth metals, etc. from diffusing into the oxide semiconductor film, and furthermore contains hydrogen. Therefore, when the hydrogen in the insulating film 314 diffuses into the oxide semiconductor film 308d, the hydrogen combines with oxygen in the oxide semiconductor film 308d to generate electrons that are carriers. As a result, the oxide semiconductor film 308d becomes highly conductive and becomes a conductive film 308c.

[0346] In addition, the silicon nitride film is preferably formed at a high temperature in order to enhance the blocking property. For example, it is preferably formed by heating at a temperature of 100°C or higher and 400°C or lower, or 300°C or higher and 400°C or lower. Also, when forming the film at a high temperature, oxygen desorbs from the oxide semiconductor used as the oxide semiconductor films 3 08a and 308b, and a phenomenon may occur in which the carrier concentration increases. Therefore, the temperature is set so that such a phenomenon does not occur. The temperature is set so that such a phenomenon does not occur.

[0347] Next, by processing the insulating film 313 in a desired region, the insulating film 314 and the openings 364 a, 364b, 364c, 364d (see FIG. 10) are formed. Note that the insulating film 314 , and the openings 364a, 364b, 364c are formed by forming a mask by fifth patterning in a desired region and etching the region not covered by the mask. This is done by forming a mask by fifth patterning in a desired region and etching the region not covered by the mask. It is possible (see Fig. 14(C)).

[0348] In addition, the opening 364a is formed so that the surface of the conductive film 304b is exposed. Also, the open ing 364b is formed so that the conductive film 310c is exposed. Further, the opening 364c is formed so that the conductive film 310e is exposed. Also, the opening 364d is formed so that the conductive film 304c is exposed.

[0349] Note that, as a method for forming the openings 364a, 364b, 364c, and 364d, for example, a dry etching method can be used. However, the method for forming the openings 364a, 364b, 364 c, and 364d is not limited to this, and a wet etching method or a forming method combining a dry etching method and a wet etching method may also be used.

[0350] Next, a conductive film 315 is formed on the insulating film 314 so as to cover the openings 364a, 364b, 364c, and 364d (see Fig. 15(A)).

[0351] As the conductive film 315, for example, it can be formed using a sputtering method.

[0352] Next, by processing the conductive film 315 in a desired region, conductive films 316a, 316b, and 316c having translucency are formed. Note that the formation of the conductive films 316a, 316b and 316c having translucency can be performed by forming a mask by sixth patterning in a desired region and etching a region not covered by the mask (see Fig. 15 (B)).

[0353] In the above steps, a pixel portion and a drive circuit portion having transistors are formed on the substrate 302 ​It is possible. In the manufacturing process shown in this embodiment, the first to sixth patterning, that is, transistors and capacitive elements can be simultaneously formed with six masks. It is possible to simultaneously form transistors and capacitive elements with six masks.

[0354] In this embodiment, hydrogen contained in the insulating film 314 is diffused into the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. However, the oxide semiconductor films 308a and 308b are covered with a mask, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d. 8b, and impurities, typically hydrogen, boron, phosphorus, tin, antimony, noble gas elements, alkali metals, alkaline earth metals, etc., are added to the oxide semiconductor film 308d to increase the conductivity of the oxide semiconductor film 308d.

[0355] Next, the structure formed on the substrate 342 provided opposite to the substrate 302 will be described below. Description will be given.

[0356] First, the substrate 342 is prepared. As the substrate 342, the materials shown for the substrate 302 can be used. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (see Fig. 16(A)). First, the substrate 342 is prepared. As the substrate 342, the materials shown for the substrate 302 can be used. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (see Fig. 16(A)). First, the substrate 342 is prepared. As the substrate 342, the materials shown for the substrate 302 can be used. Next, a light-shielding film 344 and a colored film 346 are formed on the substrate 342 (see Fig. 16(A)).

[0357] The light-shielding film 344 and the colored film 346 are formed at desired positions using various materials by printing, inkjet, etching methods using photolithography technology, etc. The light-shielding film 344 and the colored film 346 are formed at desired positions using various materials by printing, inkjet, etching methods using photolithography technology, etc.

[0358] ​Next, an insulating film 348 is formed on the light-shielding film 344 and the colored film 346 (see Fig. 16(B)). Reference

[0359] As the insulating film 348, for example, an organic insulating film such as an acrylic resin, an epoxy resin, or a polyimide can be used. By forming the insulating film 348, for example, it is possible to suppress the diffusion of impurities contained in the colored film 346 to the liquid crystal layer 320 side. However, the insulating film 348 does not necessarily have to be provided, and a structure in which the insulating film 348 is not formed may be adopted. However, the insulating film 348 does not necessarily have to be provided, and a structure in which the insulating film 348 is not formed may be adopted. However, the insulating film 348 does not necessarily have to be provided, and a structure in which the insulating film 348 is not formed may be adopted. may be used.

[0360] Next, a conductive film 350 is formed on the insulating film 348 (see Fig. 16(C)). As the conductive film 350, the materials shown for the conductive film 315 can be used. As the conductive film 350, the materials shown for the conductive film 315 can be used.

[0361] The structure formed on the substrate 342 in the above steps can be formed.

[0362] Next, alignment films 318 and 352 are formed on the substrate 302 and the substrate 342, more specifically, on the insulating film 314, the light-transmissive conductive films 316a and 316b formed on the substrate 302, and the conductive film 350 formed on the substrate 342, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. 4, the light-transmissive conductive films 316a and 316b, and on the conductive film 350 formed on the substrate 342, alignment films 318 and 352 are formed, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. 0, alignment films 318 and 352 are formed, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. Next, alignment films 318 and 352 are formed on the substrate 302 and the substrate 342, more specifically, on the insulating film 314, the light-transmissive conductive films 316a and 316b formed on the substrate 302, and the conductive film 350 formed on the substrate 342, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. Next, alignment films 318 and 352 are formed on the substrate 302 and the substrate 342, more specifically, on the insulating film 314, the light-transmissive conductive films 316a and 316b formed on the substrate 302, and the conductive film 350 formed on the substrate 342, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. Next, alignment films 318 and 352 are formed on the substrate 302 and the substrate 342, more specifically, on the insulating film 314, the light-transmissive conductive films 316a and 316b formed on the substrate 302, and the conductive film 350 formed on the substrate 342, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used. Next, alignment films 318 and 352 are formed on the substrate 302 and the substrate 342, more specifically, on the insulating film 314, the light-transmissive conductive films 316a and 316b formed on the substrate 302, and the conductive film 350 formed on the substrate 342, respectively. The alignment films 318 and 352 can be formed using a rubbing method, an optical alignment method, or the like. Then, a liquid crystal layer 320 is formed between the substrate 302 and the substrate 342. As a method for forming the liquid crystal layer 320, a dispenser method (dropping method) or an injection method in which the liquid crystal is injected using capillary action after bonding the substrate 302 and the substrate 342 can be used.

[0363] The display device shown in Fig. 11 can be manufactured through the above steps.

[0364] Note that this embodiment can be appropriately combined with other embodiments described in this specification. It can be.

[0365] <Modification Example 1> A modification example of a liquid crystal display device using a liquid crystal element for pixel 100 will be described. As shown in FIG. 11 In the liquid crystal display device, the conductive film 308c is in contact with the insulating film 314, but it can be structured to be in contact with the insulating film 305. In this case, since there is no need to provide an opening 362 as shown in FIG. 14, it is possible to reduce the step on the surfaces of the conductive films 316a and 316b having light transmittance. Therefore, it is possible to reduce the orientation disorder of the liquid crystal material contained in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured. Such a structure can be obtained by selectively etching the insulating film 306 to expose a part of the insulating film 305 before forming the oxide semiconductor film 307 in FIG. 12(B).

[0366]

[0367] <Modification Example 2> In this embodiment and the modification example, an organic insulating film such as an acrylic resin, an epoxy resin, or a polyimide may be provided between the insulating film 314, the conductive films 316a and 316 b having light transmittance, or the conductive film 316c and the alignment film 318. Since the organic insulating film such as an acrylic resin has high flatness it is possible to reduce the step on the surface of the conductive film 316b having light transmittance. Therefore it is possible to reduce the orientation disorder of the liquid crystal material contained in the liquid crystal layer 320. In addition, a semiconductor device with high contrast can be manufactured.

[0368] (Embodiment 5) In this embodiment, the transistor included in the semiconductor device described in the above embodiment In this section, one embodiment applicable to an oxide semiconductor film will be described.

[0369] The oxide semiconductor film is an oxide semiconductor having a single crystal structure (hereinafter referred to as a single crystal oxide semiconductor). , a polycrystalline oxide semiconductor (hereinafter referred to as a polycrystalline oxide semiconductor), oxide semiconductors having an amorphous structure (hereinafter referred to as microcrystalline oxide semiconductors) and amorphous oxide semiconductors having an amorphous structure (hereinafter referred to as The oxide semiconductor film may be formed of one or more of the following: Alternatively, the oxide semiconductor film may be an amorphous oxide semiconductor film. The oxide semiconductor may be a single crystal oxide semiconductor having a conductor and crystal grains. Conductor, CAAC-OS, polycrystalline oxide semiconductor, microcrystalline oxide semiconductor, and amorphous oxide semiconductor The conductor will now be described.

[0370] <Single crystal oxide semiconductor> A single-crystal oxide semiconductor film has a low impurity concentration and a low density of defect states (few oxygen vacancies). ) an oxide semiconductor film. Therefore, the carrier density can be reduced. A transistor using a crystalline oxide semiconductor film rarely has normally-on electrical characteristics. In addition, since the single crystal oxide semiconductor film has a low impurity concentration and a low density of defect states, Therefore, in the case of a transistor using a single crystal oxide semiconductor film, the number of carrier traps may be reduced. The transistor has small fluctuations in electrical characteristics and is highly reliable.

[0371] Note that the oxide semiconductor film has a high density when the number of defects is small. High crystallinity increases density. In addition, the oxide semiconductor film has a low concentration of impurities such as hydrogen. The density of the single crystal oxide semiconductor film is higher than that of the CAAC-OS film. , The CAAC-OS film has a higher density than the microcrystalline oxide semiconductor film. Also, the polycrystalline oxide semiconductor film has a higher density than the microcrystalline oxide semiconductor film. Further, the microcrystalline oxide semiconductor film has a higher density than the amorphous oxide semiconductor film. conductor film has a higher density than the microcrystalline oxide semiconductor film. Also, the microcrystalline oxide semiconductor film is non- crystalline oxide semiconductor film has a higher density than the film.

[0372] <caac-os> The CAAC-OS film is one of the oxide semiconductor films having a plurality of crystal parts. Also, CA The crystal parts included in the AC-OS film have c-axis orientation. In a plan-view TEM image, CAA The area of the crystal parts included in the C-OS film is 2500 nm 2 or more and 5 μm 2 or more, or 100 0 μm 2 or more. Also, in a cross-sectional TEM image, by having 50% or more, 80% or more , or 95% or more of the crystal parts, a thin film with physical properties close to those of a single crystal is obtained.

[0373] When the CAAC-OS film is observed by a transmission electron microscope (TEM: Transmission Elec tron Microscope), a clear boundary between crystals, that is, a crystal grain boundary (also referred to as a grain boundary) cannot be confirmed. Therefore, it can be said that in the CA AC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

[0374] When the CAAC-OS film is observed by TEM from a direction substantially parallel to the sample surface (cross-sectional TEM observation), it can be confirmed that metal atoms are arranged in layers in the crystal parts. Each layer of the metal atoms has a shape that reflects the unevenness of the surface (also referred to as the formed surface) or the upper surface of the CAAC-OS film, and is arranged parallel to the formed surface or the upper surface of the CAAC-OS film. Note that in this specification, "parallel" means a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, the case of -5° or more and 5° or less is also included. Also, "perpendicular ular" means a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included.

[0375] Therefore, the case of 85° or more and 95° or less is also included.

[0375] On the one hand, when the CAAC-OS film is observed by TEM from a direction substantially perpendicular to the sample surface (planar TEM observation), it can be confirmed that in the crystal part, metal atoms are arranged in a triangular or hexagonal shape. However, no regularity is observed in the arrangement of metal atoms between different crystal parts.

[0376] In addition, when electron beam diffraction is performed on the CAAC-OS film, spots (bright spots) showing orientation are observed.

[0377] From cross-sectional TEM observation and planar TEM observation, it can be seen that the crystal part of the CAAC-OS film has orientation.

[0378] When structural analysis is performed on the CAAC-OS film using an X-ray diffraction (XRD: X-Ray Diffraction) apparatus, in the analysis by the out-of-plane method of the CAAC-OS film, a peak may appear near a diffraction angle (2θ) of 31°. This peak is attributed to the (00x) plane (x is an integer) of the crystal of InGaZn oxide. Therefore, it can be confirmed that the crystal of the CAAC- OS film has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formed surface or the upper surface.

[0379] On the other hand, in the analysis by the in-plane method in which X-rays are incident on the CAAC-OS film from a direction substantially perpendicular to the c-axis, a peak may appear near 2θ of 56°. This peak is attributed to the (110) plane of the crystal of InGaZn oxide. For a single crystal oxide semiconductor film of InGaZn oxide, if 2θ is fixed near 56° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), when analyzing while rotating the sample with the normal vector of the sample surface as the axis (φ scan), the crystal equivalent to the (110) plane will be obtained. Six peaks attributable to crystal planes are observed. In contrast, in the case of the CAAC-OS film, even when θ is fixed near 56° and φ scanning is performed, no distinct peak appears. Even when θ is fixed near 56° and φ scanning is performed, no distinct peak appears.

[0380] From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above cross-sectional TEM observation is a plane parallel to the a-b plane of the crystal. From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above cross-sectional TEM observation is a plane parallel to the a-b plane of the crystal. From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above cross-sectional TEM observation is a plane parallel to the a-b plane of the crystal. From the above, in the CAAC-OS film, the orientations of the a-axis and b-axis are irregular between different crystal parts, but it has c-axis orientation, and it can be seen that the c-axis is oriented in a direction parallel to the normal vector of the formed surface or the upper surface. Therefore, each layer of the layered metal atoms confirmed by the above cross-sectional TEM observation is a plane parallel to the a-b plane of the crystal.

[0381] Note that the crystal is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Note that the crystal is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Note that the crystal is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Note that the crystal is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Note that the crystal is formed when the CAAC-OS film is formed or when a crystallization treatment such as heat treatment is performed. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis of the crystal may not be parallel to the normal vector of the formed surface or the upper surface of the CAAC-OS film.

[0382] Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed locally. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed locally. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed locally. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed locally. Also, the crystallinity in the CAAC-OS film may not be uniform. For example, when the crystal part of the CAAC-OS film is formed by crystal growth from near the upper surface of the CAAC-OS film, the region near the upper surface may have a higher crystallinity than the region near the formed surface. Also, when impurities are added to the CAAC-OS film, the crystallinity of the region where the impurities are added changes, and regions with different crystallinities may be formed locally.

[0383] Note that in the analysis of the CAAC-OS film by the out-of-plane method, in addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36°. When 2θ is near 36° Note that in the analysis of the CAAC-OS film by the out-of-plane method, in addition to the peak near 2θ of 31°, a peak may also appear near 2θ of 36°. When 2θ is near 36° The nearby peak indicates that a part of the CAAC-OS film contains a crystal part that does not have c-axis orientation. The CAAC-OS film preferably shows a peak at around 2θ = 31° and does not show a peak at around 2θ = 36°.

[0384] The CAAC-OS film is an oxide semiconductor film with a low impurity concentration. Impurities are elements other than the main components of the oxide semiconductor film, such as hydrogen, carbon, silicon, and transition metal elements. In particular, elements with a stronger binding force with oxygen than the metal elements constituting the oxide semiconductor film, such as silicon, will disrupt the atomic arrangement of the oxide semiconductor film by taking oxygen from the oxide semiconductor film, leading to a decrease in crystallinity. Also, heavy metals such as iron and nickel, argon, carbon dioxide, etc., have a large atomic radius (or molecular radius), so when contained inside the oxide semiconductor film, they will disrupt the atomic arrangement of the oxide semiconductor film and become a factor in reducing crystallinity. Note that impurities contained in the oxide semiconductor film may become carrier traps or carrier generation sources.

[0385] Also, the CAAC-OS film is an oxide semiconductor film with a low defect level density. For example, oxygen deficiencies in the oxide semiconductor film may become carrier traps or may become carrier generation sources by capturing hydrogen.

[0386] A low impurity concentration and a low defect level density (few oxygen deficiencies) are called high-purity intrinsic or substantially high-purity intrinsic. An oxide semiconductor film that is high-purity intrinsic or substantially high-purity intrinsic has few carrier generation sources, so the carrier density can be lowered. Therefore, a transistor using such an oxide semiconductor film has electrical characteristics (such as a threshold voltage becoming negative) (Also referred to as Maryon.) It rarely occurs. Also, high-purity genuine or substantially high-purity A genuine oxide semiconductor film has few carrier traps. Therefore, a transistor using such an oxide semiconductor film has small fluctuations in electrical characteristics and becomes a highly reliable transistor. Note that the charges trapped in the carrier traps of the oxide semiconductor film may take a long time to be released and may behave like fixed charges. Therefore, a transistor using an oxide semiconductor film with a high impurity concentration and a high density of defect levels may have unstable electrical characteristics.

[0387] Also, a transistor using a CAAC-OS film has small fluctuations in electrical characteristics due to irradiation with visible light or ultraviolet light.

[0388] <Polycrystalline oxide semiconductor> In the observation image by TEM, crystal grains can be confirmed in a polycrystalline oxide semiconductor film. The crystal grains contained in the polycrystalline oxide semiconductor film are, for example, in a particle size of 2 nm or more and 3 00 nm or less, 3 nm or more and 100 nm or less, or 5 nm or more and 50 nm or less in the observation image by TEM in many cases. Also, in the observation image by TEM, crystal grain boundaries may be confirmed in the polycrystalline oxide semiconductor film.

[0389] A polycrystalline oxide semiconductor film has a plurality of crystal grains, and the crystal orientations may be different between the plurality of crystal grains. Also, when a polycrystalline oxide semiconductor film is analyzed by the out-of-plane method using, for example, an XRD apparatus, single or multiple peaks may appear. For example, in a polycrystalline IGZO film, a peak with 2θ indicating orientation near 31° or multiple peaks indicating multiple types of orientation may appear. ​​​​​​​​​​

[0390] Since the polycrystalline oxide semiconductor film has high crystallinity, it may have high electron mobility. Therefore, a transistor using a polycrystalline oxide semiconductor film has high field-effect mobility. However, impurities may segregate at the grain boundaries of the polycrystalline oxide semiconductor film. Also, the grain boundaries of the polycrystalline oxide semiconductor film become defect levels. Since the grain boundaries of the polycrystalline oxide semiconductor film may be carrier generation sources and trap levels, a transistor using a polycrystalline oxide semiconductor film may have larger fluctuations in electrical characteristics and lower reliability compared to a transistor using a CAAC-OS film.

[0391] <Microcrystalline Oxide Semiconductor> In the observation image by TEM, it may not be possible to clearly confirm the crystalline part in the microcrystalline oxide semiconductor film. The crystalline parts contained in the microcrystalline oxide semiconductor film are often 1 nm or more and 100 nm or less, or 1 nm or more and 10 nm or less in size. In particular, nanocrystals (nc: nanocrystalline) that are microcrystals of 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less are often present. An oxide semiconductor film having such nanocrystals is called an nc-OS (nanocrystalline oxide semiconductor) film. Also, in the observation image by TEM, for example, it may not be possible to clearly confirm the grain boundaries in the nc-OS film.

[0392] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, no regularity is seen in the crystal orientation between different crystalline parts in the nc-OS film. Therefore, no orientation is seen in the whole film. Therefore, depending on the analysis method, the nc-OS film may not be distinguishable from the amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus with an X-ray having a diameter larger than that of the crystal part, no peak indicating the crystal plane is detected in the analysis by the out-of-plane method. Also, when performing electron beam diffraction (also called limited field of view electron beam diffraction) on the nc-OS film using an electron beam having a diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also called nano-beam electron beam diffraction) on the nc-OS film using an electron beam having a diameter close to or smaller than that of the crystal part (for example, 1 nm or more and 30 nm or less), spots are observed. Also, when performing nano-beam electron beam diffraction on the nc-OS film, a region with high brightness may be observed as if drawing a circle (ring-shaped ). Also, when performing nano-beam electron beam diffraction on the nc-OS film, a plurality of spots may be observed within the ring-shaped region. Fig. 17 shows an example in which nano-beam electron beam diffraction is performed on a sample having an nc-OS film while changing the measurement location. Here, the sample is cut in a direction perpendicular to the surface on which the nc-OS film is formed, and thinned to a thickness of 10 nm or less. Also, here, an electron beam with a diameter of 1 nm is incident from a direction perpendicular to the cut surface of the sample. From Fig. 17, it can be seen that when performing nano-beam electron beam diffraction on a sample having an nc-OS film, a diffraction pattern indicating the crystal plane is obtained, but no orientation to the crystal plane in a specific direction is observed.

[0393] The nc-OS film is an oxide semiconductor film with higher regularity than the amorphous oxide semiconductor film. Thus

[0394] Therefore, the nc-OS film has a lower density of defect levels than the amorphous oxide semiconductor film. However , in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, the nc- OS film has a higher density of defect levels than the CAAC-OS film.

[0395] Note that the configurations and methods shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0396] (Embodiment 6) The oxide semiconductor film disclosed in the above embodiment can be formed by sputtering, but may also be formed by other methods, for example, by thermal CVD method. As an example of the thermal CVD method, M OCVD (Metal Organic Chemical Vapor Deposi tion) method or ALD (Atomic Layer Deposition) method can be used.

[0397] Since the thermal CVD method is a film formation method that does not use plasma, it has the advantage that defects are not generated due to plasma damage.

[0398] In the thermal CVD method, the source gas and the oxidizing agent are simultaneously introduced into the chamber, and the chamber is under atmospheric pressure or reduced pressure, and the reaction is carried out near or on the substrate to deposit on the substrate to form a film.

[0399] Also, in the ALD method, the chamber is under atmospheric pressure or reduced pressure, and the source gas for the reaction is sequentially introduced into the chamber, and the film formation may be carried out by repeating the order of the gas introduction. . For example, by switching each switching valve (also called a high-speed valve), two or more Supply the upper raw material gas to the chamber in sequence, and introduce an inert gas (such as argon or nitrogen) simultaneously with or after the first raw material gas so that multiple types of raw material gases do not mix, and introduce the second raw material gas. When introducing the inert gas simultaneously, the inert gas becomes the carrier gas, and it is also possible to introduce the inert gas simultaneously when introducing the second raw material gas. Alternatively, after discharging the first raw material gas by vacuum exhaust instead of introducing the inert gas, the second raw material gas may be introduced. The first raw material gas adsorbs on the surface of the substrate to form the first layer and reacts with the subsequently introduced second raw material gas, so that the second layer is laminated on the first layer to form a thin film. By repeating this gas introduction sequence multiple times until the desired thickness is reached while controlling the gas introduction sequence, a thin film with excellent step coverage can be formed. Since the thickness of the thin film can be adjusted by the number of times the gas introduction sequence is repeated, precise film thickness adjustment is possible, which is suitable for fabricating fine FETs.

[0400] Thermal CVD methods such as the MOCVD method and the ALD method can form various films such as the metal films, oxide semiconductor films, and inorganic insulating films disclosed in the embodiments described so far. For example, when forming an InGaZnO film, trimethylindium, trimethylgallium, and dimethylzinc are used. The chemical formula of trimethylindium is In(CH3)3. The chemical formula of trimethylgallium is Ga(CH3)3. The chemical formula of dimethylzinc is Zn(CH3)2. Moreover, it is not limited to these combinations, and triethylgallium (chemical formula Ga(C2H5)3) can be used instead of trimethylgallium, and diethylzinc (chemical formula Zn(C2H5)2) can be used instead of dimethylzinc. ​ It is also possible.

[0401] For example, when forming an oxide semiconductor film, such as an In-Ga-Zn- O film, by a film forming apparatus using ALD, In(CH3)3 gas and O3 gas are sequentially and repeatedly introduced to form an In -O layer, and then Ga(CH3)3 gas and O3 gas are simultaneously introduced to form a GaO layer and further, ZnO layer is formed by simultaneously introducing Zn(CH3)2 and O3 gas. Note that the order of these layers is not limited to this example. Also, these gases may be mixed to form a mixed compound layer such as an In-Ga- O layer, an In-Zn-O layer, or a Ga-Zn-O layer. Note that H2O gas obtained by bubbling with an inert gas such as Ar instead of O3 gas may be used, but it is preferable to use O3 gas that does not contain H. Also, instead of In(CH3)3 gas, In(C2H5)3 gas may be used. Also, instead of Ga(CH3)3 gas, Ga(C2H5)3 gas may be used. Also, instead of In(CH3)3 gas, In( C2H5)3 gas may be used. Also, Zn(CH3)2 gas may be used.

[0402] Note that the configurations and methods shown in this embodiment, etc., can be appropriately combined with the configurations and methods shown in other embodiments and used.

Example

[0403] In this example, the measurement results of the Vg-Id characteristics of the transistor and the gate BT stress test will be described.

[0404] In this example, Samples 1 to 3 which are one aspect of the present invention and Comparative Samples 4 to 6 were fabricated First, the manufacturing process of Sample 1 will be described. Samples 1 to 3 which are one aspect of the present invention For this, refer to FIG. 18, and for comparative samples 4 to 6, refer to FIG. 19, and each will be described below. Each will be described below.

[0405] (Sample 1) Sample 1 includes a substrate 511, a gate electrode 515 on the substrate 511, a gate insulating film 517 on the substrate 511 and the gate electrode 515, an oxide semiconductor film 518 provided on the gate insulating film 517 and in a region overlapping with the gate electrode 515, a pair of electrodes 521 and 522 on the gate insulating film 517 and the oxide semiconductor film 518, a protective film 526 on the oxide semiconductor film 518 and the pair of electrodes 521 and 522, and a back gate electrode 527 provided on the protective film 526 and in a region overlapping with the gate electrode 515 (see FIG. 18). (See FIG. 18). .

[0406] Note that the protective film 526 is formed with a three-layer stacked structure of an oxide insulating film 523, an oxide insulating film 524, and a nitride insulating film 525. Also, both ends of the back gate electrode 527 substantially coincide with both ends of the gate electrode 515 as shown in FIG. 18(B). Further, the back gate electrode 527 is formed to cover the oxide semiconductor film 518 via the protective film 526 as shown in FIG. 18(C). (B). Also, the back gate electrode 527 is formed to cover the oxide semiconductor film 518 via the protective film 526 as shown in FIG. 18(C).

[0407] Next, the manufacturing method of sample 1 shown in FIG. 18 is shown below.

[0408] First, a glass substrate is used as the substrate 511, and the gate electrode 515 is formed on the substrate 511.

[0409] As the gate electrode 515, a tungsten film with a thickness of 200 nm is formed by sputtering, a mask is formed on the tungsten film by a photolithography process, and the mask is used ​ A part of the tungsten film was etched to form it.

[0410] Next, a gate insulating film 517 was formed on the gate electrode 515.

[0411] As the gate insulating film 517, a silicon nitride film with a thickness of 400 nm and an oxide silicon nitride film with a thickness of 50 nm were laminated to form it.

[0412] Note that the silicon nitride film had a three-layer laminated structure of a first silicon nitride film, a second silicon nitride film, and a third silicon nitride film.

[0413] As the first silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm and ammonia gas with a flow rate of 100 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus The pressure in the processing chamber was controlled to 100 Pa, and 2000 W of power was supplied using a high-frequency power source of 27.12 MHz to form a film with a thickness of 50 nm. As the second silicon nitride film, silane with a flow rate of 200 sccm, nitrogen with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus. The pressure in the processing chamber was controlled to 100 Pa, and a high-frequency power source of 27.12 MHz was used to supply 2000 W of power to form a film with a thickness of 300 nm. As the third silicon nitride film, silane with a flow rate of 200 sccm and nitrogen with a flow rate of 5000 sccm were used as source gases and supplied to the processing chamber of a plasma CVD apparatus. The pressure in the processing chamber was controlled to 100 Pa and 2000 W of power was supplied using a high-frequency power source of 27.12 MHz to form a film with a thickness of 50 nm. Note that the first silicon nitride film, the second silicon nitride film, and The substrate temperature during the formation of the third silicon nitride film was set to 350°C.

[0414] As the silicon oxynitride film, silane with a flow rate of 20 sccm and dinitrogen oxide with a flow rate of 3000 sccm were supplied as source gases into the processing chamber of a plasma CVD apparatus, the pressure in the processing chamber was controlled to 4 0 Pa, and a power of 100 W was supplied using a 27.12 MHz high-frequency power supply to form a silicon oxynitride film. Note that the substrate temperature during the formation of the silicon oxynitride film was 350°C.

[0415] Next, an oxide semiconductor film 518 overlapping the gate electrode 515 was formed via the gate insulating film 517.

[0416] Here, an oxide semiconductor film with a thickness of 35 nm was formed on the gate insulating film 517 by sputtering.

[0417] The oxide semiconductor film was formed using a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2, oxygen with a flow rate of 100 sccm as the sputtering gas was supplied into the processing chamber of the sputtering apparatus, the pressure in the processing chamber was controlled to 0.6 Pa, and a DC power of 5 kW was supplied for formation. Note that the substrate temperature during the formation of the oxide semiconductor film was set to 170°C.

[0418] Next, a pair of electrodes 521 and 522 in contact with the oxide semiconductor film 518 were formed.

[0419] Here, a conductive film was formed on the gate insulating film 517 and the oxide semiconductor film 518. As the conductive film, a 400-nm-thick aluminum film was formed on a 50-nm-thick tungsten film, and a 200-nm-thick titanium film was formed on the aluminum film. Next, photolithography ​​​​​​​​​A mask was formed on the conductive film by the photolithography process, and a part of the conductive film was etched using the mask to form a pair of electrodes 521 and 522.

[0420] Next, the substrate was moved into the depressurized processing chamber, heated at 350 °C, and then 150 W of high-frequency power was supplied to the upper electrode provided in the processing chamber using a 27.12 MHz high-frequency power source, and the oxide semiconductor film 518 was exposed to the oxygen plasma generated in the dinitrogen monoxide atmosphere.

[0421] Next, a protective film 526 was formed on the oxide semiconductor film 518 and the pair of electrodes 521 and 522. Here, as the protective film 526, an oxide insulating film 523, an oxide insulating film 524, and a nitride insulating film 525 were formed.

[0422] First, after the above oxygen plasma treatment, without exposing to the atmosphere, the oxide insulating film 523 and the oxide insulating film 524 were continuously formed. As the oxide insulating film 523, a silicon oxynitride film with a thickness of 50 nm was formed, and as the oxide insulating film 524, a silicon oxynitride film with a thickness of 400 nm was formed.

[0423] The oxide insulating film 523 was formed by plasma CVD using silane with a flow rate of 20 sccm and dinitrogen monoxide with a flow rate of 3000 sccm as source gases, with the pressure in the processing chamber being 200 Pa, the substrate temperature being 350 °C, and 100 W of high-frequency power being supplied to the parallel plate electrode.

[0424] The oxide insulating film 524 was formed by plasma CVD using silane with a flow rate of 160 sccm and dinitrogen monoxide with a flow rate of 4000 sccm as source gases, with the pressure in the processing chamber being 200 Pa, the substrate temperature being 220 °C, and 1500 W of high-frequency power being supplied to the parallel plate electrode. Under these conditions Thus, an oxygen-containing silicon oxynitride film that contains more oxygen than stoichiometric composition and from which part of the oxygen is desorbed by heating can be formed.

[0425] Next, a heat treatment was performed to desorb water, nitrogen, oxygen, etc. from the oxide insulating film 523 and the oxide insulating film 524, and part of the oxygen contained in the oxide insulating film 524 was supplied to the oxide semiconductor film 5 18. Here, a heat treatment was performed at 350 °C for 1 hour in a nitrogen and oxygen atmosphere.

[0426] Next, a nitride insulating film 525 with a thickness of 100 nm was formed on the oxide insulating film 524. The nitride insulating film 525 was formed by plasma CVD using silane with a flow rate of 50 sccm, nitrogen with a flow rate of 5000 sccm, and ammonia gas with a flow rate of 100 sccm as source gases, with the pressure in the processing chamber at 100 Pa, the substrate temperature at 350 °C, and 1000 W of high-frequency power supplied to the parallel plate electrodes.

[0427] Next, an oxide insulating film was formed on the protective film 526 (not shown). Here, tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4 ), an organic silane gas with a flow rate of 20 0 sccm, and oxygen with a flow rate of 10000 sccm were used as source gases, with the pressure in the processing chamber at 175 Pa, the substrate temperature at 350 °C, and 3300 W of high-frequency power supplied to the parallel plate electrodes.

[0428] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. Here as the back gate electrode 527, a conductive film of indium oxide-tin oxide compound (ITO-SiO2) with a thickness of 100 nm was formed by sputtering. Note that the conductive film was used The composition of the target used was In2O3:SnO2:SiO2 = 85:10:5 [wt%]. Thereafter, heat treatment was performed at 250°C for 1 hour in a nitrogen atmosphere.

[0429] Sample 1 of this example was produced through the above steps.

[0430] (Sample 2) Sample 2 has a different structure of the oxide semiconductor film 518 compared to Sample 1. Specifically, the oxide semiconductor film 518 of Sample 2 was formed into a laminated structure of a first oxide semiconductor film and a second oxide semiconductor film.

[0431] First, for the first oxide semiconductor film, a sputtering target with an atomic ratio of In:Ga:Zn = 3: 1:2 was used, and oxygen with a flow rate of 100 sccm was supplied into the processing chamber of the sputtering apparatus as the sputtering gas while controlling the pressure in the processing chamber to 0.6 Pa, and it was formed by supplying 5 kW of DC power.

[0432] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. For the second oxide semiconductor film, a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 ( atomic ratio) was used, and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm were supplied into the processing chamber of the sputtering apparatus as the sputtering gas, and the pressure in the processing chamber was controlled to 0.6 Pa, and it was formed by supplying 5 kW of DC power. Note that the substrate temperature when forming the first oxide semiconductor film and the second oxide semiconductor film was set to 170°C.

[0433] Regarding Sample 2, since the configurations other than the oxide semiconductor film 518 are the same as those of Sample 1 it can be formed by referring to the description of Sample 1. ​

[0434] (Sample 3) Sample 3 has a different structure of the oxide semiconductor film 518 compared to Sample 1. Specifically, the oxide semiconductor film of Sample 3 is a laminated structure of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film.

[0435] First, for the first oxide semiconductor film, a sputtering target with an atomic ratio of In:Ga:Zn = 1: 3:2 is used, and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm are supplied as sputtering gases into the processing chamber of the sputtering apparatus. The pressure in the processing chamber is controlled to 0.6 Pa, and a DC power of 5 kW is supplied to form it.

[0436] Next, a second oxide semiconductor film is continuously formed on the first oxide semiconductor film in a vacuum. For the second oxide semiconductor film, a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2( is used, and oxygen with a flow rate of 100 sccm and argon with a flow rate of 100 sccm are supplied as sputtering gases into the processing chamber of the sputtering apparatus. The pressure in the processing chamber is controlled to 0.6 Pa, and a DC power of 5 kW is supplied to form it.

[0437] Next, a third oxide semiconductor film is continuously formed on the second oxide semiconductor film in a vacuum. For the third oxide semiconductor film, a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2( is used, and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm are supplied as sputtering gases into the processing chamber of the sputtering apparatus. The pressure in the processing chamber is controlled to 0.6 Pa, and a DC power of 5 kW is supplied to form it. Note that the first oxide semiconductor ​The substrate temperature when forming the body film, the second oxide semiconductor film, and the third oxide semiconductor film was 17 0 °C.

[0438] For Sample 3, since the configuration other than the oxide semiconductor film 518 is the same as that of Sample 1 , it can be formed by referring to the description of Sample 1.

[0439] (Sample 4) Sample 4 includes a substrate 511, a gate electrode 515 on the substrate 511, a gate insulating film 517 on the substrate 511 and the gate electrode 515, an oxide semiconductor film 518 provided on the gate insulating film 517 and in a region overlapping with the gate electrode 515, a pair of electrodes 521, 522 on the gate insulating film 517 and the oxide semiconductor film 518, a protective film 526 on the oxide semiconductor film 518 and the pair of electrodes 521, 522, and a back gate electrode 528 provided on the protective film 526 and in a region overlapping with the gate electrode 515 (see Fig. 19). . .

[0440] Note that the protective film 526 was formed with a three-layer stacked structure of an oxide insulating film 523, an oxide insulating film 524, and a nitride insulating film 525. Also, the back gate electrode 528 was formed so as to be located inside both ends of the oxide semiconductor film 518 as shown in Fig. 19(B). Also , the back gate electrode 528 was formed so as to be located inside the oxide semiconductor film 518 through the protective film 526 as shown in Fig. 19(C). However, in Fig. 19(C), one end of the back gate electrode 528 protrudes outside the oxide semiconductor film 518 as shown. formed.

[0441] Next, the manufacturing method of Sample 4 shown in Fig. 19 is shown below.

[0442] ​ Until the formation of the protective film 526, the same manufacturing process as that of the sample 1 described above was used.

[0443] Next, an oxide insulating film was formed on the protective film 526 (not shown). Here, tetraethyl orthosilicate (TEOS: chemical formula Si(OC2H5)4 ) which is an organic silane gas with a flow rate of 20 0 sccm and oxygen with a flow rate of 10,000 sccm were used as source gases, the pressure in the processing chamber was 175 Pa, the substrate temperature was 350 °C, and high-frequency power of 3300 W was supplied to the parallel plate electrodes to form it by plasma CVD method .

[0444] Next, a back gate electrode 527 was formed on the oxide insulating film on the protective film 526. Here , as the back gate electrode 527, a conductive film of indium-doped tin oxide compound (ITO-SiO2) with a thickness of 100 nm was formed by sputtering method. Note that the composition of the target used for the conductive film was In2O3:SnO2:SiO2 = 85:10:5 [wt%] . After that, heat treatment was performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0445] The sample 4 of this example was fabricated through the above steps.

[0446] (Sample 5) Sample 5 has a different structure of the oxide semiconductor film 518 compared to Sample 4. Specifically, the oxide semiconductor film 518 of Sample 5 has a laminated structure of a first oxide semiconductor film and a second oxide semiconductor film .

[0447] First, for the first oxide semiconductor film, a target with In:Ga:Zn = 3: 1:2 (atomic ratio) was used, oxygen with a flow rate of 100 sccm and argon with a flow rate of 100 scc m were supplied into the processing chamber of the sputtering apparatus as sputtering gases, and the processing It was formed by controlling the indoor pressure to 0.6 Pa and supplying 5 kW of DC power.

[0448] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film used a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2 ( atomic ratio), and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm were supplied into the processing chamber of the sputtering apparatus as sputtering gases, and the pressure in the processing chamber was controlled to 0.6 Pa and 5 kW of DC power was supplied to form it. Note that the substrate temperature when forming the first oxide semiconductor film and the second oxide semiconductor film was 170 °C.

[0449] For Sample 5, since the configurations other than the oxide semiconductor film 518 are the same as those of Sample 4, it can be formed by referring to the description of Sample 4.

[0450] (Sample 6) Sample 6 has a different structure of the oxide semiconductor film 518 compared to Sample 4. Specifically, the oxide semiconductor film 518 of Sample 6 has a laminated structure of a first oxide semiconductor film, a second oxide semiconductor film, and a third oxide semiconductor film.

[0451] First, the first oxide semiconductor film used a sputtering target with an atomic ratio of In:Ga:Zn = 1: 3:2 (atomic ratio), and oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm were supplied into the processing chamber of the sputtering apparatus as sputtering gases, and the pressure in the processing chamber was controlled to 0.6 Pa and 5 kW of DC power was supplied to form it.

[0452] Next, a second oxide semiconductor film was continuously formed on the first oxide semiconductor film in a vacuum. The second oxide semiconductor film uses a sputtering target with an atomic ratio of In:Ga:Zn = 3:1:2( ), oxygen with a flow rate of 100 sccm and argon with a flow rate of 100 sccm are supplied into the processing chamber of the sputtering apparatus as sputtering gases, and the pressure in the processing chamber is controlled to 0.6 Pa, and a DC power of 5 kW is supplied to form it.

[0453] Next, a third oxide semiconductor film was continuously formed on the second oxide semiconductor film in a vacuum. The third oxide semiconductor film uses a sputtering target with an atomic ratio of In:Ga:Zn = 1:3:2( ), oxygen with a flow rate of 30 sccm and argon with a flow rate of 270 sccm are supplied into the processing chamber of the sputtering apparatus as sputtering gases, and the pressure in the processing chamber is controlled to 0.6 Pa, and a DC power of 5 kW is supplied to form it. Note that the substrate temperature when forming the first oxide semiconductor film, the second oxide semiconductor film, and the third oxide semiconductor film is 17 0 °C.

[0454] For Sample 6, since the configurations other than the oxide semiconductor film 518 are the same as those of Sample 4, it can be formed by referring to the description of Sample 4.

[0455] Note that Samples 1 to 6 prepared above are transistors with a channel length (L) of 6 μm and a channel width (W ) of 50 μm.

[0456] <Vg-Id Characteristics> Next, the Vg-Id characteristics were measured as the initial characteristics of the transistors of Samples 1 to 6. Here, the substrate temperature is 25 °C, the potential difference between the source and drain (hereinafter referred to as the drain voltage .) is set to 1 V and 10 V, and the potential difference between the source and gate electrodes (hereinafter referred to as the gate voltage .) was changed from -15V to +20V, and the change characteristics of the current flowing between the source and drain (hereinafter referred to as the drain current) were measured, that is, the Vg-Id characteristics were measured. Next, the gate BT stress test (hereinafter

[0457] <Gate BT stress test> referred to as the GBT test) was performed on samples 1 to 6 for which the measurement of the initial characteristics had been completed. Here, as the GBT test conditions, the substrate temperature was set to 60°C, and the measurement environment was in a dark room (dark environment), and a gate voltage of +30V was applied for 1 hour to apply stress to samples 1 to 6. The GBT test is a type of accelerated test and can evaluate the characteristic changes (i.e., changes over time) of transistors that occur during long-term use in a short time. Examining the amount of change in the characteristics of the transistor before and after the GBT test is an important indicator for examining reliability.

[0458] Figures 20 and 21 show the Vg-Id characteristics of the transistors of each sample and the Vg -Id characteristics after the GBT test. Note that Figure 20(A) shows the initial characteristics and the characteristics results after GBT of sample 1, Figure 20(B) shows the initial characteristics and the characteristics results after GBT of sample 2, Figure 20(C) shows the initial characteristics and the characteristics results after GBT of sample 3, Figure 21(A) shows the initial characteristics and the characteristics results after GBT of sample 4, Figure 21(B) shows the initial characteristics and the characteristics results after GBT of sample 5, and Figure 21(C) shows the initial characteristics and the characteristics results after GBT of sample 6, respectively.

[0459] Also, in each graph shown in Figures 20 and 21, the horizontal axis represents the gate voltage Vg, the first vertical axis represents the drain current Id, and the second vertical axis represents the field-effect mobility μFE, respectively.

[0460] Note that the horizontal axis is shown from -15V to 20V. Also, the solid line represents the Vg-Id characteristics of the initial characteristics when the drain voltage Vd is 1 V and 10V, and the field-effect mobility of the initial characteristics with respect to the gate voltage when the gate voltage Vg is 10V. The dashed line represents the Vg-Id characteristics after the GBT test when the drain voltage Vd is 1V and 10V, and the field-effect mobility after the GBT test with respect to the gate voltage when the gate voltage Vg is 10V. Note that the field-effect mobility is the result in the saturation region of each sample.

[0461] Also, in each sample, 20 transistors with the same structure were fabricated in the substrate. Therefore, in the graphs shown in FIGS. 20 and 21, the data of the 20 transistors are overlapped and shown.

[0462] From FIGS. 20 and 21, it can be seen that in Samples 1 to 6, good switching characteristics are obtained in the initial characteristics shown by the solid line. On the other hand, in the characteristics after the GBT test shown by the dashed line, in Samples 1 to 3, there is generally no change or very little change with respect to the initial characteristics (the dashed line is shown almost overlapping the solid line). However, in Samples 4 to 6 shown in FIG. 21, large variations are confirmed in the characteristics after the GBT test shown by the dashed line with respect to the initial characteristics shown by the solid line. Specifically, after the GBT test, the rising voltage shifts in the negative direction. Also, it has two peaks that change stepwise when the gate voltage (Vg) is changed from the negative direction to the positive direction. In Samples 4 to 6 shown in FIG. 21, large variations are confirmed in the characteristics after the GBT test shown by the dashed line with respect to the initial characteristics shown by the solid line. Specifically, after the GBT test, the rising voltage shifts in the negative direction. Also, it has two peaks that change stepwise when the gate voltage (Vg) is changed from the negative direction to the positive direction.

[0463] Samples 1 to 3, which are one aspect of the present invention, and the large structure of Comparative Samples 4 to 6 ​​​​​​​​As a difference, the shapes of the back gate electrodes (back gate electrode 527 and back gate electrode 528) are different. In Samples 1 to 3 which are one aspect of the present invention, the shape of the back gate electrode covers the oxide semiconductor film 518 and overlaps with the end of the gate electrode 515. That is to say, it can be said that the side surface of the channel portion of the oxide semiconductor film 518 is covered by the upper and lower gate electrodes (gate electrode 515 and back gate electrode 527). Also, in other words, at the outer peripheral portion of the side surface of the channel portion of the oxide semiconductor film 518, the upper and lower gate electrodes (gate electrode 515 and back gate electrode 527) face each other with a dielectric (gate insulating film 517 and protective film 526 ) interposed therebetween.

[0464] On the other hand, in Samples 4 to 6 for comparison, the shape of the back gate electrode 528 is formed inside the oxide semiconductor film 518.

[0465] After the GBT test, parasitic channels are likely to be formed at the outer peripheral portion of the side surface of the channel portion of the oxide semiconductor film 518. However, Samples 1 to 3 of one aspect of the present invention have the upper and lower gate electrodes (gate electrode 515 and back gate electrode 527) covering the outer peripheral portion of the side surface of the channel portion of the oxide semiconductor film 518. Therefore, the upper and lower gate electrodes can eliminate the parasitic channels that may occur at the outer peripheral portion of the side surface of the channel portion of the oxide semiconductor film 518, or reduce the influence of the parasitic channels.

Example

[0466] In this example, the life estimation of the device in the degradation characteristics after the GBT test will be described.

[0467] In this embodiment, a sample 7, which is one aspect of the present invention, was fabricated. Samples 8 to 10 were used as comparative examples. With reference to FIG. 22 for sample 7, which is one aspect of the present invention, and with reference to FIGS. 23 and 24 for the comparative samples 8 to 10, the description will be given respectively.

[0468] (Sample 7) Sample 7 includes a substrate 511, a gate electrode 515 on the substrate 511, a gate insulating film 517 on the substrate 511 and the gate electrode 515, an oxide semiconductor film 518 provided on the gate insulating film 517 and in a region overlapping with the gate electrode 515, a pair of electrodes 521 and 522 on the gate insulating film 517 and the oxide semiconductor film 518, a protective film 526 on the oxide semiconductor film 518 and the pair of electrodes 521 and 522, and a back gate electrode 527 provided on the protective film 526 and in a region overlapping with the gate electrode 515 (see FIG. 22).

[0469] Note that the protective film 526 is formed with a three-layer stacked structure of an oxide insulating film 523, an oxide insulating film 524, and a nitride insulating film 525. Also, both ends of the back gate electrode 527 substantially coincide with both ends of the gate electrode 515 as shown in FIG. 22(B). Further, the back gate electrode 527 is formed so as to cover the oxide semiconductor film 518 via the protective film 526 as shown in FIG. 22(C).

[0470] Note that the fabrication method of sample 7 shown in FIG. 22 is the same as the fabrication method of sample 1 shown in Example 1. Therefore, sample 7 can be formed by referring to the fabrication method described for sample 1.

[0471] (Sample 8) Sample 8 includes a substrate 511, a gate electrode 515 on the substrate 511, a gate insulating film 517 on the substrate 511 and the gate electrode 515, an oxide semiconductor film 518 provided on the gate insulating film 517 and in a region overlapping with the gate electrode 515, a protective film 540 provided on the oxide semiconductor film 518 and having a pair of openings 550 and 552 reaching the oxide semiconductor film 518, a pair of electrodes 521 and 522 provided on the protective film 540 and in contact with the oxide semiconductor film 518, a protective film 542 on the protective film 540 and the pair of electrodes 521 and 522, and a back gate electrode 544 provided on the protective film 542 and in a region overlapping with the gate electrode 515 (see FIG. 23). (See FIG. 23.)

[0472] Note that the ends of the back gate electrode 544 are located inside both ends of the gate electrode 515 as shown in FIG. 23(B). Also, as shown in FIG. 23(C), the back gate electrode 544 covers the oxide semiconductor film 518 through the protective films 540 and 542.

[0473] Next, the configuration of sample 8 shown in FIG. 23 is described below.

[0474] The gate electrode 515 is provided on the substrate 511. The gate electrode 515 is a laminated film of a 30-nm-thick Mo -Ti film and a 315-nm-thick Cu film.

[0475] The gate insulating film 517 is provided on the gate electrode 515. The gate insulating film 517 is a laminated film of a 30-nm-thick silicon nitride film and a 400-nm-thick silicon oxide film.

[0476] The oxide semiconductor film 518 is provided on the gate insulating film 517. The oxide semiconductor film 518 is a 50-nm-thick IGZO film.

[0477] It has a protective film 540 with openings 550 and 552 on the oxide semiconductor film 518. The protective film 540 is a silicon oxide film with a thickness of 100 nm.

[0478] It has a pair of electrodes 521 and 522 on the protective film 540 so as to cover the openings 550 and 552. The electrodes 521 and 522 are a laminated film of a Mo-Ti film with a thickness of 30 nm and a Cu film with a thickness of 425 nm.

[0479] It has a protective film 542 on the protective film 540 and the electrodes 521 and 522. The protective film 542 has a thickness of 325 nm and is a silicon oxide film.

[0480] It has a back gate electrode 544 on the protective film 542. The back gate electrode 544 is a laminated film of a Mo-Ti film with a thickness of 30 nm and an ITO film with a thickness of 10 nm.

[0481] (Sample 9) Sample 9 has a substrate 511, a gate electrode 515 on the substrate 511, a gate insulating film 517 on the substrate 511 and the gate electrode 515, an oxide semiconductor film 518 provided on the gate insulating film 517 and in a region overlapping with the gate electrode 515, a pair of electrodes 521 and 522 on the gate insulating film 517 and the oxide semiconductor film 518, and a protective film 526 on the oxide semiconductor film 518 and the pair of electrodes 521 and 522 (see FIG. 24).

[0482] Note that the protective film 526 is formed with a three-layer laminated structure of an oxide insulating film 523, an oxide insulating film 524, and a nitride insulating film 525.

[0483] Also, Sample 9 has a structure without a back gate electrode as compared with Sample 7.

[0484] Next, the method for fabricating the sample 9 shown in FIG. 24 is described below.

[0485] A gate electrode 515 was formed on the substrate 511. As the gate electrode 515, a tungsten film with a thickness of 10 n m was used.

[0486] Next, a gate insulating film 517 was formed on the gate electrode 515. As the gate insulating film 517 a silicon nitride film with a thickness of 400 nm and a silicon oxynitride film with a thickness of 50 nm were laminated to form it.

[0487] Next, an oxide semiconductor film 518 was formed on the gate insulating film 517. As the oxide semiconductor film 51 8, an IGZO film with a thickness of 35 nm was used. The IGZO film used a target with In:Ga:Zn = 1:1:1 (atomic ratio).

[0488] Next, a pair of electrodes 521 and 522 were formed on the oxide semiconductor film 518. As the electrodes 521 and 5 22, a laminated film of a tungsten film with a thickness of 50 nm, an aluminum film with a thickness of 400 nm, and a titanium film with a thickness of 200 nm was used.

[0489] Next, a protective film 526 was formed on the oxide semiconductor film 518 and the electrodes 521 and 522. As the protective film 526, a silicon oxynitride film with a thickness of 50 nm, a silicon oxynitride film with a thickness of 400 nm, and a silicon nitride film with a thickness of 100 nm were used. Note that the silicon oxynitride film with a thickness of 50 nm was formed with the substrate temperature set at 350°C. Also, the silicon oxynitride film with a thickness of 400 nm and the silicon nitride film with a thickness of 100 nm were formed with the substrate temperature set at 220°C. The sample 9 was fabricated through the above steps.

[0490]

[0491] ​(Sample 10) Sample 10 has different oxide semiconductor films 518 and post-formation heat treatments compared to Sample 9 described above. Specifically, the oxide semiconductor film 518 of Sample 10 has a laminated structure of a first oxide semiconductor film and a second oxide semiconductor film. As the first oxide semiconductor film, an IGZO film with a thickness of 35 nm was used. The first oxide semiconductor film used a target with an atomic ratio of In:Ga:Zn = 1:1:1. As the second oxide semiconductor film, an IGZO film with a thickness of 20 nm was used. The second oxide semiconductor film used a target with an atomic ratio of In:Ga:Zn = 1:3:2.

[0492] After forming the oxide semiconductor film 518 of Sample 10, heat treatment was performed at 450 °C for 1 hour in a nitrogen atmosphere. The above steps were used to fabricate Sample 10. Since the steps other than those described above for Sample 10 are the same as those of Sample 9 described above, Sample 10 can be fabricated by referring to the previous description. Note that the transistors of Sample 7, Sample 9, and Sample 10 have a channel length (L) of 6 μm and a channel width (W) of 50 μm. The transistor of Sample 8 has a channel length (L) of 10.2 μm and a channel width (W) of 82.6 μm. <Regarding the estimation of device lifetime in the plus GBT test> Next, the plus GBT tests of Samples 7 to 10 fabricated above were performed. Here, as the gate BT stress test conditions, the substrate temperature was set to 60 °C, and the measurement environment was under a darkroom (dark environment).

[0493]

[0494]

[0495]

[0496] <Regarding the estimation of device lifetime in the plus GBT test> Next, the plus GBT tests of Samples 7 to 10 fabricated above were performed. Here, as the gate BT stress test conditions, the substrate temperature was set to 60 °C, and the measurement environment was under a darkroom (dark environment). Under the conditions below, a gate voltage of +30V was applied to condition the stress time.

[0497] For Samples 7, 9, and 10, the stress time was set to 1 00 s, 500 s, 1500 s, 2000 s, and 3600 s respectively, and the variation in the threshold voltage was measured. For Sample 8, the stress time was set to 100 s, 300 s, 600 s, 1000 s, 1800 s, and 3600 s, and the variation in the threshold voltage was measured.

[0498] Fig. 25 shows the variation in the threshold voltage at each stress time for Samples 7 to 10, and the approximate curves obtained from each variation. Note that all the approximate curves shown in Fig. 25 are power approximation lines. Also, Fig. 25 is a double logarithmic graph. In Fig. 25, the horizontal axis represents the stress time expressed logarithmically, and the vertical axis represents the variation in the threshold voltage (ΔVth) expressed logarithmically. Also,

[0499] the double logarithmic graph shown in Fig. 25 has equal intervals between the logarithmic scales on the horizontal and vertical axes. From the results shown in Fig. 25, it can be seen that the angle formed between the power approximation line of the variation in the logarithmically expressed threshold voltage with respect to the logarithmically expressed stress time for Sample 7, which is one aspect of the present invention, and the straight line where the variation in the threshold voltage is 0V is in the vicinity of 17°. Also, it can be seen that the variation in the threshold voltage when the stress time is 0.1 hour is in the vicinity of 0.06V. Also, the slope of the power approximation line for Sample 7 was 0.3119 V / hr.

[0500] Also, for the comparative Sample 8, the angle formed between the power approximation line of the variation in the logarithmically expressed threshold voltage with respect to the logarithmically expressed stress time and the straight line where the variation in the threshold voltage is 0V is in the vicinity of 31° It can be seen that it is beside. Also, the amount of variation in the threshold voltage when the stress time is 0.1 hour is found to be in the vicinity of 0.05 V. Also, the slope of the power approximation line of Sample 8 was 0.599 V / hr.

[0501] Also, the angle formed by the power approximation line of the amount of variation in the threshold voltage expressed in logarithm with respect to the stress time expressed in logarithm of the comparative Sample 9 and the straight line where the amount of variation in the threshold voltage is 0 V is found to be in the vicinity of 24°. Also, the amount of variation in the threshold voltage when the stress time is 0.1 hour is found to be in the vicinity of 0.4 V. Also, the slope of the power approximation line of Sample 9 was 0.41 V / hr. is found to be in the vicinity of 0.4 V. Also, the slope of the power approximation line of Sample 9 was 0.41 V / hr.

[0502] Also, the angle formed by the power approximation line of the amount of variation in the threshold voltage expressed in logarithm with respect to the stress time expressed in logarithm of the comparative Sample 10 and the straight line where the amount of variation in the threshold voltage is 0 V is found to be in the vicinity of 27°. Also, the amount of variation in the threshold voltage when the stress time is 0.1 hour is found to be in the vicinity of 0.02 V. Also, the slope of the power approximation line of Sample 10 was 0.4 153 V / hr. is found to be in the vicinity of 0.02 V. Also, the slope of the power approximation line of Sample 10 was 0.4 153 V / hr.

[0503] As shown in FIG. 25, for Sample 7 of one aspect of the present invention, the angle formed by the power approximation line of the amount of variation in the threshold voltage expressed in logarithm with respect to the stress time expressed in logarithm and the straight line where the amount of variation in the threshold voltage is 0 V is 30° or less, and the amount of variation in the threshold voltage when the stress time is 0.1 hour is less than 0.2 V. A semiconductor device using such a relationship has a small amount of variation in the threshold voltage. Sample 7 of one aspect of the present invention can reduce the amount of variation in transistor characteristics by covering the side surface of the channel formation region of the oxide semiconductor film with upper and lower gate electrodes as found. As found. is less than 0.2 V. A semiconductor device using such a relationship has a small amount of variation in the threshold voltage. Sample 7 of one aspect of the present invention can reduce the amount of variation in transistor characteristics by covering the side surface of the channel formation region of the oxide semiconductor film with upper and lower gate electrodes as found. was found.

Claims

1. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film through the first insulating film; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film through the second insulating film; and the first conductive film has a region functioning as a first gate electrode of a transistor; the oxide semiconductor film has a region functioning as a channel formation region of the transistor; the second conductive film has a region functioning as one of a source electrode or a drain electrode of the transistor; the third conductive film has a region functioning as the other of the source electrode or the drain electrode of the transistor; the second insulating film includes an oxide insulating film and a nitride insulating film on the oxide insulating film; the fourth conductive film has a region functioning as a second gate electrode of the transistor; in the channel width direction of the transistor, the first conductive film has a region not overlapping with the oxide semiconductor film; in the channel width direction of the transistor, the fourth conductive film has a region not overlapping with the oxide semiconductor film; In a gate BT stress test under a dark room, the temperature of the substrate is set to 60°C, +30 V is applied to the first conductive film and the fourth conductive film, the stress time is set to 0.1 hour, and a semiconductor device in which the amount of variation in the threshold voltage calculated from the Vg - Id characteristics when the drain voltage of the transistor is 1 V or 10 V before and after the gate BT stress test is less than 0.2 V.

2. a first conductive film on a substrate; a first insulating film on the first conductive film; an oxide semiconductor film having a region overlapping with the first conductive film through the first insulating film; a second conductive film electrically connected to the oxide semiconductor film; a third conductive film electrically connected to the oxide semiconductor film; a second insulating film on the oxide semiconductor film; a fourth conductive film having a region overlapping with the oxide semiconductor film through the second insulating film; and the first conductive film has a region functioning as a first gate electrode of a transistor; the first insulating film includes a first nitride insulating film and a first oxide insulating film on the first nitride insulating film; The oxide semiconductor film has a region that functions as a channel formation region of the transistor. The second conductive film has a region that functions as one of a source electrode or a drain electrode of the transistor. The third conductive film has a region that functions as the other of the source electrode or the drain electrode of the transistor. The second insulating film has a second oxide insulating film and a second nitride insulating film on the second oxide insulating film. The fourth conductive film has a region that functions as a second gate electrode of the transistor. In the channel width direction of the transistor, the first conductive film has a region that does not overlap with the oxide semiconductor film. In the channel width direction of the transistor, the fourth conductive film has a region that does not overlap with the oxide semiconductor film. In a gate BT stress test under a dark room. The temperature of the substrate is set to 60°C. +30 V is applied to the first conductive film and the fourth conductive film. The stress time is set to 0.1 hour. A semiconductor device in which the amount of variation in the threshold voltage calculated from the Vg - Id characteristics is less than 0.2 V when the drain voltage of the transistor before and after the gate BT stress test is 1 V or 10 V.

3. In Claim 1 or Claim 2, The oxide semiconductor film contains In, M (where M is Al, Ga, Y, Zr, La, Ce, or Nd), and Zn. A semiconductor device.

Images