Substrate included in packaging board and method for manufacturing substrate

Abstract

To provide a substrate, a packaging board, and a method for manufacturing the substrate that appropriately distribute stress applied to a glass substrate to prevent the substrate from being damaged.SOLUTION: A substrate includes a plate-like glass substrate 21 that is included in a packaging board and has a first surface and a second surface opposed to each other, and a cavity portion 28 and a cavity extension portion 70 are disposed on the glass substrate. The cavity portion has an internal storage space therein and has one or more corners. The corner is imaginary lines where extension lines of two adjacent side surfaces of the storage space intersect each other, and the cavity extension portion is disposed at the corner, and has a corner space connected to the storage space.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] Embodiments relate to a packaging substrate applied to a packaging board, a packaging board, a method for manufacturing a board, and the like.

Background Art

[0002] In fabricating electronic components, forming a circuit on a semiconductor wafer is called the front-end (FE) process, and assembling the wafer into a state where it can be used in an actual product is called the back-end (BE) process. This back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nano-scale line widths, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, there is no technology that can perfectly package this relatively well. Therefore, the electrical performance of a semiconductor may sometimes be determined by packaging technology and the electrical connections thereby, rather than the performance of the semiconductor technology itself.

[0004] As materials for packaging substrates, ceramics or resins are applied. In the case of a ceramic substrate such as a silicon substrate, it is not easy to mount high-performance high-frequency semiconductor elements because of its high resistance value or high dielectric constant. In the case of a resin substrate, it is relatively possible to mount high-performance high-frequency semiconductor elements. However, there is a limit to reducing the wiring pitch.

[0005] Recently, silicon or glass can be applied to high-end packaging substrates. By forming through-holes in a silicon or glass substrate and applying a conductive material to these through-holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

[0006] As related prior art, there are Korean Patent Publication No. 10-2023-0035258, Korean Patent Publication No. 10-2017-0067947, etc.

Summary of the Invention

Problems to be Solved by the Invention

[0007] The purpose of the embodiment is to provide a substrate on which a cavity expansion part is formed so that the corner area of the cavity part is expanded in a packaging substrate using a glass substrate, a method for manufacturing the substrate, and a packaging substrate using the same.

[0008] Another purpose of the embodiment is to provide a method for manufacturing a packaging substrate having a cavity part including a cavity expansion part, and a packaging substrate using the same, in which the corner area of the cavity part is expanded through the glass substrate so as to ensure a sufficient distance between the corner of the cavity part and the edge of the cavity element.

Means for Solving the Problems

[0009] To achieve the above object, the substrate according to the embodiment is a plate-shaped substrate included in a packaging substrate, including a glass substrate having a first surface and a second surface facing each other, and a cavity part and a cavity expansion part are arranged on the glass substrate. The cavity part has an accommodation space inside and has one or more corners, and the corner is a virtual line where the extension lines of two adjacent side surfaces of the accommodation space intersect. The cavity expansion part is arranged at the corner and has a corner space connected to the accommodation space.

[0010] When viewed from the direction of the first surface to the second surface, the first corner is one corner where the cavity expansion part is arranged.

[0011] At the first corner, the angle on the glass substrate side of the two side surfaces can be more than 180°.

[0012] The corner space is a space in a form where a part of the glass substrate of the first corner is removed.

[0013] The edge of the corner space can have a shape of an arc of a circle or an ellipse.

[0014] The central angle of the corner space is the angle between two contact points of the two side surfaces and the arc.

[0015] The central angle of the corner space of the first corner can be 20° or more.

[0016] When viewed from the direction of the first surface to the second surface, the second corner is one corner where the cavity extension part is arranged.

[0017] In the second corner, the angle on the glass substrate side of the two side surfaces can be less than 180°.

[0018] The corner space is a space in a form where a part of the glass substrate of the second corner is removed.

[0019] The edge of the corner space has a shape of an arc of a circle or an ellipse.

[0020] The central angle of the corner space is the angle between two contact points of the two side surfaces and the arc.

[0021] The central angle of the corner space of the second corner can be 180° or less.

[0022] When viewed from the direction of the first surface to the second surface, the cavity extension part has a shape of an arc of a circle or an ellipse.

[0023] The average radius of the arc can be 40 μm or more.

[0024] The glass substrate can include glass through vias penetrating in the thickness direction.

[0025] The average radius of the arc can be 0.5 times to 3 times the radius of the glass through via.

[0026] The cavity portion can include four or more of the corners.

[0027] The cavity expansion portion can be arranged in four or more and not more than the number of the corners in the cavity portion.

[0028] The substrate can include an electronic element arranged in the cavity portion.

[0029] The distance between the side surface of the accommodation space and the electronic element is D1.

[0030] The distance between the glass wall surface of the cavity expansion portion and the electronic element is D2.

[0031] The D2 may be the same as or larger than the D1.

[0032] The substrate can include an electronic element arranged in the cavity portion.

[0033] Portions other than the electronic element in the accommodation space and the corner space can be filled with a filling material.

[0034] The filling material can include an insulating material, a metallic material, or a heat dissipation material.

[0035] The distance D3 between the end of the cavity expansion portion and the side surface of the cavity portion can be 2 μm or more.

[0036] To achieve the above object, a packaging substrate according to another embodiment includes the above-described substrate, an electronic element arranged in the cavity portion, and an upper layer arranged on the substrate and having an upper rewiring layer for transmitting an electrical signal arranged thereon.

[0037] To achieve the above object, another embodiment presents a method for manufacturing a plate-shaped substrate included in a packaging substrate.

[0038] The manufacturing method includes a step of generating a defect for forming a cavity portion and a defect for forming a cavity expansion portion in a glass substrate having a first surface and a second surface facing each other, and a step of etching the glass substrate to form a cavity portion and a cavity expansion portion.

[0039] The cavity portion is disposed in the glass substrate, has an accommodation space inside, and has one or more corners.

[0040] The corner is disposed on a virtual line where extension lines of two adjacent side surfaces of the accommodation space intersect.

[0041] The cavity expansion portion is disposed at the corner and has a corner space connected to the accommodation space.

[0042] When viewed from the direction of the first surface to the second surface, the cavity expansion portion has a shape of an arc of a circle or an ellipse.

[0043] The glass substrate includes a glass through via penetrating in the thickness direction.

[0044] The average radius of the arc can be 0.5 times to 5 times the radius of the glass through via.

Advantages of the Invention

[0045] The substrate of the embodiment, the packaging substrate including the same, and the method for manufacturing the substrate can ensure a sufficient distance between the corner of the cavity portion and the edge of the cavity element, and thereby prevent the occurrence of a short circuit of the cavity element.

[0046] In addition, the stress applied to the glass substrate can be dispersed through a cavity expansion portion that widens the corners of the cavity portion, and through this, the effect of preventing the glass substrate from being damaged can be obtained.

Brief Description of the Drawings

[0047]

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Figure 8

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Best Mode for Carrying Out the Invention

[0048] To assist in a comprehensive understanding of the methods, apparatuses, and / or systems described in this specification, the following detailed description is provided. However, various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described in this specification will become apparent after understanding the content presented in this application. For example, the order of operations described in this specification is merely exemplary and is not limited to the operations described herein. Except for steps that must proceed in a certain order, the order of operations may be changed according to the understanding of the content presented in this application. Also, the description of well-known features may be omitted to enhance clarity and conciseness after understanding the disclosure of this application. However, the omission of such features and their descriptions is not intended to be recognized as general knowledge.

[0049] The features described in this specification can be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described in this specification are provided to explain a part of the implementation methods of many possible methods, apparatuses, and / or systems described in this specification that will become apparent after understanding the disclosure of this application.

[0050] In this specification, terms such as "first", "second", "third", etc. can be used to describe various members, components, regions, layers, or cross-sections, but these members, components, regions, layers, or cross-sections are not limited to these words. Instead, such terms are used for the purpose of distinguishing one member, component, region, layer, or section from another member, component, region, layer, or section. Therefore, the first member, component, region, layer, or section referred to in the examples described in this specification can also be referred to as the second member, component, region, layer, or section without departing from the teachings of the examples.

[0051] Throughout the specification, when an element such as a layer, region, or substrate is described as "on", "connected to", or "coupled to" another element, it can be described as directly "on", "connected to", or "coupled to" the other element, or one or more other elements can intervene therebetween. In contrast, when an element is described as "directly on", "directly connected to", or "directly coupled to", no other element can intervene therebetween. Similarly, expressions such as "between" and "directly between", and "contact" and "directly contact" can also be interpreted as described above.

[0052] The terms used in this specification are for illustrative purposes only and are not used to limit the disclosure. The singular forms used in this specification are intended to include the plural forms as well, unless the context clearly indicates otherwise. The term "and / or" used in this specification includes any one or more combinations of the related listed items. The terms "comprising", "consisting of" and "including" in this specification indicate the presence of the specified features, numbers, operations, elements, components and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, operations, elements, components and / or combinations thereof. In this specification, the use of the term "can" in connection with an illustration or example (e.g., what the illustration or example includes or can embody) means that there is at least one illustration or example in which such a feature is included or embodied, but not all examples are limited to this.

[0053] In this application, "B is located on A" means that B is in direct contact with A, or is disposed on A with another layer or structure intervening therebetween, and thus, it should not be construed that B is in direct contact with A.

[0054] Unless otherwise defined, all terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the technical field to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be construed to have a meaning consistent with their meaning in the context of the prior art and the present invention, and should not be construed in an idealized or overly formal sense unless explicitly defined herein.

[0055] In the above one or more examples, the description of "A and / or B" means "A, B, or A and B".

[0056] In the above one or more examples, terms such as "first", "second", "A" or "B" are used to distinguish the same terms from each other.

[0057] In the above one or more examples, the singular form is to be construed contextually as including not only the singular form but also the plural form, unless otherwise specifically mentioned.

[0058] FIG. 1 is a conceptual diagram for explaining a cross-sectional structure of a packaging substrate according to an embodiment. FIGS. 2A and 2B are conceptual diagrams for explaining in cross-section the structures of packaging substrates according to other embodiments, respectively. FIG. 3A is a conceptual diagram for explaining a process of generating the cross-sectional structure of the packaging substrate of FIG. 2A. Further, FIG. 3B is a conceptual diagram for explaining a process of generating the cross-sectional structure of FIG. 2B.

[0059] To achieve the above object, a semiconductor device 100 according to an embodiment includes a semiconductor element part 30 where one or more semiconductor elements 32, 34, 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, transmitting electrical signals between the semiconductor elements 32, 34, 36 and the outside, and connecting to each other.

[0060] A packaging substrate 20 according to an embodiment includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity part 28 where an electronic element 40 can be located.

[0061] The semiconductor element part 30 means an element mounted on the semiconductor device and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, as the semiconductor element part 30, for example, arithmetic elements such as a CPU and a GPU (first semiconductor element: 32, second semiconductor element: 34), storage elements such as a memory chip (third semiconductor element: 36), etc. may be applied, but any semiconductor element mounted on the semiconductor device can be applied without limitation.

[0062] As the motherboard 10, a motherboard such as a printed circuit board or a printed wiring board may be applied.

[0063] The packaging substrate 20 can further include a lower layer 29 that is selectively located under the core layer.

[0064] The core layer 22 includes a glass core 21 including a first region 221 having a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 that is thinner than the first thickness, a plurality of core vias 23 penetrating the glass core 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23 and electrically connecting a first surface 213 of the glass core 21 and a second surface 214 facing the first surface through the core vias 23 (see (a) of FIG. 3A).

[0065] The second region 222 of the core layer 22 can serve as a cavity structure.

[0066] Within the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other, and these two surfaces are generally parallel to each other, so the glass core 21 has a constant thickness throughout.

[0067] The internal space 281 formed by the difference in thickness between the first region 221 and the second region 222 serves to accommodate part or all of the electronic element 40. FIGS. 2B and 3B illustrate a full cavity from which the glass core of the second region has been removed. However, the embodiments are not limited thereto, and a half cavity is also applicable. An example of the half cavity is presented in FIGS. 2A and 3A.

[0068] The glass core 21 can include core vias 23 penetrating the first surface 213 and the second surface 214. When the second thickness is not zero, the core vias 23 can be formed in both the first region 221 and the second region 222 and can be formed with an intended pitch and pattern. Also, when the second thickness is zero, the core vias 23 can be formed in the first region 221 and can be formed with an intended pitch and pattern.

[0069] As a packaging substrate for semiconductor devices, conventionally, a form in which a silicon substrate and an organic substrate are laminated has been applied. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements occurring when applied to a high-speed circuit, and there is a drawback that power loss is relatively large. Also, in the case of an organic substrate, in order to form a more complex distribution pattern, it is necessary to increase the area, but this does not conform to the manufacturing process of miniaturized electronic devices. In order to form a complex distribution pattern within a defined size, it is substantially necessary to miniaturize the pattern, but due to the characteristics of materials such as polymers applied to organic substrates, there is a substantial limit to the miniaturization of the pattern.

[0070] In an embodiment, as a method for solving such problems, the glass core 21 is applied as a support of the core layer 22. Also, together with the glass core 21, by applying a core via 23 formed through the glass core 21, the length of the electrical flow is further shortened, providing a packaging substrate 20 having a further miniaturized size, a faster reaction, and less loss characteristics.

[0071] It is preferable to apply a glass substrate applied to a semiconductor to the glass core 21. For example, a borosilicate glass substrate, a non-alkali glass substrate, etc. may be applied, but it is not limited thereto.

[0072] The core via 23 penetrates the glass core 21. The core via 23 can be formed by a method of removing a predetermined region of the glass core 21, and specifically, it can be formed by etching plate-shaped glass by a physical and / or chemical method.

[0073] Specifically, for the formation of the core via 23, after forming a defect (scratch) on the surface of the glass core by a method such as a laser, a method of chemically etching, laser etching, etc. may be applied, but it is not limited thereto.

[0074] The core vias 23 may be located in a number ranging from 100 to 3,000, from 100 to 2,500, or from 225 to 1,024, based on the unit area (1 cm × 1 cm) of the glass core 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer or the like and the performance of the packaging substrate can be improved.

[0075] The core distribution layer 24 includes a core distribution pattern 241 which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass core via a through-via, and a core insulating layer 223 that covers the core distribution pattern. The core layer 22 forms an electrically conductive layer inside thereof via a core via, thereby serving as an electrical path across the glass core 21, and connecting the upper and lower portions of the glass core at a relatively short distance, so that faster electrical signal transmission and low-loss characteristics can be achieved. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0076] The cavity portion 28 is not limited in its shape, and may be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, or the like.

[0077] The shape of the electronic element 40 may be generally cylindrical, cuboid, or polygonal.

[0078] The cavity portion 28 may include a cavity distribution pattern which is an electrically conductive layer that electrically connects the electronic element 40 and the core distribution layer 24, and an insulating layer that covers the cavity distribution pattern.

[0079] On the other hand, the cavity portion according to another embodiment may be embodied in a form that penetrates the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the formation process of the core vias 23, and the area and shape penetrating the glass core 21 may be different from those of the core vias 23.

[0080] In such an embodiment, an insulating layer may be formed after the electronic elements 40 are arranged in the cavity portion. That is, an insulating layer may be formed in the cavity portion through the process of forming the core insulating layer 223 described above.

[0081] The core distribution pattern 241 may be formed such that it can be electrically connected to the electronic element 40.

[0082] The electronic element 40 may include an active element such as a transistor, or a power transmission element such as a multilayer ceramic capacitor (MLCC), that is, a passive element.

[0083] When an element such as a transistor that serves to convert an electrical signal between a motherboard and a semiconductor element portion to an appropriate level is applied as the electronic element 40, a transistor or the like is applied to the passage of the packaging substrate 20, so that a semiconductor device 100 that is more efficient and has a high speed can be provided.

[0084] Also, a power transmission element such as a multilayer ceramic capacitor (MLCC) plays an important role in the performance of semiconductor elements. Power transmission elements, which are passive elements, are generally applied to at least 200 or more semiconductor elements, and their performance is also affected by the characteristics of the electrically conductive layer around the elements in transmitting power. In one embodiment, a non-circular core via can be applied to a place where a low-resistance electrically conductive layer is required like such a power transmission element.

[0085] On the other hand, the electronic element 40 may be applied by individually inserting passive elements such as capacitors, or an element group including a plurality of passive elements embedded (embedded) between insulator layers (electronic element insulating layers) may be inserted into the electronic element after being formed such that the electrodes are exposed. In the latter case, the workability of manufacturing the packaging substrate can be made smoother, and it is more advantageous for the insulating layer to be located in a sufficient and highly reliable manner in the complex space between elements.

[0086] The glass core 21 serves an intermediate role in connecting the semiconductor element portion 30 and the motherboard 10 to the upper and lower parts respectively, and the core via 23 serves as a path for transmitting these electrical signals, so that smooth signal transmission is achieved. For the purpose of distinguishing from the core vias in the second region 222 described later, the core vias arranged in the first region 221 are referred to as first region core vias.

[0087] An upper layer 26 is located on the first surface 213.

[0088] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a cover layer 60 in which an opening is formed where the connection electrode of the semiconductor element portion can directly abut.

[0089] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an electrically conductive layer having a predetermined pattern and being electrically connected to at least a part of the core distribution layer 24, and an upper distribution pattern 251 built in the upper insulating layer 253. The upper distribution layers 25 arranged vertically with respect to each other can be connected to each other via blind vias 252.

[0090] The upper insulating layer 253 can be applied as an insulator layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler may be applied, but it is not limited thereto.

[0091] The insulator layer may be formed by a method of forming a coating layer and curing it, or may be formed by a method of laminating an insulator film formed into a film in an uncured or semi-cured state to the core layer 22 and curing it. At this time, if a vacuum lamination method or the like is applied, the insulator can be embedded into the space inside the core via 23, and an efficient process can proceed.

[0092] In one embodiment, even when a multilayer insulator layer is laminated and applied, it may be difficult to substantially distinguish between the insulator layers, and the plurality of insulator layers are collectively referred to as an upper insulator layer. Also, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253. In such a case, the boundary therebetween is not substantially distinguished. Alternatively, in another embodiment, the boundary of the insulator layer can also be generated by setting different pressures and temperatures for curing the multilayer insulator layer.

[0093] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a preset form. For example, it may be formed by a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary portions of the insulator layer, an electrically conductive layer is formed by a method such as copper plating. After selectively removing unnecessary portions of the electrically conductive layer, an insulator layer is formed again on this electrically conductive layer. After removing unnecessary portions again, the method of forming an electrically conductive layer by a method such as plating is repeated to form the upper distribution pattern 251 in which the electrically conductive layer is formed in a vertical or horizontal direction in the intended pattern.

[0094] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, electrical signals are smoothly transmitted between the semiconductor element portion 30, and at least a part thereof is formed to include a fine pattern so that an intended complex pattern can be sufficiently accommodated. At this time, the fine pattern may have a width and a pitch each less than 4 μm, may be 3.5 μm or less, may be 3 μm or less, may be 2.5 μm or less, or may be 2.3 μm or less. The width and the pitch may be 1 μm or more (hereinafter, the description of the fine pattern is the same).

[0095] The upper surface connection layer 27 includes an upper surface connection pattern 272 located in the upper insulating layer 253, which is electrically connected to at least a part of the upper distribution pattern 251, and an upper surface connection electrode 271 that electrically connects the semiconductor element portion 30 and the upper surface connection pattern 272.

[0096] The upper surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a part thereof may be embedded while being exposed on the upper insulating layer. For example, when the upper surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating. When the upper surface connection pattern is embedded while a part thereof is exposed on the upper insulating layer, after forming a copper plating layer or the like, a part of the insulating layer or the electrically conductive layer may be removed by a method such as surface polishing or surface etching.

[0097] The upper surface connection pattern 272 can include at least a part of a fine pattern, like the upper distribution pattern 251 described above. The upper surface connection pattern 272 including such a fine pattern enables more elements to be electrically connected under a narrow area, makes the connection of electrical signals between elements or with the outside smoother, and enables more integrated packaging.

[0098] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or may be connected via an element connection portion 51 such as a solder ball.

[0099] In the case of the half-cavity substrate, the cavity portion 28 is located above and / or below the second region 222, and can include a cavity distribution layer 282 that is electrically connected to the core distribution pattern 241 and an internal space 281 where the electronic element 40 is located. The cavity distribution layer 282 can be formed via the second region core via 232 (see FIG. 2B).

[0100] Specifically, the second region 222 has a thinner thickness of the glass core 21 compared to the first region 221, and the electronic element 40 can be located in the internal space 281 formed by the difference in thickness. Further, the core via 23 and the core distribution layer 24 formed in the glass core 21 serve as an electrical connection structure for connecting the electronic element 40 and an external element.

[0101] Also, as described above, instead of the second region 222, a cavity portion in a form penetrating the first surface 213 and the second surface 214 of the glass core 21, i.e., the first region 221, can be generated, and the electronic element 40 can be arranged in the cavity portion.

[0102] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to a core distribution pattern 241 located on at least a part of the second surface 214 of the core layer 22, or may be electrically connected through a board connection portion 52 such as a solder ball. Also, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 through a lower layer (not shown) located below the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0103] In one example, in the packaging substrate 20 located between the semiconductor element portion 30 and the motherboard 10, substantially no additional other substrates can be applied other than the glass core 21.

[0104] Conventionally, when connecting an element and a motherboard, an interposer and an organic substrate were laminated and applied together therebetween. This is understood to be applied in such a multi-stage form for at least two reasons. One is that there is a problem in scale in directly bonding a fine pattern of an element to a motherboard, and the other is that a problem of damage to wiring due to a difference in thermal expansion coefficient may occur during the bonding process or the driving process of a semiconductor device.

[0105] In an embodiment, a glass core having a thermal expansion coefficient similar to that of a semiconductor element is applied, and a fine pattern having a fine scale sufficient for mounting an element is formed on the first surface of the glass core and its upper layer, thereby solving such problems.

[0106] Hereinafter, a method for manufacturing a packaging substrate according to an embodiment of the present invention will be described.

[0107] FIGS. 4 and 5 are flowcharts for explaining the manufacturing process of a packaging substrate according to an embodiment in cross-section.

[0108] First, as shown in FIG. 4(a), a glass core 21a having flat first and second surfaces is prepared, and a defect (groove) 21b is formed on the glass surface at a predetermined position for forming core vias. The glass core may be a glass core applicable to substrates of electronic devices, etc. For example, an alkali-free glass core or the like may be applied, but it is not limited thereto. As a commercially available product, products manufactured by manufacturers such as Corning, Schott, and AGC may be applied. For forming the defect (groove), methods such as mechanical etching and laser irradiation may be applied.

[0109] As shown in FIG. 4(b), the glass core 21a with the defect (groove) 21b is subjected to an etching step of forming core vias 23 through a physical or chemical etching process. In the etching process, the glass core forms vias at the defect portion, and at the same time, the surface of the glass core 21a may also be etched. In order to prevent such etching of the glass surface, a masking film or the like can be applied. However, considering the annoyance of the process of applying and removing the masking film, the defective glass core itself can be etched. In such a case, the thickness of the glass core having core vias may be slightly thinner than the thickness of the initial glass core.

[0110] Thereafter, as shown in FIGS. 4(c) and (d), a core layer manufacturing step can be performed by forming an electrically conductive layer 21d on the glass core. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited thereto.

[0111] Since the surface of the glass (including the surface of the glass core and the surface of the core via) and the surface of the copper metal have different properties, the adhesion is poor. In embodiments, the adhesion between the glass surface and the metal can be improved by two methods: the dry method and the wet method.

[0112] The dry method is a method of applying sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel can be sputtered together with copper or the like. In such a case, the adhesion between the glass and the metal can be improved by the anchor effect in which the surface morphology of the glass and the metal particles interact.

[0113] The wet method is a method of performing primer treatment, that is, a method of forming a primer layer 21c by pretreatment with a compound having a functional group such as an amine. After pretreatment with a silane coupling agent according to the intended degree of adhesion, primer treatment can be performed with a compound or particles having an amine functional group. As mentioned above, the support substrate of the embodiment needs to be highly performant enough to form a fine pattern, and this must be maintained even after primer treatment. Therefore, when such a primer contains nanoparticles, it is preferable to apply nanoparticles having an average diameter of 150 nm or less. For example, particles having an amine group are preferably nanoparticles. The primer layer may be formed by applying a bonding strength improver manufactured by, for example, the CZ series of MEC.

[0114] The seed layer / primer layer 21c can selectively form a metal layer in a state where the portion where formation of the electrically conductive layer is unnecessary has been removed or in a state where it has not been removed. Further, the seed layer / primer layer 21c can perform processing on the portions where formation of the electrically conductive layer is necessary or unnecessary in a selectively activated state or deactivated state for metal plating, and subsequent steps can be performed. For example, as the activation or deactivation treatment, light irradiation treatment such as laser light of a certain wavelength or chemical treatment may be applied. For the formation of the metal layer, a copper plating method or the like applied to the manufacture of semiconductor elements may be applied, but it is not limited thereto.

[0115] As shown in FIG. 4(e), when a part of the core distribution layer is unnecessary, it may be removed, or after a part of the seed layer has been removed or deactivated, metal plating is performed to form an electrically conductive layer in a predetermined pattern, whereby the etching layer 21e of the core distribution layer may be formed.

[0116] FIG. 5 illustrates a manufacturing step of forming an insulating layer and an upper distribution pattern according to an embodiment.

[0117] As shown in FIG. 5(a), after the formation of the core via, which is the electrically conductive layer, the core distribution layer, a step of forming an insulating layer that fills the empty space with the insulating layer can be performed. At this time, as the insulating layer to be applied, one manufactured in the form of a film can be applied, and for example, a method of vacuum laminating an insulating layer in the form of a film may be applied. When vacuum lamination is performed in this way, the insulating layer is sufficiently embedded in the empty space inside the core via, so that a core insulating layer without void formation can be formed.

[0118] FIGS. 5(b) to 5(e) illustrate an upper layer manufacturing step.

[0119] The upper layer manufacturing step is a step of forming an upper distribution layer including an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer may be formed by coating a resin composition for forming the insulating layer 23a or by laminating an insulating film. For simplicity, it is preferable to apply the method of laminating an insulating film. The lamination of the insulating film can be performed by a process of laminating and curing the insulating film. At this time, if the vacuum lamination method is applied, the insulating resin can be sufficiently embedded even in a layer where no electrically conductive layer is formed inside the core via. The upper insulating layer also directly contacts at least a part of the glass core, and therefore, one having sufficient adhesion is applied. Specifically, it is preferable that the glass core and the upper insulating layer have a characteristic that the adhesion test value according to ASTM D3359 satisfies 4B or more.

[0120] The upper distribution pattern can be formed by repeating the process of forming the insulating layer 23a, forming the electrically conductive layer 23c in a predetermined pattern, and etching unnecessary portions to form the etched layer 23d of the electrically conductive layer. In the case of the electrically conductive layers formed adjacent to each other with the insulating layer interposed therebetween, it can be formed by a method of forming blind vias 23b in the insulating layer and then performing a plating process. The formation of the blind vias may be performed by a dry etching method such as laser etching or plasma etching, or a wet etching method using a masking layer and an etching solution.

[0121] Thereafter, although not shown, an upper surface connection layer and a cover layer can be formed.

[0122] The upper connection pattern and the upper connection electrode can also be formed by a process similar to the formation of the upper sub-layer. Specifically, an etching layer of the insulating layer may be formed on the insulating layer 23e, and after forming an electrically conductive layer thereon again, it may be formed by a method such as forming an etching layer of the electrically conductive layer. However, a method of selectively forming only the electrically conductive layer without applying an etching method may also be applied. The cover layer may be formed with an opening (not shown) at a position corresponding to the upper connection electrode so that the upper connection electrode is exposed and can be directly connected to the element connection portion or the terminal of the element.

[0123] When the upper layer is generated, a step of forming the lower connection layer and the cover layer to generate the lower layer can be performed. The lower sub-layer and / or the lower connection layer, and optionally the cover layer (not shown), can be formed in a manner similar to the above-described upper connection layer and cover layer formation steps.

[0124] On the other hand, as described above, a cavity portion can be generated in the glass substrate. When processing the corner portion of the cavity portion to generate the cavity portion, in order to substantially suppress the occurrence of damage to the angular corner portion and for the smooth progress of the cavity portion generation process, usually, a curved surface can be formed in a form in which the angular portion of the corner portion is rounded. The curved surface can have a certain radius of curvature.

[0125] When embedding a cavity element in the cavity portion, it may be difficult to ensure a sufficient distance between the corner of the cavity portion and the corner of the cavity element due to the curved surface generated at the corner portion. This may increase the probability of a short circuit in the embedded cavity element. Further, in order to solve the above problem, if the corner portion of the cavity portion is processed into a sharp shape, cracks may occur in the cavity portion, and there may occur a problem of being vulnerable to breakage. As another method, when the size of the cavity portion is made very large compared to the size of the cavity element, the distance between the cavity element and the inner wall surface of the cavity portion becomes wide, and the occurrence of the angulation of the packaging substrate may become intense. Further, it may have an adverse effect on the utilization of the surface area of the packaging substrate.

[0126] Hereinafter, a structure including a glass substrate in a form processed to serve as a support substrate as a plate-like substrate included in a packaging substrate will be described as a substrate.

[0127] FIG. 6 is a diagram exemplarily showing the structure of a corner portion of a cavity portion having a radius of curvature and a cavity element.

[0128] Referring to FIG. 6, a cavity portion 28 may be formed in the glass substrate, and a cavity element 40 may be disposed in the cavity portion 28. For example, when the cavity element 40 is disposed in the cavity portion 28, a gap is formed therebetween. Here, when the corner of the cavity portion 28 is processed into a curved surface, the curved surface is usually formed inside the corner.

[0129] In this case, the distance between the embedded die, that is, the corner portion of the embedded cavity element [i.e., the edge of the cavity element] and the corner wall of the cavity is shown to be narrower than the distance in the straight portion. Contact may occur between the corner of the cavity portion 28 and the edge 61 of the cavity element. If a conducting wire is disposed here, a short circuit of the cavity element may occur.

[0130] To prevent this, if the distance between the wall of the cavity portion and the cavity element is widened as a whole, voids are likely to be formed during the formation of the insulating layer, and surface undulation may be easily formed.

[0131] To prevent the above-described problems, this specification proposes a method of forming a cavity expansion portion in the corner region of the cavity portion.

[0132] As the cavity expansion portion, for example, an embodiment in which the corner region of the cavity portion is expanded to apply a corner space is proposed. Through this, it is possible to prevent the problem that a sufficient distance cannot be ensured between the corner of the cavity portion and the corner of the cavity element due to the curved surface in the corner region during the processing of the conventional cavity portion, resulting in a high probability of short circuit. Further, since the stress applied to the glass substrate is appropriately dispersed through the corner space via the cavity expansion portion, an effect of preventing breakage of the glass substrate can be obtained.

[0133] A substrate according to an embodiment is a plate-like substrate included in a packaging substrate, and includes a glass substrate 21 having a first surface and a second surface facing each other, and a cavity portion 28 and a cavity expansion portion 70 are disposed on the glass substrate.

[0134] The cavity portion 28 has an accommodation space inside and has one or more corners.

[0135] The corner is a virtual line where the extension lines of two adjacent sides of the accommodation space intersect, and the cavity expansion part 70 is disposed at the corner and has a corner space connected to the accommodation space.

[0136] FIG. 7 is a diagram exemplarily showing the structure of a cavity part and a cavity expansion part generated according to an embodiment. FIG. 7 is a diagram conceptually simplified for explaining the cavity part of a packaging substrate generated according to an embodiment, and the content described with reference to FIGS. 1 to 5 can be applied.

[0137] Referring to FIG. 7, the glass substrate can include a cavity expansion part in which the corners are expanded in an arc shape when the cavity part 28 is viewed from above. The cavity expansion part 70 can have a corner space connected to the accommodation space of the cavity part 28.

[0138] For example, at the corners of the cavity part 28, after forming defects (scratches) by a method such as irradiation of laser energy in the same manner as when forming core vias, an etching process is performed to form both the cavity part 28 and the cavity expansion part 70.

[0139] The cavity expansion part 70 can be a region expanded in the shape of a via penetrating the glass substrate 21 at the corners of the cavity part 28. The corner space can be a space in a form in which a part of the glass substrate at the corner is removed.

[0140] For example, the edge of the corner space may be in the shape of an arc of a circle or an ellipse.

[0141] For example, the packaging substrate can include an electronic element (cavity element) 40 disposed in the cavity part.

[0142] For example, the distance between the cavity wall (side surface) of the cavity expansion part 70 and the edge 61 of the cavity element 40 may be equal to or greater than the distance between the cavity wall of the side surface of the cavity part 28 and the cavity element 40.

[0143] For example, the distance between the side surface of the accommodation space and the electronic element 40 is D1, the distance between the glass wall surface of the cavity expansion part 70 and the electronic element 40 is D2, and the D2 may be the same as or greater than the D1 (see FIG. 7). For example, the D2 may be 200 μm or less. In this case, the short-circuit prevention effect is excellent.

[0144] For example, the distance D3 between the end of the cavity expansion part 70 and the side surface of the cavity part 28 can be 2 μm or more (see FIG. 7). The distance may be 2 μm or more, 5 μm or more, 10 μm or more, 15 μm or more, 20 μm or more, 25 μm or more, 30 μm or more, 35 μm or more, 40 μm or more, 45 μm or more, 50 μm or more, 55 μm or more, or 60 μm or more. The distance may be 120 μm or less, 110 μm or less, 100 μm or less, or 90 μm or less. In this case, the degree of utilization of the space on the substrate can be increased, and it can contribute to an efficient configuration of the cavity expansion part.

[0145] The corner of the cavity part including the region expanded to the shape of the via penetrating the glass substrate at the corner of the cavity part 28 can be called a corner of the "Mickey Mouse ears" shape ("Mickey Mouse ears" shaped corner) or a corner of the "Mickey Mouse ears" ("Mickey Mouse ears" corner).

[0146] For example, when viewed from the first surface to the second surface of the glass substrate 21, the cavity expansion part 70 may be in the shape of an arc of a circle or an ellipse. The arc has a radius, and in the case of an ellipse, the average radius is treated as the radius.

[0147] The average radius of the arc can be 40 μm or more. The average radius may be 40 μm or more, 45 μm or more, 50 μm or more, 55 μm or more, 60 μm or more, 65 μm or more, 70 μm or more, 75 μm or more, 80 μm or more, 85 μm or more, 90 μm or more, 95 μm or more, or 100 μm or more. The average radius may be 200 μm or less, 180 μm or less, 160 μm or less, or 150 μm or less. In this case, it can enhance the degree of space utilization of the substrate and contribute to the configuration of an efficient cavity expansion part.

[0148] The glass substrate 21 can include glass through vias penetrating in the thickness direction.

[0149] The average radius of the arc may be 0.5 times or more, 0.7 times or more, or 0.9 times or more the radius of the glass through via. The average radius may be 3 times or less, 2.5 times or less, 2 times or less, or 1.5 times or less the radius of the glass through via. In this case, it can enhance the degree of space utilization of the substrate and contribute to the configuration of an efficient cavity expansion part.

[0150] On the other hand, FIG. 7 shows an embodiment in which the cavity expansion part 70 is an area expanded in the shape of a via penetrating the glass substrate 21, but the shape of the cavity expansion part 70 proposed in this specification is not limited to the embodiment. For example, various forms of corner shapes can be selected in consideration of interference during the embedding of a substance in the cavity part 28. Exemplarily, the cavity expansion part may be formed in a shape such as a part of a circle or a part of an ellipse.

[0151] FIG. 8 is a diagram exemplarily showing the structure of a substrate including a cavity part and a cavity element generated by another embodiment.

[0152] Referring to FIG. 8, the substrate can include a cavity part 28 in which a cavity expansion part 70 is formed at a corner. An electronic element (cavity element) 40 can be arranged in the cavity part 28.

[0153] The inner wall surface of the cavity portion 28 may be such that one surface of the glass substrate is exposed. As another example, an additional layer may be disposed on the inner wall surface of the cavity portion 28.

[0154] In FIG. 8, the core distribution pattern 241 that connects the first surface and the second surface of the glass substrate 21 as the metal layer is illustrated, but the present invention is not limited thereto, and a layer having electrical conductivity such as a heat dissipation layer may be disposed.

[0155] Specifically, one or two or more cavity elements (electronic elements) 40 may be disposed in the internal space of the cavity portion. Then, the internal space excluding the cavity may be filled with a filling material. The filling material may include an insulating material, a metallic material, or a heat dissipation material, and two or more mutually divided materials may be disposed in a predetermined arrangement.

[0156] Exemplarily, a metal layer may be disposed on the inner wall surface. Exemplarily, the metal layer may be an electrically conductive layer, and a metal layer such as copper may be applied. In this case, the accommodation space refers to the portion excluding the electrically conductive layer. Exemplarily, the thickness of the metal layer is D4, and the distance between the side surface of the accommodation space and the electronic element is D1 (see FIG. 8).

[0157] The portions other than the electronic elements in the accommodation space and the corner space may be filled with a filling material, and exemplarily, may be filled with an insulating material, a metallic material, or a heat dissipation material, and preferably may be filled with an insulating material.

[0158] The insulating material may include LCP (liquid crystal polymer), EMC (Epoxy Molding Compound), ABF (Ajinomoto Build-up Film), or MPI (Modified Polyimide).

[0159] FIG. 9 is a diagram exemplarily showing the structure of a glass substrate including a cavity portion generated by another embodiment.

[0160] Referring to FIG. 9, the glass substrate 21 can include two or more cavity portions 28 in which a number of cavity expansion portions 70 are formed. In the drawing, it is exemplified that four cavity portions are arranged. Since specific descriptions of the cavity portion, the cavity expansion portion, etc. overlap with the above-described descriptions, detailed descriptions are omitted.

[0161] As shown in FIG. 9, the cavity expansion portions 70 of different cavity portions 28 arranged adjacent to each other can have a distance of P or more.

[0162] When the distance between the side surface of the cavity portion 28 and the end portion of the cavity expansion portion 70 is D5, the P may be 1 time or more, 2 times or more, 3 times or more, or 4 times or more of the D5. Also, the P may be 20 times or less, 16 times or less, 14 times or less, 12 times or less, 10 times or less, 9 times or less, or 8 times or less of the D5. In this case, by ensuring a space (gap) of a certain distance or more, it is possible to prevent the cavity frame from being damaged. Also, it can enhance the degree of space utilization of the substrate and contribute to an efficient configuration of the cavity expansion portion.

[0163] The P may be 100 μm or more, 110 μm or more, 120 μm or more, or 130 μm or more. Also, the P may be 300 μm or less, 280 μm or less, 260 μm or less, 240 μm or less, or 220 μm or less. In this case, it may be advantageous for preventing damage to the glass substrate such as the cavity frame. Also, the substrate can stably ensure the support function and contribute to an efficient configuration of the cavity expansion portion.

[0164] FIGS. 10A, 10B, 10C, and 10D are diagrams exemplarily showing the structures of cavity portions generated by other embodiments, respectively.

[0165] The cavity portion 28 can include four or more of the corners. Exemplarily, one cavity portion can include four, eight, or twelve of the corners.

[0166] The cavity expansion portion 70 can be arranged in four or more and equal to or less than the number of the corners in the cavity portion 28. The cavity expansion portion 70 can be arranged in equal to or less than the number of the corners of the cavity portion 28.

[0167] For example, referring to FIG. 10A, in a top view, a cavity portion 28 having a rectangular shape can be generated, and cavity expansion portions 70 can be formed at four corners (denoted as M1) of the cavity portion 28. Specific descriptions of the cavity portion, the cavity expansion portion, etc. are as described above.

[0168] For example, referring to FIG. 10B, in a top view, a cavity portion 28 in a form where two rectangles intersect in a cross shape can be generated, and cavity expansion portions 70 can be formed at twelve corners of the cavity portion 28. That is, cavity expansion portions 70 can be formed at the corners where the sides of the cavity portion 28 intersect vertically. In other words, referring to FIG. 10B, in a top view, a cross-shaped cavity portion 28 can be generated, and cavity expansion portions 70 can be formed at twelve corners of the cavity portion 28. Specific descriptions of the cavity portion, the cavity expansion portion, etc. are as described above.

[0169] For example, referring to FIGS. 10C and 10D, in a top view, a cavity portion 28 in a form where one side of a rectangle protrudes convexly in a rectangular shape can be generated, and cavity expansion portions 70 can be formed at eight corners of the cavity portion 28. That is, cavity expansion portions 70 can be formed at the corners where the sides of the cavity portion 28 intersect vertically. Specific descriptions of the cavity portion, the cavity expansion portion, etc. are as described above.

[0170] On the one hand, the shape of the cavity expansion part proposed in this specification is not limited to the above embodiments. For example, considering the interference during the embedding of the substance into the cavity part, various forms of corner shapes can be selected. For example, the cavity expansion part can be formed such that when viewed from the first surface to the second surface of the glass substrate, the corner region of the cavity part is expanded. For example, the cavity expansion part can be formed such that when viewed from the first surface to the second surface of the glass substrate, the corner region of the cavity part is expanded in the shape of an arc.

[0171] Referring to FIGS. 10A, 10B, 10C, and 10D, the cavity expansion part will be described in more detail. However, the following description of the cavity expansion part is applicable to all of the above-described cavity expansion parts.

[0172] When viewed from the direction of the first surface to the second surface, the first corner M1 is one corner where the cavity expansion part is disposed.

[0173] The first corner space is a space in a form where a part of the glass substrate of the first corner M1 is removed.

[0174] The first corner M1 is disposed in contact with a first - 1 surface and a first - 2 surface, which are two wall surfaces (edges) of adjacent cavity parts. The angle between the first - 1 surface and the first - 2 surface at the first corner can be less than 180°. The angle can be 160° or less, 140° or less, 120° or less, 110° or less, 100° or less, or 90° or less. The angle can also be 30° or more, 40° or more, or 50° or more.

[0175] This angle refers to the angle viewed from the cavity part 28 side. Also, the corner space at the first corner M1 can have an edge in the shape of an arc of a circle or an ellipse.

[0176] The central angle of the corner space is the angle between two contact points of the two side surfaces and the arc. The central angle of the corner space is measured at the centroid of the corner space. Also, the central angle of the corner space is measured along the outer contour line of the corner space.

[0177] A1, which is the central angle of the corner space of the first corner M1, can be 120° or more. A1 may be 160° or more, or 180° or more.

[0178] A1, which is the central angle of the corner space of the first corner M1, can be more than 180°. A1 may be 200° or more, 235° or more, or 260° or more. A1 can be 320° or less.

[0179] When viewed in the direction from the first surface to the second surface, the second corner M2 is another example of a corner where the cavity expansion part is arranged.

[0180] The second corner M2 is arranged in contact with the second - 1 surface and the second - 2 surface, which are two wall surfaces (edges) of adjacent cavity parts. The angle between the second - 1 surface and the second - 2 surface at the second corner can be more than 180°. The angle may be 160° or less, 140° or less, 120° or less, 110° or less, 100° or less, or 90° or less. The angle may be 30° or more, 40° or more, or 50° or more. This angle refers to the angle viewed from the cavity part 28 side. Also, the corner space at the second corner M2 can have an edge in the shape of an arc of a circle or an ellipse.

[0181] The cavity protrusion of the second corner M2 can be in a shape that protrudes from the cavity part toward the glass substrate side (see Fig. 10C). The centroid of the cavity protrusion can be located within the cavity part.

[0182] The central corner A2 of the corner space of the second corner M2 can be 180° or less. The central corner A2 of the corner space of the second corner M2 may be 180° or less, 160° or less, 140° or less, 120° or less, 110° or less, or 100° or less. The central corner A2 may be 10° or more, or 20° or more.

[0183] As another embodiment, referring to FIG. 10D, the cavity expansion part described above is arranged in the first corner M1, and the second corner M2 may be chamfered by removing the angular glass part or substantially processing it into a curved surface.

[0184] When processing into a curved surface, the radius of curvature may be, for example, 35 μm or more, or 60 μm or more. The radius of curvature may be, for example, 200 μm or less.

[0185] The center of gravity of the cavity protrusion can be located outside the cavity part.

[0186] The central corner A2 of the corner space of the second corner M2 can be less than 180°. The central corner A2 of the corner space of the second corner M2 may be 170° or less, 160° or less, 140° or less, 120° or less, 110° or less, or 100° or less. The central corner A2 may be 2° or more, 5° or more, 10° or more, or 20° or more.

[0187] The embodiment can prevent the problem of high probability of short circuit by ensuring a sufficient distance between the wall of the cavity expansion part and the corner of the cavity element, and through the cavity expansion part, the stress applied to the glass substrate can be appropriately dispersed to obtain the effect of preventing the glass substrate from being damaged.

[0188] The packaging substrate according to the embodiment of the present specification applies a substrate having the above-described cavity expansion portion as a glass substrate. The packaging substrate includes the above-described substrate, an electronic element disposed in the cavity portion, and an upper layer disposed on the substrate and having an upper rewiring layer for transmitting an electrical signal. The packaging substrate may further include a lower layer. Specific descriptions of the packaging substrate, the cavity portion, the cavity expansion portion, etc. are redundant with the above descriptions, so specific descriptions are omitted. Also, specific descriptions of the upper layer, the lower layer, etc. are redundant with the above descriptions, so specific descriptions are omitted.

[0189] In addition, this specification proposes a manufacturing method for producing a packaging substrate according to an embodiment. For example, the manufacturing method for producing a packaging substrate according to the embodiment of this specification is as follows.

[0190] For example, a cavity portion 28 can be formed in a glass substrate 21 having a first surface and a second surface facing each other. The cavity portion 28 can be formed in the form of a recessed surface with only one of the first surface and the second surface open. The cavity portion 28 can be formed in the form of a recessed surface with only one of the first surface and the second surface open and can have a space in which an element is disposed. Alternatively, the cavity portion 28 can be recessed and open in the direction of the first surface or the second surface of the glass substrate 21, or can penetrate the first surface and the second surface and have a space in which an element is disposed.

[0191] Thereafter, or simultaneously with the formation of the cavity portion, a cavity expansion portion 70 can be formed in the corner region of the cavity portion 28.

[0192] The manufacturing method of the plate-shaped substrate included in the packaging substrate includes a step of generating a cavity portion forming defect and a cavity expansion portion forming defect in a glass substrate having a first surface and a second surface facing each other, and a step of etching the glass substrate to form a cavity portion and a cavity expansion portion.

[0193] The step of mounting an electronic element on the cavity portion may further be included.

[0194] The substrate manufactured in this way can prevent the problem of an increased probability of a short circuit by ensuring a sufficient gap between the wall of the cavity expansion portion and the corner of the cavity element, and can obtain an effect of preventing breakage of the glass substrate by appropriately dispersing the stress applied to the glass substrate through the cavity expansion portion.

[0195] The present specification described above has been described with reference to the embodiments shown in the drawings, but this is merely exemplary, and those having ordinary knowledge in the art will understand that various modifications and variations of the embodiments are possible hereinafter. That is, the scope of rights of the present specification is not limited to the above-described embodiments, and various modifications and improvements made by those skilled in the art using the basic concepts of the embodiments defined in the appended claims also belong to the scope of rights of the embodiments. Therefore, the true technical protection scope of the present specification must be determined by the technical idea of the appended claims.

Description of Reference Numerals

[0196] 100 Semiconductor device 10 Motherboard 30 Semiconductor element portion 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging substrate 21, 21a Glass substrate 22 Core layer 223 Core insulating layer 213 First surface 214 Second surface 23 Core via 24 Core distribution layer 241 Core distribution pattern 26 Upper layer 25 Upper distribution layer 251 Upper distribution pattern 252 Blind via 253 Upper insulating layer 27 Upper connection layer 271 Upper connection electrode 272 Upper connection pattern 28 Cavity part 281 Internal space 282 Cavity distribution layer 40 Cavity element 50 Connection part 51 Element connection part 52 Board connection part 61 Edge of cavity element 70 Cavity extension part

Claims

1. A plate-shaped substrate included in a packaging substrate, comprising a glass substrate having a first surface and a second surface facing each other, wherein a cavity portion and a cavity expansion portion are disposed on the glass substrate, the cavity portion has an accommodation space inside and has one or more corners, the corner is a virtual line where extension lines of two adjacent side surfaces of the accommodation space intersect, the cavity expansion portion is disposed at the corner and has a corner space connected to the accommodation space, a substrate.

2. When viewed in the direction from the first surface to the second surface, the first corner is one corner where the cavity expansion portion is disposed, at the first corner, the angle on the glass substrate side of the two side surfaces is more than 180°, the corner space is a space in a form in which a part of the glass substrate at the first corner is removed, the edge of the corner space has a shape of an arc of a circle or an ellipse, the central angle of the corner space is an angle between two contact points of the two side surfaces and the arc, the central angle of the corner space of the first corner is 20° or more, the substrate according to claim 1.

3. When viewed in the direction from the first surface to the second surface, the second corner is one corner where the cavity expansion portion is disposed, at the second corner, the angle on the glass substrate side of the two side surfaces is less than 180°, the substrate according to claim 1.

4. the corner space is a space in a form in which a part of the glass substrate at the second corner is removed, the edge of the corner space has a shape of an arc of a circle or an ellipse, the central angle of the corner space is an angle between two contact points of the two side surfaces and the arc, the central angle of the corner space of the second corner is 180° or less, the substrate according to claim 3.

5. When viewed in the direction from the first surface to the second surface, the cavity expansion portion has a shape of an arc of a circle or an ellipse, the average radius of the arc is 40 μm or more, the substrate according to claim 1.

6. the glass substrate includes a glass through-via penetrating in the thickness direction, the average radius of the arc is 0.5 times to 3 times the radius of the glass through-via, the substrate according to claim 5.

7. the cavity portion includes four or more of the corners, the cavity expansion portion is disposed on the cavity portion four or more times and not more than the number of the corners, the substrate according to claim 1. ​

8. The substrate includes an electronic element disposed in the cavity portion, a distance between a side surface of the accommodation space and the electronic element is D1, a distance between a glass wall surface of the cavity expansion portion and the electronic element is D2, The substrate according to claim 1, wherein the D2 is the same as or greater than the D1.

9. The substrate includes an electronic element disposed in the cavity portion, portions other than the electronic element in the accommodation space and the corner space are filled with a filling material, The substrate according to claim 1, wherein the filling material includes an insulating material, a metallic material, or a heat dissipating material.

10. The substrate according to claim 1, wherein a distance D3 between an end portion of the cavity expansion portion and a side surface of the cavity portion is 2 μm or more.

11. A packaging substrate including the substrate according to claim 1, an electronic element disposed in the cavity portion, and an upper layer disposed on the substrate and having an upper rewiring layer for transmitting an electrical signal disposed thereon.

Images