Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing heat.SOLUTION: According to one embodiment, a semiconductor device 1 includes a semiconductor substrate 50 having an upper surface 51 and a lower surface 52, a conductive layer CL13 formed above the semiconductor substrate 50, and a conductive layer MP10 formed on the upper surface of the conductive layer CL13, and when viewed from above, the conductive layer MP10 is formed in a region inside the edge of the conductive layer CL13, the thickness of the conductive layer MP10 is greater than the thickness of the conductive layer CL13, the thermal conductivity of the conductive layer MP10 is greater than the thermal conductivity of the conductive layer CL13, and the resistivity of the conductive layer MP10 is less than the resistivity of the conductive layer CL13.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] Patent Document 1 discloses a semiconductor device having a conductive layer for pads on a semiconductor substrate.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] When a large current flows through a semiconductor device via pads, the semiconductor device may generate heat.

[0005] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0006] According to one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, a first conductive layer formed above the semiconductor substrate, and a second conductive layer formed on the upper surface of the first conductive layer. When viewed from above, the second conductive layer is formed in a region inside the edge of the first conductive layer, the thickness of the second conductive layer is greater than the thickness of the first conductive layer, the thermal conductivity of the second conductive layer is greater than the thermal conductivity of the first conductive layer, and the resistivity of the second conductive layer is less than the resistivity of the first conductive layer.

[0007] According to one embodiment, a semiconductor device includes a semiconductor substrate having an upper surface and a lower surface, a first conductive layer formed above the semiconductor substrate, and a second conductive layer formed on the upper surface of the first conductive layer. When viewed from above, the second conductive layer is formed in a region inside the edge of the first conductive layer, and the second conductive layer has a plurality of fins extending in one direction in a plane parallel to the upper surface of the first conductive layer.

Effects of the Invention

[0008] According to the above embodiment, a semiconductor device capable of suppressing heat generation can be provided.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Embodiments for Carrying Out the Invention

[0010] For clarity of explanation, the following descriptions and drawings are appropriately omitted and simplified as necessary. In each drawing, the same reference numerals are assigned to the same elements, and redundant explanations are omitted as needed.

[0011] First, in <Comparative Example>, the semiconductor device according to the comparative example is described. Then, in <New Problems Found by the Inventor>, the new problems found by the inventor regarding the semiconductor device of the comparative example are described. And in <Embodiment 1> and <Embodiment 2>, the semiconductor devices according to the respective embodiments are described. This makes the semiconductor devices according to the respective embodiments clearer. Note that the semiconductor device according to the comparative example and the new problems found by the inventor are also within the scope of the technical idea of the embodiments.

[0012] <Comparative Example> A semiconductor device according to a comparative example will be described. FIG. 1 is a plan view illustrating a semiconductor device 101 according to the comparative example. FIG. 2 is a cross-sectional view illustrating the semiconductor device 101 according to the comparative example, showing a cross-section taken along line II-II in FIG. 1. In the figures shown below including FIGS. 1 and 2, some reference numerals are omitted so that the figures do not become complicated. Also, in the following plan views including FIG. 1, the bonding wires BW10 and BW20 may be omitted. As shown in FIGS. 1 and 2, the semiconductor device 101 according to the comparative example includes a semiconductor substrate 50 as a substrate. In the following description, the semiconductor substrate 50 will be used to describe the substrate of the semiconductor device 101. Note that the substrate is not necessarily limited to the semiconductor substrate 50. The semiconductor substrate 50 is plate-shaped and has plate surfaces on both sides. The semiconductor substrate 50 has one plate surface and the other plate surface on the opposite side of the one plate surface.

[0013] Here, for the sake of convenience in the description of the semiconductor device 101, an XYZ orthogonal coordinate axis system is introduced. The direction orthogonal to one plate surface of the semiconductor substrate 50 is defined as the Z-axis direction. One of them is the +Z-axis direction and the other is the -Z-axis direction. Two directions orthogonal to the Z-axis direction and orthogonal to each other are defined as the X-axis direction and the Y-axis direction. For the sake of convenience in the description, the +Z-axis direction is called upward and the -Z-axis direction is called downward. Therefore, one plate surface of the semiconductor substrate 50 is called the upper surface 51 and the other plate surface is called the lower surface 52. The semiconductor substrate 50 has the upper surface 51 and the lower surface 52. Note that upward, downward, the upper surface 51, and the lower surface 52 are for the sake of convenience in the description and do not indicate the direction in which the actual semiconductor device 101 is arranged.

[0014] When viewed from above, the semiconductor device 101 has a power device section 110 and a control circuit section 120. Note that the outer frame indicates that no conductive layer CL13 or the like is formed up to the edge of the semiconductor device 101. Hereinafter, as an example, the power device section 110 and the control circuit section 120 in the semiconductor device 101 will be described as being formed on a single semiconductor substrate 50 like a monolithic IPD (Monolithic Intelligent Power Device), but it is not limited thereto. For example, the power device section 110 and the control circuit section 120 in the semiconductor device 101 may be formed on different semiconductor substrates 50, respectively. That is, the power device section 110 and the control circuit section 120 may each be configured alone. Also, in the semiconductor device 101, the power device section 110 and the control circuit section 120 may be formed in an MCM (Multi Chip Module)-type IPD in which a plurality of chips are stacked.

[0015] The power device section 110 includes, for example, a semiconductor substrate 50, a device, an insulating layer IL10, a conductive layer CL10, and a through-conductor TC10. A device is formed on the semiconductor substrate 50 in the power device section 110. The power device includes, as an example, those constituting the IPD. Note that the power device is not limited to the IPD and may be a single power device. The IPD may include a vertical power MOS transistor formed on the semiconductor substrate 50, specifically, a trench-type MOSFET (Trench Metal Oxide Semiconductor Field Effect Transistor). Thus, the device may include a transistor TR10 formed on the semiconductor substrate 50. Note that the power device section 110 may sometimes be simply referred to as a device section, and in that case, the device in the device section is not limited to a power device.

[0016] The power device section 110 may include a plurality of transistors TR10, a plurality of insulating layers IL10, a plurality of conductive layers CL10, and a plurality of through-conductors TC10. The plurality of transistors TR10 may sometimes be collectively referred to as the transistor TR10.

[0017] The power device section 110 may include an insulating layer IL11, an insulating layer IL12, and an insulating layer IL13. Here, a plurality of insulating layers IL10 such as the insulating layer IL11, the insulating layer IL12, and the insulating layer IL13 may be collectively referred to as the insulating layer IL10. Note that the power device section 110 is not limited to three insulating layers IL10, and may include two or less insulating layers IL10, or may include four or more insulating layers IL10. The insulating layer IL10 is formed on the semiconductor substrate 50. Each insulating layer IL10 among the plurality of insulating layers IL10 is alternately laminated on the semiconductor substrate 50 with each conductive layer CL in the plurality of conductive layers CL10.

[0018] The power device section 110 may include a conductive layer CL11, a conductive layer CL12, and a conductive layer CL13. Here, a plurality of conductive layers CL10 such as the conductive layer CL11, the conductive layer CL12, and the conductive layer CL13 may be collectively referred to as the conductive layer CL10. Note that the power device section 110 is not limited to three conductive layers CL10, and may include two or less conductive layers CL10, or may include four or more conductive layers CL10. The conductive layer CL10 is formed on the semiconductor substrate 50. Each conductive layer CL10 among the plurality of conductive layers CL10 is alternately laminated on the semiconductor substrate 50 with each insulating layer IL10 in the plurality of insulating layers IL10.

[0019] For example, an insulating layer IL11 is disposed on the semiconductor substrate 50, and a conductive layer CL11 is disposed on the insulating layer IL11. An insulating layer IL12 is disposed on the conductive layer CL11, and a conductive layer CL12 is disposed on the insulating layer IL12. An insulating layer IL13 is disposed on the conductive layer CL12, and a conductive layer CL13 is disposed on the insulating layer IL13.

[0020] The power device section 110 may include a plurality of through conductors TC10. Here, the plurality of through conductors TC10 may be collectively referred to as the through conductor TC10. Also, the through conductor TC10 may be referred to as a via conductor. Each of the plurality of through conductors TC10 in the plurality of through conductors TC10 is formed on the semiconductor substrate 50. Each through conductor TC10 is disposed inside a through hole that penetrates the insulating layer IL10. The through conductor TC10 connects the upper and lower conductive layers CL10 sandwiching the insulating layer IL10.

[0021] When the transistor TR10 in the power device section 110 is a vertical power MOS transistor, the uppermost conductive layer CL13 in the conductive layer CL10 may be used as the source electrode. Therefore, the source of the transistor TR10 in the power device section 110 is connected to the conductive layer CL13 via a wiring including the through conductor TC10.

[0022] The control circuit section 120 includes, for example, a semiconductor substrate 50, a control circuit, an insulating layer IL20, a conductive layer CL20, and a through conductor TC20. The control circuit section 120 includes a control circuit formed on the semiconductor substrate 50. The control circuit controls the devices in the power device section 110. Thus, in the control circuit section 120, a control circuit for controlling the devices in the power device section 110 is formed on the semiconductor substrate 50. The control circuit includes, as an example, planar MOSFETs such as CMOS (Complementary MOS) and LDMOS (Laterally Diffused MOS). That is, the control circuit may include a transistor TR20. Therefore, in the control circuit section 120, the transistor TR20 is formed on the semiconductor substrate 50.

[0023] The control circuit section 120 may include a plurality of transistors TR20, a plurality of insulating layers IL20, a plurality of conductive layers CL20, and a plurality of through conductors TC20. The plurality of transistors TR20 may be collectively referred to as the transistor TR20.

[0024] The control circuit unit 120 may include an insulating layer IL21, an insulating layer IL22, and an insulating layer IL23. Here, a plurality of insulating layers IL20 such as the insulating layer IL21, the insulating layer IL22, and the insulating layer IL23 may be collectively referred to as the insulating layer IL20. Note that the control circuit unit 120 is not limited to three insulating layers IL20, and may include two or less insulating layers IL20, or may include four or more insulating layers IL20. The insulating layer IL20 is formed on the semiconductor substrate 50. Each insulating layer IL20 among the plurality of insulating layers IL20 is alternately laminated on the semiconductor substrate 50 with each conductive layer CL20 among the plurality of conductive layers CL20.

[0025] The control circuit unit 120 may include a conductive layer CL21, a conductive layer CL22, and a conductive layer CL23. Here, a plurality of conductive layers CL20 such as the conductive layer CL21, the conductive layer CL22, and the conductive layer CL23 may be collectively referred to as the conductive layer CL20. Note that the control circuit unit 120 is not limited to three conductive layers CL20, and may include two or less conductive layers CL20, or may include four or more conductive layers CL20. The conductive layer CL20 is formed on the semiconductor substrate 50. Each conductive layer CL20 among the plurality of conductive layers CL20 is alternately laminated on the semiconductor substrate 50 with each insulating layer IL20 among the plurality of insulating layers IL20.

[0026] For example, an insulating layer IL21 is disposed on the semiconductor substrate 50, and a conductive layer CL21 is disposed on the insulating layer IL21. An insulating layer IL22 is disposed on the conductive layer CL21, and a conductive layer CL22 is disposed on the insulating layer IL22. An insulating layer IL23 is disposed on the conductive layer CL22, and a conductive layer CL23 is disposed on the insulating layer IL23.

[0027] The control circuit unit 120 may include a plurality of through conductors TC20. Here, the plurality of through conductors TC20 may be collectively referred to as the through conductor TC20. Each through conductor TC20 among the plurality of through conductors TC20 is formed on the semiconductor substrate 50. Each through conductor TC20 is disposed inside a through hole that penetrates the insulating layer IL20. The through conductor TC20 connects the upper and lower conductive layers CL20 sandwiching the insulating layer IL20.

[0028] Each layer of the conductive layer CL10 in the power device section 110 and each layer of the conductive layer CL20 in the control circuit section 120 may include portions at the same height from the upper surface 51 of the semiconductor substrate 50. For example, the conductive layer CL11 may include the conductive layer CL21 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. The conductive layer CL12 may include the conductive layer CL22 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. The conductive layer CL13 may include the conductive layer CL23 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. For example, each layer of the conductive layer CL10 may be formed in the same process steps as each layer of the conductive layer CL20. Specifically, for example, each layer of the conductive layer CL10 may be formed simultaneously with each layer of the conductive layer CL20.

[0029] Each layer of the insulating layer IL10 in the power device section 110 and each layer of the insulating layer IL20 in the control circuit section 120 may include portions at the same height from the upper surface 51 of the semiconductor substrate 50. For example, the insulating layer IL11 may include the insulating layer IL21 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. The insulating layer IL12 may include the insulating layer IL22 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. The insulating layer IL13 may include the insulating layer IL23 and a portion at the same height from the upper surface 51 of the semiconductor substrate 50. For example, each layer of the insulating layer IL10 may be formed in the same process steps as each layer of the insulating layer IL20. Specifically, for example, each layer of the insulating layer IL10 may be formed simultaneously with each layer of the insulating layer IL20.

[0030] When the semiconductor substrate 50 is viewed from above, a plurality of pad portions PD10 are set on the upper surface of the conductive layer CL13 in the power device section 110. The pad portions PD10 may not be clearly distinguishable in appearance when the cover film described later is not formed. Thus, the region where the conductive layer CL13 is formed has a plurality of pad portions PD10. Bonding wires BW10 are connected to the pad portions PD10. That is, each of the plurality of bonding wires BW10 among the plurality of bonding wires BW10 is connected to each of the plurality of pad portions PD10 among the plurality of pad portions PD10, respectively.

[0031] Each bonding wire BW10 may be connected to each pad portion PD10 in all the pad portions PD10 set on the upper surface of the conductive layer CL13, or each bonding wire BW10 may be connected to some of the pad portions PD10 in the pad portions PD10 set on the upper surface of the conductive layer CL13. Note that a plurality of bonding wires BW10 may be connected to a predetermined single pad portion PD10, or there may be a pad portion PD10 to which no bonding wire BW10 is connected.

[0032] When viewed from above, each pad portion PD10 is arranged in the region where the conductive layer CL13 is formed, but each pad portion PD10 is arranged in a biased and scattered manner.

[0033] The conductive layer CL23 in the control circuit portion 120 includes a plurality of pad portions PD20. In the control circuit portion 120, a plurality of conductive layers CL23 may be formed on the insulating layer IL23. Each conductive layer CL23 may correspond to each pad portion PD20, respectively. A bonding wire BW20 is connected to the pad portion PD20. In order to distinguish the bonding wire BW20 of the control circuit portion 120 from the bonding wire BW10 of the power device portion 110, it may be called a control bonding wire. Each bonding wire BW20 in the plurality of bonding wires BW20 is connected to each pad portion PD20 in the plurality of pad portions PD20.

[0034] Each bonding wire BW20 may be connected to each pad portion PD20 in all the pad portions PD20 formed from the plurality of conductive layers CL23, or each bonding wire BW20 may be connected to some of the pad portions PD20 in the pad portion PD20 of the conductive layer CL23. Note that a plurality of bonding wires BW20 may be connected to a predetermined single pad portion PD20. Also, there may be a pad portion PD20 to which no bonding wire BW20 is connected.

[0035] <Problems newly discovered by the inventor> The semiconductor device 101 passes a current to the transistor TR10 in the power device section 110 via the bonding wire BW10. Also, the semiconductor device 101 passes a current to the transistor TR20 in the control circuit section 120 via the bonding wire BW20. Thereby, the semiconductor device 101 can be operated.

[0036] When a large current flows through the semiconductor device 101, the semiconductor device 101 may generate heat. For example, when a large current flows through the transistor TR10 such as a power MOS in the power device section 110 via the bonding wire BW10, the pad portion PD10 in the conductive layer CL13 has a locally higher current density than the surroundings. As a result, the semiconductor device 101 generates heat. In order to suppress the heat generation of the semiconductor device 101, it is conceivable to increase the thickness of the conductive layer CL10. However, simply increasing the thickness of the conductive layer CL10 increases the size of the semiconductor device 101 and may not obtain such an effect of suppressing heat generation.

[0037] Therefore, an attempt is made to reduce the heat generation of the semiconductor device by changing the material that functions as the conductive layer to a material having higher thermal conductivity than the conductive layer CL10 and adding a material having higher thermal conductivity than the conductive layer CL10 on the conductive layer CL10. With such a configuration, the heat generation of the semiconductor device can be suppressed.

[0038] <Embodiment 1> Next, the semiconductor device 1 according to Embodiment 1 will be described. FIG. 3 is a plan view illustrating the semiconductor device 1 according to Embodiment 1. FIG. 4 is a cross-sectional view illustrating the semiconductor device 1 according to Embodiment 1, showing the cross-section taken along line IV-IV in FIG. 3. As shown in FIGS. 3 and 4, the semiconductor device 1 of the present embodiment also includes a semiconductor substrate 50 as a substrate, similarly to the semiconductor device 101 of the comparative example. The semiconductor device 1 also includes a power device section 10 and a control circuit section 20. Note that the outer frame indicates that no conductive layer MP10 or the like is formed up to the edge of the semiconductor device 1.

[0039] In addition to the power device section 110 of the comparative example, the power device section 10 further includes a conductive layer MP10. The conductive layer MP10 is formed on the upper surface of the conductive layer CL13. Specifically, the conductive layer MP10 is formed in a layered manner on the upper surface of the conductive layer CL13 so as to be in contact with the upper surface of the conductive layer CL13. As a result, the conductive layer MP10 is laminated on the conductive layer CL13. The conductive layer CL13 may be referred to as the first conductive layer, and the conductive layer MP10 may be referred to as the second conductive layer. Therefore, the semiconductor device 1 includes a semiconductor substrate 50 having an upper surface 51 and a lower surface 52, a first conductive layer formed above the semiconductor substrate 50, and a second conductive layer formed on the upper surface of the first conductive layer.

[0040] When viewed from above, the conductive layer MP10 is formed in a region inside the edge of the conductive layer CL13. As an example, when the conductive layer MP10 is formed on the conductive layer CL13 by plating, a mask is placed on the conductive layer CL13. The conductive layer MP10 is formed in a portion not covered by the mask on the conductive layer CL13. As a result, the conductive layer MP10 is formed in a region inside the edge of the conductive layer CL13. Note that the method of forming the conductive layer MP10 on the conductive layer CL13 is not limited to plating.

[0041] Preferably, the thickness of the conductive layer MP10 is greater than the thickness of the conductive layer CL13. Preferably, the thermal conductivity of the conductive layer MP10 is greater than the thermal conductivity of the conductive layer CL13. Preferably, the resistivity of the conductive layer MP10 is smaller than the resistivity of the conductive layer CL13. By adopting such a configuration, heat dissipation in the conductive layer CL13 and the conductive layer MP10 can be promoted, and heat generation of the semiconductor device 1 can be suppressed.

[0042] For example, the conductive layers CL11, CL12, and CL13 may contain aluminum. On the other hand, the conductive layer MP10 may contain copper. Also, the conductive layer MP10 may include a plating layer formed by plating. By adopting such a configuration, heat dissipation in the conductive layer CL13 and the conductive layer MP10 can be further promoted, and heat generation of the semiconductor device 1 can be further suppressed.

[0043] A plurality of bonding wires BW10 are connected to the region where the conductive layer MP10 is formed in the power device unit 10. Also, a plurality of bonding wires BW20 are connected to the region where the conductive layer CL23 is formed in the control circuit unit 20. In order to distinguish the bonding wire BW20 in the control circuit unit 20 from the bonding wire BW10 in the power device unit 10, it may be referred to as a control bonding wire.

[0044] The thickness of the bonding wire BW10 in the power device unit 10 is preferably larger than the thickness of the bonding wire BW20 in the control circuit unit 20. The current flowing through the bonding wire BW10 is larger than the current flowing through the bonding wire BW20. Therefore, by making the thickness of the bonding wire BW10 in the power device unit 10 larger than the thickness of the bonding wire BW20 in the control circuit unit 20, the current density flowing through the bonding wire BW10 can be reduced, and heat generation of the semiconductor device 1 can be suppressed.

[0045] FIG. 5 is a plan view illustrating a plurality of pad portions PD10 on a conductive layer MP10 in the power device portion 10 of the semiconductor device 1 according to Embodiment 1. As shown in FIG. 5, each pad portion PD10 is dispersedly arranged in a region where the conductive layer MP10 is formed. That is, each pad portion PD10 is scattered evenly on the conductive layer MP10 without bias. Specifically, when viewed from above, the region where the conductive layer MP10 is formed has a plurality of pad portions PD10 to which each bonding wire BW in the plurality of bonding wires BW is connected. Further, compared with the arrangement in FIG. 1, in the arrangement in FIG. 5, each pad portion PD10 is evenly scattered without bias also in the X direction. And when the region where the conductive layer MP10 is formed is divided into several regions AR, each region AR includes at least one pad portion PD10. Note that each region AR has the same shape and the same area as each other. By adopting such a configuration, the current flowing into and out of the conductive film MP10 through the bonding wire BW10 can be dispersed, and the concentration of the current can be alleviated. Therefore, heat generation of the semiconductor device 1 can be suppressed.

[0046] The control circuit portion 20 may have the same configuration as the control circuit portion 120 of the comparative example. The conductive layer CL23 may be referred to as a third conductive layer. Therefore, the control circuit portion 20 includes a semiconductor substrate 50, a control circuit, and a third conductive layer formed above the semiconductor substrate 50 and including a portion having the same height as the first conductive layer from the upper surface 51 of the semiconductor substrate 50.

[0047] FIG. 6 is a plan view illustrating the semiconductor device 1 according to Embodiment 1. FIG. 7 is a cross-sectional view illustrating the semiconductor device 1 according to Embodiment 1, showing a cross-section taken along line VII-VII in FIG. 6. As shown in FIGS. 6 and 7, the semiconductor device 1 may further include a conductive layer MP20 in the control circuit section 20. The conductive layer MP20 may be referred to as a fourth conductive layer. The conductive layer MP20 is formed on the upper surface of the conductive layer CL23. Specifically, the conductive layer MP20 is formed in a layered manner on the upper surface of the conductive layer CL23 so as to be in contact with the upper surface of the conductive layer CL23. Thereby, the conductive layer MP20 is laminated on the conductive layer CL23. The conductive layer MP20 may include a portion at the same height as the conductive layer MP10 from the upper surface 51 of the semiconductor substrate 50. For example, the conductive layer MP20 may be formed in the same process step as the conductive layer MP10. Specifically, the conductive layer MP20 may be formed simultaneously in the same plating process as the conductive layer MP10.

[0048] When viewed from above, the conductive layer MP20 may be formed in a region inside the edge of the conductive layer CL23. For example, the conductive layer MP20 may include a plating layer. The bonding wire BW20 is connected to a region where the conductive layer CL24 is formed.

[0049] FIGS. 8 and 9 are cross-sectional views illustrating the semiconductor device 1 according to Embodiment 1. As shown in FIGS. 8 and 9, the semiconductor device 1 may further include a conductive thin film TF10 in the power device section 10. The conductive thin film TF10 is formed on the upper surface of the conductive layer MP10. Specifically, the conductive thin film TF10 is formed in a layered manner on the upper surface of the conductive layer MP10 so as to be in contact with the upper surface of the conductive layer MP10. Thereby, the conductive thin film TF10 is laminated on the conductive layer MP10.

[0050] The conductive layer MP10 is connected to the bonding wire BW10 with the conductive thin film TF10 interposed therebetween. The conductive thin film TF10 can improve the bondability of the bonding wire BW10. The conductive thin film CF10 may include at least any one of, for example, nickel, palladium, and gold.

[0051] As shown in FIG. 8, the conductive thin film TF10 may be formed over the entire upper surface of the conductive layer MP10. Alternatively, as shown in FIG. 9, the conductive thin film TF10 may be formed on a part of the upper surface of the conductive layer MP10. The part may include, for example, the region of the pad portion PD10. By forming the conductive thin film TF10 on at least the region of the pad portion PD10 on the upper surface of the conductive layer MP10, the bonding property of the bonding wire BW10 can be improved.

[0052] Note that the conductive thin film TF10 may be formed on the upper surface of the conductive layer CL23 or the upper surface of the conductive layer MP20 in the control circuit portion 20. Thereby, the bonding property of the bonding wire BW20 can be improved.

[0053] FIGS. 10 to 12 are cross-sectional views illustrating the semiconductor device 1 according to Embodiment 1. As shown in FIGS. 10 to 12, the semiconductor device 1 may further include a cover film CV10. As shown in FIG. 10, the cover film CV10 may be formed to cover the conductive layer MP10. Alternatively, as shown in FIG. 11, the cover film CV10 may be formed to cover the conductive layer MP10 and the conductive thin film TF10. Even when the cover film CV10 is formed, as shown in FIGS. 11 and 12, the conductive thin film TF10 may be formed over the entire upper surface of the conductive layer MP10 or on a part of the upper surface of the conductive layer MP10. The part may include, for example, the region of the pad portion PD10.

[0054] The cover film CV10 includes a plurality of openings OP10. Each opening OP10 corresponds to each pad portion PD10. Therefore, the bonding wire BW10 is connected to the pad portion PD10 exposed through the opening OP10 of the cover film CV10. The cover film CV10 may include, for example, polyimide.

[0055] Note that the cover film CV10 may be formed to cover the conductive layer CL23 in the control circuit unit 20, or may be formed to cover the conductive layer CL23 and the conductive layer MP20. Further, the cover film CV10 may be formed to cover the conductive layer CL23 and the conductive layer MP20 in the control circuit unit 20. Then, the bonding wire BW20 in the control circuit unit 20 is connected to the pad portion PD20 exposed at the opening OP10 of the cover film CV10 in the control circuit unit 20.

[0056] Next, the effects of the present embodiment will be described. The semiconductor device 1 of the present embodiment includes a conductive layer MP10 formed on the upper surface of the conductive layer CL13. Thereby, the heat dissipation of the semiconductor device 1 can be improved and heat generation can be suppressed. Further, the thickness of the conductive layer MP10 may be larger than the thickness of the conductive layer CL13, the thermal conductivity of the conductive layer MP10 may be larger than the thermal conductivity of the conductive layer CL13, and the resistivity of the conductive layer MP10 may be smaller than the resistivity of the conductive layer CL13. Therefore, heat generation of the semiconductor device 1 can be further suppressed.

[0057] The plurality of pad portions PD10 may be arranged in a dispersed manner. Thereby, the current flowing through the semiconductor device 1 can be dispersed and the current density can be reduced. Therefore, heat generation of the semiconductor device 1 can be reduced. Further, the thickness of the bonding wire BW10 of the power device unit 10 may be larger than the thickness of the bonding wire BW20 of the control circuit unit 20. With such a configuration, heat generation of the semiconductor device 1 can be further reduced.

[0058] <Embodiment 2> Next, the semiconductor device of Embodiment 2 will be described. In the semiconductor device of this embodiment, a conductive layer having fins is formed. FIG. 13 is a plan view illustrating the semiconductor device 1a according to Embodiment 2. FIG. 14 is a plan view illustrating the semiconductor device 1b according to Embodiment 2. FIG. 15 is a cross-sectional view illustrating the semiconductor device 1b according to Embodiment 2, showing the cross-section taken along line XV-XV in FIG. 14. In FIGS. 14 and 15, in order not to complicate the drawing, the number and spacing of the fins FN42 in FIG. 14 are not made to correspond to the number and spacing of the fins FN42 in FIG. 15.

[0059] As shown in FIG. 13, the semiconductor device 1a of this embodiment has a power device portion 30 and a control circuit portion 20. The power device portion 30 further includes a conductive layer MP30 in addition to the power device portion 110 of the comparative example. The conductive layer MP30 is formed on the upper surface of the conductive layer CL13. The conductive layer MP30 includes a plurality of fins FN30, a plurality of pad portions PD30, and an annular portion RN30.

[0060] The fins FN30 extend in one direction in a plane parallel to the upper surface of the conductive layer CL13. The fins FN30 extend, for example, in the X-axis direction. Note that the fins FN30 may extend in the Y-axis direction or in a direction inclined from the X-axis direction and the Y-axis direction. The lower surface of the fin FN30 is in contact with the conductive layer CL13. The plurality of fins FN30 are adjacent to each other, for example, in the Y-axis direction. A groove is formed between adjacent fins FN30. The groove between the fins FN30 extends in the X-axis direction. The groove between the fins FN30 penetrates from the upper surface to the lower surface of the conductive layer MP30.

[0061] The pad portion PD30 is connected to each of the bonding wires in the plurality of bonding wires BW10. Among the plurality of fins FN30, some of the fins FN30 may extend in the X-axis direction from the pad portion PD30. Specifically, the fin FN30 may include portions extending in the +X-axis direction side and the -X-axis direction side in the X-axis direction from the pad portion PD30. Also, some of the fins FN30 may not be connected to the pad portion PD30.

[0062] The annular portion RN30 is formed in an annular shape. For example, the annular portion RN30 may be formed in an annular shape along the edge of the conductive layer CL13. The plurality of fins FN30 and the plurality of pad portions PD30 are surrounded by the annular portion RN30. The annular portion RN30 has the ends on the +X-axis direction side and the -X-axis direction side in the X-axis direction of the fin FN30 connected thereto.

[0063] The upper surfaces of the plurality of fins FN30, the plurality of pad portions PD30, and the annular portion RN30 may be at the same height as the upper surface 51 of the semiconductor substrate 50. That is, the upper surfaces of the plurality of fins FN30, the plurality of pad portions PD30, and the annular portion RN30 may be located at the same height in the Z-axis direction.

[0064] As shown in FIGS. 14 and 15, the semiconductor device 1b may include a power device portion 40 and a control circuit portion 20. The power device portion 40 further includes a conductive layer MP40 in addition to the power device portion 110 of the comparative example. The conductive layer MP40 is formed on the upper surface of the conductive layer CL13. In the semiconductor device 1b, the conductive layer MP40 includes a plurality of fins FN41, a plurality of fins FN42, a plurality of pad portions PD40, and an annular portion RN40.

[0065] The fin FN41 extends in one direction in a plane parallel to the upper surface of the conductive layer CL13. The fin FN41 extends, for example, in the X-axis direction. Note that the fin FN41 may extend in the Y-axis direction or in a direction inclined from the X-axis direction and the Y-axis direction. The plurality of fins FN41 are adjacent to each other in the Y-axis direction.

[0066] The fin FN42 extends in a direction intersecting with one direction in the in-plane parallel to the upper surface of the conductive layer CL13. The fin FN42 extends, for example, in the Y-axis direction. Note that the fin FN42 may extend in the X-axis direction or in a direction inclined from the X-axis direction and the Y-axis direction as long as it extends in a direction intersecting with the fin FN41. The plurality of fins FN42 are adjacent to each other in the X-axis direction.

[0067] The lower surfaces of the fins FN41 and FN42 are in contact with the conductive layer CL13. Holes are formed between adjacent fins FN41 and between adjacent fins FN42. Thus, the holes surrounded by the adjacent fins FN41 and the adjacent fins FN42 penetrate from the upper surface to the lower surface of the conductive layer MP40. With such a configuration, the fins FN41 and FN42 have a mesh-like shape.

[0068] The pad portion PD40 is connected to each of the plurality of bonding wires BW10. The fin FN41 includes portions extending from the pad portion PD40 to the +X-axis direction side and the -X-axis direction side in the X-axis direction. The fin FN42 includes portions extending from the pad portion PD40 to the +Y-axis direction side and the -Y-axis direction side in the Y-axis direction.

[0069] The annular portion RN40 is formed in an annular shape. The annular portion RN40 may be formed in an annular shape along the edge of the conductive layer CL13, for example. The plurality of fins FN41, the plurality of fins FN42, and the plurality of pad portions PD30 are surrounded by the annular portion RN40. The annular portion RN40 has the ends on the +X-axis direction side and the -X-axis direction side in the X-axis direction of the fin FN41 connected, and the ends on the +Y-axis direction side and the -Y-axis direction side in the Y-axis direction of the fin FN42 connected.

[0070] The upper surfaces of the plurality of fins FN41, the plurality of fins FN42, the plurality of pad portions PD40, and the annular portion RN40 may be at the same height as the upper surface 51 of the semiconductor substrate 50. That is, the upper surfaces of the plurality of fins FN41, the plurality of fins FN42, the plurality of pad portions PD40, and the annular portion RN40 may be located at the same height in the Z-axis direction.

[0071] FIGS. 16 and 17 are cross-sectional views illustrating a semiconductor device 1b according to Embodiment 2. As shown in FIGS. 16 and 17, the semiconductor device 1b further includes a conductive thin film TF40. The conductive thin film TF40 is formed on the upper surface of the conductive layer MP40. Specifically, the conductive thin film TF40 is formed in layers on the upper surface of the conductive layer MP40 so as to be in contact with the upper surface of the conductive layer MP40. Thereby, the conductive thin film TF40 is laminated on the conductive layer MP40. The conductive layer MP40 is connected to the bonding wire BW10 with the conductive thin film TF40 interposed therebetween.

[0072] As shown in FIG. 16, the conductive thin film TF40 may be formed over the entire upper surface of the conductive layer MP40, or as shown in FIG. 17, the conductive thin film TF40 may be formed on a part of the upper surface of the conductive layer MP40. The part includes, for example, the region of the pad portion PD40. By forming the conductive thin film TF40 at least in the region of the pad portion PD40 on the upper surface of the conductive layer MP40, the bonding property of the bonding wire BW10 can be improved.

[0073] Figs. 18 to 20 are cross-sectional views illustrating the semiconductor device 1b according to Embodiment 2. As shown in Figs. 18 to 20, the semiconductor device 1b may further include a cover film CV40. As shown in Fig. 18, the cover film CV40 may be formed to cover the fins FN41 and FN42 of the conductive layer MP40. Alternatively, as shown in Fig. 19, the cover film CV40 may be formed to cover the fins FN41 and FN42 of the conductive layer MP40 and the conductive thin film TF40. Even when the cover film CV10 is formed, as shown in Figs. 19 and 20, the conductive thin film TF40 may be formed over the entire upper surface of the conductive layer MP10 or may be formed on a part of the upper surface of the conductive layer MP10. The part includes, for example, the region of the pad portion PD40.

[0074] The cover film CV40 includes a plurality of openings OP40. Each opening OP40 corresponds to each pad portion PD40. Therefore, the bonding wire BW10 is connected to the pad portion PD40 exposed through the opening OP40 of the cover film CV40.

[0075] In Embodiments 1 and 2, the conductive layers MP10 to MP40 are assumed to be connected to the bonding wires BW1010 and BW20, but the present invention is not limited thereto. The conductive layers MP10 to MP40 may be connected to at least one of a clip, a ribbon, and a two-stitch bonding wire.

[0076] Next, the effects of the present embodiment will be described. In the semiconductor device 1a of the present embodiment, the fin FN30 is formed on the conductive layer MP30. In the semiconductor device 1b, the fins FN41 and FN42 are formed on the conductive layer MP40. Since the fins FN30 and the like expand the heat dissipation area and improve the function of dissipating heat, heat generation of the semiconductor devices 1a and 1b can be reduced.

[0077] In addition, by having fins FN30 or the like, the heat dissipation function can be enhanced, so that the thicknesses of the conductive layer MP30 and the conductive layer MP40 can be made smaller than the thicknesses of the conductive layer MP10 and the conductive layer MP20 in Embodiment 1. Thereby, warping during the manufacture of the conductive layer MP30 and the conductive layer MP40 can be suppressed.

[0078] By using a clip, a ribbon, a 2-stitch bonding wire, or the like instead of the bonding wires BW1010 and BW20, these paths can be used as heat transfer paths. Therefore, local heat generation can be suppressed, and heat generation of the semiconductor devices 1a and 1b or the like can be suppressed. Other configurations and effects are included in the descriptions of the comparative example and Embodiment 1.

[0079] As described above, the disclosure made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present disclosure is not limited to the above embodiments and the comparative example, and various modifications can be made without departing from the gist thereof. For example, a combination of the configurations of the comparative example and Embodiments 1 to 2 as appropriate is also within the scope of the technical idea of the embodiments. Further, the following configurations are also within the scope of the technical idea of the embodiments.

[0080] (Appendix 21) The second conductive layer is connected to at least one of a clip, a ribbon, and a 2-stitch bonding wire. The semiconductor device according to Appendix 1. (Appendix 22) Formed in an MCM-type IPD The semiconductor device according to Appendix 1. (Appendix 23) Further comprising a conductive thin film formed on the upper surface of the second conductive layer. The conductive thin film contains at least one of nickel, palladium, and gold. The semiconductor device according to Appendix 1. (Appendix 24) The first conductive layer contains aluminum. The second conductive layer contains copper. The semiconductor device according to Appendix 1. (Supplementary Note 25) When viewed from above, the region where the second conductive layer is formed has a plurality of pad portions to which each bonding wire in the plurality of bonding wires is connected respectively. It further includes a cover film formed to cover the second conductive layer. The cover film includes a plurality of openings. Each opening corresponds to each pad portion. The cover film contains polyimide. The semiconductor device according to Supplementary Note 1.

Explanation of Reference Signs

[0081] 1, 1a, 1b Semiconductor device 10, 30, 40 Power device portion 20 Control circuit portion 50 Semiconductor substrate 51 Upper surface 52 Lower surface 101 Semiconductor device 110 Power device portion 120 Control circuit portion AR Region BW10, BW20 Bonding wire CV10, CV40 Cover film CL10, CL11, CL12, CL13 Conductive layer CL20, CL21, CL22, CL23 Conductive layer FN30, FN41, FN42 Fin IL10, IL11, IL12, IL13 Insulating layer IL20, IL21, IL22, IL23 Insulating layer MP10, MP20, MP30, MP40 Conductive layer OP10, OP40 Opening PD10, PD20, PD30, PD40 Pad portion RN30, RN40 Annular portion TC10, TC20 Through-conductor TF10, TF40 Conductive thin film TR10, TR20 Transistor

Claims

1. A semiconductor substrate having an upper surface and a lower surface, A first conductive layer formed above the semiconductor substrate, A second conductive layer formed on the upper surface of the first conductive layer, Comprising, When viewed from above, the second conductive layer is formed in a region inside the edge of the first conductive layer, The thickness of the second conductive layer is greater than the thickness of the first conductive layer, The thermal conductivity of the second conductive layer is greater than the thermal conductivity of the first conductive layer, The resistivity of the second conductive layer is smaller than the resistivity of the first conductive layer, A semiconductor device.

2. When viewed from above, the region where the second conductive layer is formed has a plurality of pad portions to which each bonding wire in the plurality of bonding wires is connected respectively, When the region where the second conductive layer is formed is divided into several areas, each area includes at least one of the pad portions, The semiconductor device according to claim 1.

3. A device portion in which a device is formed on the semiconductor substrate, A control circuit portion in which a control circuit for controlling the device is formed on the semiconductor substrate, Having, The device portion is, The semiconductor substrate, The device, The first conductive layer, The second conductive layer, Including, The control circuit portion is, The semiconductor substrate, The control circuit, A third conductive layer formed above the semiconductor substrate and including a portion at the same height as the first conductive layer from the upper surface of the semiconductor substrate, Including, When viewed from above, the region where the third conductive layer is formed is connected to a plurality of control bonding wires, The thickness of the bonding wire of the device portion is greater than the thickness of the control bonding wire of the control circuit portion, The semiconductor device according to claim 2.

4. Further comprising a fourth conductive layer formed on the upper surface of the third conductive layer and including a portion at the same height as the second conductive layer from the upper surface of the semiconductor substrate, When viewed from above, The fourth conductive layer is formed in a region inside the edge of the third conductive layer, The control bonding wire is connected to the region where the fourth conductive layer is formed, The semiconductor device according to claim 3.

5. Further comprising a conductive thin film formed on the upper surface of the second conductive layer, The second conductive layer is connected to the bonding wire with the conductive thin film interposed therebetween, The semiconductor device according to claim 2.

6. Further comprising a cover film formed to cover the second conductive layer, The cover film includes a plurality of openings, each opening corresponding to each pad portion, The semiconductor device according to claim 2.

7. further comprising a conductive thin film formed on the upper surface of the second conductive layer, the cover film being formed to cover the second conductive layer and the conductive thin film, The semiconductor device according to claim 6.

8. the device portion includes a plurality of transistors, the source of the transistor being connected to the first conductive layer via wiring including a via conductor, The semiconductor device according to claim 3.

9. the device portion includes a vertical power MOS transistor formed on the semiconductor substrate, The semiconductor device according to claim 3.

10. the second conductive layer includes a plating layer, The semiconductor device according to claim 1.

11. the second conductive layer includes a plurality of fins extending in one direction in a plane parallel to the upper surface of the first conductive layer, The semiconductor device according to claim 1.

12. the second conductive layer further has a plurality of pad portions to which each bonding wire of the plurality of bonding wires is respectively connected, the fin including portions extending from the pad portion to one side and the other side in the one direction, The semiconductor device according to claim 11.

13. the second conductive layer further includes a plurality of fins extending in another direction intersecting the one direction in a plane parallel to the upper surface of the first conductive layer, The semiconductor device according to claim 11.

14. the second conductive layer further has a plurality of pad portions to which each bonding wire of the plurality of bonding wires is respectively connected, the fin including portions extending from the pad portion to one side and the other side in the one direction, and portions extending from the pad portion to one side and the other side in the other direction, including, The semiconductor device according to claim 13.

15. the second conductive layer includes an annular portion formed annularly along the edge, the annular portion connecting the one-side end and the other-side end of the fin in the one direction, The semiconductor device according to claim 11.

16. further comprising a conductive thin film formed on the upper surface of the second conductive layer, the second conductive layer being connected to the bonding wire with the conductive thin film interposed therebetween, The semiconductor device according to claim 12.

17. further comprising a cover film formed to cover the second conductive layer, the cover film including a plurality of openings, each opening corresponding to each pad portion, The semiconductor device according to claim 12.

18. Further comprising a conductive thin film formed on the upper surface of the second conductive layer, The cover film is formed so as to cover the second conductive layer and the conductive thin film, The semiconductor device according to claim 17.

19. A semiconductor substrate having an upper surface and a lower surface, A first conductive layer formed above the semiconductor substrate, A second conductive layer formed on the upper surface of the first conductive layer, Comprising: When viewed from above, the second conductive layer is formed in a region inside the edge of the first conductive layer, The second conductive layer has a plurality of fins extending in one direction in a plane parallel to the upper surface of the first conductive layer, Semiconductor device.

20. The second conductive layer further has a plurality of pad portions to which each bonding wire in the plurality of bonding wires is connected, The fin includes portions extending from the pad portion to one side and the other side in the one direction, The semiconductor device according to claim 19.

Images