Semiconductor device

Abstract

To provide a semiconductor device capable of improving the reliability of electrical connection between a wiring board and a semiconductor element.SOLUTION: A semiconductor device 10 includes a wiring board 20, a semiconductor element 40, a bonding member 50 for bonding connection pads 30 of the wiring board 20 to electrode pads 41 of the semiconductor element 40, and a sealing resin 60 for sealing the gap between the wiring board 20 and the semiconductor element 40. The planar shape of each connection pad 30 includes a first body portion 31, a plurality of first protrusions 32 that protrude from the first body portion 31 toward a central region of the semiconductor element 40 in plan view, and a first recess portion 33. The planar shape of each bonding member 50 includes a second body portion 51, a plurality of second protrusions 52 that protrude from the second body portion 51 toward the central region, and a second recess portion 53. A first space S10 surrounded by the upper surface of the substrate body 21, the inner surface of the first recess portion 33, the inner surface of the second recess portion 53, and the lower surface of the electrode pad 41 is opened in only one direction.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Conventionally, a semiconductor device having a wiring board, a semiconductor element mounted on the wiring board, and a sealing resin for sealing between the wiring board and the semiconductor element is known (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the above semiconductor device, improvement in electrical connection reliability between the wiring board and the semiconductor element is desired.

Means for Solving the Problems

[0005] According to one aspect of the present invention, there is provided a wiring substrate including a substrate body, a wiring substrate having a plurality of connection pads formed on an upper surface of the substrate body, a semiconductor element having a plurality of electrode pads and mounted on the wiring substrate, a bonding member for bonding the connection pads and the electrode pads, and a sealing resin for sealing between the wiring substrate and the semiconductor element. The planar shape of the connection pad has a first main body portion, a plurality of first protruding portions protruding from the first main body portion toward a central region of the semiconductor element in a plan view, and a first recess surrounded by the first main body portion and the plurality of first protruding portions. The planar shape of the bonding member has a second main body portion formed on the first main body portion, a plurality of second protruding portions formed on the plurality of first protruding portions so as to protrude from the second main body portion toward the central region, and a second recess surrounded by the second main body portion and the plurality of second protruding portions. A first space surrounded by an upper surface of the substrate body, an inner surface of the first recess, an inner surface of the second recess, and a lower surface of the electrode pad is open only in one direction.

Advantages of the Invention

[0006] According to one aspect of the present invention, there is an effect that the electrical connection reliability between the wiring substrate and the semiconductor element can be improved.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

[0008] Hereinafter, an embodiment will be described with reference to the accompanying drawings. Note that the attached drawings may, for the sake of convenience, show an enlarged view of the characteristic parts to make the characteristics easier to understand, and the dimensional ratios of the respective components may vary in each drawing. Also, in the sectional views, for the sake of making the sectional structures of the respective members easier to understand, the hatching of some members is shown by changing it to a satin pattern, and the hatching of some members is omitted. In the plan views, hatching is applied to some members to make the planar shapes of the respective members easier to understand. In each drawing, the X-axis, Y-axis, and Z-axis that are perpendicular to each other are shown. In the following description, for the sake of convenience, the direction extending along the X-axis is referred to as the X-axis direction, the direction extending along the Y-axis is referred to as the Y-axis direction, and the direction extending along the Z-axis is referred to as the Z-axis direction. Note that in this specification, "in plan view" means looking at the object from the Z-axis direction unless otherwise specified. Also, in this specification, "planar shape" means the shape of the object as seen from the Z-axis direction unless otherwise specified. "Up, down, left, and right" in this specification are the directions when the signs indicating the respective members in each drawing can be correctly read in the correct position. "Opposite" in this specification means that surfaces or members are in front of each other, including not only the case where they are completely in front of each other but also the case where they are partially in front of each other. Also, "opposite" in this specification includes both the case where another member is interposed between two parts and the case where nothing is interposed between two parts. "Identical" in this specification includes not only the case of being exactly the same but also the case where there are some differences between the comparison objects due to the influence of dimensional tolerances and the like.

[0009] (Overall Configuration of Semiconductor Device 10) As shown in FIGS. 1 and 2, the semiconductor device 10 includes a wiring substrate 20, one or more (in this embodiment, one) semiconductor elements 40 mounted on the upper surface of the wiring substrate 20, and bonding members 50 and 55 that bond the wiring substrate 20 and the semiconductor element 40 to each other. As shown in FIG. 2, the semiconductor device 10 includes a sealing resin 60 that seals between the wiring substrate 20 and the semiconductor element 40, and external connection terminals 70. Note that FIG. 1 is a plan view of the semiconductor device 10 shown in FIG. 2 as viewed from above, and the semiconductor element 40 is drawn in a perspective manner.

[0010] (Structure of Wiring Substrate 20) As shown in FIGS. 2 and 3, the wiring substrate 20 has, for example, a substrate body 21, a wiring layer 22, and a solder resist layer 23.

[0011] As the substrate body 21, a wiring structure in which an insulating resin layer and a wiring layer are alternately laminated can be used. The wiring structure may have, for example, a core substrate or may not have a core substrate. As the material of the insulating resin layer, for example, a thermosetting insulating resin can be used. As the thermosetting insulating resin, for example, an insulating resin such as an epoxy resin, a polyimide resin, or a cyanate resin can be used. Also, as the material of the insulating resin layer, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The insulating resin layer may contain, for example, fillers such as silica or alumina. Note that the thickness of the substrate body 21 can be, for example, about 50 μm to 200 μm.

[0012] As shown in FIG. 1, the planar shape of the substrate body 21 is formed, for example, in a rectangular shape. The planar shape of the substrate body 21 is not limited to a rectangular shape and can be any shape. The planar size of the substrate body 21 is larger than the planar size of the semiconductor element 40. The planar size of the substrate body 21 can be, for example, about 5 mm × 5 mm to 20 mm × 20 mm.

[0013] As shown in FIGS. 2 and 3, the wiring layer 22 is formed on the upper surface of the substrate body 21. The wiring layer 22 is electrically connected to the external connection terminal 70, for example, via a wiring layer or a through electrode in the substrate body 21. As the material of the wiring layer 22, for example, copper (Cu) or a copper alloy can be used.

[0014] As shown in FIG. 2, the wiring layer 22 has one or more (in this embodiment, four) connection pads 30 and one or more (in this embodiment, 32) connection pads 35. The connection pads 30 and 35 are pads for mounting electronic components that are electrically connected to the semiconductor element 40.

[0015] The solder resist layer 23 is the outermost insulating layer of the outermost layer (here, the uppermost layer) of the wiring board 20. The solder resist layer 23 is formed on the upper surface of the substrate body 21. The solder resist layer 23 is formed on the upper surface of the substrate body 21 so as to cover, for example, a part of the wiring layer 22. The solder resist layer 23 is formed so as to cover, for example, the wiring layer 22 provided in the outer peripheral region of the upper surface of the substrate body 21. The solder resist layer 23 is laminated on the upper surface of the substrate body 21 so as to expose the connection pads 30, 35, for example. In the solder resist layer 23, openings 23X are formed which penetrate the solder resist layer 23 in the thickness direction and expose a part of the upper surface of the connection pads 30, 35 and the substrate body 21.

[0016] As shown in FIG. 4, the openings 23X are formed so as to overlap, for example, the mounting region where the semiconductor element 40 is mounted in a plan view. The openings 23X are formed so as to overlap, for example, the entire mounting region in a plan view. The planar size of the openings 23X is formed to be slightly larger than the planar size of the semiconductor element 40, for example. In other words, the solder resist layer 23 is formed so as to surround the semiconductor element 40 in a plan view. The solder resist layer 23 of the present embodiment is formed so as to cover the outer peripheral region of the upper surface of the substrate body 21 over the entire circumferential direction. The openings 23X are formed so as to expose the wiring layer 22 in the mounting region as the connection pads 30, 35, for example. The openings 23X are formed so as to expose the upper surface of the substrate body 21 in the mounting region.

[0017] As the material of the solder resist layer 23, for example, an insulating resin mainly composed of a photosensitive resin such as a phenolic resin or a polyimide resin can be used. The solder resist layer 23 may contain, for example, fillers such as silica and alumina.

[0018] On the surface of the wiring layer 22 exposed from the solder resist layer 23, that is, on the surface (upper surface and side surfaces, or only the upper surface) of the connection pads 30 and 35, a surface treatment layer is formed as required. Examples of the surface treatment layer include a gold (Au) layer, a nickel (Ni) layer / Au layer (a metal layer formed by laminating the Ni layer and the Au layer in this order), a Ni layer / palladium (Pd) layer / Au layer (a metal layer formed by laminating the Ni layer, the Pd layer, and the Au layer in this order), and the like. Other examples of the surface treatment layer include a Ni layer / Pd layer (a metal layer formed by laminating the Ni layer and the Pd layer in this order), a Pd / Au layer (a metal layer formed by laminating the Pd layer and the Au layer in this order), and the like. Here, the Au layer is a metal layer made of Au or an Au alloy, the Ni layer is a metal layer made of Ni or an Ni alloy, and the Pd layer is a metal layer made of Pd or a Pd alloy. As these Au layer, Ni layer, and Pd layer, for example, a metal layer (electroless plating layer) formed by an electroless plating method or a metal layer (electrolytic plating layer) formed by an electrolytic plating method can be used. Further, as the surface treatment layer, an OSP (Organic Solderability Preservative) film formed by performing an antioxidant treatment such as OSP treatment on the surface of the wiring layer 22 can also be used. As the OSP film, for example, an organic film such as an azole compound or an imidazole compound can be used.

[0019] (Structure of connection pad 30) The plurality of connection pads 30 are provided, for example, in the central region of the upper surface of the substrate body 21 in a plan view. The plurality of connection pads 30 are provided in the central region of the mounting region where the semiconductor element 40 is mounted. The plurality of connection pads 30 are provided, for example, adjacent to each other. The plurality of connection pads 30 are arranged, for example, in a matrix shape (in this embodiment, 2×2) in the central region of the mounting region in a plan view. More specifically, two connection pads 30 are arranged side by side with a gap therebetween along the X-axis direction, and two connection pads 30 are arranged side by side with a gap therebetween along the Y-axis direction. Each connection pad 30 faces the adjacent connection pad 30 in the X-axis direction with a gap therebetween and faces the adjacent connection pad 30 in the Y-axis direction with a gap therebetween. In other words, a gap S1 is formed between two adjacent connection pads 30 in the X-axis direction, and a gap S2 is formed between two adjacent connection pads 30 in the Y-axis direction. In this embodiment, the width of the gap S1, that is, the dimension of the gap S1 along the X-axis direction, is smaller than the width of the gap S2, that is, the dimension of the gap S2 along the Y-axis direction. In the following description, for convenience, the overlapping portion of the gap S1 and the gap S2 is referred to as a gap S3. The gap S3 is provided, for example, at the plane center of the mounting region. The gap S3 is provided, for example, at the center of the region where the four connection pads 30 are provided in a plan view. It should be noted that the four connection pads 30 are electrically insulated from each other.

[0020] The planar shape of each connection pad 30 has a first main body portion 31, a plurality (five in this embodiment) of first protruding portions 32 protruding from the first main body portion 31, and one or more (four in this embodiment) first recessed portions 33 surrounded by the first main body portion 31 and the two first protruding portions 32. The planar shape of each connection pad 30 is formed, for example, in a comb shape as a whole.

[0021] The first main body portion 31 is formed so as to connect a plurality of first protruding portions 32. The first main body portion 31 is formed, for example, to extend in a strip shape along the X-axis direction. In other words, the length direction of the first main body portion 31 coincides with the X-axis direction. The first main body portion 31 has a predetermined width in the Y-axis direction, for example. In other words, the width direction of the first main body portion 31 coincides with the Y-axis direction. The outer surface of the first main body portion 31 is formed flush with the outer surface of the first protruding portion 32, for example.

[0022] Each first protruding portion 32 is formed so as to protrude from the first main body portion 31 toward the central region of the semiconductor element 40 in plan view. Each first protruding portion 32 is formed so as to protrude from the first main body portion 31 toward the connection pad 30 facing in the Y-axis direction, for example. Each first protruding portion 32 extends along a direction intersecting the length direction of the first main body portion 31 (here, the X-axis direction), here, the Y-axis direction orthogonal to the length direction of the first main body portion 31. Each first protruding portion 32 is formed to extend in a strip shape along the Y-axis direction. Each first protruding portion 32 has a predetermined width in the X-axis direction. Each first protruding portion 32 is formed continuously and integrally with the first main body portion 31. The plurality of first protruding portions 32 are provided at intervals along the length direction of the first main body portion 31 (here, the X-axis direction). The plurality of first protruding portions 32 are formed to extend parallel to each other, for example. The plurality of first protruding portions 32 are formed so that the protruding amounts from the first main body portion 31 are the same as each other, for example. That is, the plurality of first protruding portions 32 are formed so that the length dimensions along the Y-axis direction are the same as each other. The outer surfaces of the two first protruding portions 32 provided at both ends in the length direction of the first main body portion 31 (here, the X-axis direction) among the plurality of first protruding portions 32 are formed flush with the outer surface of the first main body portion 31, for example.

[0023] The plurality of first recesses 33 are partitioned from each other by the first protrusions 32. Each first recess 33 is formed to be recessed from the central region of the semiconductor element 40 toward the outer peripheral region in plan view. Each first recess 33 is formed to be recessed from the protruding tip of the first protrusion 32 toward the first main body portion 31 in plan view. Each first recess 33 is constituted by a space surrounded by the first main body portion 31 and two first protrusions 32 adjacent to each other in the X-axis direction. Each first recess 33 is formed in a shape in which the inner end portion of the first recess 33 (that is, the end portion on the first main body portion 31 side) is blocked by the first main body portion 31. As shown in FIG. 3, each first recess 33 is formed so as to penetrate the connection pad 30 in the thickness direction (here, the Z-axis direction).

[0024] (Structure of connection pad 35) As shown in FIG. 4, the plurality of connection pads 35 are provided, for example, in the outer peripheral region of the upper surface of the substrate body 21 in plan view. The plurality of connection pads 35 are provided in the outer peripheral region of the mounting region where the semiconductor element 40 is mounted. The plurality of connection pads 35 are arranged peripherally in the outer peripheral region of the mounting region in plan view. That is, the plurality of connection pads 35 are provided along the outer peripheral region of the mounting region. The plurality of connection pads 35 are provided apart from each other. The plurality of connection pads 35 are electrically insulated from each other. Each connection pad 35 is provided apart from the plurality of connection pads 30. Each connection pad 35 is electrically insulated from the plurality of connection pads 30.

[0025] The wiring layer 22 constituting each connection pad 35 extends, for example, from the outer peripheral region of the mounting region toward the outer peripheral edge of the substrate body 21. A part of the wiring layer 22 constituting each connection pad 35 is covered by the solder resist layer 23.

[0026] (Structure of semiconductor element 40) As shown in FIG. 2, the semiconductor element 40 has a plurality of electrode pads 41 and 45 formed on the circuit formation surface (here, the lower surface) of the semiconductor element 40. The semiconductor element 40 is flip-chip mounted on the upper surface of the wiring substrate 20. The electrode pad 41 of the semiconductor element 40 is electrically connected to the connection pad 30 of the wiring substrate 20 via the bonding member 50. The electrode pad 45 of the semiconductor element 40 is electrically connected to the connection pad 35 of the wiring substrate 20 via the bonding member 55. Thereby, the semiconductor element 40 is electrically connected to the wiring layer 22 of the wiring substrate 20 via the electrode pads 41 and 45 and the bonding members 50 and 55.

[0027] As the semiconductor element 40, for example, a logic chip such as a CPU (Central Processing Unit) chip or a GPU (Graphics Processing Unit) chip can be used. Also, as the semiconductor element 40, for example, a memory chip such as a DRAM (Dynamic Random Access Memory) chip, an SRAM (Static Random Access Memory) chip, or a flash memory chip can be used. When a plurality of semiconductor elements 40 are mounted on the wiring substrate 20, a logic chip and a memory chip may be combined and mounted on the wiring substrate 20.

[0028] As shown in FIG. 1, the planar shape of the semiconductor element 40 is, for example, formed in a rectangular shape. The planar shape of the semiconductor element 40 is not limited to a rectangular shape and can be any shape. The planar size of the semiconductor element 40 can be, for example, about 3 mm × 3 mm to 12 mm × 12 mm. The thickness of the semiconductor element 40 can be, for example, about 50 μm to 100 μm.

[0029] As shown in FIG. 2, a plurality of electrode pads 41 are provided so as to face a plurality of connection pads 30 respectively. A plurality of electrode pads 45 are provided so as to face a plurality of connection pads 35 respectively. The electrode pads 41 and 45 are formed in a columnar shape so as to protrude downward from the circuit formation surface of the semiconductor element 40, for example. The electrode pads 41 and 45 are, for example, metal posts. The electrode pads 41 and 45 in this example are formed in a prismatic shape. The thickness of each of the electrode pads 41 and 45 can be, for example, about 2 μm to 50 μm. As the material of each of the electrode pads 41 and 45, for example, copper or a copper alloy can be used.

[0030] The planar shape of each of the electrode pads 41 and 45 is formed in a rectangular shape. The planar shape of each of the electrode pads 41 and 45 is not limited to a rectangular shape and can be any shape. Here, as shown in FIG. 4, each of the electrode pads 41 is provided so as to overlap with the entirety of each connection pad 30 in a plan view, for example. Each of the electrode pads 41 is provided so as to overlap with a plurality of first recesses 33 provided in each connection pad 30 in a plan view, for example.

[0031] (Structure of the bonding member 50) As shown in FIG. 2, each bonding member 50 is provided on the upper surface of each connection pad 30. Each bonding member 50 is provided between the upper surface of each connection pad 30 and the lower surface of the electrode pad 41. Each bonding member 50 is bonded to the upper surface of each connection pad 30 and is also bonded to the lower surface of each electrode pad 41.

[0032] As shown in FIG. 1, the planar shape of each bonding member 50 is formed in a shape similar to the planar shape of each connection pad 30, for example. The planar shape of each bonding member 50 has, for example, a second main body portion 51 and a plurality (five in this embodiment) of second protruding portions 52 protruding from the second main body portion 51. The planar shape of each bonding member 50 has one or more (four in this embodiment) second recesses 53 surrounded by the second main body portion 51 and the two second protruding portions 52. The planar shape of each bonding member 50 is formed in a comb shape as a whole, for example.

[0033] The second main body portion 51 is provided on the upper surface of the first main body portion 31. The second main body portion 51 is formed, for example, so as to entirely cover the upper surface of the first main body portion 31. The second main body portion 51 is formed so as to connect a plurality of second protruding portions 52. The second main body portion 51 is formed, for example, so as to extend in a strip shape along the X-axis direction. In other words, the length direction of the second main body portion 51 coincides with the X-axis direction. The second main body portion 51 has a predetermined width in the Y-axis direction, for example. In other words, the width direction of the second main body portion 51 coincides with the Y-axis direction.

[0034] Each second protruding portion 52 is provided on the upper surface of each first protruding portion 32. Each second protruding portion 52 is formed, for example, so as to entirely cover the upper surface of each first protruding portion 32. Each second protruding portion 52 is formed so as to protrude from the second main body portion 51 toward the central region of the semiconductor element 40 in a plan view. Each second protruding portion 52 extends along the Y-axis direction, which intersects the length direction (here, the X-axis direction) of the second main body portion 51, that is, the Y-axis direction orthogonal to the length direction of the second main body portion 51. Each second protruding portion 52 is formed so as to extend in a strip shape along the Y-axis direction. Each second protruding portion 52 has a predetermined width in the X-axis direction. Each second protruding portion 52 is formed continuously and integrally with the second main body portion 51. The plurality of second protruding portions 52 are provided at intervals along the length direction (here, the X-axis direction) of the second main body portion 51. The plurality of second protruding portions 52 are formed, for example, so as to extend parallel to each other. The plurality of second protruding portions 52 are formed, for example, so that the protruding amounts from the second main body portion 51 are the same as each other. That is, the second protruding portions 52 are formed so that the length dimensions along the Y-axis direction are the same as each other.

[0035] The plurality of second recesses 53 are partitioned from each other by the second protrusions 52. Each second recess 53 is formed to be recessed from the central region of the semiconductor element 40 toward the outer peripheral region in a plan view. Each second recess 53 is formed to be recessed from the protruding tip of the second protrusion 52 toward the second main body portion 51 in a plan view. Each second recess 53 is constituted by a space surrounded by the second main body portion 51 and two second protrusions 52 adjacent to each other in the X-axis direction. Each second recess 53 is provided so as to overlap with each first recess 33 in a plan view. Each second recess 53 is formed to communicate with each first recess 33. Each second recess 53 is formed in a shape in which the inner end portion (that is, the end portion on the second main body portion 51 side) of the second recess 53 is blocked by the second main body portion 51. As shown in FIG. 3, each second recess 53 is formed to penetrate the joining member 50 in the thickness direction (here, the Z-axis direction).

[0036] As shown in FIG. 5, the joining member 50 is formed so as to fill the gap between the upper surface of the connection pad 30 and the lower surface of the electrode pad 41. The joining member 50 is in close contact with the upper surface of the connection pad 30 without a gap and is also in close contact with the lower surface of the electrode pad 41 without a gap. At this time, the joining member 50 is continuously formed over the entire upper surface of the connection pad 30 by the second main body portion 51 and the second protrusions 52. And the inner end of the second recess 53 is blocked by the second main body portion 51 and the second protrusions 52. Also, the inner end portion of the first recess 33 is blocked by the first main body portion 31 and the first protrusions 32. Thereby, a first space S10 surrounded by the upper surface of the substrate main body 21, the inner surface of the first recess 33, the inner surface of the second recess 53, and the lower surface of the electrode pad 41 is formed in a shape of being blocked like a cul-de-sac. That is, the first space S10 is open only in one direction. More specifically, the first space S10 communicates with another space, here the gap S2, only through the openings of the first recess 33 and the second recess 53. Specifically, the first space S10 is separated from other spaces other than the gap S2 by the connection pad 30 and the joining member 50. That is, the connection pad 30 and the joining member 50 function as a partition wall that partitions the first space S10 and other spaces.

[0037] (Structure of the joining member 55) As shown in FIG. 2, each joining member 55 is provided on the upper surface of each connection pad 35. Each joining member 55 is provided between the upper surface of each connection pad 35 and the lower surface of each electrode pad 45. Each joining member 55 is joined to the upper surface of each connection pad 35 and is also joined to the lower surface of each electrode pad 45.

[0038] As shown in FIG. 1, the planar shape of each joining member 55 is formed, for example, in a shape similar to the planar shape of each connection pad 35. The planar shape of each joining member 50 in the present embodiment is formed in a rectangular shape.

[0039] Note that, as each of the joining members 50 and 55, for example, a tin (Sn) layer or a solder layer can be used. As the material of the solder layer, for example, lead-free solder such as Sn-silver (Ag)-based, Sn-copper (Cu)-based, or Sn-Ag-Cu-based can be used.

[0040] (Structure of the encapsulating resin 60) As shown in FIG. 2, the encapsulating resin 60 is formed so as to encapsulate the space between the upper surface of the substrate body 21 and the lower surface of the semiconductor element 40. The encapsulating resin 60 is formed so as to fill the space between the upper surface of the substrate body 21 and the lower surface of the semiconductor element 40. The encapsulating resin 60 is formed so as to cover the entire upper surface of the substrate body 21 exposed from the solder resist layer 23, the entire surfaces of the connection pads 30 and 35, the entire surfaces of the joining members 50 and 55, and the entire surfaces of the electrode pads 41 and 45. The encapsulating resin 60 is formed so as to fill the opening 23X of the solder resist layer 23. The encapsulating resin 60 is formed so as to cover the entire upper surface of the solder resist layer 23. The encapsulating resin 60 is formed so as to encapsulate the semiconductor element 40. The encapsulating resin 60 is formed so as to embed the semiconductor element 40. The encapsulating resin 60 is formed so as to embed at least the lower surface and the side surfaces of the semiconductor element 40. Specifically, the encapsulating resin 60 is formed so as to cover the entire lower surface and the entire side surfaces of the semiconductor element 40. The encapsulating resin 60 is formed, for example, so as to expose the entire upper surface of the semiconductor element 40.

[0041] As shown in FIG. 1, the encapsulating resin 60 is formed so as to fill the first recess 33 and the second recess 53. The encapsulating resin 60 is formed so as to fill the first space S10 surrounded by the upper surface of the substrate body 21, the inner surface of the first recess 33, the inner surface of the second recess 53, and the lower surface of the electrode pad 41. The encapsulating resin 60 is formed so as to fill the gaps S1, S2, and S3.

[0042] The encapsulating resin 60 has, for example, voids 61. The encapsulating resin 60 of the present embodiment has four voids 61. The voids 61 are provided in the first space S10. That is, the voids 61 are provided inside the first recess 33 and inside the second recess 53. The voids 61 are provided, for example, at the innermost end of the first space S10. The voids 61 may be provided in all of the first spaces S10, or may be provided only in some of the first spaces S10. In the encapsulating resin 60 of the present embodiment, the voids 61 are provided in some of the first spaces S10. The voids 61 are not provided in the spaces between two adjacent connection pads 30, that is, the gaps S1, S2, and S3.

[0043] As the material of the encapsulating resin 60, for example, a non-photosensitive insulating resin mainly composed of a thermosetting resin can be used. As the material of the encapsulating resin 60, for example, an insulating resin such as an epoxy resin or a polyimide resin, or a resin material in which fillers such as silica and alumina are mixed into these resins can be used. As the encapsulating resin 60, for example, a mold resin can be used.

[0044] As shown in FIGS. 2 and 3, the external connection terminals 70 are formed on the lower surface of the substrate body 21 of the wiring substrate 20. The external connection terminals 70 are connection terminals that are electrically connected to pads provided on a mounting substrate such as a mother board (not shown), for example. As the external connection terminals 70, for example, solder balls or lead pins can be used. The external connection terminals 70 in this example are solder balls.

[0045] Here, according to FIG. 18, the semiconductor device 10A of the comparative example will be described. In the semiconductor device 10A, the planar shape of each connection pad 30A is formed in a rectangular shape, and the planar shape of each bonding member 50A provided on each connection pad 30A is formed in a rectangular shape. In this semiconductor device 10A, voids 61A may occur in the encapsulating resin 60A. In the example shown in FIG. 18, the voids 61A are formed in the spaces between two adjacent connection pads 30A, specifically in the gaps S2 and S3. When the voids 61A are formed in the gaps S2 and S3, a part of each connection pad 30A is exposed in the voids 61A. When such voids 61A occur, for example, when the semiconductor device 10A is connected to a mounting substrate such as a mother board by heating or the like, the molten bonding member 50A flows into the voids 61A. Then, through the bonding member 50A that has flowed into the voids 61A, the adjacent connection pads 30A are short-circuited. Thus, when voids 61A occur in the space between adjacent connection pads 30A, a short-circuit failure occurs between the adjacent connection pads 30A.

[0046] On the other hand, as shown in FIG. 5, in the semiconductor device 10 of the present embodiment, the connection pad 30 is provided with a first recess 33, and the bonding member 50 is provided with a second recess 53. Then, the first space S10 surrounded by the first recess 33, the second recess 53, the substrate body 21, and the electrode pad 41 is formed in a shape that is blocked like a cul-de-sac and in a shape in which voids 61 (see FIG. 1) are likely to occur. According to this configuration, as shown in FIG. 1, voids 61 can be intentionally generated in the first space S10 existing inside the connection pad 30. Thereby, it is possible to preferably suppress the occurrence of voids 61 in the space between adjacent connection pads 30, that is, the gaps S1, S2, and S3.

[0047] (Manufacturing method of semiconductor device 10) Next, the manufacturing method of the semiconductor device 10 will be described. For the sake of convenience of explanation, parts that will finally become the components of the semiconductor device 10 are described with the reference numerals of the final components.

[0048] First, in the process shown in FIG. 6, a wiring board 20 having a substrate body 21, a wiring layer 22 having connection pads 30 and 35, and a solder resist layer 23 having an opening 23X is prepared. Since this wiring board 20 can be manufactured by a known manufacturing method, detailed description thereof is omitted here.

[0049] Next, in the processes shown in FIGS. 7 and 8, a semiconductor element 40 is prepared. As shown in FIG. 7, the semiconductor element 40 has electrode pads 41 and 45 formed on a circuit formation surface (here, the lower surface). Subsequently, the semiconductor element 40 is mounted on the connection pads 30 and 35 of the wiring board 20. For example, the electrode pads 41 and 45 of the semiconductor element 40 are respectively joined to the connection pads 30 and 35 of the wiring board 20 via joining members 50 and 55. Specifically, when the joining members 50 and 55 are solder layers, a flux (not shown) is appropriately applied on the connection pads 30 and 35, and the connection pads 30 and 35 and the electrode pads 41 and 45 are aligned with each other with the joining members 50 and 55 interposed therebetween. Thereafter, a reflow process is performed at a temperature of about 230° C. to 260° C. Thereby, the joining members 50 and 55, which are solder layers, are melted, and the connection pads 30 and 35 and the electrode pads 41 and 45 are electrically connected to each other via the joining members 50 and 55. At this time, as shown in FIG. 8, the semiconductor element 40 is arranged so as to overlap with the opening 23X of the solder resist layer 23 in a plan view. Further, the connection pads 30 and 35 and the joining members 50 and 55 are arranged so as to be exposed from the opening 23X of the solder resist layer 23.

[0050] Next, in the process shown in FIG. 9, a sealing resin 60 that seals between the wiring substrate 20 and the semiconductor element 40 is formed. The sealing resin 60 is formed so as to fill the space between the upper surface of the substrate body 21 and the lower surface of the semiconductor element 40. The sealing resin 60 is formed so as to embed at least the lower surface and the side surface of the semiconductor element 40. The sealing resin 60 can be formed, for example, by a resin molding method. For example, when a mold resin having thermosetting properties is used as the material of the sealing resin 60, the structure shown in FIGS. 7 and 8 is housed in a mold (not shown), and a pressure (for example, 5 MPa to 10 MPa) is applied to the mold to introduce the fluidized mold resin. Then, the mold resin is heated and cured at a temperature of about 180° C. to form the sealing resin 60. After completing the required sealing process, the structure with the sealing resin 60 formed is taken out of the mold. As a method of filling the mold resin, for example, methods such as a transfer molding method, a compression molding method, and an injection molding method can be used. When the sealing resin 60 is formed so as to cover the upper surface of the semiconductor element 40, for example, the semiconductor element 40 and the sealing resin 60 are thinned from the upper surface side. For example, the upper surface of the sealing resin 60 and the upper surface of the semiconductor element 40 are ground by back grinding or the like to thin the semiconductor element 40 and the sealing resin 60. Thereby, the upper surface of the sealing resin 60 and the upper surface of the semiconductor element 40 are formed flush with each other.

[0051] Thereafter, the external connection terminal 70 shown in FIG. 2 is formed on the lower surface of the wiring substrate 20. Through the above manufacturing process, the semiconductor device 10 of the present embodiment can be manufactured. Here, FIGS. 10 to 12 are diagrams schematically showing an example of the state in which the liquid sealing resin 60 flows on the wiring substrate 20 in the process shown in FIG. 9. Hereinafter, the state of flow of the sealing resin 60 when the liquid sealing resin 60 is supplied from the outer peripheral region of the wiring substrate 20 will be described.

[0052] As shown in FIG. 10, first, when the liquid sealing resin 60 is supplied to the outer peripheral region of the wiring board 20, the sealing resin 60 flows so as to cover the outer peripheral region of the wiring board 20 over the entire circumferential direction. Specifically, the sealing resin 60 flows so as to cover the outer peripheral region located outside the four joining members 50 of the wiring board 20 over the entire circumferential direction. For example, the sealing resin 60 flows so as to cover the solder resist layer 23 and the connection pad 35. For example, the sealing resin 60 flows so as to fill the gap between the connection pad 30 and the connection pad 35. At this time, the sealing resin 60 has not yet flowed into the gaps S1, S2, and S3.

[0053] Subsequently, as shown in FIG. 11, the sealing resin 60 flows so as to spread from the outer peripheral region of the wiring board 20 into the gaps S1 and S2. The sealing resin 60 flowing inside the gap S1 spreads toward the gap S3 through the gap S1. For example, the sealing resin 60 flows from the upper outer peripheral region in the figure toward the gap S3, and the sealing resin 60 flows from the lower outer peripheral region in the figure toward the gap S3. Then, the sealing resin 60 flowing from the upper outer peripheral region in the figure toward the gap S3 and the sealing resin 60 flowing from the lower outer peripheral region in the figure toward the gap S3 merge near the gap S3. The sealing resin 60 that has merged near the gap S3 in this way flows so as to spread in the X-axis direction from the gap S3. Specifically, it flows so as to spread from the gap S3 toward the left in the figure and spread from the gap S3 toward the right in the figure. That is, the sealing resin 60 that has merged near the gap S3 flows so as to spread from the gap S3 into the gap S2. At this time, the gaps S1 and S3 are filled with the sealing resin 60.

[0054] In addition, the sealing resin 60 that spreads from the outer peripheral region of the wiring board 20 into the gap S2 flows through the gap S2 toward the gap S3 and also flows so as to spread from the gap S2 into the first space S10 provided in each connection pad 30 and each joining member 50. For example, the sealing resin 60 flows from the left outer peripheral region in the figure toward the gap S3, and the sealing resin 60 also flows from the right outer peripheral region in the figure toward the gap S3. Further, the sealing resin 60 flows so as to spread into the first space S10 in the order closer to the outer peripheral region of the wiring board 20.

[0055] Subsequently, similarly, the sealing resin 60 flows through the gap S2 toward the gap S3 and also flows so as to spread from the gap S2 into the first space S10. As a result, as shown in FIG. 12, the sealing resin 60 is formed so as to spread over the entire upper surface of the wiring board 20. That is, the sealing resin 60 is formed so as to fill the gaps S1, S2, and S3 and all of the first spaces S10.

[0056] Here, each first space S10 is formed in a shape that is blocked like a cul-de-sac. That is, the first space S10 is open only in one direction. More specifically, the first space S10 communicates with other spaces, here the gap S2, only through the openings of the first recess 33 and the second recess 53. For this reason, the sealing resin 60 flows into each first space S10 only from the openings of the first recess 33 and the second recess 53. That is, the inflow direction of the sealing resin 60 into the first space S10 is restricted to one direction. In such a first space S10, voids 61 are likely to occur. By forming the first space S10 in which voids 61 are likely to occur in this way, voids 61 can be intentionally generated in the first space S10. By generating voids 61 in the first space S10, the fluidity of the sealing resin 60 in the spaces other than the first space S10, here the gaps S1, S2, and S3, can be improved. As a result, it is possible to preferably suppress the occurrence of voids 61 in the gaps S1, S2, and S3, which are the spaces between adjacent connection pads 30.

[0057] Next, the operation and effects of the present embodiment will be described. (1) The semiconductor device 10 includes a wiring substrate 20 having a plurality of connection pads 30, a semiconductor element 40 having a plurality of electrode pads 41, a bonding member 50 that bonds the connection pads 30 and the electrode pads 41, and a sealing resin 60 that seals between the wiring substrate 20 and the semiconductor element 40. The planar shape of each connection pad 30 has a first main body portion 31, a plurality of first protruding portions 32 that protrude from the first main body portion 31 toward the central region of the semiconductor element 40 in a plan view, and a first recessed portion 33 surrounded by the first main body portion 31 and the plurality of first protruding portions 32. The planar shape of each bonding member 50 has a second main body portion 51 formed on the first main body portion 31, and a plurality of second protruding portions 52 formed on the plurality of first protruding portions 32 so as to protrude from the second main body portion 51 toward the central region of the semiconductor element 40 in a plan view. Each bonding member 50 has a second recessed portion 53 surrounded by the second main body portion 51 and the plurality of second protruding portions 52.

[0058] According to this configuration, a first recess 33 surrounded by the first main body 31 and the plurality of first protrusions 32 is provided in the connection pad 30, and a second recess 53 surrounded by the second main body 51 and the plurality of second protrusions 52 is provided in the joining member 50. Here, the first recess 33 and the second recess 53 are formed in a shape in which the inner ends are blocked by the first main body 31 and the second main body 51. Therefore, the first space S10 formed by the first recess 33 and the second recess 53 is formed in a shape that is blocked like a dead end. As a result, the first space S10 is formed in a shape in which voids 61 are likely to occur when the sealing resin 60 is formed. By forming the first space S10 in which the voids 61 are likely to occur in this way, the voids 61 can be intentionally generated in the first space S10. Then, by generating the voids 61 in the first space S10, the fluidity of the sealing resin 60 in the spaces other than the first space S10, here the gaps S1, S2, S3, can be improved. Thereby, it is possible to suitably suppress the occurrence of voids 61 in the gaps S1, S2, S3 which are the spaces between the adjacent connection pads 30. Therefore, it is possible to suitably suppress the occurrence of a short circuit failure between the two connection pads 30 due to the formation of the voids 61. As a result, the electrical connection reliability between the wiring board 20 and the semiconductor element 40 can be improved.

[0059] (2) The first space S10 surrounded by the upper surface of the substrate body 21, the inner surface of the first recess 33, the inner surface of the second recess 53, and the lower surface of the electrode pad 41 is open only in one direction. Thereby, since the inflow direction of the resin into the first space S10 can be regulated in one direction, voids 61 are likely to occur inside the first space S10. Thereby, it is possible to suitably suppress the occurrence of voids 61 in the gaps S1, S2, S3.

[0060] (3) By providing the first space S10, a speed difference can be created between the encapsulation resin 60 flowing through the gap S1 and the encapsulation resin 60 flowing through the gap S2 communicating with the first space S10. As a result, it becomes possible to first fill the gap S3, which has the highest risk of being the shortest, with the encapsulation resin 60 flowing through the gap S1. Furthermore, the encapsulation resin 60 that has filled the gap S3 then merges with the encapsulation resin 60 flowing through the gap S2, and the voids generated at that time are washed away towards the first space S10. As a result, no voids remain in the gaps S1, S2, and S3 where a short circuit defect may occur.

[0061] (4) The encapsulation resin 60 has voids 61 provided in the first space S10. In other words, the voids 61 are formed in the first space S10 provided between two first protrusions 32 of a single connection pad 30. Therefore, even when the joining member 50 flows into the voids 61, the two first protrusions 32 of a single connection pad 30 are electrically connected through the joining member 50. That is, even when the joining member 50 flows into the voids 61, only the two first protrusions 32 at the same potential are electrically connected through the joining member 50. Therefore, even when the joining member 50 flows into the voids 61, no short circuit defect occurs.

[0062] (5) In this way, by forming the first space S10 provided between the two first protrusions 32 of a single connection pad 30 into a structure where voids 61 are likely to occur, voids 61 can be generated in the first space S10 where there is no risk of short circuit defects. And by generating voids 61 in the first space S10, the generation of voids 61 in the gaps S1, S2, and S3 where there is a possibility of short circuit defects can be preferably suppressed. In this way, the position where voids 61 are generated can be moved to a position that does not affect the product quality, that is, a position where there is no risk of short circuit defects. In other words, the position where voids 61 are likely to occur can be controlled.

[0063] (6) The planar shape of the connection pad 30 has three or more (in this embodiment, five) first protrusions 32 and a plurality (in this embodiment, four) of first recesses 33. The planar shape of the joining member 50 has three or more (in this embodiment, five) second protrusions 52 and a plurality (in this embodiment, four) of second recesses 53. The plurality of first recesses 33 are partitioned from each other by the first protrusions 32. The plurality of second recesses 53 are partitioned from each other by the second protrusions 52.

[0064] According to this configuration, a plurality (in this embodiment, four) of first spaces S10 are provided for one connection pad 30. Thereby, since a large number of first spaces S10 where voids 61 are likely to occur can be provided for one connection pad 30, it is possible to more preferably suppress the occurrence of voids 61 in spaces other than the first space S10, here the gaps S1, S2, and S3.

[0065] (Modification example) The above embodiment can be implemented with the following modifications. The above embodiment and the following modification examples can be implemented in combination with each other within a technically non - conflicting range.

[0066] · The structure of the connection pad 30 in the above embodiment can be appropriately changed. Similarly, the structure of the joining member 50 can be appropriately changed. · The number of the first protrusions 32 of the connection pad 30 in the above embodiment is not particularly limited. Similarly, the number of the second protrusions 52 of the joining member 50 is not particularly limited.

[0067] · For example, as shown in FIG. 13, the planar shape of the connection pad 30 may be changed to a shape having a first main body portion 31, two first protrusions 32, and one first recess 33. In this case, the planar shape of the joining member 50 may be changed to a shape having a second main body portion 51, two second protrusions 52, and one second recess 53.

[0068] ·For example, as shown in FIG. 14, the first main body 31 may be formed to protrude outward beyond the outer surface of the first protrusion 32. In this case, the second main body 51 may be formed to protrude outward beyond the outer surface of the second protrusion 52.

[0069] ·For example, as shown in FIG. 15, a plurality of first protrusions 32 may be formed such that the protruding amounts from the first main body 31 are different from each other. In this modified example, among the two first protrusions 32, the first protrusion 32 provided near the outer peripheral region of the wiring board 20 is formed such that the protruding amount from the first main body 31 is smaller. In this case, a plurality of second protrusions 52 may be formed such that the protruding amounts from the second main body 51 are different from each other. In this modified example, among the two second protrusions 52, the second protrusion 52 provided near the outer peripheral region of the wiring board 20 is formed such that the protruding amount from the second main body 51 is smaller.

[0070] ·The number of connection pads 30 in the above embodiment is not particularly limited. Similarly, the number of joining members 50 is not particularly limited. ·The arrangement of the plurality of connection pads 30 in the above embodiment is not particularly limited. Similarly, the arrangement of the plurality of joining members 50 is not particularly limited. The plurality of connection pads 30 and the plurality of joining members 50 may be changed to an arrangement other than a matrix.

[0071] ·For example, as shown in FIG. 16, the connection pad 35 may be omitted. ·In the above embodiment, the opening 23X of the solder resist layer 23 is formed so as to expose the entire connection pad 30, but it is not limited thereto.

[0072] ·For example, as shown in FIG. 16, an opening 23X of the solder resist layer 23 may be formed so as to expose a part of the connection pad 30. The opening 23X is formed so as to expose a first portion 31A of the first main body portion 31 that is connected to a plurality of first protruding portions 32, the plurality of first protruding portions 32, and the first recessed portion 33. In this case, the first main body portion 31 has a first portion 31A exposed from the opening 23X and a second portion 31B covered by the solder resist layer 23. The first protruding portion 32 in this modified example protrudes from the first portion 31A of the first main body portion 31 toward the central region of the semiconductor element 40 in a plan view. The second main body portion 51 of the bonding member 50 in this modified example is provided on the upper surface of the first portion 31A of the first main body portion 31.

[0073] ·For example, as shown in FIG. 16, the semiconductor element 40 may be provided so as to overlap the solder resist layer 23 in a plan view. For example, the planar size of the semiconductor element 40 may be formed larger than the planar size of the opening 23X of the solder resist layer 23.

[0074] ·For example, as shown in FIG. 17, the sealing resin 60 may be embodied as an underfill resin that fills the gap between the wiring substrate 20 and the semiconductor element 40. ·The structure of the wiring substrate 20 in the above embodiment can be appropriately changed. For example, the solder resist layer 23 may be omitted.

[0075] ·The structure of the electrode pad 41 in the above embodiment can be appropriately changed. For example, the planar shape of the electrode pad 41 may be changed to a shape similar to the planar shape of the connection pad 30.

[0076] ·The number of semiconductor elements 40 mounted on the wiring substrate 20 in the above embodiment is not particularly limited. For example, a plurality of semiconductor elements 40 may be mounted on the wiring substrate 20.

Description of Reference Numerals

[0077] 10 Semiconductor device 20 Wiring substrate 21 Substrate body 22 Wiring layer 23 Solder resist layer 23X Opening 30 Connection pad 31 First main body part 31A First part 31B Second part 32 First protruding part 33 First recessed part 40 Semiconductor element 41 Electrode pad 50 Bonding member 51 Second main body part 52 Second protruding part 53 Second recessed part 60 Encapsulation resin 61 Void S1, S2, S3 Gap S10 First space

Claims

1. A semiconductor device comprising a substrate body, a wiring substrate having a plurality of connection pads formed on an upper surface of the substrate body, a semiconductor element having a plurality of electrode pads and mounted on the wiring substrate, a bonding member for bonding the connection pads and the electrode pads, and a sealing resin for sealing between the wiring substrate and the semiconductor element, wherein a planar shape of the connection pad has a first main body portion, a plurality of first protruding portions protruding from the first main body portion toward a central region of the semiconductor element in a plan view, and a first recess surrounded by the first main body portion and the plurality of first protruding portions, a planar shape of the bonding member has a second main body portion formed on the first main body portion, a plurality of second protruding portions formed on the plurality of first protruding portions so as to protrude from the second main body portion toward the central region, and a second recess surrounded by the second main body portion and the plurality of second protruding portions, and a first space surrounded by an upper surface of the substrate body, an inner surface of the first recess, an inner surface of the second recess, and a lower surface of the electrode pad is open only in one direction.

2. The semiconductor device according to claim 1, wherein the sealing resin has voids provided in the first space.

3. The wiring substrate further has a solder resist layer formed on the upper surface of the substrate body, the solder resist layer has an opening penetrating in a thickness direction thereof, and the opening exposes at least a portion of the first main body portion connected to the plurality of first protruding portions, the plurality of first protruding portions, and the first recess.

4. The semiconductor device according to claim 3, wherein the opening exposes the entire plurality of connection pads.

5. The first main body portion has a first portion exposed from the opening and a second portion covered by the solder resist layer, the plurality of first protruding portions protrude from the first portion toward the central region, and the second main body portion is provided on the first portion.

6. The planar shape of the connection pad has three or more of the first protruding portions and a plurality of the first recesses, the planar shape of the bonding member has three or more of the second protruding portions and a plurality of the second recesses, and the plurality of first recesses are partitioned from each other by the first protruding portions. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The semiconductor device according to claim 1, wherein the plurality of second recesses are partitioned from each other by the second protrusions.

7. The semiconductor device according to claim 1, wherein the plurality of first protrusions have different protrusion amounts from the first main body portion.

8. The encapsulating resin is formed to cover the entire side surface of the semiconductor element, The semiconductor device according to claim 1, wherein the encapsulating resin is formed to expose the entire upper surface of the semiconductor element.

9. The plurality of connection pads are arranged in a matrix in a plan view, The semiconductor device according to claim 1, wherein two adjacent connection pads among the plurality of connection pads are arranged close to each other.

Images