Thin film transistor substrate and display using the same

Abstract

To provide a display capable of preventing a shift in threshold voltage.SOLUTION: One example of the present invention provides a thin film transistor substrate which includes a substrate, a buffer layer provided on the substrate and provided with buffer grooves, an active layer on the buffer layer, and a gate electrode on the active layer, in which the active layer is configured to have a step on the buffer groove, and in which one end of the gate electrode is superimposed on a sloping surface in the buffer groove, and a display including the substrate.SELECTED DRAWING: Figure 2A

Description

Technical Field

[0001] This specification relates to a thin film transistor substrate and a display device using the same.

Background Art

[0002] Since a thin film transistor can be manufactured on a glass substrate or a plastic substrate, it is widely used as a switching element or a driving element of a display device such as a liquid crystal display device or an organic light emitting device.

[0003] For a display panel for driving an organic light emitting device (OLED), various types of thin film transistors can be used, such as a driving thin film transistor for causing individual pixels to emit light, a switching thin film transistor for adjusting the amount of voltage applied to the driving thin film transistor, a Logic-GIP thin film transistor for controlling the thin film transistor provided in the display area, and a Buffer-GIP thin film transistor for controlling the supply of overall power.

[0004] In order to realize a high mobility element, in a thin film transistor having a top gate structure, the oxide semiconductor layer can be made conductive through a process using the gate electrode as a mask. However, in such a process of making the oxide semiconductor layer conductive, the region made conductive may penetrate excessively, and the channel region may be formed smaller than the region where the channel region is set, thereby shortening the channel length and shifting the threshold voltage (Vth) in the negative (-) direction. In particular, when the width of the oxide semiconductor layer is large, the penetration degree of the region made conductive becomes large, and the channel length may become even shorter.

[0005] When the threshold voltage (Vth) shifts in the negative (-) direction, leakage current may occur in the initial image. As a result, problems may occur such that the panel including the thin film transistor may have a driving failure due to the leakage current, and the power consumption of the panel may increase.

Summary of the Invention

Problems to be Solved by the Invention

[0006] This specification is devised to solve the above-described conventional problems. By disposing an active layer on a buffer groove provided in a buffer layer, oxygen vacancies diffusing through a conductor formation process are prevented from deeply penetrating into the channel, thereby preventing the threshold voltage (Vth) of the thin film transistor from shifting in the negative (-) direction. An object is to provide a thin film transistor substrate and a display device including the same.

Means for Solving the Problems

[0007] To achieve the above object, an embodiment of the present invention includes a substrate, a buffer layer provided on the substrate and provided with buffer grooves, an active layer provided on the buffer layer, and a gate electrode provided on the active layer. The active layer is configured to form a step on the buffer grooves, and one end of the gate electrode overlaps with an inclined surface provided in the buffer grooves, and provides a thin film transistor substrate and a display device including the same.

[0008] Furthermore, an embodiment of the present invention includes a substrate, a buffer layer provided on the substrate and having buffer grooves, an active layer provided on the buffer layer, and a gate electrode provided on the active layer. The buffer groove includes a bottom surface and an inclined surface connected to the bottom surface. The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion. The channel portion overlaps with the bottom surface and the inclined surface, and one end of the channel portion is located on the inclined surface of the buffer groove. A thin film transistor substrate and a display device including the same are provided.

Effects of the Invention

[0009] According to the present invention as described above, the following effects are achieved.

[0010] According to an embodiment of the present invention, by overlapping both ends of the gate electrode with the inclined surfaces of the buffer grooves provided in the buffer layer and positioning the channel portion of the active layer inside the buffer grooves, that is, forming the channel portion with a short length, the on-current characteristics of the thin film transistor substrate according to an embodiment of the present invention can be improved.

[0011] Furthermore, according to an embodiment of the present invention, by providing the active layer on the inclined surface of the buffer groove, the length of the channel portion does not become too short during the conductor formation process, so that the threshold voltage (Vth) of the thin film transistor substrate according to an embodiment of the present invention does not shift in the negative (-) direction.

[0012] The effects of the present invention are not limited to the above effects, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0014] The advantages, features, and methods for achieving them of the present invention will become apparent by referring to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but can be embodied in various different forms, and the present embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge in the technical field to which the present invention pertains of the scope of the invention, and the present invention is only defined by the scope of the claims.

[0015] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and the present invention is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to the same components. In the description of the present invention, when it is determined that a specific description of related known technologies may unnecessarily obscure the gist of the present invention, the detailed description thereof will be omitted. When terms such as "including", "having", "consisting of", etc. referred to in the present invention are used, other parts can be added unless "only" is used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0016] In the interpretation of components, even if there is no separate explicit description of the error range, it shall be interpreted as including the error range.

[0017] In the case of the description of the positional relationship, for example, when the positional relationship between two parts is described by "on ~", "above ~", "below ~", "beside ~", etc., unless the expressions "immediately" or "directly" are used, one or more other parts may be located between the two parts.

[0018] In the case of the description of the time relationship, for example, when the chronological relationship is described by "after ~", "subsequent to ~", "next to ~", "before ~", etc., unless the expressions "immediately" or "directly" are used, it can include cases where it is not continuous.

[0019] First, second, etc. are used to describe various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may also be the second component within the technical idea of the present invention.

[0020] The features of each of several embodiments of the present invention can be partially or wholly combined or combined with each other, and various linkages and drives are technically possible. Each embodiment can be implemented independently of each other or can be implemented together in an associated relationship.

[0021] Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

[0022] FIG. 1 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.

[0023] As can be seen from FIG. 1, a thin film transistor substrate according to an embodiment of the present invention includes a buffer layer 110, an active layer 120, a gate electrode 140, a source electrode 161, and a drain electrode 162.

[0024] The active layer 120 can extend in a first direction, for example, the horizontal direction. A source electrode 161 can be provided on one side of the active layer 120, for example, the left side, and a drain electrode 162 can be provided on the other side of the active layer 120, for example, the right side.

[0025] The gate electrode 140 can extend in a second direction, for example, the vertical direction. In this case, the second direction can correspond to a direction perpendicular to the first direction. The gate electrode 140 overlaps with the active layer 120.

[0026] The source electrode 161 can be electrically connected to one side of the active layer 120 through a first contact hole (CH1), and the drain electrode 162 can be electrically connected to the other side of the active layer 120 through a second contact hole (CH2).

[0027] According to an embodiment of the present invention, the buffer layer 110 can be formed on the entire surface of the thin film transistor substrate according to an example of an embodiment of the present invention so as to overlap with the active layer 120, the gate electrode 140, the source electrode 161, and the drain electrode 162. In this case, by providing a buffer groove (BG) in the buffer layer 110, it is possible to prevent the length of the channel portion provided in the active layer 120 from becoming excessively short. This will be specifically described with reference to FIG. 2A below.

[0028] The buffer groove (BG) can overlap with the active layer 120 and the gate electrode 140 in a region where the active layer 120 and the gate electrode 140 overlap. In this case, the buffer groove (BG) can have a first width (W BG ) in the horizontal direction, the gate electrode 140 can have a second width (W GE ) in the horizontal direction, and the active layer 120 can have a first length (L ACT ) in the horizontal direction.

[0029] According to an embodiment of the present invention, the first width (W of the buffer groove (BG)BG ) is formed to be larger than the second width (W of the gate electrode 140 GE ), and the first width (W of the buffer groove (BG) can be formed to be smaller than the first length (L of the active layer 120 BG ). ACT )

[0030] FIG. 2A is a cross-sectional view of a thin film transistor substrate according to an embodiment of the present invention. In this case, FIG. 2A corresponds to the cross-section I-I' of FIG. 1.

[0031] As can be seen from FIG. 2A, a thin film transistor substrate according to an embodiment of the present invention includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating film 130, a gate electrode 140, an interlayer insulating film 150, a source electrode 161, and a drain electrode 162.

[0032] The substrate 100 can be made of glass or plastic. In particular, the substrate 100 can be made of a flexible transparent plastic, such as polyimide. When polyimide is used as the substrate 100, a heat-resistant polyimide that can withstand high temperatures can be used in consideration of the high-temperature evaporation process performed on the substrate 100.

[0033] The buffer layer 110 can be formed on the substrate 100. The buffer layer 110 can protect the active layer 120 by blocking air and moisture. The buffer layer 110 can be composed of an inorganic insulator such as silicon oxide, silicon nitride, or a metal oxide, but is not necessarily limited thereto, and can be composed of an organic insulator.

[0034] According to an embodiment of the present invention, the buffer layer 110 may include a buffer groove (BG) formed to be recessed from the upper surface (US) of the buffer layer 110. The buffer groove (BG) is formed by removing a partial region of the upper surface of the buffer layer 110.

[0035] The buffer groove (BG) includes a bottom surface (BS) provided at the deepest part from the upper surface (US) of the buffer layer 110, and an inclined surface (IS) connected to the bottom surface (BS) and forming a first angle (θ1) with the bottom surface (BS).

[0036] The first angle (θ1) formed by the bottom surface (BS) and the inclined surface (IS) of the buffer groove (BG) can be 30 degrees or more and 45 degrees or less. When the first angle (θ1) formed by the bottom surface (BS) and the inclined surface (IS) is less than 30 degrees, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffused from the first connection portion 122a or the second connection portion 122b. When the first angle (θ1) formed by the bottom surface (BS) and the inclined surface (IS) exceeds 45 degrees, the thickness of the active layer 120 deposited on the inclined surface (IS) and the active layer 120 deposited on the bottom surface (BS) and the upper surface (US) may become different from each other, and there may occur a problem that the characteristics of the element become non-uniform.

[0037] By adjusting the first height (H1) of the bottom surface (BS) of the buffer groove (BG) and the second height (H2) of the upper surface (US) of the buffer layer 110, the first angle (θ1) of the inclined surface (IS) can be adjusted. In this case, the first height (H1) and the second height (H2) can be defined as the distance from the lower surface of the buffer layer 110 to the bottom surface (BS) of the buffer groove (BG) and the distance from the lower surface of the buffer layer 110 to the upper surface (US) of the buffer layer 110, respectively.

[0038] According to an embodiment of the present invention, the depth (H2 - H1) of the bottom surface (BS) of the buffer groove (BG) can be 1.41 μm or more and 2 μm or less. When the depth (H2 - H1) of the bottom surface (BS) of the buffer groove (BG) is less than 1.41 μm, the length of the channel portion 121 may be excessively shortened due to oxygen vacancies diffusing from the first connection portion 122a or the second connection portion 122b. When the depth (H2 - H1) of the bottom surface (BS) of the buffer groove (BG) exceeds 2 μm, the thickness of the active layer 120 deposited on the inclined surface (IS) and the active layer 120 deposited on the bottom surface (BS) and the upper surface (US) may become different from each other, and there may occur a problem that the characteristics of the element become non-uniform.

[0039] The active layer 120 may be provided so as to overlap with the buffer groove (BG) on the buffer layer 110. Specifically, the active layer 120 may be provided on a part of the upper surface of the buffer layer 110, the inclined surface (IS) of the buffer groove (BG), and the bottom surface (BS) of the buffer groove (BG). The active layer 120 may be provided so as to form a step on the buffer groove (BG). In this case, the active layer 120 may have a first length (L ACT ) in the lateral direction.

[0040] The active layer 120 may be configured to include a semiconductor material, for example, an oxide semiconductor material. The oxide semiconductor material may include, for example, at least one of an IZO (InZnO)-based oxide semiconductor material, an IGO (InGaO)-based oxide semiconductor material, an ITO (InSnO)-based oxide semiconductor material, an IGZO (InGaZnO)-based oxide semiconductor material, an IGZTO (InGaZnSnO)-based oxide semiconductor material, a GZTO (GaZnSnO)-based oxide semiconductor material, a GZO (GaZnO)-based oxide semiconductor material, an ITZO (InSnZnO)-based oxide semiconductor material, and an FIZO (FeInZnO)-based oxide semiconductor material.

[0041] The active layer 120 includes a channel portion 121, a first connection portion 122a, a second connection portion 122b, a first diffusion portion 123a, and a second diffusion portion 123b. In this case, the first connection portion 122a is provided on one side of the channel portion 121, for example, the left side, and the second connection portion 122b is provided on the other side of the channel portion 121, for example, the right side. The first diffusion portion 123a is provided between the channel portion 121 and the first connection portion 122a, and the second diffusion portion 123b may be provided between the channel portion 121 and the second connection portion 122b.

[0042] The channel portion 121 is provided inside the buffer groove (BG). Specifically, the central portion of the channel portion 121 is provided on the bottom surface (BS) of the buffer groove (BG), and one end and the other end of the channel portion 121 may be provided on the inclined surface (IS) of the buffer groove (BG).

[0043] The channel portion 121 includes a first region that contacts the bottom surface (BS) again and a second region that connects to the first region and contacts the inclined surface (IS). In this case, the first region and the second region can form a first angle (θ1) like the bottom surface (BS) and the inclined surface (IS) of the buffer groove (BG).

[0044] The channel portion 121 overlaps with the gate electrode 140. According to an embodiment of the present invention, one end of the channel portion 121, for example, the left end, can correspond to one end of the gate electrode 140, for example, the left end, and the other end of the channel portion 121, for example, the right end, can correspond to the other end of the gate electrode 140, for example, the right end. However, it is not limited thereto.

[0045] The first connection portion 122a and the second connection portion 122b can be made conductive by a conductor formation process of performing plasma treatment on a semiconductor material using, for example, the gate electrode 140 as a mask. For example, in the process of patterning the gate insulating film 130 provided on the active layer 120, a partial region of the active layer 120 can be made conductive. After the gate insulating film 130 is formed entirely on the active layer 120, it can be etched (Etch) by plasma to form a pattern. In this case, a partial region of the active layer 120 that is etched and exposed in the process of patterning the gate insulating film 130 is made conductive, and the first connection portion 122a and the second connection portion 122b can be formed.

[0046] The conductor formation process can be defined as a process of imparting conductivity to an oxide semiconductor material. The oxide semiconductor material that has undergone the conductor formation process can have conductivity. The conductor formation process can include, for example, a plasma process of adding plasma to conductify, but is not limited thereto. More specifically, when plasma is added to an oxide semiconductor material, for example, oxygen vacancies are formed while oxygen contained inside the oxide semiconductor escapes, and electrons can move through the oxygen vacancies. Eventually, the oxide semiconductor material becomes conductive due to the oxygen vacancies. When plasma is used in the conductor formation process, the plasma can contain, for example, fluorine (F). Specifically, the plasma containing fluorine (F) can be, for example, sulfur hexafluoride (SF6) and nitrogen trifluoride (NF3). However, the plasma for conducting the first connection portion 122a and the second connection portion 122b is not limited thereto and can contain various substances known in the art.

[0047] Through the conductor formation process, a partial region of the active layer 120, for example, the first connection portion 122a and the second connection portion 122b, can be made conductive. Therefore, the first connection portion 122a and the second connection portion 122b are superior in conductivity compared to the channel portion 121, and each can serve as a wiring or a source / drain electrode.

[0048] The first diffusion portion 123a and the second diffusion portion 123b can be formed during the process of forming the first connection portion 122a or the second connection portion 122b, respectively. Specifically, through the conductor formation process, the oxygen vacancies formed in the first connection portion 122a or the second connection portion 122b diffuse toward the center direction of the channel portion 121, and the first diffusion portion 123a and the second diffusion portion 123b are formed by the oxygen vacancies diffused in the center direction of the channel portion 121.

[0049] For example, while the oxygen vacancies formed in the first connection part 122a diffuse in the direction of the channel part 121, the first diffusion part 123a can be formed. Similarly, while the oxygen vacancies formed in the second connection part 122b diffuse, the second diffusion part 123b can be formed.

[0050] Since the conductivity of the first diffusion part 123a and the second diffusion part 123b progresses due to the oxygen vacancies diffused from the first connection part 122a and the second connection part 122b, their conductivity is relatively lower than that of the first connection part 122a and the second connection part 122b, but relatively higher than that of the channel part 121.

[0051] According to an embodiment of the present invention, the first diffusion part 123a and the second diffusion part 123b can be located within the inclined surface (IS) of the buffer groove (BG). Specifically, either one of the one end and the other end of the first diffusion part 123a or the second diffusion part 123b can be located within the inclined surface (IS). By forming in this way, even if oxygen vacancies diffuse from the first connection part 122a or the second connection part 122b, the length of the channel part 121 as designed can be ensured. Since the length of the channel part 121 can be ensured as designed, a thin film transistor substrate with a short channel can be realized without the threshold voltage (Vth) shifting in the negative (-) direction.

[0052] According to an embodiment of the present invention, one end of the first diffusion part 123a, for example, the left end, corresponds to one end of the gate insulating film 130 and one end of the gate electrode 140, and the other end of the first diffusion part 123a, for example, the right end, is located within the inclined surface (IS) of the buffer groove (BG). Similarly, one end of the second diffusion part 123b, for example, the right end, corresponds to the other end of the gate insulating film 130 and the other end of the gate electrode 140, and the other end of the second diffusion part 123b, for example, the left end, is located within the inclined surface (IS) of the buffer groove (BG). On the other hand, the meaning of corresponding in this specification means being located on a straight line or on any one plane.

[0053] The gate insulating film 130 is provided on the active layer 120. In this case, the upper surface of the gate insulating film 130 can have a third width (W GIa ), and the third width (W GIa ) can be smaller than the first length (L ACT ) of the active layer 120.

[0054] The gate insulating film 130 is formed by etching using the gate electrode 140 as a mask and can be formed to the same size as the gate electrode 140. However, it is not limited thereto.

[0055] One end of the gate insulating film 130, for example, the left end, can correspond to one end of the gate electrode 140, and the other end of the gate insulating film 130, for example, the right end, can correspond to the other end of the gate electrode 140. Therefore, the third width (W GIa ) of the gate insulating film 130 can be the same as the second width (W GE ) of the gate electrode 140.

[0056] The gate insulating film 130 can be provided to form a step on the buffer groove (BG). Specifically, it can be provided such that the height of the central portion of the gate insulating film 130 is lower than the height of the end portion.

[0057] The gate insulating film 130 can include a silicon nitride film (SiNx) or a silicon oxide film (SiOx), but is not limited thereto. The gate insulating film 130 can be composed of a single layer or a plurality of layers including an inorganic insulator and / or an organic insulator.

[0058] The gate electrode 140 is provided on the gate insulating film 130. The lateral width of the gate electrode 140 is configured to be longer than the lateral width of the bottom surface (BS) of the buffer groove (BG) and can be configured to be smaller than the entire width of the buffer groove (BG).

[0059] The gate electrode 140 overlaps with the buffer groove (BG). Specifically, one end and the other end of the gate electrode 140 are formed to overlap with the inclined surface (IS) of the buffer groove (BG).

[0060] According to an embodiment of the present invention, by overlapping one end and the other end of the gate electrode 140 with the inclined surface (IS) of the buffer groove (BG) respectively, the channel portion 121 of the active layer 120 can be provided inside the buffer groove (BG). That is, the channel portion 121 is formed with a short channel to enhance the on-current characteristics of the thin-film transistor substrate according to an embodiment of the present invention, and further, to prevent the channel portion 121 from becoming excessively short so that the threshold voltage (Vth) of the thin-film transistor substrate according to an embodiment of the present invention does not shift in the negative direction (Negative shift).

[0061] The gate electrode 140 can be configured to form a step on the buffer groove (BG). Specifically, it can be configured such that the height at the central portion of the gate electrode 140 is lower than the height at the end portion. In this case, the height of the gate electrode 140 can be defined as the height from the upper surface of the substrate 100 to the upper surface of the central portion of the gate electrode 140, or the height from the upper surface of the substrate 100 to the upper surface of the end portion of the gate electrode 140.

[0062] The gate electrode 140 can include at least one of aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), tantalum (Ta), neodymium (Nd), and titanium (Ti). The gate electrode 140 can also have a structure including one metal layer, or a multilayer structure including at least two metal layers with different physical properties respectively.

[0063] The interlayer insulating film 150 insulates between the gate electrode 140 and the source electrode 161, and further insulates between the gate electrode 140 and the drain electrode 162. The interlayer insulating film 150 may be composed of a single layer or a plurality of layers including an inorganic insulator and / or an organic insulator.

[0064] The interlayer insulating film 150 may be provided with a first contact hole (CH1) and a second contact hole (CH2). Accordingly, a part of the upper surface of the first connection portion 122a of the active layer 120 can be exposed by the first contact hole (CH1), and further, a part of the upper surface of the second connection portion 122b of the active layer 120 can be exposed by the second contact hole (CH2).

[0065] The source electrode 161 and the drain electrode 162 may be provided on the interlayer insulating film 150.

[0066] The source electrode 161 can be electrically connected to the first connection portion 122a of the active layer 120 through the first contact hole (CH1), and the drain electrode 162 can be electrically connected to the second connection portion 122b of the active layer 120 through the second contact hole (CH2).

[0067] The source electrode 161 and the drain electrode 162 can be formed of the same material as the gate electrode 140, but are not limited thereto, and can be formed of materials according to the knowledge in the art.

[0068] FIG. 2B is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, FIG. 2B corresponds to the cross-section I-I' of FIG. 1. On the other hand, since the embodiment of FIG. 2B is the same as FIG. 2A except for the configurations of the channel portion and the intermediate portion, the following description will focus on the different configurations.

[0069] As can be seen from FIG. 2B, a thin film transistor substrate according to another embodiment of the present invention may include a substrate 100, a buffer layer 110, an active layer 120, a gate insulating film 130, a gate electrode 140, an interlayer insulating film 150, a source electrode 161, and a drain electrode 162. On the other hand, in the embodiment of FIG. 2B, the first height (H1) of the bottom surface (BS) of the buffer groove (BG) is the same as that of the embodiment of FIG. 2A, but the upper surface (US) of the buffer layer 110 is different from the first height (H1) and has a third height (H3) from the lower surface of the buffer layer 110, whereby the inclined surface (IS) of the buffer groove (BG) can be formed at a second angle (θ2) different from the first angle (θ1).

[0070] According to another embodiment of the present invention, the channel portion 121 of the active layer 120 may not be provided on the inclined surface (IS) of the buffer groove (BG) and can be formed only on the bottom surface (BS) of the buffer groove (BG). Specifically, one end and the other end of the channel portion 121, for example, the left end and the right end, are both provided on the bottom surface (BS) of the buffer groove (BG), and both the one end and the other end of the channel portion 121 may not be provided on the inclined surface (IS) of the buffer groove (BG).

[0071] Furthermore, the first diffusion portion 123a and the second diffusion portion 123b can be formed to cover the entire inclined surface (IS) of the buffer groove (BG). In this case, the first diffusion portion 123a and the second diffusion portion 123b can be in contact with the channel portion 121 at the boundary between the bottom surface (BS) of the buffer groove (BG) and the inclined surface (IS) of the buffer groove (BG). Specifically, one end of the first diffusion portion 123a, for example, the right end, can be in contact with one end of the channel portion 121, for example, the left end, at the boundary between the bottom surface (BS) and the inclined surface (IS). Similarly, one end of the second diffusion portion 123b, for example, the left end, can be in contact with the other end of the channel portion 121, for example, the right end, at the boundary between the bottom surface (BS) and the inclined surface (IS).

[0072] According to another embodiment of the present invention, since the oxygen vacancies diffused from the first connection portion 122a and the second connection portion 122b do not reach the active layer 120 disposed on the bottom surface (BS) of the buffer groove (BG), the length of the channel portion 121 provided on the bottom surface (BS) of the buffer groove (BG) may not become excessively short. Further, since the length of the channel portion 121 does not become excessively short, a thin-film transistor substrate with a short channel can be configured without the threshold voltage (Vth) shifting in the negative (-) direction.

[0073] FIGS. 3A and 3B are schematic views respectively showing cross-sections of a thin-film transistor substrate according to an embodiment of the present invention and a thin-film transistor substrate according to a comparative example in a simplified manner. FIGS. 3A and 3B are cross-sectional views showing only the substrate, buffer layer, active layer, gate insulating film, and gate electrode for convenience of explanation of the thin-film transistor substrate according to the embodiment of FIG. 2A or the thin-film transistor substrate according to the comparative example.

[0074] First, since the thin-film transistor substrate of FIG. 3A is the same as the thin-film transistor substrate of FIG. 2A, repeated description will be omitted. Further, since the thin-film transistor substrate according to the comparative example of FIG. 3B has the same configuration except for the configuration of the buffer groove, the same reference numerals will be used to describe the remaining configuration, and repeated description will be omitted.

[0075] The thin-film transistor substrate according to the comparative example includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating film 130, and a gate electrode 140 as shown in FIG. 3B. However, no separate buffer groove is provided in the buffer layer 110 of the thin-film transistor substrate according to the comparative example.

[0076] FIG. 3C is a graph of carrier concentration according to the distance to the diffusion part of the thin film transistor substrate according to an embodiment and a comparative example of the present invention. In this case, FIG. 3C relates to a graph of carrier concentration according to the distance to the thin film transistor substrate according to the embodiment of FIG. 3A and the comparative example of FIG. 3B, each including an active layer (20 μm × 10 μm) having a length of 20 μm and a width of 10 μm. The distance means the distance measured along the active layer 120 in the channel part 121 direction from one end of the first connection part 122a, for example, the right end close to the channel part 121.

[0077] Point a in FIG. 3C relates to the carrier concentration at one end, for example, the left end of the first diffusion part 123a of the thin film transistor substrate according to the embodiment of FIG. 3A and the comparative example of FIG. 3B, and point b in FIG. 3C relates to the carrier concentration at the other end, for example, the right end of the first diffusion part 123a of the thin film transistor substrate according to the embodiment of FIG. 3A and the comparative example of FIG. 3B.

[0078] As can be seen from FIG. 3C, at point a, since one end of the first diffusion part 123a is in contact with the first connection part 122a, it can be confirmed that the carrier concentration is relatively high. On the other hand, at point b, the other end of the first diffusion part 123a is far away from the first connection part 122a. In this case, it can be confirmed that the carrier concentration gradually decreases from point a to point b. On the other hand, it can be seen that the carrier concentration at point b is about 0.28 times different from the carrier concentration at point a. As a result, at a point about 1 μm away from the first connection part 122a, for example, from point b, the diffusion of oxygen vacancies is significantly reduced and the carrier concentration becomes relatively low, so that it can function as the channel part 121.

[0079] Looking at FIG. 3A again, since the first diffusion portion 123a is provided on the inclined surface (IS), oxygen vacancies diffuse only from point a to point b from the first connection portion 122a. In this case, since one end of the first diffusion portion 123a, for example, the right end, diffuses only up to the point (point b) corresponding to the gate electrode 140, the length of the channel portion 121 can be ensured to be the designed length without becoming excessively short.

[0080] On the other hand, looking at FIG. 3B, in the comparative example according to FIG. 3B, since there is no separate buffer groove (BG), the first diffusion portion 123a is provided on a plane. Therefore, when oxygen vacancies diffuse from point a to point b from the first connection portion 122a, one end of the first diffusion portion 123a, for example, the right end, is located inside the gate electrode 140, unlike the case of FIG. 3A. Accordingly, the lateral width of the channel portion 121 is formed shorter than the lateral width of the gate electrode 140. Eventually, according to the comparative example of FIG. 3B, a channel portion 121 having a length shorter than the designed length is obtained.

[0081] Eventually, as in the embodiment of FIG. 3A, when the buffer groove (BG) is provided in the buffer layer 110 and the active layer 120 is provided on the buffer groove (BG), the first diffusion portion 123a and the second diffusion portion 123b are provided on the inclined surface (IS) of the buffer groove (BG), and the length of the channel portion 121 can be ensured to be the designed length.

[0082] On the other hand, in FIGS. 3A to 3C, the case where the length of the active layer 120 is 20 μm and the width is 10 μm has been mainly described with respect to the carrier concentration depending on the distance, but the length and width of the active layer 120 are not limited thereto and can be formed in various sizes according to the knowledge in the art.

[0083] FIGS. 4A to 4E are cross-sectional process diagrams for manufacturing a thin film transistor substrate according to an embodiment of the present invention. On the other hand, the cross-sectional process diagrams of FIGS. 4A to 4E relate to the process of manufacturing the embodiment of FIG. 2A, and the same components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0084] First, as can be seen from FIG. 4A, a substrate 100 is prepared, and a buffer layer 110 is formed on the substrate 100. Then, a buffer groove (BG) is formed in the buffer layer 110. In this case, the buffer groove (BG) is formed such that the bottom surface (BS) and the inclined surface (IS) of the buffer groove (BG) form a first angle (θ1) with each other.

[0085] Next, as can be seen from FIG. 4B, an active layer 120 is formed on the buffer layer 110. In this case, the active layer 120 can be formed so as to cover all of the buffer grooves (BG). Therefore, the active layer 120 can cover the bottom surface (BS) and the inclined surface (IS) of the buffer groove (BG), and a part of the upper surface (US) of the buffer layer 110.

[0086] Since the active layer 120 is formed so as to cover the buffer grooves (BG) and a part of the upper surface (US) of the buffer layer 110, the active layer 120 can be provided to form a step on the buffer layer 110.

[0087] Next, as can be seen from FIG. 4C, a gate insulating film layer 130a is formed on the buffer layer 110 and the active layer 120, and a gate electrode 140 is patterned on the gate insulating film layer 130a. In this case, the gate insulating film layer 130a can be formed on the entire surface of the substrate 100.

[0088] Since the gate insulating film layer 130a and the gate electrode 140 are formed so as to overlap with the buffer groove (BG), the gate insulating film layer 130a and the gate electrode 140 are formed so as to have a step such that the height of the central portion is lower than the height of the end portion.

[0089] Although not specifically shown in the figure for the gate electrode 140, after depositing a metal material layer for forming the gate electrode 140 on the entire surface of the substrate 100, the metal material layer is patterned according to the design to form the gate electrode 140. On the other hand, it is not limited thereto.

[0090] Next, as can be seen from FIG. 4D, using the gate electrode 140 as a mask, the gate insulating film layer 130a can be patterned to form the gate insulating film 130. In this case, dry etching can be used to pattern the gate insulating film 130. However, it is not limited thereto, and various methods according to the level of those skilled in the art well-known in the art can be used.

[0091] Furthermore, in the process of forming the gate insulating film 130, a part of the active layer 120, for example, a part that was covered by the gate insulating film layer 130a but is exposed while being etched, can be exposed to the plasma applied in the etching process. In this case, since a part of the active layer 120 is made of an oxide semiconductor material, it becomes conductive while oxygen vacancies are generated. Eventually, a part of the active layer 120 that was covered by the gate insulating film layer 130a but is exposed while being etched becomes the first connection part 122a and the second connection part 122b.

[0092] Also, in another part of the active layer 120 covered by the gate insulating film 130, oxygen vacancies formed in the first connection part 122a and / or the second connection part 122b diffuse in the direction of the channel part 121, thereby making another part of the active layer 120 conductive, and the other part of the conductive active layer 120 becomes the first diffusion part 123a and the second diffusion part 123b.

[0093] Finally, as can be seen from FIG. 4E, an interlayer insulating film 150 is formed so as to cover the buffer layer 110, the active layer 120, the gate insulating film 130, and the gate electrode 140. In this case, a first contact hole (CH1) and a second contact hole (CH2) are provided in the interlayer insulating film 150, and a part of the upper surface of the first connection part 122a and a part of the upper surface of the second connection part 122b are respectively exposed. When a source electrode 161 and a drain electrode 162 are formed on the interlayer insulating film 150, the source electrode 161 is electrically connected to the first connection part 122a through the first contact hole (CH1), and the drain electrode 162 is electrically connected to the second connection part 122b through the second contact hole (CH2).

[0094] FIG. 5 is a cross-sectional view of a thin film transistor substrate according to another embodiment of the present invention. In this case, FIG. 5 corresponds to cross-section I-I' of FIG. 1. On the other hand, since the embodiment of FIG. 5 is the same as the embodiment of FIG. 2A except for the configuration of the gate insulating film, repetitive description is omitted.

[0095] As can be seen from FIG. 5, a thin film transistor substrate according to another embodiment of the present invention includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating film 130, a gate electrode 140, an interlayer insulating film 150, a source electrode 161, and a drain electrode 162.

[0096] According to another embodiment of the present invention, the gate insulating film 130 is formed to be larger in size than the gate electrode 140. Specifically, the upper surface of the gate insulating film 130 can have a fourth width (W GIb ) in the horizontal direction, and the fourth width (W GIb ) of the gate insulating film 130 may be shorter than the first length (L ACT ) of the active layer 120 and larger than the second width (W GE ) of the gate electrode 140. Therefore, one end and the other end of the gate insulating film 130 do not correspond to one end and the other end of the gate electrode 140, and are provided outside the gate electrode 140.

[0097] Since the gate insulating film 130 is formed larger than the gate electrode 140, a part of the upper surface of the gate insulating film 130 can be exposed to the outside without being covered by the gate electrode 140.

[0098] The gate insulating film 130 overlaps a part of the buffer groove (BG) and the upper surface (US) of the buffer layer 110. The gate insulating film 130 is provided on the buffer groove (BG), and one end, for example, the left end and the other end, for example, the right end of the gate insulating film 130 can be provided on the upper surface (US) of the buffer layer 110, respectively.

[0099] In this case, one end of the gate insulating film 130 can be located between one end of the gate electrode 140 and one end of the active layer 120, and the other end of the gate insulating film 130 can be disposed between the other end of the gate electrode 140 and the other end of the active layer 120.

[0100] According to still another embodiment of the present invention, the first diffusion portion 123a and the second diffusion portion 123b may be provided under the gate insulating film 130. Specifically, the first diffusion portion 123a and the second diffusion portion 123b may be provided under a portion of the gate insulating film 130 that is not covered by the gate electrode 140.

[0101] Furthermore, the first diffusion portion 123a and the second diffusion portion 123b can be formed over a region extending from the upper surface (US) of the buffer layer 110 to the inclined surface (IS) of the buffer groove (BG). Therefore, one end of the first diffusion portion 123a, for example, the left end and one end of the second diffusion portion 123b, for example, the right end are provided on the upper surface (US) of the buffer layer 110, and the other end of the first diffusion portion 123a, for example, the right end and the other end of the second diffusion portion 123b, for example, the left end are provided on the inclined surface (IS) of the buffer groove (BG).

[0102] By forming in this way, since the length in the direction of the channel portion 121 from the first connection portion 122a and the second connection portion 122b becomes long, even if oxygen vacancies diffuse in the direction of the channel portion 121 from the first connection portion 122a or the second connection portion 122b, the length of the channel portion 121 as designed can be ensured. Eventually, since the length of the channel portion 121 can be ensured as designed, a thin film transistor substrate with a short channel can be realized without the threshold voltage (Vth) shifting in the negative (-) direction (Negative Sift).

[0103] On the other hand, although not specifically shown in the figure in FIG. 5, in another embodiment of the present invention, the gate insulating film 130 is formed larger than the gate electrode 140, and a part of the upper surface of the gate insulating film 130 is not covered by the gate electrode 140 and is exposed to the outside. Further, as in the embodiment of FIG. 2B described above, oxygen vacancies diffused from the first connection portion 122a and the second connection portion 122b reach within the inclined surface (IS) of the buffer groove (BG), so that the first diffusion portion 123a and the second diffusion portion 123b are formed to cover the entire inclined surface (IS) of the buffer groove (BG), and the channel portion 121 can be provided only on the bottom surface (BS) of the buffer groove (BG).

[0104] FIGS. 6A to 6F are cross-sectional process views of manufacturing a thin film transistor substrate according to another embodiment of the present invention. On the other hand, the cross-sectional process views of FIGS. 6A to 6F relate to the process of manufacturing the embodiment of FIG. 5, and the same components are denoted by the same reference numerals, and repeated descriptions are omitted.

[0105] First, as can be seen from FIG. 6A, a substrate 100 is prepared, and after a buffer layer 110 is formed on the substrate 100, a buffer groove (BG) is formed in the buffer layer 110. On the other hand, since the manufacturing process of FIG. 6A is the same as the manufacturing process of FIG. 4A, repeated descriptions are omitted.

[0106] Next, as can be seen from FIG. 6B, an active layer 120 is formed on the buffer layer 110. On the other hand, since the manufacturing process of FIG. 6B is the same as the manufacturing process of FIG. 4B, repeated descriptions are omitted.

[0107] Next, as can be seen from FIG. 6C, a gate insulating film layer 130a is formed on the buffer layer 110 and the active layer 120, and a gate electrode 140 is patterned on the gate insulating film layer 130a. In this case, the gate insulating film layer 130a can be formed on the entire surface of the substrate 100.

[0108] On the gate electrode 140, a resist pattern 200 used for patterning the gate electrode 140 is formed. The gate electrode 140 is patterned using the resist pattern 200 as a mask.

[0109] The resist pattern 200 can be formed with a width wider than the width of the gate electrode 140 in the first direction to be formed. Further, the resist pattern 200 can be formed with a width wider than the width of the buffer groove (BG) in the first direction.

[0110] Since the gate insulating film layer 130a and the gate electrode 140 are formed so as to overlap with the buffer groove (BG), the gate insulating film layer 130a and the gate electrode 140 are formed so as to have a step such that the height of the central portion is lower than the height of the end portion.

[0111] Next, as can be seen from FIG. 6D, using the resist pattern 200 as a mask, the gate insulating film layer 130a can be patterned to form the gate insulating film 130. In this case, dry etching can be used to pattern the gate insulating film 130. However, it is not limited thereto, and various methods according to the level of those skilled in the art widely known in the industry can be used.

[0112] According to still another embodiment of the present invention, since the gate insulating film 130 is formed using the resist pattern 200 as a mask, it can be formed with a width larger than that of the gate electrode 140. Therefore, one end and the other end of the gate insulating film 130 are respectively provided outside the gate electrode 140 and formed on the upper surface (US) of the buffer layer 110.

[0113] In the process of forming the gate insulating film 130, a part of the active layer 120, for example, a part that was covered by the gate insulating film layer 130a but is exposed while being etched, may be exposed to the plasma applied in the etching process. In this case, since a part of the active layer 120 is made of an oxide semiconductor material, it becomes conductive while oxygen vacancies are generated. Eventually, a part of the active layer 120 that was covered by the gate insulating film layer 130a but is etched and exposed becomes the first connection part 122a and the second connection part 122b.

[0114] Also, in another part of the active layer 120 covered by the gate insulating film 130, oxygen vacancies formed in the first connection part 122a and / or the second connection part 122b diffuse in the direction of the channel part 121, causing another part of the active layer 120 to become conductive. Another part of the conductive active layer 120 becomes the first diffusion part 123a and the second diffusion part 123b.

[0115] According to another embodiment of the present invention, since the gate insulating film 130 is provided on the upper surface (US) of the buffer layer 110, the first diffusion part 123a and the second diffusion part 123b can also be provided on the upper surface (US) of the buffer layer 110. By being formed in this way, the distance from the first connection part 122a or the second connection part 122b to the channel part 121 direction becomes longer, and the length of the channel part 121 as designed can be ensured.

[0116] Next, as can be seen from FIG. 6E, the resist pattern 200 can be removed through a stripping process.

[0117] Finally, as can be seen from FIG. 6F, an interlayer insulating film 150, a source electrode 161, and a drain electrode 162 are formed. On the other hand, since the manufacturing process of FIG. 6F is the same as the manufacturing process of FIG. 4E, repeated omissions are omitted.

[0118] FIG. 7 is a cross-sectional view of a display device including a thin film transistor substrate according to an embodiment of the present invention.

[0119] As can be seen from FIG. 7, the display device according to an embodiment of the present invention includes a substrate 100, a buffer layer 110, an active layer 120, a gate insulating film 130, a gate electrode 140, an interlayer insulating film 150, a source electrode 161, a drain electrode 162, a planarization layer 170, a first electrode 300, a bank layer 310, a light-emitting layer 320, and a second electrode 330.

[0120] The substrate 100, the buffer layer 110, the active layer 120, the gate insulating film 130, the gate electrode 140, the interlayer insulating film 150, the source electrode 161, and the drain electrode 162 are the same as those in the above-described embodiment. Therefore, only the different configurations will be described below.

[0121] The planarization layer 170 is provided on the source electrode 161 and the drain electrode 162. A third contact hole (CH3) is provided in the planarization layer 170. The drain electrode 162 is exposed by the third contact hole (CH3). However, in some cases, the source electrode 161 can also be exposed by the third contact hole (CH3).

[0122] The first electrode 300 is formed on the planarization layer 170 and is connected to the source electrode 161 or the drain electrode 162 through the third contact hole (CH3). The first electrode 300 can function as an anode.

[0123] The bank layer 310 is provided to cover the edge of the first electrode 300 and defines a light-emitting region. Therefore, the upper surface region of the first electrode 300 that is exposed without being covered by the bank layer 310 becomes the light-emitting region.

[0124] The light-emitting layer 320 is provided on the first electrode 300. The light-emitting layer 320 can include red, green, and blue light-emitting layers that are patterned for each pixel, or can be a white light-emitting layer connected to all pixels. When the light-emitting layer 320 is a white light-emitting layer, the light-emitting layer 320 can be configured to include, for example, a first stack including a blue light-emitting layer, a second stack including, for example, a yellow-green light-emitting layer, and a charge generation layer provided between the first stack and the second stack, but is not necessarily limited thereto.

[0125] The second electrode 330 is provided on the light-emitting layer 320. The second electrode 330 can function as a cathode.

[0126] Although not shown in the figure, a sealing layer for preventing the penetration of moisture and oxygen can be further formed on the second electrode 330.

[0127] FIG. 8 is a schematic diagram of a display device according to an embodiment of the present invention.

[0128] As can be seen from FIG. 8, a display device according to an embodiment of the present invention can include a display panel 410, a gate driver 420, a data driver 430, and a control unit 440.

[0129] The display panel 410 includes gate lines (GL) and data lines (DL), and pixels (P) are arranged in the intersection regions of the gate lines (GL) and the data lines (DL). An image is displayed by driving the pixels (P). The gate lines (GL), the data lines (DL), and the pixels (P) can be arranged on the substrate 100.

[0130] The control unit 440 controls the gate driver 420 and the data driver 430. The control unit 440 outputs a gate control signal (GCS) for controlling the gate driver 420 and a data control signal (DCS) for controlling the data driver 430 by using signals supplied from an external system (not shown). Further, after sampling the input video data input from the external system, the control unit 440 rearranges it and supplies the rearranged digital video data (RGB) to the data driver 430.

[0131] The gate control signal (GCS) includes a gate start pulse (GSP), a gate shift clock (GSC), a gate output enable signal (GOE), a start signal (Vst), a gate clock (GCLK), and the like. Further, the gate control signal (GCS) can include a control signal for controlling a shift register.

[0132] The data control signal (DCS) includes a source start pulse (SSP), a source shift clock signal (SSC), a source output enable signal (SOE), a polarity control signal (POL), and the like.

[0133] The data driver 430 supplies a data voltage to the data lines (DL) of the display panel 410. Specifically, the data driver 430 converts the video data (RGB) input from the control unit 440 into an analog data voltage and supplies the data voltage to the data lines (DL).

[0134] The gate driver 420 can be implemented on the display panel 410. In this way, the structure in which the gate driver 420 is directly implemented on the display panel 410 is called a gate in panel (GIP) structure. Specifically, in the gate in panel (GIP) structure, the gate driver 420 can be arranged on the substrate 100.

[0135] The gate driver 420 can include a shift register 450.

[0136] The shift register 450 sequentially supplies gate pulses to the gate lines (GL) during one frame using the start signal and gate clock transmitted from the control unit 440. Here, one frame refers to the period during which one image is output via the display panel 410. The gate pulse has a turn-on voltage capable of turning on the switching element (thin film transistor) arranged in the pixel (P).

[0137] Also, during the remaining period when no gate pulse is supplied in one frame, the shift register 450 supplies a gate-off signal capable of turning off the switching element to the gate line (GL). The gate pulse and the gate-off signal can be collectively referred to as a gate signal (GS).

[0138] FIG. 9 is a circuit diagram for one pixel provided in the display device according to an embodiment of the present invention.

[0139] As can be seen from FIG. 9, the display device according to an embodiment of the present invention includes first to second thin film transistors (T1, T2) and a capacitor (Cst).

[0140] The first thin film transistor (T1) is a driving thin film transistor, and the second thin film transistor (T2) is a switching thin film transistor.

[0141] The first thin film transistor (T1) is switched by the data voltage (Vdata) supplied from the second thin film transistor (T2), generates a data current from the driving voltage (VDD) supplied from the power line (PL), and supplies it to the organic light emitting diode (OLED).

[0142] The second thin film transistor (T2) is switched by the gate signal (GS) supplied to the gate line (GL), and supplies the data voltage (Vdata) supplied from the data line (DL) to the first thin film transistor (T1).

[0143] According to an embodiment of the present invention, the thin film transistor substrate according to the foregoing embodiment can be used as a thin film transistor substrate including any one of the first thin film transistor (T1) and the second thin film transistor (T2).

[0144] The capacitor (Cst) serves to maintain the data voltage supplied to the first thin film transistor (T1) for one frame, and is provided between the gate electrode and the source electrode of the first thin film transistor (T1).

[0145] The organic light emitting diode (OLED) emits predetermined light by the data current supplied from the first thin film transistor (T1).

[0146] As described above, the embodiments of the present invention have been described in more detail with reference to the accompanying drawings. However, the present invention is not necessarily limited to such embodiments, and can be variously modified and implemented without departing from the technical idea of the present invention. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention but to explain it, and the scope of the technical idea of the present invention is not limited by such embodiments. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The protection scope of the present invention should be construed according to the scope of the claims, and all technical ideas within the equivalent scope should be construed as being included in the scope of the rights of the present invention.

Explanation of Reference Numerals

[0147] 100: Substrate 110: Buffer layer 120: Active layer 130: Gate insulating film 140: Gate electrode 150: Interlayer insulating film 161: Source electrode 162: Drain electrode BG: Buffer groove BS: Bottom surface IS: Inclined surface 200: Resist pattern

Claims

1. A substrate, a buffer layer provided on the substrate and having a buffer groove including an inclined surface, an active layer provided on the buffer layer, and a gate electrode provided on the active layer, wherein the active layer is configured to have a step on the buffer groove, and one end of the gate electrode overlaps with the inclined surface provided in the buffer groove, a thin film transistor substrate.

2. The thin film transistor substrate according to claim 1, wherein one end of the gate electrode overlaps with a part of the active layer provided on the inclined surface of the buffer groove.

3. Further comprising a gate insulating film provided between the active layer and the gate electrode, wherein the gate insulating film overlaps with the buffer groove, and one end of the gate insulating film corresponds to one end of the gate electrode, the thin film transistor substrate according to claim 1.

4. Further comprising a gate insulating film provided between the active layer and the gate electrode, wherein the gate insulating film overlaps with the buffer groove, and one end of the gate insulating film is provided between one end of the active layer and one end of the gate electrode, the thin film transistor substrate according to claim 1.

5. The gate insulating film has a first width, the gate electrode has a second width, and the active layer has a first length, wherein the first width of the gate insulating film is larger than the second width of the gate electrode and smaller than the first length of the active layer, the thin film transistor substrate according to claim 4.

6. The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion, wherein the channel portion includes a first region in contact with the bottom surface of the buffer groove and a second region in contact with the inclined surface of the buffer groove, the thin film transistor substrate according to claim 1.

7. The thin film transistor substrate according to claim 6, wherein one end of the second region of the channel portion is located within the inclined surface.

8. The thin film transistor substrate according to claim 6, wherein one end of the second region of the channel portion corresponds to one end of the gate electrode.

9. The thin film transistor substrate according to claim 6, wherein one end of the diffusion portion is located within the inclined surface of the buffer groove.

10. The thin film transistor substrate according to claim 9, wherein the other end of the diffusion portion corresponds to one end of the gate electrode.

11. The thin film transistor substrate according to claim 9, wherein the other end of the diffusion portion is located between one end of the gate electrode and one end of the active layer.

12. The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion. One end of the channel portion is provided on the bottom surface of the buffer groove, and one end of the diffusion portion is provided on the inclined surface. The thin film transistor substrate according to claim 1, wherein one end of the channel portion and one end of the diffusion portion are in contact with each other at the boundary between the bottom surface and the inclined surface of the buffer groove.

13. The buffer groove further includes a bottom surface connected to the inclined surface. The thin film transistor substrate according to claim 1, wherein the angle formed by the bottom surface and the inclined surface is 30 degrees or more and 45 degrees or less.

14. The buffer groove further includes a bottom surface connected to the inclined surface. The thin film transistor substrate according to claim 1, wherein the depth of the bottom surface of the buffer groove is 1.41 μm or more and 2 μm or less.

15. A buffer layer provided on the substrate and having a buffer groove, An active layer provided on the buffer layer, A gate electrode provided on the active layer, The buffer groove includes a bottom surface and an inclined surface connected to the bottom surface, The active layer includes a channel portion, a connection portion provided on one side of the channel portion, and a diffusion portion provided between the channel portion and the connection portion. The thin film transistor substrate, wherein the channel portion overlaps with the bottom surface and the inclined surface, and one end of the channel portion is located on the inclined surface of the buffer groove.

16. The width of the bottom surface of the buffer groove is smaller than the width of the gate electrode. The thin film transistor substrate according to claim 15, wherein the total width of the bottom surface and the inclined surface of the buffer groove is larger than the width of the gate electrode.

17. Further including a gate insulating film provided between the active layer and the gate electrode. The thin film transistor substrate according to claim 15, wherein the entire region of the diffusion portion overlaps with the gate insulating film.

18. The thin film transistor substrate according to claim 15, wherein a part of the diffusion portion does not overlap with the gate electrode.

19. The thin film transistor substrate according to claim 15, wherein one end of the channel portion corresponds to one end of the gate electrode.

20. Including a thin film transistor substrate. The thin film transistor substrate is a substrate, a buffer layer provided on the substrate and having buffer grooves, an active layer provided on the buffer layer, and a gate electrode provided on the active layer, wherein the active layer is configured to have a step on the buffer grooves, and one end of the gate electrode is configured to overlap an inclined surface provided in the buffer grooves.

Images