Universal logic memory block using a plurality of universal logic memory cells

Abstract

To provide a universal logic memory block using a plurality of universal logic memory cells.SOLUTION: A universal logic memory block 500 implements various combinational logical operations in a single structure by combining logical operation results from a plurality of universal logic memory cells 510 using triple-gate silicon elements driven by a positive feedback loop. A switch box 520 determines the directions of input voltage applied to the universal logic memory cells and output voltage outputted from the universal logic memory cells 510. A line switch 530 controls interconnection between the switch box 520 and the universal logic memory cells 510.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] [Cross - Reference to Related Applications] This application claims the benefit of priority based on Korean Patent Application No. 10 - 2023 - 0191706 filed on December 26, 2023, and all the contents disclosed in the document of the Korean patent application are incorporated herein by reference.

[0002] The present invention relates to a general - purpose logic memory block using a plurality of general - purpose logic memory cells. More specifically, the present invention relates to a technology for implementing a general - purpose logic memory block that combines logical operation results in a plurality of general - purpose logic memory cells using triple - gate silicon devices driven by a positive feedback loop to implement various combinational logic operations in a single structure.

Background Art

[0003] In a conventional von Neumann - based computer system, a processor and a memory are separated, and data is transmitted via a bus.

[0004] However, with the increase in computing performance, a bottleneck phenomenon occurs due to the difference in data - processing speeds between the processor and the memory, and it has begun to show limitations in processing large - volume data.

[0005] In other words, the von Neumann - based system, which is a revolutionary development in the semiconductor industry, has improved the integration density and performance of modern computers. However, due to the physical separation between the processor and the memory hierarchy, a lot of energy is consumed, and there are drawbacks such as long data transmission and waiting times.

[0006] Considering the increase in data - intensive applications such as 5G communication standards, the Internet of Things (IoT), and artificial intelligence (AI) after the Fourth Industrial Revolution, a new computing paradigm is essential for large - scale data - processing requirements.

[0007] To solve the above problems, research on logic in memory (LIM) technology that integrates computing and memory functions has been intensifying and accelerating.

[0008] Since logic in memory technology performs the computing function of a processor and the memory function of a memory in the same space, it can reduce the latency and power consumption that occur during data transmission, and can significantly improve the integration level of the system.

[0009] Conventional logic in memory technology has been actively studied based on SRAM (static random access memory) and DRAM (dynamic RAM) corresponding to volatile memory elements, and ReRAM (resistive RAM), MRAM (magnetoresistive RAM), PCRAM (phase-change RAM), etc. corresponding to non-volatile memory elements.

[0010] In the case of logic in memory technology based on volatile memory elements, a large number of transistors are required for stable operation, so there are limitations in terms of large overall area and high power consumption.

[0011] Also, in the case of logic in memory technology based on non-volatile memory elements, a complex process is required because non-silicon materials are used, and it is difficult to be put into practical use due to low device uniformity and stability.

[0012] In addition, the logic in memory technology that has already been studied cannot implement all basic CMOS logic operations in one cell, and individual circuits and wiring are required for logic operations, resulting in low integration.

[0013] Therefore, there is a need to develop a general-purpose logic in memory cell technology that can be fabricated by utilizing silicon-based CMOS processes, perform all basic logic operations in one cell, and store the values.

[0014] Conventional logic memory technologies have been studied in various memories such as DRAM (dynamic random access memory), SRAM (static RAM) which are volatile memory elements, and PRAM (phase-change RAM), ReRAM (resistive RAM), MRAM (magnetoresistive RAM) which are non-volatile memory elements.

[0015] However, since these cannot define n-channel and p-channel, there are difficulties in applying them to existing CMOS logic operations.

[0016] In particular, logic-memory technologies based on non-volatile memory elements generally require new process procedures that are not the silicon-based CMOS process, and it is difficult to put them into practical use due to low device uniformity and reliability.

[0017] Combinatorial logic operations are performed in a structure where basic logic operations are arranged sequentially, and a logic operation circuit with a specific structure is required according to each logic operation, so there are difficulties in improving the integration density.

Summary of the Invention

Problems to be Solved by the Invention

[0018] An object of the present invention is to implement a general-purpose logic memory block that combines the logic operation results in a plurality of general-purpose logic memory cells using triple-gate silicon devices driven by a positive feedback loop, and implements various combinatorial logic operations in a single structure.

[0019] Another object of the present invention is to implement a general-purpose logic memory block that performs combinatorial logic operations for combining logic operation results by utilizing the CMOS process and stores the results of the combinatorial logic operations.

[0020] The present invention embodies a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element applying an existing CMOS process, performs binary combinational logic operations in a general-purpose logic memory block using the general-purpose logic memory cell, and aims to embody a general-purpose logic memory block capable of storing the results of the operations.

[0021] The present invention aims to improve the limitations of processing speed and integration due to the data bottleneck phenomenon through the integration of logical operations and storage functions.

[0022] The present invention aims to embody a general-purpose logic memory block that significantly improves the operation efficiency compared to existing CMOS logic circuits by performing various binary combinational logic operations in a single structure through the channel mode reconfiguration characteristics of the triple-gate silicon element.

[0023] The present invention aims to improve standby power efficiency with excellent memory characteristics that maintain logical operation values without structural changes and external biases by using the channel mode reconfiguration characteristics.

Means for Solving the Problems

[0024] A general-purpose logic memory block according to an embodiment of the present invention includes a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, a switch box that determines the direction of an input voltage applied to the general-purpose logic memory cell and an output voltage output from the general-purpose logic memory cell, and a line switch that controls the interconnection between the switch box and the general-purpose logic memory cell. In a structure in which a plurality of the general-purpose logic memory cells are arranged according to a preset setting, by controlling the interconnection with respect to the logic operation function of the general-purpose logic memory cell according to the determined directions of the input voltage and the output voltage, combinational logic operation functions and memory functions can be performed.

[0025] The general-purpose logic memory cells are arranged in a plurality of rows and a plurality of columns according to the previous settings, the switch box and the line switch are arranged between the general-purpose logic memory cells, and the number of the line switches is determined according to the number of the input voltages transmitted through the switch box, and the combinational logic operation function can be implemented with at least one output based on the output voltage.

[0026] The switch box applies a first input voltage V IN1 and a second input voltage V IN2 to the general-purpose logic memory cells that operate as an XOR gate and the general-purpose logic memory cells that operate as an AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, and outputs the output from the general-purpose logic memory cell that operates as the XOR gate as the sum S, and can control to output the output from the general-purpose logic memory cell that operates as the AND gate as the carry number COUT.

[0027] The switch box applies a first input voltage V IN1 , a second input voltage V IN2 and a third input voltage V CIN to the general-purpose logic memory cells that operate as a first XOR gate and a second XOR gate and the general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, outputs the output from the general-purpose logic memory cell that operates as the second XOR gate as the sum S, and after transmitting the outputs from the general-purpose logic memory cells that operate as the first AND gate and the second AND gate to the input of the general-purpose logic memory cell that operates as an OR gate, can control to output the output voltage as the carry number COUT.

[0028] The switch box applies an input voltage V to general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN Applies a selection voltage V to a general-purpose logic memory cell that operates as a NOT gate among the logic operation functions. S Outputs the output from the general-purpose logic memory cell operating as the first AND gate as a first output OUT1, and can control to output the output from the general-purpose logic memory cell operating as the second AND gate as a second output OUT2.

[0029] The switch box applies a first input voltage V and a second input voltage V to general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN1 And a second input voltage V. IN2 Applies a selection voltage V to a general-purpose logic memory cell that operates as a NOT gate among the logic operation functions. S After transmitting the output from the general-purpose logic memory cell operating as the first AND gate and the output from the general-purpose logic memory cell operating as the second AND gate to the input of a general-purpose logic memory cell that operates as an OR gate, it can control to output the output voltage as an output OUT.

[0030] The switch box applies a first input voltage V and a second input voltage V to general-purpose logic memory cells that operate as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, and to general-purpose logic memory cells that operate as a first NOT gate and a second NOT gate among the logic operation functions. IN1 And a second input voltage V. IN2to selectively apply a first input voltage to the general-purpose logic memory cell operating as the first AND gate to control the output of the general-purpose logic memory cell operating as the second AND gate to control the output of the general-purpose logic memory cell operating as the second AND gate to control the output of the general-purpose logic memory cell operating as the third AND gate to control the output of the general-purpose logic memory cell operating as the fourth AND gate to control the output of the general-purpose logic memory cell operating as the fourth AND gate to control the output of the general-purpose logic memory cell operating as the third output OUT3.

[0031] The switch box applies a second input voltage V to the general-purpose logic memory cells operating as a first OR gate and a second OR gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN2 , the third input voltage V IN3 and the fourth input voltage V IN4 to control the output of the general-purpose logic memory cell operating as the first OR gate as a first output OUT1, and the output of the general-purpose logic memory cell operating as the second OR gate as a second output OUT2.

[0032] The switch box supplies a first input voltage V to the general-purpose logic memory cells operating as an XNOR gate and an XOR gate, the general-purpose logic memory cells operating as a first NOT gate and a second NOT gate, and the general-purpose logic memory cells operating as a first AND gate and a second AND gate, among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns. IN1 and the second input voltage V IN2 to selectively apply a first output OUT1 to the general-purpose logic memory cell operating as the XNOR gate, to control the output of the general-purpose logic memory cell operating as the XOR gate as a second output OUT2, to control the output of the general-purpose logic memory cell operating as the second AND gate as a third output OUT3, and to control the output of the general-purpose logic memory cell operating as the first AND gate as a fourth output OUT4.

[0033] The switch box selectively applies a first input voltage V IN1 to a general-purpose logic memory cell that operates as a first XOR gate and a second XOR gate among the general-purpose logic memory cells arranged in the plurality of rows and columns, applies a second input voltage V IN2 and a third input voltage V IN3 , controls the first input voltage V IN1 as a first output OUT1, controls the output of the general-purpose logic memory cell operating as the first XOR gate as a second output OUT2, and can control the output of the general-purpose logic memory cell operating as the second XOR gate as a third output OUT3.

[0034] The general-purpose logic memory cell includes a first network element and a second network element using a plurality of triple-gate silicon elements. Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region. A supply voltage is applied to the drain region and the source region, and a gate region in which first and second programming gate electrodes and a control gate electrode are formed on the channel region is included. According to the level of the program voltage V PG applied through the first and second programming gate electrodes, the channel region under the first and second programming gate electrodes in the channel region performs one of a first channel mode and a second channel mode. Based on the level of the control voltage V CG applied through the control gate electrode, it is determined to be in one of an on state and an off state. The first network element and the second network element can perform the logic operation function and the memory function according to the level of the output voltage V OUT changed by the one state in the one channel mode performed.

[0035] The first network element and the second network element are composed of a first parallel connection part where a common drain region is connected between a first series connection part in which drain regions and source regions of two out of four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second series connection part in which drain regions and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection part where a common source region is connected. The drain voltage V DD among the common voltages is applied through the first parallel connection part of the first network element, and the source voltage V SS among the common voltages is applied through the second parallel connection part of the second network element. The output voltage V OUT can be measured at a part where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected as any one of them.

[0036] In the triple-gate silicon element, the drain region is in a p-doped state, the source region is in an n-doped state, the channel region is in an intrinsic state, and in the channel region, the channel region under the first and second programming gate electrodes operates as an n-channel corresponding to the first channel mode when the level of the program voltage V PG is at a positive level, and can operate as a p-channel corresponding to the second channel mode when the level of the program voltage V PG is at a negative level.

[0037] When the drain voltage V DD applied to the drain region, the source voltage V SS applied to the source region, the program voltage V PG and the control voltage V CG are applied at zero levels, the memory function can be performed while maintaining the level of the output voltage V OUT .

Advantages of the Invention

[0038] The present invention can implement a general-purpose logic memory block that implements various combinational logic operations in a single structure by combining the logic operation results in a plurality of general-purpose logic memory cells using a triple-gate silicon device driven by a positive feedback loop.

[0039] The present invention can implement a general-purpose logic memory block that performs a combinational logic operation for combining logic operation results by utilizing a CMOS process and stores the result of the combinational logic operation.

[0040] The present invention utilizes a triple-gate silicon device, which is a silicon-based feedback memory device applying an existing CMOS process, to implement a general-purpose logic memory cell, performs a binary combinational logic operation with a general-purpose logic memory block using the general-purpose logic memory cell, and can implement a general-purpose logic memory block capable of storing the result of the operation.

[0041] The present invention can improve the limits of processing speed and integration due to the data bottleneck phenomenon through the fusion of a logic operation and a storage function.

[0042] The present invention can implement a general-purpose logic memory block that significantly improves the operation efficiency compared to an existing CMOS logic circuit by performing various binary combinational logic operations in a single structure through the channel mode reconfiguration characteristic of a triple-gate silicon device.

[0043] The present invention can improve standby power efficiency with excellent memory characteristics that maintain logic operation values without changing the structure and external bias by using the channel mode reconfiguration characteristic.

Brief Description of the Drawings

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[0045] Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings.

[0046] The embodiments and the terms used therein are not intended to limit the technology described in this specification to specific embodiments, but should be understood to include various modifications, equivalents, and / or alternatives of the embodiments.

[0047] In the following description of various embodiments, if it is determined that a detailed description of related known functions or configurations may obscure the gist of the invention, the detailed description thereof will be omitted.

[0048] And the terms described below are terms defined in consideration of the functions in various embodiments, which may vary depending on the intention or convention of the user or operator. Therefore, the definition should be made based on the content throughout this specification.

[0049] In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0050] Singular expressions can include plural expressions unless the context clearly indicates otherwise.

[0051] In this document, expressions such as "A or B" or "at least one of A and / or B" can include all possible combinations of the items listed together.

[0052] Expressions such as "first", "second", "primary", or "secondary" can modify the component without regard to order or importance and are only used to distinguish one component from another, without limiting the component.

[0053] When it is mentioned that a certain (e.g., first) component is "connected (functionally or communicatively)" or "connected" to another (e.g., second) component, the certain component can be directly connected to the other component or can be connected via another component (e.g., a third component).

[0054] In this specification, "(configured to)" can be used interchangeably with, depending on the context, for example, "suitable for", "capable of", "modified to", "made to", "able to", or "designed to" in terms of hardware or software.

[0055] In certain situations, the expression "a device configured to" can mean that the device, together with other devices or components, "is capable of".

[0056] For example, the phrase "a processor configured (or set) to perform A, B, and C" can mean a dedicated processor (e.g., an embedded processor) for performing the operation or a general-purpose processor (e.g., a CPU or an application processor) capable of performing the operation by executing one or more software programs stored in a memory device.

[0057] Also, the term "or" means the inclusive "or" rather than the exclusive "or".

[0058] That is, unless otherwise specified or clear from the context, the expression "x uses a or b" means any one of the natural inclusive permutations.

[0059] As used hereinafter, terms such as "... part" and "[... device]" mean a unit that processes at least one function or operation, which can be embodied in hardware, software, or a combination of hardware and software.

[0060] FIGS. 1A and 1B are diagrams for explaining a triple-gate silicon element that constitutes a general-purpose logic memory cell according to an embodiment of the present invention.

[0061] FIG. 1A illustrates the structure of a triple-gate silicon element that constitutes a general-purpose logic memory cell according to an embodiment of the present invention.

[0062] Referring to FIG. 1A, a triple-gate silicon element 100 according to an embodiment of the present invention includes a drain region 101, a channel region 102, a source region 103, and a gate region. The gate region includes a first and a second programming gate electrode 106 and a control gate electrode 105 formed on a gate insulating film 104.

[0063] As an example, a drain electrode may be connected to the drain region 101 to apply a drain voltage, and a source electrode for applying a source voltage may be connected and formed in the source region 103.

[0064] According to an embodiment of the present invention, the triple-gate silicon element 100 includes a drain region 101, a channel region 102, and a source region 103 that are p-i-n nanostructures.

[0065] As an example, the drain region 101 may be in a p-doped state, the source region 103 may be in an n-doped state, and the channel region 102 may be in an intrinsic state.

[0066] In the channel region 102, the channel region under the first and second programming gate electrodes 106 operates as an n-channel corresponding to the first channel mode when the level of the program voltage V PG is at a positive level, and can operate as a p-channel corresponding to the second channel mode when the level of the program voltage V PG is at a negative level.

[0067] The triple-gate silicon element 100 can be composed of a plurality of elements to form a general-purpose logic memory cell.

[0068] That is, the triple-gate silicon element 100 is composed of a plurality of elements to form a general-purpose logic memory cell, and a part of the plurality of elements can be composed of a first network element and a part can be composed of a second network element.

[0069] The triple-gate silicon element 100, according to the level of the program voltage V PG applied through the first and second programming gate electrodes 106, the channel region under the first and second programming gate electrodes 106 in the channel region can perform any one of the first channel mode and the second channel mode.

[0070] Also, the triple-gate silicon element 100 can be determined to be in either an on state or an off state based on the level of the control voltage V CG applied through the control gate electrode.

[0071] Therefore, the general-purpose logic memory cell can perform a logic operation function and a memory function based on the level of the output voltage V OUT that changes according to any one of the states in any one of the previously performed channel modes.

[0072] For example, since the first and second programming gate electrodes 106 are electrically connected, the same program voltage V is applied at one time.PG can be applied.

[0073] FIG. 1B illustrates a circuit symbol related to the operating state of a general-purpose logic memory cell according to an embodiment of the present invention.

[0074] Referring to FIG. 1B, a circuit symbol 111 according to an embodiment of the present invention illustrates a circuit symbol when the channel region of a triple-gate silicon element operates as an n-channel in the first channel mode.

[0075] As an example, a circuit symbol 110 illustrates a circuit symbol when the channel region of a triple-gate silicon element operates as a p-channel in the second channel mode.

[0076] In circuit symbols 110 and 111, in a nanostructure including a drain region, a channel region, a source region, and a gate region, first and second programming gate electrodes and a control gate electrode are formed in the gate region, a programming gate terminal PG and a control gate terminal CG are connected, a drain electrode is formed in the drain region, a drain terminal D is connected, a source electrode is formed in the source region, and a source terminal S is connected.

[0077] Circuit symbol 111 indicates that the triple-gate silicon element is in the first channel mode state through the channel mode state region.

[0078] In other words, circuit symbol 111 can indicate that the triple-gate silicon element is operating as an n-channel by showing the channel mode state region in a solid form.

[0079] Circuit symbol 110 indicates that the triple-gate silicon element is in the second channel mode state through the channel mode state region.

[0080] The circuit symbol 110 can indicate that the triple-gate silicon device is operating as a p-channel by showing the channel mode state region in an empty form.

[0081] For example, the triple-gate silicon device can be referred to as a triple-gate feedback field-effect device.

[0082] FIGS. 2A to 2C are diagrams for explaining the operating principle of a triple-gate silicon device according to an embodiment of the present invention.

[0083] FIG. 2A illustrates the operating principle when the triple-gate silicon device according to an embodiment of the present invention operates as a p-channel.

[0084] Referring to FIG. 2A, when a positive voltage is applied to the triple-gate silicon device 200 according to an embodiment of the present invention via the drain terminal and a negative voltage corresponding to a negative level of the program voltage is applied from the programming gate terminal, the channel region under the programming gate electrode PG in the channel region is programmed as a p-channel and operates as a p-channel.

[0085] When the triple-gate silicon device 200 according to an embodiment of the present invention operates as a p-channel, the operating state is determined to be on when the level of the control voltage applied via the control gate terminal is lower than the latch-up voltage which is the voltage when the current rapidly increases, and is determined to be off when the level of the applied control voltage is higher than the latch-up voltage.

[0086] As an example, the triple-gate silicon device is determined to be in an on state or an off state based on the level of the control voltage applied via the control gate terminal.

[0087] The on and off operating states of the triple-gate silicon device can be additionally explained through the energy band 201 corresponding to the off state and the energy band 202 corresponding to the on state.

[0088] When the triple-gate silicon device according to an embodiment of the present invention operates as a p-channel, the energy band 202 when in the on state and the energy band 201 when in the off state can be confirmed based on the level of the control voltage.

[0089] According to the energy band 201 and the energy band 202, when the channel regions under the first and second programming gate electrodes in the channel region perform the second channel mode corresponding to the p-channel mode, when the level of the control voltage V CG decreases to a level lower than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the first programming gate electrode adjacent to the drain region in the channel region becomes low, and a second positive feedback loop in which holes are injected from the drain region due to the lowered potential barrier is generated, resulting in an on state in which current flows.

[0090] That is, the triple-gate silicon device can switch from the energy band 201 to the energy band 202 when the second positive feedback loop occurs.

[0091] It can be confirmed that the injection and accumulation of charges are repeated, a positive feedback loop is generated, and the device switches to the on state in which current flows.

[0092] For example, the second positive feedback loop can be a positive feedback loop in which holes become the majority carriers in the channel region.

[0093] Figure 2B illustrates the operating principle when the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel.

[0094] Referring to Figure 2B, when a negative voltage is applied to the triple-gate silicon device 210 according to an embodiment of the present invention via the source terminal and a positive voltage corresponding to the positive level of the program voltage is applied from the programming gate terminal, the channel region under the programming gate electrode PG in the channel region is programmed as an n-channel and operates as an n-channel.

[0095] As an example, the triple-gate silicon device is determined to be in an on state or an off state based on the level of the control voltage applied via the control gate terminal.

[0096] When the triple-gate silicon device 210 according to an embodiment of the present invention operates as an n-channel, the operating state is determined to be in an on state when the level of the control voltage applied via the control gate terminal is higher than the latch-up voltage, which is the voltage when the current rapidly increases, and is determined to be in an off state when the level is lower than the latch-up voltage.

[0097] When the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel, the energy band 211 when it is in an off state is illustrated based on the level of the control voltage, and the energy band 212 when it is in an on state is illustrated.

[0098] Referring to the energy band 211 and the energy band 212, when the channel regions under the first and second programming gate electrodes in the channel region perform the first channel mode corresponding to the n-channel mode, the control voltage V CGWhen the level of [[ID=]] increases to a level higher than the latch-up voltage, the height of the potential barrier between the channel region under the control gate electrode and the channel region under the second programming gate electrode adjacent to the source region in the channel region decreases. Due to the decreased potential barrier, a first positive feedback loop is generated where electrons are injected from the source region, resulting in an on state where current flows.

[0099] That is, in the triple-gate silicon device, a first positive feedback loop occurs, causing a switch from energy band 201 to energy band 202.

[0100] It can be confirmed that the injection and accumulation of charges are repeated, a positive feedback loop is generated, and the device switches to an on state where current flows.

[0101] For example, the first positive feedback loop can be a positive feedback loop in which electrons become majority carriers in the channel region.

[0102] FIG. 2C illustrates the operations related to the first and second positive feedback loops when the triple-gate silicon device according to an embodiment of the present invention operates as an n-channel and a p-channel.

[0103] Referring to FIG. 2C, graph 220 shows the operating characteristics of the triple-gate silicon device in the n-channel mode, and graph 221 shows the operating characteristics of the triple-gate silicon device in the p-channel mode.

[0104] Graph 220 shows that when a triple-gate silicon device operating in n-channel mode has on and off states according to the voltage applied to the control gate electrode, if the control gate voltage is lower than the latch-up voltage, which is the voltage at which the current rapidly increases, the flow of electrons and holes is blocked by the potential barrier and it has an off state. And when the control gate voltage increases and becomes higher than the latch-up voltage, electrons in the source region cross the potential barrier and are injected into the channel, accumulated in the potential well adjacent to the drain region, indicating that the height of the potential barrier decreases.

[0105] Thereby, holes in the drain region are injected into the channel, accumulated in the potential well adjacent to the source region, and the height of the potential barrier decreases.

[0106] The injection and accumulation of charges are repeated to generate a positive feedback loop, resulting in an on state where current flows.

[0107] Graph 221 shows that in the case of a triple-gate silicon device operating in p-channel mode, when the control gate voltage is higher than the latch-up voltage, the flow of electrons and holes is blocked by the potential barrier and it is in an off state. When the control gate voltage decreases and becomes lower than the latch-up voltage, holes in the drain region cross the potential barrier and are injected into the channel, accumulated in the potential well adjacent to the source region, indicating the characteristic that the height of the potential barrier decreases.

[0108] According to an embodiment of the present invention, the triple-gate silicon device can be an element in which a first positive feedback loop or a second positive feedback loop is formed according to the level of the control voltage applied to the gate region, and at the same time, the on or off state is variably controlled in the first channel mode and the second channel mode. Here, the first channel mode is the n-channel mode, and the second channel mode is the p-channel mode.

[0109] In addition, the triple-gate silicon device is turned on while charge carriers are accumulated in the potential well of the channel region to form a positive feedback loop, which can be utilized as a memory function for storing data in the channel region.

[0110] Therefore, the present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon device, which is a silicon-based feedback memory device applying an existing CMOS process.

[0111] FIG. 3 is a diagram for explaining a general-purpose logic memory cell according to an embodiment of the present invention.

[0112] FIG. 3 illustrates a circuit diagram of a general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon devices according to an embodiment of the present invention.

[0113] Referring to FIG. 3, a general-purpose logic memory cell 300 according to an embodiment of the present invention includes a first network element 310 and a second network element 311, and the first network element 310 and the second network element 311 are composed of a plurality of triple-gate silicon devices 301.

[0114] More specifically, the first network element 310 and the second network element 311 include a first series connection portion in which the drain regions and source regions of two of the four triple-gate silicon devices are connected in series, and a common drain region between the first series connection portion and a second series connection portion in which the drain regions and source regions of the remaining two triple-gate silicon devices are connected in series, and a first parallel connection portion to which the common drain region is connected, and a second parallel connection portion to which the common source region is connected.

[0115] The first network element 310 can be referred to as a pull-up network element, and the second network element 311 can be referred to as a pull-down network element.

[0116] According to an embodiment of the present invention, the general-purpose logic memory cell 300 controls the supply voltage, the voltage corresponding to the voltage applied via the program gate electrode, and the input voltage applied via the control gate electrode to “0” to perform a memory function of maintaining the already set voltage state.

[0117] According to an embodiment of the present invention, each of the first network element 310 and the second network element 311 is composed of four triple-gate silicon elements, and can be referred to as being divided into two triple-gate silicon elements as the upper side, the lower side, the left side, and the right side, or can be referred to as being divided into one triple-gate silicon element as the upper left side, the upper right side, the lower left side, and the lower right side.

[0118] The triple-gate silicon elements arranged at each position can be selectively driven in either the first channel mode or the second channel mode.

[0119] The above-described configuration can be changed according to the arrangement of the network elements, and may be differently referred to depending on the changed connection configuration.

[0120] The first network element 310 has a drain voltage V among the common voltages applied via the first parallel connection portion of the first network element 310. DD is applied.

[0121] The second network element 311 has a source voltage V among the common voltages applied via the second parallel connection portion of the second network element 311. SS is applied.

[0122] The output voltage V can be measured at the portion where the second parallel connection portion of the first network element 310 and the first parallel connection portion of the second network element 311 are connected in the general-purpose logic memory cell 300 according to an embodiment of the present invention. OUT is measured.

[0123] The general-purpose logic memory cell 300 is composed of a first network element 310 and a second network element 311, and the drain voltage V DD and the source voltage V SS are used to implement a logical operation based on the content measured by the output voltage V OUT .

[0124] The general-purpose logic memory cell 300 according to an embodiment of the present invention uses a plurality of triple-gate silicon elements.

[0125] Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region, and a supply voltage is applied to the drain region and the source region, and a gate region is formed on the channel region with first and second programming gate electrodes and a control gate electrode formed thereon.

[0126] In addition, each of the plurality of triple-gate silicon elements, according to the level of the program voltage V PG applied through the first and second programming gate electrodes, the channel region under the first and second programming gate electrodes in the channel region operates in one of the first channel mode and the second channel mode, and based on the level of the control voltage V CG applied through the control gate electrode, it can be determined to be in either an on state or an off state.

[0127] The first network element 310 and the second network element 311 can perform a logical operation function and a memory function according to any one of the states already determined in any one of the already performed channel modes.

[0128] The logical operation function is a logical operation function related to NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates.

[0129] Therefore, the present invention can implement a general-purpose logic memory cell that provides a logic operation function and a memory function by using a triple-gate silicon device driven by a positive feedback loop.

[0130] In addition, the present invention can implement a general-purpose logic memory cell that performs all basic logic operations in a single structure using a triple-gate silicon device and stores the operation results.

[0131] FIG. 4A is a diagram for explaining the operation of the NOT gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0132] FIG. 4A illustrates a circuit diagram and a timing diagram in the operation of the NOT gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0133] Referring to FIG. 4A, in the general-purpose logic memory cell 400 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon device constituting the first network element performs the second channel mode, and the triple-gate silicon device constituting the second network element performs the first channel mode.

[0134] At this time, when the level of the control voltage V CG which is the input voltage IN applied through the control gate terminal CG is a negative level, the level of the output voltage V OUT measured through the output terminal is a positive level, and when the level of the control voltage V CG is a positive level, the general-purpose logic memory cell 400 can perform a logic operation function corresponding to the operation of the NOT gate in which the level of the output voltage V OUT is a negative level.

[0135] In the timing diagram 401, when the negative-level input voltage V IN corresponding to "0" is applied, the positive-level output voltage V OUTillustrates that it is logically operated and output.

[0136] Also, the timing diagram 401 illustrates that when a positive-level input voltage V corresponding to "1" is applied, a negative-level output voltage V corresponding to "0" is logically operated and output. IN is applied, a negative-level output voltage V corresponding to "0" OUT illustrates that it is logically operated and output.

[0137] Also, it shows that when the supply voltage V, program voltage V, and input voltage V are removed, it performs a memory function of maintaining (holding) the calculated logical value. SUP , program voltage V PG , input voltage V IN is removed, it performs a memory function of maintaining (holding) the calculated logical value.

[0138] For example, the supply voltage V is composed of the drain voltage V and the source voltage V, and the program voltage V is composed of the program voltage V corresponding to the n-channel and the program voltage V corresponding to the p-channel. SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V corresponding to the n-channel PG N , and the program voltage V corresponding to the p-channel PG P is composed.

[0139] Also, the general-purpose logic memory cell, based on the programming voltage applied through the programming gate terminal PG, has the triple-gate silicon element constituting the first network element operating in the first channel mode, the triple-gate silicon element constituting the second network element operating in the second channel mode, and when the level of the control voltage V which is the input voltage IN applied through the control gate terminal CG is at a positive level, the level of the output voltage V measured through the output terminal is at a positive level, and when the level of the control voltage V is at a negative level, it can perform a logical operation function corresponding to the operation of the YES gate where the level of the output voltage V is at a negative level. CG is at a positive level, the level of the output voltage V measured through the output terminal OUT is at a positive level, and when the level of the control voltage V CG is at a negative level, the level of the output voltage V OUT is at a negative level, it can perform a logical operation function corresponding to the operation of the YES gate.

[0140] Figure 4B is a diagram for explaining the operation of the AND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0141] Figure 4B illustrates a circuit diagram and a timing diagram in the operation of the AND gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0142] Referring to Figure 4B, in the general-purpose logic memory cell 410 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element operates in the first channel mode, and the triple-gate silicon element constituting the second network element operates in the second channel mode.

[0143] Also, in the general-purpose logic memory cell 410, among the control voltages V CG the first control voltage IN1 is applied to the upper side of the first network element and the left side of the second network element, and among the control voltages V CG the second control voltage IN2 is applied to the lower side of the first network element and the right side of the second network element.

[0144] Thereby, when either one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is a negative level, the general-purpose logic memory cell 410 performs a logical operation to determine the level of the output voltage V OUT as a negative level.

[0145] Also, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are positive levels, the general-purpose logic memory cell 410 performs the operation of an AND gate to determine the level of the output voltage V OUT as a positive level.

[0146] The timing diagram 411 shows two input voltages V IN1 , V IN2When inputs corresponding to "00", "01", "10", and "11" are applied, the output voltage V OUT performs a binary logic operation function by calculating values corresponding to "0", "0", "0", and "1".

[0147] Also, when the supply voltage V SUP , the program voltage V PG , the input voltage V IN1 , V IN2 are removed, it performs a memory function of maintaining (holding) the calculated logical value.

[0148] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0149] Figure 4C is a diagram for explaining the operation of the OR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0150] Figure 4C illustrates a circuit diagram and a timing diagram in the operation of the OR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0151] Referring to Figure 4C, in the general-purpose logic memory cell 420 according to an embodiment of the present invention, based on the programming voltage applied through the programming gate terminal PG, the triple-gate silicon element constituting the first network element performs the first channel mode, and the triple-gate silicon element constituting the second network element performs the second channel mode.

[0152] Also, the general-purpose logic memory cell 420 has a control voltage V CGAmong them, the first control voltage IN1 is applied to the left side of the first network element and the upper side of the second network element, and the control voltage V CG Among them, the second control voltage IN2 is applied to the right side of the first network element and the lower side of the second network element.

[0153] As a result, when any one of the levels of the first control voltage V IN1 and the second control voltage V IN2 is a positive level, the level of the output voltage V OUT is determined to be a positive level.

[0154] Also, when both levels of the first control voltage V IN1 and the second control voltage V IN2 are negative levels, the level of the output voltage V OUT is determined to be a negative level.

[0155] The timing diagram 421 shows that for two input voltages V IN1 , V IN2 , when inputs corresponding to "00", "01", "10", and "11" are applied, the values corresponding to "0", "1", "1", and "1" are calculated at the output voltage V OUT , indicating that a binary logic operation function is performed.

[0156] Also, it shows that when the supply voltage V SUP , the program voltage V PG , the input voltages V IN1 , V IN2 are removed, a memory function of maintaining (holding) the calculated logical value is performed.

[0157] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is the program voltage V PG Nand the program voltage V corresponding to the p-channel PG P It is composed of

[0158] FIG. 4D is a diagram for explaining the operation of the XNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0159] FIG. 4D illustrates a circuit diagram and a timing diagram in the operation of the XNOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0160] Referring to FIG. 4D, in the general-purpose logic memory cell 430 according to an embodiment of the present invention, the left side of the triple-gate silicon element constituting the first network element performs the first channel mode, the right side performs the second channel mode, and among the triple-gate silicon elements constituting the second network element, the upper left side performs the second channel mode, the upper right side performs the first channel mode, the lower left side performs the first channel mode, and the lower right side performs the second channel mode.

[0161] The general-purpose logic memory cell 430 according to an embodiment of the present invention has a control voltage V CG Among them, the first control voltage V IN1 Is applied to the upper sides of the first network element and the second network element, and the control voltage V CG Among them, the second control voltage V IN2 Is applied to the lower sides of the first network element and the second network element.

[0162] According to an embodiment of the present invention, when the levels of the first control voltage V IN1 And the second control voltage V IN2 Are the same level as each other, the level of the output voltage V OUT Is output as a positive level, and when the levels of the first control voltage V IN1 And the second control voltage V IN2 Are different levels from each other, the output voltage V OUTIt is possible to perform an XNOR logic operation function that determines the level of [[ID=]] as a negative level.

[0163] Timing diagram 431 shows that when inputs corresponding to "00", "01", "10", and "11" are applied to two input voltages V IN1 , V IN2 , the output voltage V OUT performs a binary logic operation function by calculating values corresponding to "1", "0", "0", and "1".

[0164] Also, it shows that a memory function is performed to maintain (Hold) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , and the input voltages V IN1 , V IN2 are removed.

[0165] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0166] Figure 4E is a diagram for explaining the operation of the XOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0167] Figure 4E illustrates a circuit diagram and a timing diagram in the operation of the XOR gate of the general-purpose logic memory cell according to an embodiment of the present invention.

[0168] Referring to FIG. 4E, in a general-purpose logic memory cell 440 according to an embodiment of the present invention, among the triple-gate silicon elements constituting the first network element, the upper left side performs the second channel mode, the upper right side performs the first channel mode, the lower left side performs the first channel mode, the lower right side performs the second channel mode, among the triple-gate silicon elements constituting the second network element, the left side performs the first channel mode, and the right side performs the second channel mode.

[0169] A general-purpose logic memory cell 440 according to an embodiment of the present invention has a control voltage V CG Among them, the first control voltage V IN1 Is applied to the upper sides of the first network element and the second network element, and the control voltage V CG Among them, the second control voltage V IN2 Is applied to the lower sides of the first network element and the second network element.

[0170] As an example, when both the levels of the first control voltage V IN1 And the second control voltage V IN2 Are positive levels or both are negative levels, the level of the output voltage V OUT Is determined to be a negative level.

[0171] Also, when the levels of the first control voltage V IN1 And the second control voltage V IN2 Are different from each other, the level of the output voltage V OUT Is output as a positive level.

[0172] The timing diagram 441 shows that for two input voltages V IN1 , V IN2 , when inputs corresponding to "00", "01", "10", and "11" are applied, values corresponding to "0", "1", "1", and "0" are calculated by the output voltage V OUT , indicating that a binary logic operation function is performed.

[0173] Also, it indicates that it performs a memory function of maintaining (holding) the calculated logical value even when the supply voltage V SUP , the program voltage V PG , the input voltage V IN1 , V IN2 are removed.

[0174] For example, the supply voltage V SUP is composed of the drain voltage V DD and the source voltage V SS , and the program voltage V PG is composed of the program voltage V PG N corresponding to the n-channel, and the program voltage V PG P corresponding to the p-channel.

[0175] Therefore, the present invention can improve the limits of processing speed and integration due to the data bottleneck phenomenon through the integration of logical operation and storage function.

[0176] Also, the present invention can improve the standby power efficiency with excellent memory characteristics of maintaining the logical operation value without changing the structure and external bias by using the channel type variable characteristic.

[0177] FIG. 5 is a diagram for explaining a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to an embodiment of the present invention.

[0178] FIG. 5 illustrates the components of a general-purpose logic memory block using a plurality of general-purpose logic memory cells according to an embodiment of the present invention.

[0179] Referring to FIG. 5, according to an embodiment of the present invention, a general-purpose logic memory block 500 includes general-purpose logic memory cells 510 including a first network element and a second network element using a plurality of triple-gate silicon elements, and is implemented by using a plurality of these.

[0180] As an example, the switch box 520 can determine the direction of the input voltage applied to the general-purpose logic memory cell and the output voltage output from the general-purpose logic memory cell 510.

[0181] The line switch 530 according to an embodiment of the present invention controls the interconnection between the switch box 520 and the general-purpose logic memory cell 510.

[0182] According to an embodiment of the present invention, the general-purpose logic memory block 500 controls the interconnection with respect to the logic operation function of the general-purpose logic memory cell 510 according to the determined input voltage and output voltage directions in a structure in which a plurality of general-purpose logic memory cells 510 are arranged according to a preset, and can perform a combinational logic operation function and a memory function.

[0183] As an example, in the general-purpose logic memory block 500, the general-purpose logic memory cells 510 are arranged in a plurality of rows and a plurality of columns according to a preset, and a switch box 520 and a line switch 530 are arranged between the general-purpose logic memory cells 510.

[0184] The number of line switches 530 is determined so as to correspond to the number of input voltages transmitted through the switch box 520, and the general-purpose logic memory block 500 implements a combinational logic operation function with at least one output based on the output voltage.

[0185] The general-purpose logic memory block 500 can implement various combinational logic operation functions with a single structure by selectively implementing a binary logic operation function in the general-purpose logic memory cell 510.

[0186] The combinational logic operation function is implemented through a combination of logic operation functions related to NOT, YES, NAND, NOR, AND, OR, XNOR, and XOR gates based on the binary logic operation function.

[0187] The combinational logic operation function can include operations such as those of a half adder, a full adder, a demultiplexer, a multiplexer, an encoder, a bit comparator, and a bit binary to gray code converter.

[0188] The general-purpose logic memory block 500 can embody not only the above-described combinational logic operation function but also various combinations of logical operations in a single structure.

[0189] Combinational logic operations are performed in a structure where basic logic operations are sequentially arranged, designed in a structure that enables interconnection between the input and output ports of each cell. When an input voltage is applied, various combinational logic operations are performed according to the type and connection method of the logic gates of each cell, and the operation results can be stored.

[0190] Therefore, the present invention can implement a general-purpose logic memory cell by utilizing a triple-gate silicon element, which is a silicon-based feedback memory element applying an existing CMOS process, and perform binary combinational logic operations with a general-purpose logic memory block using the general-purpose logic memory cell, and implement a general-purpose logic memory block capable of storing the operation results.

[0191] FIG. 6 and FIG. 7 are diagrams for explaining the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0192] FIG. 6 illustrates a structure related to the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0193] Referring to FIG. 6, a general-purpose logic memory block 600 according to an embodiment of the present invention implements the operation of a half adder based on the control of a switch box 620 and a line switch 630 for a general-purpose logic memory cell 610 operating as an XOR gate and a general-purpose logic memory cell 611 operating as an AND gate.

[0194] The switch box 620 applies a first input voltage V IN1 and a second input voltage V IN2 to the general-purpose logic memory cell 610 operating as an XOR gate and the general-purpose logic memory cell 611 operating as an AND gate among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns.

[0195] Also, the switch box 620 controls to output the output from the general-purpose logic memory cell 610 operating as an XOR gate as the sum S and the output from the general-purpose logic memory cell 611 operating as an AND gate as the carry Cout.

[0196] FIG. 7 illustrates a timing diagram related to the operation of a half adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0197] Referring to FIG. 7, a timing diagram 700 according to an embodiment of the present invention shows the operation of a half adder of a general-purpose logic memory block that derives operation results as the sum S and the carry Cout for the first input voltage V IN1 and the second input voltage V IN2 .

[0198] The general-purpose logic memory block 600 outputs a logic operation value corresponding to a half adder by distributing input / output voltages and performs a memory function of maintaining the operation result even when all voltages are removed.

[0199] FIGS. 8 and 9 are diagrams for explaining the operation of a full adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0200] FIG. 8 illustrates a structure related to the operation of a full adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0201] Referring to FIG. 8, a general-purpose logic memory block 800 according to an embodiment of the present invention implements the operation of a full adder based on the control of a switch box 820 and a line switch 830 for general-purpose logic memory cells operating as a first XOR gate 810 and a second XOR gate 811, general-purpose logic memory cells operating as a first AND gate 812 and a second AND gate 813, and a general-purpose logic memory cell operating as an OR gate 814.

[0202] As an example, the switch box 820 applies a first input voltage V IN1 , a second input voltage V IN2 , and a third input voltage V CIN to general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns, among which are general-purpose logic memory cells operating as the first XOR gate 810 and the second XOR gate 811 of the logical operation functions, and general-purpose logic memory cells operating as the first AND gate 812 and the second AND gate 813.

[0203] Also, the switch box 820 outputs the output from the general-purpose logic memory cell operating as the second XOR gate 811 as the sum S, and after transmitting the outputs from the general-purpose logic memory cells operating as the first AND gate 812 and the second AND gate 813 to the input of the general-purpose logic memory cell operating as the OR gate 814, controls to output the output voltage as the carry Cout.

[0204] FIG. 9 illustrates a timing diagram related to the operation of a full adder of a general-purpose logic memory block according to an embodiment of the present invention.

[0205] Referring to FIG. 9, a timing diagram 900 according to an embodiment of the present invention includes a first input voltage V IN1 , a second input voltage V IN2 , and a third input voltage VCIN Shows the operation of a full adder of a general-purpose logic memory block that derives operation results as sum S and carry number COUT with respect to

[0206] The general-purpose logic memory block 800 outputs a logical operation value corresponding to a full adder by distributing input / output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0207] Figures 10 and 11 are diagrams for explaining the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0208] Figure 10 illustrates a structure related to the operation of a demultiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0209] Referring to Figure 10, a general-purpose logic memory block 1000 according to an embodiment of the present invention implements the operation of a demultiplexer based on the control of a switch box 1020 and a line switch 1030 for a general-purpose logic memory cell operating as a first AND gate 1011 and a second AND gate 1012, and a general-purpose logic memory cell operating as a NOT gate 1010.

[0210] As an example, the switch box 1020 applies an input voltage V to a general-purpose logic memory cell operating as a first AND gate 1011 and a second AND gate 1012 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. IN to apply.

[0211] Also, the switch box 1020 applies a selection voltage V to a general-purpose logic memory cell operating as a NOT gate 1010 among the logical operation functions. S to apply.

[0212] As a result, the switch box 1020 controls to output, as the first output OUT1, the output from the general-purpose logic memory cell operating as the first AND gate 1011, and to output, as the second output OUT2, the output from the general-purpose logic memory cell operating as the second AND gate 1012.

[0213] FIG. 11 illustrates a timing diagram related to the operation of the demultiplexer of the general-purpose logic memory block according to an embodiment of the present invention.

[0214] Referring to FIG. 11, a timing diagram 1100 according to an embodiment of the present invention shows the operation of the demultiplexer according to the order of outputting as the first output OUT1 and the second output OUT2 with respect to the input voltage V IN and the selection voltage V S .

[0215] The general-purpose logic memory block 1000 outputs a logical operation value corresponding to the demultiplexer by distributing the input / output voltage, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0216] FIGS. 12 and 13 are diagrams for explaining the operation of the multiplexer of the general-purpose logic memory block according to an embodiment of the present invention.

[0217] FIG. 12 illustrates a structure related to the operation of the 2*1 multiplexer of the general-purpose logic memory block according to an embodiment of the present invention.

[0218] Referring to FIG. 12, a general-purpose logic memory block 1200 according to an embodiment of the present invention implements the operation of the 2*1 multiplexer based on the control of the switch box 1220 and the line switch 1230 for the general-purpose logic memory cells operating as the first AND gate 1211 and the second AND gate 1212, the general-purpose logic memory cell operating as the NOT gate 1210, and the general-purpose logic memory cell operating as the OR gate 1213.

[0219] As an example, the switch box 1220 applies a first input voltage V IN1 and a second input voltage V IN2 to general-purpose logic memory cells that operate as a first AND gate 1211 and a second AND gate 1212 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns.

[0220] The switch box 1220 according to an embodiment of the present invention applies a selection voltage V S to a general-purpose logic memory cell that operates as a NOT gate 1210 among the logic operation functions.

[0221] As an example, the switch box 1220 can control to transmit the output from the general-purpose logic memory cell operating as the first AND gate 1211 and the output from the general-purpose logic memory cell operating as the second AND gate 1212 to the input of the general-purpose logic memory cell operating as an OR gate 1213, and then output the output voltage as the output OUT.

[0222] FIG. 13 illustrates a timing diagram related to the operation of a 2*1 multiplexer of a general-purpose logic memory block according to an embodiment of the present invention.

[0223] Referring to FIG. 13, a timing diagram 1300 according to an embodiment of the present invention shows the operation of the multiplexer according to the order of output as the output OUT with respect to the first input voltage V IN1 , the second input voltage V IN2 and the selection voltage V S .

[0224] The general-purpose logic memory block 1200 outputs a logic operation value corresponding to a 2*1 multiplexer by distributing input / output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0225] FIGS. 14 and 15 are diagrams for explaining the operation of a decoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0226] FIG. 14 illustrates a structure related to the operation of a decoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0227] Referring to FIG. 14, a general-purpose logic memory block 1400 according to an embodiment of the present invention implements the operation of a 2*4 decoder based on the control of a switch box 1420 and a line switch 1430 for general-purpose logic memory cells operating as a first NOT gate 1410 and a second NOT gate 1411, and general-purpose logic memory cells operating as a first AND gate 1412, a second AND gate 1413, a third AND gate 1414, and a fourth AND gate 1415.

[0228] As an example, the switch box 1420 selectively applies a first input voltage V IN1 and a second input voltage V IN2 to general-purpose logic memory cells operating as a first AND gate 1412, a second AND gate 1413, a third AND gate 1414, and a fourth AND gate 1415 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns, and general-purpose logic memory cells operating as a first NOT gate 1410 and a second NOT gate 1411 among the logic operation functions.

[0229] The switch box 1420 controls the output of the general-purpose logic memory cell operating as the first AND gate 1412 as the first output OUT1, controls the output of the general-purpose logic memory cell operating as the second AND gate 1413 as the second output OUT2, controls the output of the general-purpose logic memory cell operating as the third AND gate 1414 as the fourth output OUT4, and controls the output of the general-purpose logic memory cell operating as the fourth AND gate 1415 as the third output OUT3.

[0230] FIG. 15 illustrates a timing diagram related to the operation of a decoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0231] Referring to FIG. 15, a timing diagram 1500 according to an embodiment of the present invention is a first input voltage VIN1 and the second input voltage V IN2 shows the operation of the decoder in the order of outputting as the first output OUT1, the second output OUT2, the third output OUT3, and the fourth output OUT4 with respect to

[0232] The general-purpose logic memory block outputs a logical operation value corresponding to a 2*4 decoder by distributing input and output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0233] FIGS. 16 and 17 are diagrams for explaining the operation of an encoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0234] FIG. 16 illustrates a structure related to the operation of an encoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0235] Referring to FIG. 16, a general-purpose logic memory block 1600 according to an embodiment of the present invention implements the operation of the encoder based on the control of a switch box 1620 and a line switch 1630 for general-purpose logic memory cells operating as a first OR gate 1610 and a second OR gate 1611.

[0236] As an example, the switch box 1620 applies the second input voltage V IN2 , the third input voltage V IN3 , and the fourth input voltage V IN4 to the general-purpose logic memory cells operating as the first OR gate 1610 and the second OR gate 1611 among the general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns. Here, the first input voltage V IN1 is not applied to the general-purpose logic memory cells.

[0237] The switch box 1620 controls the output of the general-purpose logic memory cell operating as the first OR gate 1610 as the first output OUT1, and controls the output of the general-purpose logic memory cell operating as the second OR gate 1611 as the second output OUT2.

[0238] Figure 17 illustrates a timing diagram related to the operation of an encoder of a general-purpose logic memory block according to an embodiment of the present invention.

[0239] Referring to Figure 17, a timing diagram 1700 according to an embodiment of the present invention shows the operation of an encoder in the order of outputting a first output OUT1 and a second output OUT2 with respect to a first input voltage V IN1 , a second input voltage V IN2 , a third input voltage V IN3 and a fourth input voltage V IN4 .

[0240] The general-purpose logic memory block outputs a logical operation value corresponding to a 4*2 encoder by distributing input / output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0241] Figures 18 and 19 are diagrams for explaining the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention.

[0242] Figure 18 illustrates a structure related to the operation of a bit comparator of a general-purpose logic memory block according to an embodiment of the present invention.

[0243] Referring to Figure 18, a general-purpose logic memory block 1800 according to an embodiment of the present invention implements the operation of a bit comparator based on the control of a switch box 1820 and a line switch 1830 for general-purpose logic memory cells operating as an XNOR gate 1810 and an XOR gate 1811, general-purpose logic memory cells operating as a first NOT gate 1812 and a second NOT gate 1813, and general-purpose logic memory cells operating as a first AND gate 1814 and a second AND gate 1815.

[0244] As an example, the switch box 1820 includes general-purpose logic memory cells arranged in a plurality of rows and columns. Among them, the general-purpose logic memory cells operating as XNOR gates 1810 and XOR gates 1811, the general-purpose logic memory cells operating as the first NOT gate 1812 and the second NOT gate 1813, and the general-purpose logic memory cells operating as the first AND gate 1814 and the second AND gate 1815 are selectively applied with the first input voltage V IN1 and the second input voltage V IN2 .

[0245] In addition, the switch box 1820 controls the output of the general-purpose logic memory cell operating as the XNOR gate 1810 as the first output OUT1, controls the output of the general-purpose logic memory cell operating as the XOR gate 1811 as the second output OUT2, controls the output of the general-purpose logic memory cell operating as the second AND gate 1815 as the third output OUT3, and controls the output of the general-purpose logic memory cell operating as the first AND gate 1814 as the fourth output OUT4.

[0246] FIG. 19 illustrates a timing diagram related to the operation of the bit comparator of the general-purpose logic memory block according to an embodiment of the present invention.

[0247] Referring to FIG. 19, the timing diagram 1900 according to an embodiment of the present invention shows the operation of the bit comparator according to the order of outputting to the first output OUT1 to the fourth output OUT4 with respect to the first input voltage V IN1 and the second input voltage V IN2 .

[0248] The general-purpose logic memory block outputs a logical operation value corresponding to the bit comparator by distributing the input / output voltage, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0249] Figures 20 and 21 are diagrams for explaining the operation of a bit binary to gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0250] Figure 20 illustrates a structure related to the operation of a bit binary to gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0251] Referring to Figure 20, a general-purpose logic memory block 2000 according to an embodiment of the present invention implements the operation of a bit binary to gray code converter based on the control of a switch box 2020 and a line switch 2030 for a first XOR gate 2010 and a second XOR gate 2011.

[0252] As an example, the switch box 2020 selectively applies a first input voltage V IN1 , a second input voltage V IN2 and a third input voltage V IN3 to general-purpose logic memory cells operating as the first XOR gate 2010 and the second XOR gate 2011 among general-purpose logic memory cells arranged in a plurality of rows and a plurality of columns.

[0253] Accordingly, the switch box 2020 controls the first input voltage V IN1 as a first output OUT1, controls the output of a general-purpose logic memory cell operating as the first XOR gate 2010 as a second output OUT2, and controls the output of a general-purpose logic memory cell operating as the second XOR gate 2011 as a third output OUT3.

[0254] Figure 21 illustrates a timing diagram related to the operation of a bit binary to gray code converter of a general-purpose logic memory block according to an embodiment of the present invention.

[0255] Referring to Figure 21, a timing diagram 2100 according to an embodiment of the present invention includes a first input voltage V IN1 to a third input voltage V IN3Shows the operation of a bit binary-Gray code converter according to the order of output as the first output OUT1 to the third output OUT3.

[0256] The general-purpose logic memory block outputs a logical operation value corresponding to a bit binary-Gray code converter by distributing input and output voltages, and performs a memory function of maintaining the operation result even when all voltages are removed.

[0257] Therefore, the present invention combines logical operation results in a plurality of general-purpose logic memory cells using triple-gate silicon elements driven by a positive feedback loop, and can implement a general-purpose logic memory block that implements various combinational logical operations in a single structure.

[0258] In the specific embodiments described above, the components included in the invention are represented as singular or plural by the presented specific embodiments.

[0259] However, the singular or plural expressions are selected to suit the situation presented for the convenience of explanation, and the above-described embodiments are not limited to singular or plural components. Components expressed in the plural may be composed of a single one, and components expressed in the singular may also be composed of a plurality.

[0260] On the other hand, although specific embodiments have been described in the description of the invention, it goes without saying that various modifications are possible as long as they do not deviate from the scope of the technical idea encompassed by the various embodiments.

[0261] Therefore, the scope of the present invention should not be defined as being limited to the described embodiments, but should be defined not only by the claims described later, but also by those equivalent to the scope of these claims.

Claims

1. A general-purpose logic memory cell including a first network element and a second network element using a plurality of triple-gate silicon elements, a switch box for determining the direction of an input voltage applied to the general-purpose logic memory cell and an output voltage output from the general-purpose logic memory cell, and a line switch for controlling the interconnection between the switch box and the general-purpose logic memory cell, wherein, in a structure in which a plurality of the general-purpose logic memory cells are arranged according to a preset, by controlling the interconnection with respect to the logic operation function of the general-purpose logic memory cell based on the direction of the applied input voltage and the output voltage, a combinational logic operation function and a memory function are performed. A general-purpose logic memory block characterized by this.

2. The general-purpose logic memory cells are arranged in a plurality of rows and a plurality of columns according to the preset, the switch box and the line switch are arranged between the general-purpose logic memory cells, and the number of the line switches is determined so as to correspond to the number of the input voltages transmitted through the switch box, and the combinational logic operation function is realized with at least one output based on the output voltage. The general-purpose logic memory block according to Claim 1, characterized by this.

3. The switch box applies a first input voltage (V ＩＮ１ ), and a second input voltage (V ＩＮ２ ) to a general-purpose logic memory cell operating as an XOR gate and a general-purpose logic memory cell operating as an AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, outputs the output from the general-purpose logic memory cell operating as the XOR gate as a sum (S), and controls to output the output from the general-purpose logic memory cell operating as the AND gate as a carry number (COUT). The general-purpose logic memory block according to claim 2, characterized in that.

4. The switch box includes general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, and general-purpose logic memory cells that operate as a first XOR gate and a second XOR gate among the logic operation functions, and general-purpose logic memory cells that operate as a first AND gate and a second AND gate. A first input voltage (V ＩＮ１ ), a second input voltage (V ＩＮ２ ), and a third input voltage (V ＣＩＮ ) are applied, the output from the general-purpose logic memory cell operating as the second XOR gate is output as a sum (S), and the outputs from the general-purpose logic memory cells operating as the first AND gate and the second AND gate are transmitted to the input of the general-purpose logic memory cell operating as an OR gate, and then the output voltage is output as a carry (COUT). The general-purpose logic memory block according to claim 2, characterized in that it is controlled as such.

5. The switch box applies an input voltage (V ＩＮ ) to general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, and applies a selection voltage (V Ｓ ) to general-purpose logic memory cells that operate as a NOT gate among the logic operation functions, outputs the output from the general-purpose logic memory cell operating as the first AND gate as a first output (OUT1), and outputs the output from the general-purpose logic memory cell operating as the second AND gate as a second output (OUT2), and controls the same. The general-purpose logic memory block according to claim 2.

6. The switch box applies a first input voltage (V ＩＮ１ ) and a second input voltage (V ＩＮ２ ) to general-purpose logic memory cells that operate as a first AND gate and a second AND gate among the general-purpose logic memory cells arranged in the plurality of rows and columns, and applies a selection voltage (V Ｓ ) to a general-purpose logic memory cell that operates as a NOT gate among the logic operation functions, and after transmitting the output from the general-purpose logic memory cell operating as the first AND gate and the output from the general-purpose logic memory cell operating as the second AND gate to the input of the general-purpose logic memory cell operating as an OR gate, controls to output the output voltage as output (OUT). The general-purpose logic memory block according to claim 2, characterized in that.

7. The switch box selectively applies a first input voltage (V ＩＮ１ ), and a second input voltage (V ＩＮ２ ) to general-purpose logic memory cells that operate as a first AND gate, a second AND gate, a third AND gate, and a fourth AND gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, controls the output of the general-purpose logic memory cell operating as the first AND gate as a first output (OUT1), controls the output of the general-purpose logic memory cell operating as the second AND gate as a second output (OUT2), controls the output of the general-purpose logic memory cell operating as the third AND gate as a fourth output (OUT4), and controls the output of the general-purpose logic memory cell operating as the fourth AND gate as a third output (OUT3). The general-purpose logic memory block according to claim 2, characterized in that.

8. The switch box applies a second input voltage (V ＩＮ２ ), a third input voltage (V ＩＮ３ ), and a fourth input voltage (V ＩＮ４ ) to general-purpose logic memory cells that operate as the first OR gate and the second OR gate among the general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns, controls the output of the general-purpose logic memory cell operating as the first OR gate as a first output (OUT1), and controls the output of the general-purpose logic memory cell operating as the second OR gate as a second output (OUT2). The general-purpose logic memory block according to claim 2, characterized in that.

9. The switch box selectively applies a first input voltage (V ＩＮ１ ), and a second input voltage (V ＩＮ２ ) to general-purpose logic memory cells arranged in the plurality of rows and columns and operating as XNOR gates, XOR gates, first NOT gates, second NOT gates, first AND gates, and second AND gates, controls the output of the general-purpose logic memory cell operating as the XNOR gate as a first output (OUT1), controls the output of the general-purpose logic memory cell operating as the XOR gate as a second output (OUT2), controls the output of the general-purpose logic memory cell operating as the second AND gate as a third output (OUT3), and controls the output of the general-purpose logic memory cell operating as the first AND gate as a fourth output (OUT4). The general-purpose logic memory block according to claim 2, characterized by that.

10. The switch box selectively applies a first input voltage (V ＩＮ１ ), a second input voltage (V ＩＮ２ ), and a third input voltage (V ＩＮ３ ) to general-purpose logic memory cells arranged in the plurality of rows and the plurality of columns and operating as a first XOR gate and a second XOR gate, controls the first input voltage (V ＩＮ１ ) as a first output (OUT1), controls the output of the general-purpose logic memory cell operating as the first XOR gate as a second output (OUT2), and controls the output of the general-purpose logic memory cell operating as the second XOR gate as a third output (OUT3). The general-purpose logic memory block according to claim 2, characterized in that.

11. The general-purpose logic memory cell includes a first network element and a second network element using a plurality of triple-gate silicon elements. Each of the plurality of triple-gate silicon elements includes a drain region, a channel region, and a source region. A supply voltage is applied to the drain region and the source region. The gate region has a first and a second programming gate electrode and a control gate electrode formed thereon over the channel region. Depending on the level of the program voltage (V ＰＧ ), in the channel region, the channel region under the first and the second programming gate electrodes operates in either the first channel mode or the second channel mode. Based on the level of the control voltage (V ＣＧ ), it is determined to be in either an on state or an off state. The first network element and the second network element perform the logic operation function and the memory function according to the level of the output voltage (V ＯＵＴ ) that changes according to the performed one of the channel modes and the one of the states. The general-purpose logic memory block according to claim 2, characterized in that.

12. The first network element and the second network element are configured by a first parallel connection part to which a common drain region is connected between a first series connection part in which drain regions and source regions of two of the four triple-gate silicon elements among the plurality of triple-gate silicon elements are connected in series, and a second series connection part in which drain regions and source regions of the remaining two triple-gate silicon elements are connected in series, and a second parallel connection part to which a common source region is connected. A drain voltage (V ＤＤ ), among the common voltages, is applied through the first parallel connection part of the first network element, and a source voltage (V ＳＳ ), among the common voltages, is applied through the second parallel connection part of the second network element. The output voltage (V ＯＵＴ ) is measured as any one at a part where the second parallel connection part of the first network element and the first parallel connection part of the second network element are connected. The general-purpose logic memory block according to claim 11, characterized in that.

13. The triple-gate silicon element has a p-doped drain region, an n-doped source region, an intrinsic channel region, and in the channel region, the channel region under the first and second programming gate electrodes operates as an n-channel corresponding to the first channel mode when the level of the program voltage (V ＰＧ ) is a positive level, and operates as a p-channel corresponding to the second channel mode when the level of the program voltage (V ＰＧ ) is a negative level. The general-purpose logic memory block according to claim 12, characterized in that.

14. The general-purpose logic memory cell maintains the level of the output voltage (V ＤＤ ), and performs the memory function when the drain voltage (V ＳＳ ) applied to the drain region, the source voltage (V ＰＧ ) applied to the source region, the program voltage (V ＣＧ ) and the control voltage (V ＯＵＴ ) are applied at zero levels. The general-purpose logic memory block according to claim 11.

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