Carrier substrate and method for manufacturing semiconductor package using the same
By integrating organic patterns with higher thermal expansion coefficients into the carrier substrate, the issues of warping and deflection are mitigated, resulting in improved performance and reliability of semiconductor packages.
Patent Information
- Application Number
- JP2024211886
- Authority / Receiving Office
- JP · JP
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2023-12-26
- Filing Date
- 2024-12-05
- Publication Date
- 2025-07-08
AI Technical Summary
Existing carrier substrates face challenges in achieving improved performance and reliability due to thermal expansion mismatches, leading to warping and deflection during semiconductor package manufacturing.
Incorporating organic patterns with higher thermal expansion coefficients into the carrier substrate, specifically on the front and back surfaces, to compensate for thermal expansion differences with other materials, thereby reducing warping and enhancing structural integrity.
The inclusion of organic patterns with varying thermal expansion coefficients improves the carrier substrate's deflection and reliability, resulting in enhanced performance and reliability of the semiconductor package.
Smart Images
Figure 2025102688000001_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to a carrier substrate and a method for manufacturing a semiconductor package using the same.
Background Art
[0002] Over the past few decades, computing power and wireless communication technology have rapidly developed due to technological, material, and manufacturing process discoveries. As a result, the direct implementation of high-performance transistors has become possible, and the integration speed has doubled approximately every 18 months according to Moore's law. The miniaturization, thinning, and power efficiency improvement of systems are the perpetual goals of the semiconductor manufacturing industry. At the current point where economic and physical process limitations have been reached, three-dimensional integrated packaging has been presented as an effective solution.
[0003] The development of three-dimensionally integrated devices began with CMOS (complementary metal-oxide-semiconductor) integrated elements presented in 1980 and has since evolved through 30 years of continuous research and development. Examples of three-dimensional integration technologies include the integration of logic circuits and memory circuits, sensor packaging, and heterogeneous integration of MEMS (micro-electromechanical system) and CMOS. Three-dimensional integration technology enables not only the reduction of form factor but also the achievement of high reliability, low power consumption, and low manufacturing cost.
Summary of the Invention
Problems to be Solved by the Invention
[0004] The problem to be solved by the present invention is to provide a carrier substrate with improved performance and reliability.
[0005] The problem to be solved by the present invention is also to provide a method for manufacturing a semiconductor package with improved performance and reliability.
[0006] The problems to be solved by the technical idea of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.
Means for Solving the Problems
[0007] According to an embodiment based on the technical idea of the present invention, a carrier substrate is provided. The carrier substrate includes a main layer including a first surface and a second surface opposite to each other, a first trench on the first surface, and a first organic pattern in the first trench.
[0008] According to an embodiment based on the technical idea of the present invention, a method for manufacturing a semiconductor package is provided. The method for manufacturing the semiconductor package includes providing a carrier substrate, disposing a semiconductor chip on the carrier substrate, and forming a redistribution layer electrically connected to the semiconductor chip. The carrier substrate includes a first surface and a second surface opposite to each other, a main layer including the first surface and the second surface, a first trench on the first surface, and a first organic pattern in the first trench.
[0009] According to an embodiment based on the technical idea of the present invention, a method for manufacturing a semiconductor package is provided. The method for manufacturing the semiconductor package includes providing a carrier substrate, forming a redistribution layer including a redistribution insulating layer and a redistribution pattern surrounded by the redistribution insulating layer on a front surface of the carrier substrate, and disposing a semiconductor chip on the redistribution layer so as to be electrically connected to the redistribution pattern. The carrier substrate includes the front surface, a back surface opposite to the front surface, a main layer including the back surface and the front surface, a front trench on the front surface, and a front organic pattern in the front trench. The coefficient of thermal expansion of the main layer is smaller than the coefficient of thermal expansion of the front organic pattern, and the coefficient of thermal expansion of the main layer is smaller than the coefficient of thermal expansion of the redistribution insulating layer.
Advantages of the Invention
[0010] According to an embodiment based on the technical idea of the present invention, a carrier substrate with improved deflection can be provided.
[0011] According to an embodiment based on the technical idea of the present invention, a carrier substrate with improved performance and reliability can be provided.
[0012] According to an embodiment based on the technical idea of the present invention, a method for manufacturing a semiconductor package with improved performance and reliability can be provided.
Brief Description of the Drawings
[0013]
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Mode for Carrying Out the Invention
[0014] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. For the same components in the drawings, the same reference numerals are used, and redundant descriptions thereof are omitted. In the following drawings, the thickness and size of each layer are exaggerated for convenience and clarity of explanation, and thus may be slightly different from the actual shape and ratio.
[0015] FIG. 1 is a perspective view of a carrier substrate 100 according to an embodiment based on the technical idea of the present invention. FIG. 2 is a plan view of the carrier substrate 100 according to an embodiment based on the technical idea of the present invention. FIG. 3 is a cross-sectional view of the carrier substrate 100 according to an embodiment based on the technical idea of the present invention.
[0016] Referring to FIGS. 1 to 3, the carrier substrate 100 also includes a front surface 100_1 and a back surface 100_2 that are opposite to each other. In the present specification, the front surface 100_1 of the carrier substrate 100 can be a surface facing the vertical upward direction (+Z direction). The back surface 100_2 of the carrier substrate 100 is also a surface facing the vertical downward direction (-Z direction). In some embodiments, the front surface 100_1 of the carrier substrate 100 is also the surface on which the semiconductor chip 180 is disposed in the manufacturing process of the semiconductor package 10 (FIG. 19M) described later.
[0017]
[0018] In some embodiments, the carrier substrate 100 also includes a main layer 110. The main layer 110 also includes a front surface and a back surface that are opposite to each other, and the front surface and the back surface of the main layer 110 respectively include the front surface 100_1 and the back surface 100_2 of the carrier substrate 100. For example, the front surface of the main layer 110 faces the vertical upward direction (+Z direction), and the back surface faces the vertical downward direction (-Z direction). For example, the front surface of the main layer 110 is also the surface on which the semiconductor chip 180 is disposed in the manufacturing process of the semiconductor package 10 (FIG. 19M) described later.In one embodiment, the main layer 110 may also include one selected from a silicon layer and a germanium layer. In some other embodiments, the main layer 110 may also include a glass substance. In some other embodiments, the main layer 110 may also include alumina.
[0019] In some embodiments, a front trench 120T may be arranged on the front surface 100_1 of the carrier substrate 100. In some embodiments, a front organic pattern 120 may be arranged in the front trench 120T.
[0020] In some embodiments, the front trench 120T of the carrier substrate 100 may also include a grid shape. For example, the front trench 120T of the carrier substrate 100 may also include a grid shape extending in a first horizontal direction (X direction) and a second horizontal direction (Y direction).
[0021] In some embodiments, the front organic pattern 120 may also include an organic substance. In some embodiments, the coefficient of thermal expansion of the main layer 110 and the coefficient of thermal expansion of the front organic pattern 120 may also be different from each other. In some embodiments, the coefficient of thermal expansion of the main layer 110 is smaller than the coefficient of thermal expansion of the front organic pattern 120.
[0022] In one embodiment, a scribe line 140 may be disposed on the front surface 100_1 of the carrier substrate 100. The scribe line 140 may indicate the boundary of the region where the semiconductor chip 180 is to be disposed in the manufacturing process of the semiconductor package 10 (FIG. 19M) described later. The scribe line 140 is also a line for cutting the molding layer 190 that molds the semiconductor chip 180 after the semiconductor chip 180 is disposed in the manufacturing process of the semiconductor package 10 (FIG. 19M) described later. In some embodiments, the scribe line 140 is not directly cut. In some embodiments, the scribe line 140 of the carrier substrate 100 also includes a grid shape. For example, the scribe line 140 of the carrier substrate 100 includes a grid shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction).
[0023] In some embodiments, the front organic pattern 120 may be formed around the scribe line 140. Specifically, the front trench 120T region where the front organic pattern 120 is disposed also includes the scribe line 140.
[0024] In some embodiments, the carrier substrate 100 also includes a notch 160. In some embodiments, the front organic pattern 120 of the carrier substrate 100 may extend in the direction of the notch 160, that is, the same direction as the second horizontal direction (Y direction), and the direction perpendicular thereto, that is, the first horizontal direction (X direction).
[0025] FIGS. 4A and 4B are cross-sectional views of carrier substrates 100A and 100B according to other embodiments based on the technical idea of the present invention. Hereinafter, the differences from the carrier substrate 100 described with reference to FIGS. 1 to 3 will be mainly described.
[0026] Referring to FIG. 4A, the carrier substrate 100A also includes a front surface 100A_1 and a back surface 100A_2 that are opposite to each other, and a main layer 110. A front trench 120TA may be disposed on the front surface 100A_1 of the carrier substrate 100A. A front organic pattern 120A may be disposed in the front trench 120TA.
[0027] In some embodiments, the front trench 120TA of the carrier substrate 100A has an upper horizontal width that is wider than the lower horizontal width. For example, the cross-section of the front trench 120TA is also trapezoidal with an upper horizontal width wider than the lower horizontal width. For example, the front trench 120TA of the carrier substrate 100A may have a decreasing horizontal width as the vertical level decreases.
[0028] Referring to FIG. 4B, the carrier substrate 100B also includes a front surface 100B_1 and a back surface 100B_2 that are opposite to each other, and a main layer 110. A front trench 120TB may be disposed on the front surface 100B_1 of the carrier substrate 100B. A full-surface organic pattern 120B may be disposed in the front trench 120TB.
[0029] In some embodiments, the front trench 120TB of the carrier substrate 100B may increase and then decrease in horizontal width as the vertical level decreases. For example, the front trench 120TB of the carrier substrate 100B may also include a portion having a horizontal width wider than the horizontal width of the opening.
[0030] FIGS. 5A and 5B are cross-sectional views of carrier substrates 101A, 101B according to other embodiments according to the technical idea of the present invention.
[0031] Referring to FIGS. 5A and 5B, the horizontal width, depth, and spacing of the front trenches 121TA, 121TB of the carrier substrates 101A, 101B can be variously selected according to the design.
[0032] As illustrated in FIG. 5A, the carrier substrate 101A also includes a front surface 101A_1 and a back surface 101A_2 that are opposite to each other, and a main layer 110. A front trench 121TA can be disposed on the front surface 101A_1 of the carrier substrate 101A. A front organic pattern 121A can be disposed in the front trench 121TA. For example, the horizontal width of each of the front trenches 121TA is smaller than the depth of each of the front trenches 121TA.
[0033] As illustrated in FIG. 5B, the carrier substrate 101B also includes a front surface 101B_1 and a back surface 101B_2 that are opposite to each other, and a main layer 110. A front trench 121TB can be disposed on the front surface 101B_1 of the carrier substrate 101B. A front organic pattern 121B can be disposed in the front trench 121TB. For example, the horizontal width of each of the front trenches 121TB is larger than the depth of each of the front trenches 121TB.
[0034] FIGS. 6 and 7 are plan views of carrier substrates 102 and 103 according to other embodiments according to the technical idea of the present invention. Hereinafter, the differences from the carrier substrate 100 described with reference to FIGS. 1 to 3 will be mainly described.
[0035] Referring to FIG. 6, the front organic pattern 122 of the carrier substrate 102 can extend in the direction of the notch 160, that is, in a direction intersecting the second horizontal direction (Y direction) at 45°. In some embodiments, the scribe line 142 and the front trench 122T of the carrier substrate 102 can also extend in the direction of the notch 160, that is, in a direction intersecting the second horizontal direction (Y direction) at 45°.
[0036] Referring to FIG. 7, the carrier substrate 103 also includes a scribe line 140 and a front organic pattern 123 on the main layer 110. The front organic pattern 123 is not formed around at least a part of the scribe line 140 of the carrier substrate 103. In other words, the front organic pattern 123 of the carrier substrate 103 is not formed around all the scribe lines 140. The horizontal interval between the front organic patterns 123 of the carrier substrate 103 is wider than the horizontal interval between the front trenches 130T (FIGS. 1 to 3) of the carrier substrate 100 (FIGS. 1 to 3).
[0037] FIGS. 8 and 9 are drawings for explaining a carrier substrate 100 according to an embodiment based on the technical idea of the present invention. Specifically, FIG. 8 is a cross-sectional view showing a carrier substrate 1 of a comparative example and a material layer 2 on the carrier substrate 1 being heated and cooled during a process for explaining the carrier substrate 100. FIG. 9 is a cross-sectional view showing the carrier substrate 100 and the material layer 2 on the carrier substrate 100 being heated and cooled during a process, as compared with the carrier substrate 1 of the comparative example.
[0038] Referring to FIG. 8, a material layer 2 can be disposed on the front surface of the carrier substrate 1. For example, the material layer 2 also includes a material having a coefficient of thermal expansion larger than that of the carrier substrate 1. During a semiconductor package manufacturing process, the carrier substrate 1 and the material layer 2 can be heated and cooled.
[0039] As illustrated in FIG. 8, when the carrier substrate 1 and the material layer 2 are heated, the carrier substrate 1 and the material layer 2 can expand. At this time, due to the difference in the coefficient of thermal expansion, the degrees of expansion of the carrier substrate 1 and the material layer 2 may be different. For example, the degree of expansion of the carrier substrate 1 is smaller than the degree of expansion of the material layer 2.
[0040] Subsequently, when the carrier substrate 1 and the material layer 2 are cooled, the carrier substrate 1 and the material layer 2 may contract. At this time, due to the difference in the coefficient of thermal expansion, the degrees of contraction of the carrier substrate 1 and the material layer 2 may be different. For example, the degree of cooling of the carrier substrate 1 is smaller than the degree of contraction of the material layer 2. While the material layer 2 on the carrier substrate 1 contracts more significantly than the carrier substrate 1, warpage of the carrier substrate 1 may be caused.
[0041] Referring to FIG. 9, the material layer 2 may be disposed on the front surface of the carrier substrate 100 according to an embodiment according to the technical idea of the present invention. For example, the material layer 2 may also include a material having a coefficient of thermal expansion larger than that of the carrier substrate 100. During the semiconductor package manufacturing process, the carrier substrate 100 and the material layer 2 may be heated and cooled.
[0042] As illustrated in FIG. 9, when the carrier substrate 100 and the material layer 2 are heated, the carrier substrate 100 and the material layer 2 may expand. At this time, due to the difference in the coefficient of thermal expansion, the degrees of expansion of the carrier substrate 100 and the material layer 2 may be different. For example, the degree of expansion of the carrier substrate 100 is smaller than the degree of expansion of the material layer 2.
[0043] Subsequently, when the carrier substrate 100 and the material layer 2 are cooled, the carrier substrate 100 and the material layer 2 may contract. At this time, due to the difference in the coefficient of thermal expansion, the degrees of contraction of the carrier substrate 100 and the material layer 2 may be different. For example, the degree of contraction of the carrier substrate 100 is smaller than the degree of contraction of the material layer 2. At this time, when the carrier substrate 100 includes the front organic pattern 120 on the contact surface with the material layer 2 (that is, the front surface of the carrier substrate 100), while the front organic pattern 120 contracts to a high level, warpage of the carrier substrate 100 may be improved.
[0044] Specifically, as described above, the front organic pattern 120 also includes a coefficient of thermal expansion greater than that of the main layer 110. Therefore, when the carrier substrate 100 is cooled, the front organic pattern 120 contracts more than the main layer 110, thereby compensating for the difference in the degree of contraction between the carrier substrate 100 and the material layer 2. Therefore, when the carrier substrate 100 includes the front organic pattern 120 on the front surface, the warping of the carrier substrate 100 due to heating and contraction can be improved. Specifically, in the case where the material layer 2 having a coefficient of thermal expansion greater than that of the main layer 110 of the carrier substrate 100 is disposed on the front surface of the carrier substrate 100, the carrier substrate 100 including the front organic pattern 120 can have improved warping due to heating and contraction.
[0045] Similarly, the carrier substrates 100A, 100B, 101A, 101B, 102, 103 illustrated in FIGS. 4A, 4B, 5A, 5B, 6, and 7 include the front organic patterns 120A, 120B, 121A, 121B, 122, 123 on their respective front surfaces, whereby the warping of the carrier substrates 100A, 100B, 101A, 101B, 102, 103 due to heating and contraction can be improved.
[0046] Embodiments according to the technical idea of the present invention may provide carrier substrates 100, 100A, 100B, 101A, 101B, 102, 103 including front organic patterns 120, 120A, 120B, 121A, 121B, 122, 123. Specifically, embodiments according to the technical idea of the present invention may provide carrier substrates 100, 100A, 100B, 101A, 101B, 102, 103 with improved deflection due to heating and shrinkage. That is, embodiments according to the technical idea of the present invention may provide carrier substrates 100, 100A, 100B, 101A, 101B, 102, 103 with improved performance and reliability. According to the foregoing embodiments, the main layer 110 of the carrier substrate is formed of a material such as silicon, germanium, glass, or alumina, and the front organic patterns 120, 120A, 120B, 121A, 121B, 122, 123 include an organic material, for example, a polymer, for example, a thermoplastic polymer such as polyethylene (PE), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polyvinyl chloride (PVC). The organic material may have a coefficient of thermal expansion greater than that of the carrier substrate. However, the exemplification of the organic material is not limited to the foregoing, and may include various substances.
[0047] FIG. 10 is a plan view of a carrier substrate 200 according to an embodiment according to the technical idea of the present invention. FIG. 11 is a cross-sectional view of the carrier substrate 200 according to an embodiment according to the technical idea of the present invention.
[0048] Referring to FIGS. 10 and 11, the carrier substrate 200 also includes a front surface 200_1 and a back surface 200_2. The front surface 200_1 of the carrier substrate 200 is also a surface facing the vertical upward direction (+Z direction). The back surface 200_2 of the carrier substrate 200 is also a surface facing the vertical downward direction (-Z direction). In some embodiments, the front surface 200_1 of the carrier substrate 200 is also the surface on which semiconductor chips are arranged in the semiconductor package manufacturing process. For example, the back surface 200_2 of the carrier substrate 200 is also the surface on which process equipment is arranged in the semiconductor package manufacturing process.
[0049] In some embodiments, the carrier substrate 200 also includes a main layer 210. The main layer 210 also includes a front surface and a back surface that are opposite to each other, and the front surface and the back surface of the main layer 210 also include the front surface 200_1 and the back surface 200_2 of the carrier substrate 200, respectively. For example, the front surface of the main layer 210 faces the vertical upward direction (+Z direction), and the back surface faces the vertical downward direction (-Z direction). For example, the front surface of the main layer 210 is also the surface on which semiconductor chips are arranged in the semiconductor package manufacturing process. For example, the back surface of the main layer 210 is also the surface on which process equipment is arranged in the semiconductor package manufacturing process.
[0050] In some embodiments, a back trench 230T may be arranged on the back surface 200_2 of the carrier substrate 200. In some embodiments, a back organic pattern 230 may be arranged in the back trench 230T.
[0051] In some embodiments, the back trench 230T of the carrier substrate 200 also includes a grid shape. For example, the back trench 230T of the carrier substrate 200 also includes a grid shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction). Similarly, the back organic pattern 230 of the carrier substrate 200 also includes a grid shape. For example, the back organic pattern 230 of the carrier substrate 200 also includes a grid shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction).
[0052] In one embodiment, the back organic pattern 230 also contains organic substances. In one embodiment, the coefficients of thermal expansion of the main layer 210 and the back organic pattern 230 may be different from each other. In one embodiment, the coefficient of thermal expansion of the main layer 210 is smaller than that of the back organic pattern 230.
[0053] In one embodiment, the carrier substrate 200 also includes a notch 260. In one embodiment, the back organic pattern 230 of the carrier substrate 200 may extend in the direction of the notch 260, i.e., the same direction as the second horizontal direction (Y direction), and in a direction perpendicular thereto, i.e., the first horizontal direction (X direction).
[0054] In one embodiment, the carrier substrate 200 also includes an attachment region 270 on the back surface 200_2. For example, the attachment region 270 is also the region where a chuck is attached in the semiconductor manufacturing process. For example, the chuck may be attached to the attachment region 270 of the carrier substrate 200 and support and / or fix the carrier substrate 200 during the semiconductor manufacturing process. In one embodiment, the attachment region 270 may be formed at the central portion of the back surface 200_2 of the carrier substrate 200.
[0055] In one embodiment, the back trench 230T of the carrier substrate 200 is not formed in the attachment region 270. For example, the back trench 230T of the carrier substrate 200 may be formed on the back surface 200_2 excluding the attachment region 270. Similarly, the back organic pattern 230 is not formed in the attachment region 270. For example, the back trench 230T and the back organic pattern 230 do not overlap with the attachment region 270 in the vertical direction (Z direction).
[0056] In one embodiment, by including the back organic pattern 230 on the back surface 200_2 in the carrier substrate 200, the deflection due to heating and contraction of the carrier substrate 200 can be improved.
[0057] Specifically, as described above, the back organic pattern 230 also includes a coefficient of thermal expansion greater than that of the main layer 210. Therefore, when the carrier substrate 200 is cooled, the back organic pattern 230 can shrink more than the main layer 210. For example, when a material layer having a coefficient of thermal expansion smaller than that of the main layer 210 of the carrier substrate 200 is disposed on the front surface 200_1 of the carrier substrate 200, the back organic pattern 230 can shrink more than the main layer 210 and compensate for the difference in the degree of shrinkage between the carrier substrate 200 and the material layer. Therefore, when the carrier substrate 200 includes the back organic pattern 230 on the back surface 200_2, the bending due to heating and shrinkage of the carrier substrate 200 can be improved.
[0058] According to an embodiment of the technical idea of the present invention, a carrier substrate 200 including a back organic pattern 230 can be provided. Specifically, according to an embodiment of the technical idea of the present invention, a carrier substrate 200 with improved bending due to heating and shrinkage can be provided.
[0059] FIGS. 12A to 12C are plan views of carrier substrates 200A, 200B, and 200C according to an embodiment of the technical idea of the present invention. FIGS. 13 and 14 are plan views of carrier substrates 201 and 201A according to an embodiment of the technical idea of the present invention. Hereinafter, the differences from the carrier substrate 200 described with reference to FIGS. 10 and 11 will be mainly described.
[0060] Referring to FIG. 12A, the carrier substrate 200A also includes a main layer 210 and a back trench 230TA on the back surface 200A_2. A back organic pattern 230A can be disposed in the back trench 230TA.
[0061] In one embodiment, the back trenches 230TA of the carrier substrate 200A also include concentric circular shapes. For example, the back trenches 230TA of the carrier substrate 200A may include one or more concentric circular shapes with the same interval between each other. Similarly, the back organic pattern 230A of the carrier substrate 200A may include concentric circular shapes. For example, the back organic pattern 230A of the carrier substrate 200A may include one or more concentric circular shapes with the same interval between each other.
[0062] In one embodiment, the back trenches 230TA and the back organic pattern 230A of the carrier substrate 200A are not arranged on the adhesion region 270 on the back surface 200A_2.
[0063] Referring to FIG. 12B, the carrier substrate 200B may also include a main layer 210 and back trenches 230TB on the back surface 200B_2. A back organic pattern 230B may be arranged in the back trenches 230TB.
[0064] In one embodiment, the back trenches 230TB of the carrier substrate 200B also include concentric circular shapes. For example, the back trenches 230TA of the carrier substrate 200B may include one or more concentric circular shapes with different intervals between each other. Similarly, the back organic pattern 230B of the carrier substrate 200B may include concentric circular shapes. For example, the back organic pattern 230B of the carrier substrate 200B may include one or more concentric circular shapes with different intervals between each other.
[0065] In one embodiment, the back trenches 230TB and the back organic pattern 230B of the carrier substrate 200B are not arranged on the adhesion region 270 on the back surface 200B_2.
[0066] Referring to FIG. 12C, the carrier substrate 200C may also include a main layer 210 and back trenches 230TC on the back surface 200C_2. A back organic pattern 230C may be arranged in the back trenches 230TC.
[0067] In one embodiment, the back trenches 230TC of the carrier substrate 200C also include a lattice shape and a concentric circle shape. For example, the back trenches 230TC of the carrier substrate 200C also include a lattice shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), and one or more concentric circle shapes with the same interval between them. Similarly, the back organic pattern 230C of the carrier substrate 200C also includes a lattice shape and a concentric circle shape. For example, the back organic pattern 230C of the carrier substrate 200C also includes a lattice shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction), and one or more concentric circle shapes with the same interval between them.
[0068] In one embodiment, the back trenches 230TC and the back organic pattern 230C of the carrier substrate 200C are not arranged on the adhesion region 270 on the back surface 200C_2.
[0069] Referring to FIG. 13, the carrier substrate 201 also includes a main layer 210 and back trenches 231T on the back surface 201_2. A back organic pattern 231 may be arranged in the back trenches 231T.
[0070] In one embodiment, the back trenches 231T and the back organic pattern 231 of the carrier substrate 201 also include a lattice shape. For example, the back trenches 231T and the back organic pattern 231 of the carrier substrate 201 also include a lattice shape extending in the first horizontal direction (X direction) and the second horizontal direction (Y direction).
[0071] In one embodiment, the carrier substrate 201 also includes an adhesion region 271 on the back surface 201_2. For example, the carrier substrate 201 may also include a plurality of adhesion regions 271. In one embodiment, the back trenches 231T and the back organic pattern 231 of the carrier substrate 201 are not formed on the adhesion region 271.
[0072] Referring to FIG. 14, the carrier substrate 201A also includes a main layer 210 and a back trench 231TA on the back surface 201A_2. A back organic pattern 231A may be disposed within the back trench 231TA.
[0073] In some embodiments, the back trench 231TA and the back organic pattern 231A of the carrier substrate 201A also include a concentric shape. In some embodiments, the back trench 231TA and the back organic pattern 231A of the carrier substrate 201A are not formed on the adhesion region 271.
[0074] Similar to the description with reference to FIGS. 10 and 11, the carrier substrates 200A, 200B, 200C, 201, 201A illustrated in FIGS. 12A to 12C, 13, and 14 each include back organic patterns 230A, 230B, 230C, 231, 231A on their respective back surfaces 200A_2, 200B_2, 200C_2, 201_2, 201A_2, so that the deflection of the carrier substrates 200A, 200B, 200C, 201, 201A due to heating and shrinkage can be improved.
[0075] Embodiments according to the technical idea of the present invention can provide carrier substrates 200, 200A, 200B, 200C, 201, 201A including back organic patterns 230, 230A, 230B, 230C, 231, 231A. Specifically, embodiments according to the technical idea of the present invention can provide carrier substrates 200, 200A, 200B, 200C, 201, 201A with improved bending due to heating and shrinkage. According to the foregoing embodiments, the main layer of the carrier substrate is formed of a material such as silicon, germanium, glass, or alumina, and the front organic pattern includes an organic material, for example, a polymer, for example, a thermoplastic polymer such as polyethylene (PE), polypropylene (PP), polycarbonate (PC), polystyrene (PS), polyvinyl chloride (PVC). The organic material may have a coefficient of thermal expansion greater than that of the carrier substrate. However, the exemplification of the organic material is not limited to the foregoing and may include various substances.
[0076] FIGS. 15 to 18 are cross-sectional views of carrier substrates 300, 400, 500, 501 according to embodiments according to the technical idea of the present invention. Hereinafter, the differences from the carrier substrate 100 described with reference to FIGS. 1 to 3 will be mainly described.
[0077] Referring to FIG. 15, the carrier substrate 300 also includes a front surface 300_1 and a back surface 300_2 that are opposite to each other, and a main layer 310. The carrier substrate 300 also includes a front trench (not shown) on the front surface 300_1 and a front organic pattern 320 in the front trench. In some embodiments, the coefficient of thermal expansion of the main layer 310 of the carrier substrate 300 is greater than that of the front organic pattern 320.
[0078] Referring to FIG. 16, the carrier substrate 400 also includes a front surface 400_1 and a back surface 400_2 that are opposite to each other, and a main layer 410. The carrier substrate 400 also includes a back trench (not shown) on the back surface 400_2 and a back organic pattern 430 within the back trench. In some embodiments, the coefficient of thermal expansion of the main layer 410 of the carrier substrate 400 is greater than that of the back organic pattern 430. For example, according to the embodiments of FIGS. 15 and 16, the main layer of the carrier substrate 300, or the carrier substrate 400, is formed of a material such as silicon, germanium, glass, or alumina, and the front organic pattern 320 or the back organic pattern 430 includes an organic material, a polymer, such as a thermosetting polymer like epoxy resin, phenolic resin, unsaturated polyester resin, silicon resin, or melamine formaldehyde resin. The organic material may have a coefficient of thermal expansion smaller than that of the carrier substrate. However, the exemplification of the organic material is not limited to the foregoing and may include various substances.
[0079] Referring to FIG. 17, the carrier substrate 500 also includes a front surface 500_1 and a back surface 500_2 that are opposite to each other, and a main layer 510. The carrier substrate 500 also includes a front trench (not shown) on the front surface 500_1 and a front organic pattern 520 within the front trench. The carrier substrate 500 also includes a back trench (not shown) on the back surface 500_2 and a back organic pattern 530 within the back trench.
[0080] In some embodiments, the front organic pattern 520 on the front surface 500_1 and the back organic pattern 530 on the back surface 500_2 of the carrier substrate 500 may overlap in the vertical direction (Z direction).
[0081] In one embodiment, the coefficient of thermal expansion of the front organic pattern 520 on the front surface 500_1 of the carrier substrate 500 is greater than that of the main layer 510. In one embodiment, the coefficient of thermal expansion of the back organic pattern 530 on the back surface 500_2 of the carrier substrate 500 is greater than that of the main layer 510. In this embodiment, the main layer 510 of the carrier substrate 500 is formed of a material such as silicon, germanium, glass, or alumina, and the front organic pattern 520 and the back organic pattern 530 each include an organic material, for example, a polymer, such as a thermoplastic polymer such as polyethylene (PE), polypropylene (PP), polycarbonate (PC), polystyrene (PS), or polyvinyl chloride (PVC). The organic material may have a coefficient of thermal expansion greater than that of the carrier substrate 500.
[0082] In one embodiment, the front organic pattern 520 and the back organic pattern 530 also include a substance having the same coefficient of thermal expansion. For example, the front organic pattern 520 and the back organic pattern 530 may also include the same substance.
[0083] In some other embodiments, the front organic pattern 520 and the back organic pattern 530 also include substances having different coefficients of thermal expansion from each other. For example, the coefficient of thermal expansion of the front organic pattern 520 is greater than that of the back organic pattern 530. For example, the coefficient of thermal expansion of the front organic pattern 520 is smaller than that of the back organic pattern 530.
[0084] Referring to FIG. 18, the carrier substrate 501 also includes a front surface 501_1 and a back surface 501_2 that are opposite to each other, and a main layer 510. The carrier substrate 501 also includes a front trench (not shown) on the front surface 501_1 and a front organic pattern 521 in the front trench. The carrier substrate 501 also includes a back trench (not shown) on the back surface 501_2 and a back organic pattern 531 in the back trench.
[0085] In one embodiment, the front organic pattern 521 on the front surface 501_1 of the carrier substrate 501 and the back organic pattern 531 on the back surface 501_2 do not overlap in the vertical direction (Z direction).
[0086] In one embodiment, the coefficient of thermal expansion of the front organic pattern 521 on the front surface 501_1 of the carrier substrate 501 is greater than that of the main layer 510. In one embodiment, the coefficient of thermal expansion of the back organic pattern 531 on the back surface 501_2 of the carrier substrate 501 is greater than that of the main layer 510.
[0087] In one embodiment, the front organic pattern 521 and the back organic pattern 531 also contain a substance having the same coefficient of thermal expansion. For example, the front organic pattern 521 and the back organic pattern 531 also contain the same substance.
[0088] In some other embodiments, the front organic pattern 521 and the back organic pattern 531 also contain substances having different coefficients of thermal expansion from each other. For example, the coefficient of thermal expansion of the front organic pattern 521 is greater than that of the back organic pattern 531. For example, the coefficient of thermal expansion of the front organic pattern 521 is smaller than that of the back organic pattern 531.
[0089] Figures 19A to 19M are drawings for explaining a method of manufacturing a semiconductor package 10 (Figure 19M) according to an embodiment based on the technical idea of the present invention. Specifically, Figures 19A to 19M are drawings for explaining a method of manufacturing the carrier substrate 100 described with reference to Figures 1 to 3 and a method of manufacturing the semiconductor package 10 (Figure 19M) using the carrier substrate 100. Figures 19A to 19C are drawings for explaining a method of manufacturing the carrier substrate 100. Figures 19D to 19M are drawings for explaining a method of manufacturing the semiconductor package 10 using the carrier substrate 100. In particular, Figures 19D to 19I are enlarged cross-sectional views corresponding to an enlarged partial region of Figure 19C.
[0090] Referring to FIG. 19A, a main layer 110 can be provided. A photoresist pattern PR can be provided on the main layer 110. The photoresist pattern PR can expose a partial region of the main layer 110. For example, the photoresist pattern PR can expose a partial region of the main layer 110 where a front trench 120T is to be formed in a process described later.
[0091] Referring to FIG. 19B, using the photoresist pattern PR as an etching mask, a partial region of the main layer 110 can be etched. As a result, a front trench 120T can be formed on the front surface of the main layer 110. The process of forming the front trench 120T can be performed using a dry etching process and / or a wet etching process.
[0092] Referring to FIG. 19C, a front organic pattern 120 can be formed in the front trench 120T. The process of forming the front organic pattern 120 also includes applying an organic substance on the front trench 120T and the front surface of the main layer 110, and then removing a part of the organic substance on the front surface of the main layer 110. As a result, a carrier substrate 100 including the main layer 110 and the front organic pattern 120 on the front surface 100_1 can be manufactured.
[0093] Referring to FIG. 19D, a plurality of pads 151 can be formed on the front surface 100_1 of the carrier substrate 100. The plurality of pads 151 can be formed at positions that do not overlap with the front organic pattern 120 in the vertical direction (Z direction). The plurality of pads 151 are also terminal connection pads for attaching external connection terminals 191 (FIG. 19M) in a process described later.
[0094] Subsequently, a first rewiring insulating layer 153_1 covering a plurality of pads 151 may be formed on the front surface 100_1 of the carrier substrate 100. Thereafter, a part of the first rewiring insulating layer 153_1 may be etched to expose the plurality of pads 151. In some embodiments, the coefficient of thermal expansion of the first rewiring insulating layer 153_1 is greater than that of the main layer 110.
[0095] In some embodiments, the first rewiring insulating layer 153_1 also contains an organic substance. The first rewiring insulating layer 153_1 can be formed, for example, from a material film composed of an organic compound. In some embodiments, the first rewiring insulating layer 153_1 can be formed from a material film composed of an organic polymer substance. In some embodiments, the first rewiring insulating layer 153_1 can be formed from photosensitive polyimide (PSPI).
[0096] In some embodiments, the coefficient of thermal expansion of the organic substance contained in the first rewiring insulating layer 153_1 is also substantially the same as that of the organic substance of the front surface organic pattern 120 of the carrier substrate 100.
[0097] In some other embodiments, the coefficient of thermal expansion of the organic substance contained in the first rewiring insulating layer 153_1 is greater than or smaller than that of the organic substance of the front surface organic pattern 120 of the carrier substrate 100. In other words, the material of the front surface organic pattern 120 of the carrier substrate 100 can be variably changed by design.
[0098] Referring to FIG. 19E, a first rewiring pattern 152_1 can be formed that is electrically connected to a plurality of pads 151 exposed by the first rewiring insulating layer 153_1. In some embodiments, the first rewiring pattern 152_1 also contains a conductive material. For example, the first rewiring pattern 152_1 can be, but is not limited to, a metal such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), or an alloy thereof.
[0099] Referring to FIG. 19F, a second rewiring insulating layer 153_2 can be formed over the first rewiring pattern 152_1 on the first rewiring insulating layer 153_1. Thereafter, a portion of the second rewiring insulating layer 153_2 can be etched to expose a partial region of the first rewiring pattern 152_1.
[0100] Referring to FIG. 19G, a second rewiring pattern 152_2 can be formed that is electrically connected to the first rewiring pattern 152_1 exposed by the second rewiring insulating layer 153_2.
[0101] Subsequently, a third rewiring insulating layer 153_3 can be formed over the second rewiring pattern 152_2 on the second rewiring insulating layer 153_2. Thereafter, a portion of the third rewiring insulating layer 153_3 can be etched to expose a partial region of the second rewiring pattern 152_2.
[0102] As a result, a rewiring layer 150 including a plurality of rewiring insulations 153 and rewiring patterns 152 can be formed on the front surface 100_1 of the carrier substrate 100.
[0103] Referring to FIG. 19H, solder 185 can be formed on the second rewiring pattern 152_2 exposed by the third rewiring insulating layer 153_3. In some embodiments, solder 185 also contains a conductive material. For example, solder 185 may contain tin (Sn), lead (Pb), silver (Ag), copper (Cu), or a combination thereof.
[0104] Referring to FIGS. 19I and 19J, semiconductor chip 180 can be mounted on solder 185. Chip connection pads 181 can be arranged on the active surface of semiconductor chip 180. Semiconductor chip 180 can be electrically connected to the rewiring pattern 152 of the rewiring layer 150 by chip connection pads 181 and solder 185.
[0105] In some embodiments, semiconductor chip 180 does not overlap in the vertical (Z) direction with the front organic pattern 120 on the front surface 100_1 of carrier substrate 100.
[0106] In some embodiments, semiconductor chip 180 is, for example, a central processing unit (CPU) chip, a graphic processing unit (GPU) chip or an application processor (AP) chip. In some embodiments, semiconductor chip 180 is, for example, a dynamic random access memory (DRAM) chip, a static random access memory (SRAM) chip, a flash memory chip, an electrically erasable programmable read-only memory (EEPROM) chip, a phase-change random access memory (PRAM) chip, a magnetic a random access memory chip or an RRAM (resistive random access memory) chip as well.
[0107] Referring to FIG. 19K, a molding layer 190 that molds the redistribution layer 150, the solder 185, and the semiconductor chip 180 can be formed. The molding layer 190 can surround the redistribution layer 150, the plurality of solders 185, and the plurality of semiconductor chips 180. In some embodiments, the coefficient of thermal expansion of the molding layer 190 is greater than that of the main layer 110. The molding layer 190 also includes an epoxy resin, a silicon resin, or a combination thereof. For example, the molding layer 190 also includes an epoxy mold compound (EMC).
[0108] Referring to FIG. 19L, the carrier substrate 100 can be removed. Specifically, the carrier substrate 100 can be debonded from the redistribution layer 150 and the semiconductor chip 180.
[0109] Referring to FIG. 19M, the redistribution layer 150 and the molding layer 190 can be cut. Thereby, the molding layer 190 can surround one semiconductor chip 180. Subsequently, a plurality of external connection terminals 191 electrically connected to the plurality of pads 151 can be formed. In some embodiments, the external connection terminals 191 also include a conductive material. For example, the external connection terminals 191 also include tin (Sn), lead (Pb), silver (Ag), copper (Cu), or a combination thereof. The semiconductor package 10 can be electrically connected to an external device by the plurality of external connection terminals 191.
[0110] According to an embodiment based on the technical idea of the present invention, a method for manufacturing a semiconductor package 10 using a carrier substrate 100 including a front organic pattern 120 may be provided. Specifically, by including the front organic pattern 120 on the front surface 100_1 of the carrier substrate 100, it is possible to improve the bending of the carrier substrate 100 that may occur during the process of manufacturing the semiconductor package 10.
[0111] For example, the process of manufacturing the semiconductor package 10 may also include a process of forming a redistribution insulation 153 having a coefficient of thermal expansion greater than that of the main layer 110 on the front surface 100_1 of the carrier substrate 100. Also, the process of manufacturing the semiconductor package 10 may include a heating process and a cooling process.
[0112] Therefore, according to an embodiment based on the technical idea of the present invention, by providing the carrier substrate 100 including the front organic pattern 120, it is possible to improve the bending of the carrier substrate 100 that may be caused by the difference in the coefficient of thermal expansion from the redistribution insulation 153 while the process of manufacturing the semiconductor package 10 is being performed.
[0113] Also, by improving the bending of the carrier substrate 100 that may occur during the process of manufacturing the semiconductor package 10, the performance and reliability of the semiconductor package 10 can be improved. That is, according to an embodiment based on the technical idea of the present invention, a method for manufacturing a semiconductor package 10 with improved performance and reliability may be provided.
[0114] FIGS. 20A to 20E are drawings for explaining a method for manufacturing a semiconductor package 11 according to an embodiment based on the technical idea of the present invention. Specifically, FIGS. 20A to 20E are drawings for explaining a method for manufacturing the semiconductor package 11 that is performed following FIG. 19C. FIGS. 20A to 20E are drawings for explaining a method for manufacturing the semiconductor package 11 using the carrier substrate 100.
[0115] Referring to FIG. 20A, the semiconductor chip 182 can be disposed on the front surface 100_1 of the carrier substrate 100. The semiconductor chip 182 also includes chip connection pads (not shown) on the active surface.
[0116] In some embodiments, the semiconductor chip 182 does not overlap vertically (in the Z direction) with the front organic pattern 120 formed on the front surface 100_1 of the carrier substrate 100. For example, the semiconductor chip 182 can be disposed between the front organic patterns 120.
[0117] In some embodiments, the chip connection pads of the semiconductor chip 182 can be disposed so as to overlook the front surface 100_1 of the carrier substrate 100. In some other embodiments, different from what is shown, the semiconductor chip 182 can be disposed such that the chip connection pads are opposite to the front surface 100_1 of the carrier substrate 100.
[0118] Referring to FIG. 20B, a molding layer 192 for molding the semiconductor chip 182 can be formed. The molding layer 192 can surround a plurality of semiconductor chips 182 disposed on the front surface 100_1 of the carrier substrate 100. The coefficient of thermal expansion of the molding layer 192 is larger than that of the main layer 110 of the carrier substrate 100.
[0119] Referring to FIG. 20C, the carrier substrate 100 can be removed. Specifically, the carrier substrate 100 can be debonded from the semiconductor chip 182.
[0120] Referring to FIG. 20D, a redistribution layer 154 can be formed on the active surface of the semiconductor chip 182. The redistribution layer 154 also includes at least one layer of redistribution insulating layer and a redistribution pattern. The redistribution pattern can penetrate at least a part of at least one layer of redistribution insulating layer. The semiconductor chip 182 can be electrically connected to the redistribution pattern of the redistribution layer 154. Subsequently, external connection terminals 194 can be formed on an exposed part of the redistribution pattern.
[0121] Referring to FIG. 20E, the rewiring layer 150 and the molding layer 190 can be cut to form the semiconductor package 11. Thereby, the molding layer 190 can surround one semiconductor chip 180.
[0122] According to an embodiment of the technical idea of the present invention, a method for manufacturing a semiconductor package 11 using a carrier substrate 100 including a front organic pattern 120 can be provided. Specifically, since the carrier substrate 100 includes the front organic pattern 120 on the front surface 100_1, the deflection of the carrier substrate 100 that may occur during the process of manufacturing the semiconductor package 11 can be improved.
[0123] For example, the process of manufacturing the semiconductor package 11 may also include a step of forming a molding layer 190 having a coefficient of thermal expansion greater than that of the main layer 110 on the front surface 100_1 of the carrier substrate 100. Also, the process of manufacturing the semiconductor package 11 may include a heating process and a cooling process.
[0124] Therefore, according to an embodiment of the technical idea of the present invention, by providing the carrier substrate 100 including the front organic pattern 120, the deflection of the carrier substrate 100 that may be caused by the difference in the coefficient of thermal expansion with the molding layer 190 can be improved while the process of manufacturing the semiconductor package 11 is being performed.
[0125] Also, by improving the deflection of the carrier substrate 100 that may occur during the process of manufacturing the semiconductor package 11, the performance and reliability of the semiconductor package 11 can be improved. That is, according to an embodiment of the technical idea of the present invention, a method for manufacturing a semiconductor package 11 with improved performance and reliability can be provided.
[0126] As described above, the embodiments of the present invention have been described with reference to the accompanying drawings. It should be understood that the embodiments described above are illustrative in all respects and not restrictive.
Description of Reference Numerals
[0127] 10 Semiconductor package 100 Carrier substrate 110 Main layer 120 Front organic pattern 120T Front trench 140 Scribe line 150 Rewiring layer 151 Multiple pads 152 Rewiring pattern 153 Rewiring insulating layer 160 Notch 180 Semiconductor chip 185 Solder 190 Molding layer 191 External connection terminal 200 Carrier substrate 210 Main layer 230 Back organic pattern 230T Back trench 270 Adhesion area
Claims
1. A first surface and a second surface that are opposite to each other, A main layer including the first surface and the second surface, A first trench on the first surface, A first organic pattern in the first trench, and a carrier substrate characterized by including the same.
2. The carrier substrate according to claim 1, wherein the coefficient of thermal expansion of the main layer is smaller than the coefficient of thermal expansion of the first organic pattern.
3. The carrier substrate according to claim 1, wherein the coefficient of thermal expansion of the main layer is larger than the coefficient of thermal expansion of the first organic pattern.
4. A second trench on the second surface, A second organic pattern in the second trench, and the carrier substrate according to claim 1, further characterized by including the same.
5. The carrier substrate according to claim 4, wherein the first organic pattern and the second organic pattern include different substances from each other.
6. The carrier substrate according to claim 4, wherein the coefficient of thermal expansion of the main layer is smaller than the coefficient of thermal expansion of the second organic pattern.
7. The carrier substrate according to claim 1, wherein in plan view, the first trench has a lattice shape.
8. The carrier substrate according to claim 1, wherein in plan view, the first trench has a concentric shape.
9. Providing a carrier substrate, Disposing a semiconductor chip on the carrier substrate, Forming a redistribution layer electrically connected to the semiconductor chip, and including: The carrier substrate, A first surface and a second surface that are opposite to each other, A main layer including the first surface and the second surface, A first trench on the first surface, A first organic pattern in the first trench, and a method for manufacturing a semiconductor package characterized by including the same.
10. The method for manufacturing a semiconductor package according to claim 9, wherein the coefficient of thermal expansion of the main layer is smaller than the coefficient of thermal expansion of the first organic pattern.
11. The method for manufacturing a semiconductor package according to claim 9, wherein the step of disposing the semiconductor chip on the carrier substrate is performed after the step of forming the redistribution layer.
12. The step of forming the redistribution layer, Forming a redistribution insulating layer on the first surface of the carrier substrate, Forming a redistribution pattern surrounded by the redistribution insulating layer, and including: The semiconductor chip is disposed on the redistribution layer and electrically connected to the redistribution pattern. The method of manufacturing a semiconductor package according to claim 10, wherein a coefficient of thermal expansion of the main layer is smaller than a coefficient of thermal expansion of the redistribution insulating layer.
13. The method of manufacturing a semiconductor package according to claim 9, wherein the step of forming the redistribution layer is performed after the step of disposing the semiconductor chip on the carrier substrate.
14. The semiconductor chip is disposed on the first surface of the carrier substrate. After the step of disposing the semiconductor chip and before the step of forming the redistribution layer, the method further includes a step of forming a molding layer for molding the semiconductor chip. The method of manufacturing a semiconductor package according to claim 13, wherein a coefficient of thermal expansion of the main layer is smaller than a coefficient of thermal expansion of the molding layer.
15. The method of manufacturing a semiconductor package according to claim 9, wherein the first organic pattern does not overlap with the semiconductor chip.
16. The semiconductor chip is disposed on the second surface of the carrier substrate. The method of manufacturing a semiconductor package according to claim 9, wherein the redistribution layer is formed on the second surface of the carrier substrate.
17. The carrier substrate further includes a second trench on the second surface, and a second organic pattern in the second trench. The method of manufacturing a semiconductor package according to claim 9.
18. A step of providing a carrier substrate; A step of forming a redistribution layer including a redistribution insulating layer and a redistribution pattern surrounded by the redistribution insulating layer on a front surface of the carrier substrate; A step of disposing a semiconductor chip on the redistribution layer so as to be electrically connected to the redistribution pattern. The carrier substrate includes the front surface and a back surface opposite to the front surface, a main layer including the back surface and the front surface, a front trench on the front surface, and a front organic pattern in the front trench. A coefficient of thermal expansion of the main layer is smaller than a coefficient of thermal expansion of the front organic pattern, and The method of manufacturing a semiconductor package, wherein the coefficient of thermal expansion of the main layer is smaller than a coefficient of thermal expansion of the redistribution insulating layer.
19. The method of manufacturing a semiconductor package according to claim 18, wherein, in a plan view, the front trench has a lattice shape.
20. Forming a molding layer for molding the redistribution layer and the semiconductor chip on the front surface of the carrier substrate; The method of manufacturing a semiconductor package according to claim 18, further comprising a step of debonding the carrier substrate from the redistribution layer, the semiconductor chip, and the molding layer.