Semiconductor device

Abstract

To improve the active clamp tolerance.SOLUTION: A semiconductor device 1 includes a semiconductor element 20 including a substrate including a transistor formation region 29 with a shape other than a tetragon, where a transistor is formed, and an electrode pad 21 on the transistor formation region 29, and a first bonding wire 41 connected to the electrode pad 21. The electrode pad 21 is provided to cover the center of gravity of the transistor formation region 29 in a plan view. In the plan view, the first bonding wire 41 overlaps the center of gravity of the transistor formation region 29 at a connection point with the electrode pad 21.SELECTED DRAWING: Figure 31A

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] As an example of a semiconductor device, a vertical MOSFET is known in which a drain electrode is formed on a surface on the side mounted on a lead frame, and a source electrode pad and a gate electrode pad are formed on a surface opposite to the surface on which the drain electrode is formed (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0004] [Summary] By the way, a semiconductor device may be connected to an inductive load and is required to have a function of absorbing energy released from this inductive load at turn-off. If the energy applied from the inductive load to the semiconductor device exceeds a predetermined value, the semiconductor device may fail due to a temperature rise. An index indicating how much energy accumulated in the inductive load can be absorbed is shown by the active clamp tolerance. As the value of the active clamp tolerance increases, more energy accumulated in the inductive load can be absorbed. Therefore, it is preferable that the value of the active clamp tolerance is large.

[0005] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the centroid of the transistor formation region in a plan view, and in the plan view, a connection region where the first connection member is connected to the electrode pad includes the centroid position of the transistor formation region.

[0006] The inventor of the present application focused on the connection position of the electrode pad to the transistor formation region of the semiconductor element of the first connection member connected to the semiconductor element for improving the active clamp tolerance of the semiconductor device. And the inventor of the present application obtained the finding that when the first connection member is connected to the position of the electrode pad corresponding to the centroid position of the transistor formation region, the active clamp tolerance is improved. In view of this point, the present semiconductor device is configured such that the connection region where the first connection member is connected to the electrode pad includes the centroid position of the transistor formation region. Therefore, the active clamp tolerance can be improved.

[0007] A semiconductor device according to an aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at a plurality of locations. The transistor formation region is divided into a plurality of divided regions having equal areas with each other according to the number of connection locations of the first connection member. The electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in a plan view thereof. In the plan view, the connection region where the first connection member is connected to the electrode pad includes the centroid position of each of the plurality of divided regions.

[0008] The inventor of the present application focused on the connection position of the electrode pad to the transistor formation region of the semiconductor element of the first connection member connected to the semiconductor element for improving the active clamp tolerance of the semiconductor device. And the inventor of the present application obtained the finding that when the first connection member is connected to the positions of the electrode pads corresponding to the centroid positions of the two divided regions obtained by dividing the transistor formation region into two divided regions having equal areas with each other, the active clamp tolerance is improved. In view of this point, the present semiconductor device is configured such that the connection region where the first connection member is connected to the electrode pad includes the centroid positions of the plurality of divided regions obtained by dividing the transistor formation region into two divided regions having equal areas with each other. Therefore, the active clamp tolerance can be improved.

[0009] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle on which transistors are formed, and a semiconductor element having electrode pads on the transistor formation region, and a plurality of first connection members connected to the electrode pads. The transistor formation region is divided into a plurality of divided regions having equal areas with respect to each other according to the number of the first connection members. The electrode pads are provided so as to cover the center of gravity of each of the plurality of divided regions in a plan view thereof. A connection region where the plurality of first connection members are respectively connected to the electrode pads in the plan view includes the center of gravity positions of each of the plurality of divided regions.

[0010] The inventor of the present application focused on the connection position of the electrode pads of the semiconductor element with respect to the transistor formation region of the first connection member connected to the semiconductor element for improving the active clamp tolerance of the semiconductor device. And the inventor of the present application has obtained a finding that when the first connection members are connected to the positions of the electrode pads corresponding to the center of gravity positions of the plurality of divided regions obtained by dividing the transistor formation region into a plurality of divided regions having equal areas with respect to each other according to the number of the first connection members, the active clamp tolerance is improved. In view of this point, in this semiconductor device, a connection region where a plurality of first connection members are connected to an electrode pad is configured to include the center of gravity positions of each of the plurality of divided regions obtained by dividing the connection region into a plurality of divided regions having equal areas with respect to each other according to the number of the first connection members. Therefore, the active clamp tolerance can be improved.

[0011] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view. In the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region. The substrate is formed with a plurality of trenches and a plurality of functional element formation regions arranged along each of the plurality of trenches and including a channel formation region serving as a current path. The plurality of functional element formation regions include a first functional element formation region in which the area of the channel formation region per unit area is relatively small, and a second functional element formation region in which the area of the channel formation region per unit area is relatively large. The first functional element formation region is provided in a region where heat generation should be suppressed among the plurality of functional element formation regions. A metal layer for electrically connecting the functional element formation region and the electrode pad is formed between the functional element formation region and the electrode pad. At least a portion of the metal layer facing the electrode pad is provided with one or more slits.

[0012] A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view. In the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region. The electrode pad has a first protective layer covering the interlayer insulating film, a first electrode layer covering the first protective layer, a second protective layer covering the first electrode layer, and a second electrode layer covering the second protective layer. The Vickers hardness of each of the first protective layer and the second protective layer is greater than the Vickers hardness of each of the first electrode layer and the second electrode layer.

[0013] A semiconductor device according to an aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, and a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view. In the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region. The first connection member is an aluminum wire wedge-bonded to the electrode pad.

[0014] A semiconductor device according to an aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed, and a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view. In the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region. The first connection member is a copper wire wedge-bonded to the electrode pad.

[0015] A semiconductor device according to an aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a rectangle in which transistors are formed and a control circuit region provided with a circuit for controlling the transistors, a temperature sensor provided in the control circuit region, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad. The transistor formation region has a first region and a second region having a larger area than the first region. The temperature sensor is disposed at a position adjacent to the transistor formation region. The electrode pad is provided so as to cover the centers of gravity of the first region and the second region in a plan view. In the plan view, a connection region where the first connection member is connected to the electrode pad includes the center of gravity position of the transistor formation region. A semiconductor device according to one aspect of the present disclosure includes a substrate including a transistor formation region having a shape other than a square in which transistors are formed, and a semiconductor element having an electrode pad on the transistor formation region, and a first bonding wire connected to the electrode pad. The electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view, and in the plan view, the first bonding wire overlaps the center of gravity of the transistor formation region at a connection point with the electrode pad.

Brief Description of Drawings

[0016]

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[0017] [Detailed description] Hereinafter, embodiments of a semiconductor device will be described with reference to the drawings. The following embodiments illustrate configurations and methods for embodying a technical idea, and do not limit the materials, shapes, structures, arrangements, dimensions, etc. of each component to those described below. The following embodiments can be variously modified.

[0018] In this specification, the state where "member A is connected to member B" includes the case where member A and member B are physically directly connected, and the case where member A and member B are indirectly connected via other members that do not affect the electrical connection state.

[0019] Similarly, the state where "member C is provided between member A and member B" includes the case where member A and member C, or member B and member C are directly connected, and the case where member A and member C, or member B and member C are indirectly connected via other members that do not affect the electrical connection state.

[0020] (First Embodiment) As shown in FIGS. 1(a) to 3, the semiconductor device 1 includes a lead frame 10, a semiconductor element 20 mounted on the lead frame 10, and a sealing resin 30 that seals a part of the lead frame 10 and the semiconductor element 20. The semiconductor element 20 includes, for example, a transistor connected to an inductive load and turns the transistor on and off. In the semiconductor device 1, for example, it is preferable that the on-resistance of the semiconductor element 20 is 30 mΩ or less. An example of the on-resistance of the semiconductor element 20 is 28 mΩ. The semiconductor device 1 is used, for example, in a control circuit of in-vehicle electrical components. Examples of in-vehicle electrical components include an engine, an air conditioner, a steering device, and the like. As for the size of the sealing resin 30, the dimension in the lateral direction X is about 6.6 mm, the dimension in the longitudinal direction Y is about 6.1 mm, and the dimension in the thickness direction Z is about 2.3 mm. Note that the semiconductor device 1 may be used in a control device for equipment other than in-vehicle electrical components (for example, an outdoor unit of an air conditioner).

[0021] The sealing resin 30 has a first side surface 31 and a second side surface 32 that are side surfaces in the lateral direction X, a third side surface 33 and a fourth side surface 34 that are side surfaces in the longitudinal direction Y, and a fifth side surface 35 and a sixth side surface 36 that are side surfaces in the thickness direction Z. The sealing resin 30 is formed of a thermosetting resin in which a filler is dispersedly blended. An example of the thermosetting resin is an epoxy resin. An example of the filler is a silica filler. An example of the blending ratio of the filler with respect to the epoxy resin is 85 to 90% by volume. It is preferable that the sealing resin 30 is made of a material having a linear expansion coefficient greater than 10 ppm / K and less than 15 ppm / K. The linear expansion coefficient of the sealing resin 30 can be changed, for example, by the blending ratio of the filler. In the present embodiment, the linear expansion coefficient of the sealing resin 30 is 12 ppm / K.

[0022] The lead frame 10 includes a first lead frame 11, a second lead frame 12, and a third lead frame 13. Each of the lead frames 11, 12, 13 is formed of, for example, copper (Cu). A nickel (Ni) plating is applied to the outer surface of each of the lead frames 11, 12, 13. FIGS. 3 and 4 show an example of a plating layer 14 of the first lead frame 11 and the second lead frame 12.

[0023] As shown in FIGS. 1(a) and 2, the first lead frame 11 is configured to include an output terminal OUT. It has a first island portion 11a and a first terminal portion 11b. The first island portion 11a and the first terminal portion 11b are integrally formed. Alternatively, the first island portion 11a and the first terminal portion 11b may be formed separately and then connected to each other.

[0024] The first island portion 11a is formed in a substantially rectangular shape in a plan view. A part of the first island portion 11a in the longitudinal direction Y protrudes in the longitudinal direction Y from the third side surface 33 of the sealing resin 30. As shown in FIGS. 1(b) and 1(c), the first island portion 11a is exposed from the sixth side surface 36 of the sealing resin 30. The first island portion 11a has a main body portion 11c located within the sealing resin 30, a narrow portion 11d provided at a position near the third side surface 33 within the sealing resin 30, and a tip portion 11e extending in the longitudinal direction Y from the narrow portion 11d. A part of the tip portion 11e protrudes from the third side surface 33 of the sealing resin 30. In this embodiment, the dimension of the tip portion 11e in the lateral direction X is smaller than the dimension of the main body portion 11c in the lateral direction X. A concave portion 11f that is recessed toward the third side surface 33 is provided at the leading edge of the tip portion 11e in the longitudinal direction Y. Since the narrow portion 11d forms a concave portion in the lateral direction X in the first island portion 11a, the adhesion with the sealing resin 30 is improved and the movement of the first island portion 11a in the longitudinal direction Y with respect to the sealing resin 30 can be suppressed.

[0025] As shown in FIGS. 1(a) and 1(c), the area of the portion of the main body portion 11c of the first island portion 11a that is exposed from the sixth side surface 36 of the sealing resin 30 is smaller than the area of the main body portion 11c in a plan view. More specifically, the portion of the main body portion 11c on the fifth side surface 35 side of the sealing resin 30 in the thickness direction Z is longer in the lateral direction X than the portion of the main body portion 11c on the sixth side surface 36 side of the sealing resin 30. Thereby, the portion of the main body portion 11c on the fifth side surface 35 side of the sealing resin 30 is sandwiched by the sealing resin 30 in the thickness direction Z, so that the movement of the first lead frame 11 in the thickness direction Z can be suppressed.

[0026] Note that the shape of the first island portion 11a can be arbitrarily changed. For example, at least one of the narrow portion 11d and the concave portion 11f may be omitted. Also, the dimension of the tip portion 11e in the lateral direction X may be equal to or greater than the dimension of the main body portion 11c in the lateral direction X. Further, the tip portion 11e may constitute the output terminal OUT. Also, the area of the portion of the main body portion 11c of the first island portion 11a that is exposed from the sixth side surface 36 of the sealing resin 30 and the area of the main body portion 11c in plan view may be equal to each other.

[0027] As shown in FIG. 4, the first terminal portion 11b that constitutes the output terminal OUT protrudes in the longitudinal direction Y from the fourth side surface 34 of the sealing resin 30. The portion of the first terminal portion 11b that protrudes from the fourth side surface 34 of the sealing resin 30 is located on the fifth side surface 35 side of the sealing resin 30 rather than the first island portion 11a in the thickness direction Z. The first terminal portion 11b has a first bent portion 11g that is bent toward the fifth side surface 35 from the portion connected to the first island portion 11a, an inclined portion 11h that inclines so as to extend toward the fifth side surface 35 as it goes toward the fourth side surface 34 of the sealing resin 30, a second bent portion 11i that is bent again near the fourth side surface 34 of the sealing resin 30, and a tip portion 11j that is orthogonal to the thickness direction Z and extends in the longitudinal direction Y. A part of the tip portion 11j protrudes from the fourth side surface 34 of the sealing resin 30. In the present embodiment, the first bent portion 11g, the inclined portion 11h, the second bent portion 11i, and the tip portion 11j are integrally formed.

[0028] As shown in FIG. 2, the second lead frame 12 constitutes the input terminal IN. The second lead frame 12 is disposed on the first side surface 31 side and the fourth side surface 34 side of the sealing resin 30. The second lead frame 12 has a second island portion 12a and a second terminal portion 12b. The second island portion 12a and the second terminal portion 12b are integrally formed. Note that the second island portion 12a and the second terminal portion 12b may be connected to each other after being individually formed.

[0029] The second island portion 12a is formed in a rectangular shape in which the length in the lateral direction X is longer than the length in the longitudinal direction Y in plan view. The second island portion 12a is arranged closer to the fourth side surface 34 of the sealing resin 30 than the first island portion 11a in the longitudinal direction Y. The second island portion 12a is arranged closer to the first side surface 31 of the sealing resin 30 than the first terminal portion 11b in the lateral direction X. The second island portion 12a is arranged closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a in the thickness direction Z.

[0030] The second terminal portion 12b extends in the longitudinal direction Y from a portion closer to the first side surface 31 of the sealing resin 30 in the second island portion 12a. The second terminal portion 12b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the longitudinal direction Y of the portion protruding from the fourth side surface 34 of the sealing resin 30 in the second terminal portion 12b is longer than the length in the longitudinal direction Y of the portion protruding from the fourth side surface 34 of the sealing resin 30 in the first terminal portion 11b. The second terminal portion 12b is formed by being bent so that the tip portion thereof is at the same position as that of the first island portion 11a in the thickness direction Z.

[0031] The third lead frame 13 constitutes a ground terminal GND. The third lead frame 13 has a third island portion 13a and a third terminal portion 13b. The third island portion 13a and the third terminal portion 13b are integrally formed. Incidentally, after the third island portion 13a and the third terminal portion 13b are separately formed, they may be connected to each other.

[0032] The third island portion 13a is formed in a rectangular shape in which the length in the lateral direction X is longer than the length in the longitudinal direction Y in plan view. The third island portion 13a is arranged closer to the fourth side surface 34 of the sealing resin 30 than the first island portion 11a in the longitudinal direction Y. The third island portion 13a is arranged closer to the second side surface 32 of the sealing resin 30 than the first terminal portion 11b in the lateral direction X. The third island portion 13a is arranged closer to the fifth side surface 35 of the sealing resin 30 than the first island portion 11a in the thickness direction Z (see FIG. 3).

[0033] The third terminal portion 13b extends in the longitudinal direction Y from a portion near the second side surface 32 of the sealing resin 30 in the third island portion 13a. The third terminal portion 13b protrudes from the fourth side surface 34 of the sealing resin 30. The length in the longitudinal direction Y of the portion protruding from the fourth side surface 34 of the sealing resin 30 in the third terminal portion 13b is longer than the length in the longitudinal direction Y of the portion protruding from the fourth side surface 34 of the sealing resin 30 in the first terminal portion 11b, and is equal to the length in the longitudinal direction Y of the portion protruding from the fourth side surface 34 of the sealing resin 30 in the second terminal portion 12b. The third terminal portion 13b is formed by being bent so that its tip end portion is at the same position in the thickness direction Z of the first island portion 11a (see FIG. 3).

[0034] As shown in FIGS. 2 and 3, the semiconductor element 20 is mounted on the surface 11x of the main body portion 11c of the first lead frame 11. Specifically, solder SD is applied to the surface 11x of the main body portion 11c. The semiconductor element 20 is placed on the solder SD. As shown in FIG. 2, the semiconductor element 20 is arranged in a portion of the main body portion 11c near the fourth side surface 34 of the sealing resin 30 in the longitudinal direction Y (near the second island 12a and the third island 13a in the longitudinal direction Y). The semiconductor element 20 is arranged at the center of the main body portion 11c in the lateral direction X.

[0035] The semiconductor element 20 of the present embodiment is a power MOSFET or an IGBT. The semiconductor element 20 is formed in a rectangular shape in which the lateral direction X is the longitudinal direction with respect to the longitudinal direction Y in plan view. As the size of the semiconductor element 20 of the present embodiment, the dimension in the longitudinal direction Y is 2.25 mm, and the dimension in the lateral direction X is 2.68 mm. Note that the shape or dimension of the semiconductor element 20 in plan view is not limited to this. For example, the semiconductor element 20 may be formed in a square in which the dimension in the longitudinal direction Y and the dimension in the lateral direction X are equal to each other.

[0036] On the surface 20x of the semiconductor element 20, a source pad 21 which is an example of an electrode pad and a gate pad 22 which is an example of a control electrode pad are provided. On the back surface 20y of the semiconductor element 20 (see FIG. 3), that is, on the surface of the semiconductor element 20 facing the first island portion 11a, a drain electrode is provided. The drain electrode is electrically connected to the first island portion 11a (first lead frame 11) via a solder SD.

[0037] One end of a first wire 41 which is an example of a connection member is connected to the source pad 21. The other end of the first wire 41 is connected to the third island portion 13a of the third lead frame 13. The first wire 41 is connected to the source pad 21 and the third island portion 13a respectively by, for example, wedge bonding. In this embodiment, the number of the first wires 41 is one. The first wire 41 of this embodiment is an aluminum wire in which aluminum (Al) is used. The wire diameter of the first wire 41 is preferably, for example, 100 μm or more. The wire diameter of the first wire 41 is more preferably, for example, 300 μm to 400 μm. In this embodiment, the wire diameter of the first wire 41 is about 300 μm. Note that the first wire 41 may be a copper wire in which copper (Cu) is used.

[0038] As shown in FIG. 2, one end of a second wire 42 is connected to the gate pad 22. The other end of the second wire 42 is connected to the second island portion 12a of the second lead frame 12. The second wire 42 is connected to the gate pad 22 and the second island portion 12a respectively by, for example, wedge bonding. In this embodiment, the number of the second wires 42 is one. As the material of the second wire 42, for example, aluminum (Al) or copper (Cu) is used. Aluminum is used for the second wire 42 of this embodiment. The wire diameter of the second wire 42 is smaller than the wire diameter of the first wire 41. The wire diameter of the second wire 42 is, for example, 125 μm.

[0039] As shown in FIGS. 2 and 5, the semiconductor element 20 has a substrate 50 that is rectangular in plan view. The substrate 50 has a first side surface 51 and a second side surface 52 along the longitudinal direction Y, and a third side surface 53 and a fourth side surface 54 along the lateral direction X. The first side surface 51 is the side surface of the substrate 50 on the first side surface 31 side of the encapsulating resin 30, the second side surface 52 is the side surface of the substrate 50 on the second side surface 32 side of the encapsulating resin 30, the third side surface 53 is the side surface of the substrate 50 on the third side surface 33 side of the encapsulating resin 30, and the fourth side surface 54 is the side surface of the substrate 50 on the fourth side surface 34 side of the encapsulating resin 30.

[0040] The semiconductor element 20 has a switching circuit 23 having a plurality of power MISFETs (Metal Insulator Semiconductor Field Effect Transistors) as an example of functional elements formed in the surface layer portion of the substrate 50. The semiconductor element 20 further has, as an example of a control circuit for controlling the switching circuit 23, an overcurrent protection (OCD: Over Current Detection) circuit 24, a thermal shutdown (TSD: Thermal Shut Down) circuit 25, an under-voltage lockout (UVLO: Under Voltage Lock Out) circuit 26, a temperature sensor 27, and a current sensor 28. The overcurrent protection circuit 24, the thermal shutdown circuit 25, the under-voltage lockout circuit 26, the temperature sensor 27, and the current sensor 28 are all formed in the surface layer portion of the substrate 50. That is, the semiconductor element 20 is an IPS (Intelligent Power Switch) in which the switching circuit 23 (power MISFET), the overcurrent protection circuit 24, the thermal shutdown circuit 25, the under-voltage lockout circuit 26, the temperature sensor 27, and the current sensor 28 are formed in the surface layer portion of the common substrate 50.

[0041] The switching circuit 23 is formed within the active region 29 set on the substrate 50. The active region 29 is formed in a substantially L shape so as to avoid the gate pad 22 and the temperature sensor 27 in a plan view. More specifically, the active region 29, in terms of its shape in a plan view, has a first side 29a closest to the first side surface 51 of the substrate 50, a second side 29b closest to the third side surface 53 of the substrate 50, a third side 29c closest to the second side surface 52 of the substrate 50, and a fourth side 29d closest to the fourth side surface 54 of the substrate 50, as well as a fifth side 29e and a sixth side 29f that constitute the notch portion of the active region 29. The fifth side 29e is a side extending in the vertical direction Y, and the sixth side 29f is a side extending in the horizontal direction X. One end of the first side 29a is connected to the second side 29b, and the other end of the first side 29a is connected to the sixth side 29f. The end of the second side 29b opposite to the first side 29a is connected to the third side 29c. The end of the third side 29c opposite to the second side 29b is connected to the fourth side 29d. The end of the fourth side 29d opposite to the third side 29c is connected to the fifth side 29e. The end of the fifth side 29e opposite to the fourth side 29d is connected to the sixth side 29f. As can be seen from FIG. 5, the length of the first side 29a is shorter than the length of the third side 29c, and the length of the second side 29b is longer than the length of the fourth side 29d. The active region 29 is covered by the source pad 21. The source pad 21 is formed in a substantially L shape in a plan view. More specifically, the source pad 21 is provided closer to the third side surface 53 on the substrate 50. The source pad 21 is formed in a substantially L shape in a plan view by cutting out the region on the substrate 50 where the gate pad 22 is disposed, that is, the region on the first side surface 51 side and the second side surface 52 side of the substrate 50. In the present embodiment, the shape of the source pad 21 is a similar shape to the shape of the active region 29. Note that the shape of the source pad 21 and the shape of the active region 29 can be arbitrarily changed. In one example, the shape of the source pad 21 may be different from the shape of the active region 29.

[0042] Also, as shown in FIGS. 2 and 5, in the semiconductor element 20, a control circuit region 29LG is formed so as to avoid the source pad 21 and the gate pad 22. The control circuit region 29LG includes a first portion on the fourth side surface 54 side of the substrate 50 with respect to the source pad 21 and the gate pad 22, and a second portion extending from the first portion toward the third side surface 53 side of the substrate 50. This second portion is formed between the gate pad 22 and the source pad 21 in the lateral direction X. In the control circuit region 29LG, an overcurrent protection circuit 24, an overheat protection circuit 25, an under-voltage malfunction prevention circuit 26, and a temperature sensor 27 are provided. The overcurrent protection circuit 24, the overheat protection circuit 25, and the under-voltage malfunction prevention circuit 26 are provided in a region on the fourth side surface 54 side of the substrate 50 with respect to the active region 29 in the control circuit region 29LG. The overcurrent protection circuit 24, the overheat protection circuit 25, and the under-voltage malfunction prevention circuit 26 are arranged in a row in the lateral direction X. The under-voltage malfunction prevention circuit 26 is arranged on the first side surface 51 side of the substrate 50 with respect to the overcurrent protection circuit 24 and the overheat protection circuit 25 in the control circuit region 29LG. A part of the under-voltage malfunction prevention circuit 26 is adjacent to the gate pad 22 in the vertical direction Y.

[0043] The temperature sensor 27 is provided in the control circuit region 29LG. The position of the temperature sensor 27 is set to the position where the temperature becomes the highest in a region outside the source pad 21 when the semiconductor device 1 is driven. The position of the temperature sensor 27 is set based on, for example, a temperature distribution of the substrate 50 when the semiconductor device 1 is driven by simulation or the like. In the present embodiment, the temperature sensor 27 is arranged near the intersection of the fifth side 29e and the sixth side 29f of the active region 29.

[0044] The current sensor 28 is arranged between the overcurrent protection circuit 24 and the source pad 21 on the substrate 50. The current sensor 28 is provided in the active region 29. The current sensor 28 is arranged closer to the overcurrent protection circuit 24 than the source pad 21 in the vertical direction Y.

[0045] Next, with reference to FIG. 6, the electrical configuration of the semiconductor device 1 will be described. FIG. 6 shows an example of the circuit configuration of the semiconductor device 1. FIG. 6 shows an example in which the battery 2 and the inductive load 3 are externally connected to the output terminal OUT and the ground terminal GND. Further, FIG. 6 shows an example in which the inductive load 3 is a relay including the coil L.

[0046] The switching circuit 23 is connected between the output terminal OUT and the ground terminal GND. The switching circuit 23 includes the above-mentioned power MISFET (hereinafter, “MISFET23a”), which is an example of a power transistor. MISFET23a has a gate terminal G as a control terminal, a drain terminal D, and a source terminal S. The switching circuit 23 is provided such that the drain terminal D of MISFET23a is connected to the output terminal OUT and the source terminal S is connected to the ground terminal GND. Note that the switching circuit 23 includes a plurality of power MISFETs, but only one MISFET23a is shown in FIG. 6 for convenience of explanation.

[0047] An input wiring 43 is connected between the input terminal IN and the gate terminal G of MISFET23a. A ground wiring 44 is connected between the ground terminal GND and the source terminal S of MISFET23a. Between the input wiring 43 and the ground wiring 44, a diode D1, a first resistor R1, an overcurrent protection circuit 24, an overheat protection circuit 25, a low-voltage malfunction prevention circuit 26, and a second resistor R2 are connected in parallel to each other in this order from the input terminal IN side. A third resistor R3 is connected in series between the first resistor R1 and the overcurrent protection circuit 24 in the input wiring 43. A fourth resistor R4 is connected in series between the low-voltage malfunction prevention circuit 26 and the second resistor R2 in the input wiring 43.

[0048] The current sensor 28 is electrically connected to the overcurrent protection circuit 24. The current sensor 28 detects, for example, the current flowing through the switching circuit 23. The current value detected by the current sensor 28 is provided to the overcurrent protection circuit 24. The overcurrent protection circuit 24 is driven based on the current value provided from the current sensor 28. In one example, when a current (overcurrent) equal to or greater than a predetermined value flows through the switching circuit 23 due to a short circuit, the overcurrent protection circuit 24 limits the current and protects the circuit.

[0049] The temperature sensor 27 is electrically connected to the overheat protection circuit 25. The temperature sensor 27 detects the temperature of the substrate 50. The temperature of the substrate 50 detected by the temperature sensor 27 is provided to the overheat protection circuit 25. The overheat protection circuit 25 is driven based on the temperature of the substrate 50 provided from the temperature sensor 27. In one example, when the temperature of the substrate 50 becomes equal to or greater than a predetermined value, the overheat protection circuit 25 stops the switching circuit 23 by the overcurrent protection circuit 24 and protects the circuit. As a result, the temperature rise of the substrate 50 is suppressed.

[0050] The low-voltage malfunction prevention circuit 26 is configured to prohibit the switching circuit 23 from operating when the potential difference between the input wiring 43 and the ground wiring 44 is equal to or less than a predetermined value, and to permit the switching circuit 23 to operate when the potential difference is greater than the predetermined value.

[0051] A clamp diode D2 is electrically connected between the gate terminal G and the drain terminal D of the MISFET 23a. The clamp diode D2 is formed by reversely biasing two diodes. The two diodes may include a Zener diode. Note that the number of diodes constituting the clamp diode D2 can be arbitrarily changed.

[0052] When the input terminal IN is at a high level, the MISFET 23a of the semiconductor device 1 turns on, and current flows from the battery 2 through the coil L of the inductive load 3 and the MISFET 23a. Next, when the input terminal IN changes from a high level to a low level, the MISFET 23a turns off. At this time, due to the current flowing through the inductive load 3, the voltage Vout at the output terminal OUT rises. The voltage Vout at the output terminal OUT rises to a voltage (for example, 48V) determined by the battery 2 through the clamp diode D2. As the output voltage Vout rises, the current flowing through the resistor R2 via the clamp diode D2 causes the gate voltage of the MISFET 23a to rise slightly. As a result, a current flows through the MISFET 23a. In this way, a state is achieved in which a gate voltage is generated and a small amount of current flows through the MISFET 23a, that is, an active clamp state. This active clamp state continues until the current from the battery 2 to the MISFET 23a becomes 0A, and the output voltage Vout drops to the voltage of the battery 2.

[0053] 〔Connection to the source pad of the first wire〕 FIGS. 7 and 8 are enlarged plan views showing a part of the substrate 50. In FIG. 7, the active region 29 is shown by a solid line, and the source pad 21 is shown by a two-dot chain line. In FIG. 8, the active region 29 is shown by a broken line, and the source pad 21 is shown by a solid line.

[0054] The inventor of the present application focused on the connection position of the first wire 41 connected to the source pad 21 of the semiconductor element 20 for improving the active clamp tolerance Eac of the semiconductor device 1. Then, the inventor of the present application obtained the finding that when the first wire 41 is connected to a connection position including the centroid position GC of the active region 29 of the semiconductor element 20, the active clamp tolerance Eac is improved. In view of this point, in the present embodiment, the first wire 41 is connected to the source pad 21 so as to overlap the centroid position GC of the active region 29.

[0055] Here, the centroid position GC of the active region 29 is obtained as follows. As shown in FIG. 7, first, the active region 29 is divided into a first region RA1 and a second region RA2, which are two regions. The first region RA1 and the second region RA2 are preferably rectangular regions. Next, the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2 are obtained. As shown in FIG. 7, since the first region RA1 and the second region RA2 are each rectangular, the centroid position GA1 of the first region RA1 is the intersection of the diagonals of the first region RA1, and the centroid position GA2 of the second region RA2 is the intersection of the diagonals of the second region RA2. Next, the area SA1 of the first region RA1 and the area SA2 of the second region RA2 are obtained respectively. Next, on the line segment LA connecting the centroid position GA1 and the centroid position GA2, based on the relationship between the distance DA1 between the centroid position GA1 and the centroid position GC of the active region 29, the distance DA2 between the centroid position GA2 and the centroid position GC of the active region 29, the area SA1 of the first region RA1, and the area SA2 of the second region RA2, the centroid position GC of the active region 29 is obtained. Specifically, the ratio of the distance DA2 to the distance DA1 (DA2 / DA1) is equal to the inverse ratio of the ratio of the area SA2 of the second region RA2 to the area SA1 of the first region RA1 (SA1 / SA2) (DA2 / DA1 = SA1 / SA2). Thus, by obtaining at least one of the distances DA1 and DA2, the centroid position GC of the active region 29 can be obtained. Also, as shown in FIG. 7, the source pad 21 is provided so as to cover the centroid position GC of the active region 29.

[0056] The dashed-dotted line region RX shown in Fig. 7 indicates the tool head for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown) (hereinafter referred to as wedge RX). The wedge bonding apparatus moves the wedge RX so that the center of the wedge RX is positioned on the centroid position GC of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap the centroid position GC of the active region 29 as shown in Fig. 8. That is, the contact region (wedge RX) of the first wire 41 with the source pad 21 includes the centroid position GC of the active region 29. In the present embodiment, the center position of the connection region (wedge RX) of the first wire 41 to the source pad 21 coincides with the centroid position GC of the active region 29.

[0057] Also, as shown in Figs. 2 and 8, the connection portion 41a connected to the source pad 21 in the first wire 41 extends in a direction different from the lateral direction X and the longitudinal direction Y in a plan view of the semiconductor device 1. In the present embodiment, the connection portion 41a extends from the semiconductor element 20 toward the third island portion 13a.

[0058] As shown in Fig. 8, the two-dot chain line region RS surrounding the connection portion 41a of the first wire 41 is a margin considering the variation in the wire diameter of the first wire 41 and the variation in the connection position of the first wire 41 to the source pad 21 by the wedge bonding apparatus. That is, the connection portion 41a of the first wire 41 is always positioned within the region RS. For example, the region RS may be set as an opening 89 (both shown in Fig. 9) in which the surface protection film 88 is opened from the source pad 21. The opening 89 is preferably set to be wider than the region RS.

[0059] That is, in the first embodiment, as shown in Fig. 7, the active region 29 has a substantially L shape formed by combining a small rectangular first region RA1 and a large rectangular second region RA2. The first wire 41 as a connection member and the source pad 21 are connected to each other at a position on the line segment LA connecting the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2.

[0060] Further, the semiconductor element 20 includes a transistor. The semiconductor device includes a second lead frame (external control terminal) 12 for controlling on and off of the transistor, and a third lead frame (external terminal) 13 connected to a first wire 41 as a connection member. As shown in FIG. 2, the second lead frame 12 is disposed on the side of the small square-shaped first region RA1, and the third lead frame 13 is disposed on the side of the large square-shaped second region RA2. In other words, the second lead frame 12 is disposed at a position closer to the first region RA1 than the second region RA2, and the third lead frame 13 is disposed at a position closer to the second region RA2 than the first region RA1.

[0061] Also, as shown in FIGS. 2 and 5, the semiconductor element 20 includes a gate pad (control metal pad) 22 connected to the second lead frame (external control terminal) 12. The gate pad 22 is disposed in a square-shaped region where no transistor is located among the regions surrounded by the extension line of the side (first side 29a) of the small square-shaped first region RA1 and the extension line of the side (fourth side 29d) of the large square-shaped second region RA2.

[0062] Also, as shown in FIG. 5, the source pad 21 is also substantially L-shaped. The source pad 21 is formed across the small square-shaped first region RA1 and the large square-shaped second region RA2 included in the active region 29. The source pad 21 is configured such that the first side 29a, which is the most distant from the second region RA2 in the source pad 21, coincides with the position where the gate pad 22 is provided in the lateral direction X. Specifically, as shown in FIG. 5, the gate pad 22 has a left side and a right side in the lateral direction X, and the left side of the gate pad 22 extends at a position more distant from the second region RA2 than the right side of the gate pad 22 in the lateral direction X. The first side 29a of the source pad 21 coincides with the position between the left side and the right side of the gate pad 22 in the lateral direction X.

[0063] Also, the temperature sensor 27 is disposed between the gate pad 22 and the source pad 21. 〔Structure of MISFET〕 Referring to FIGS. 9 to 11, the detailed structure of the MISFET 23a will be described.

[0064] As shown in FIG. 9, the substrate 50 on which the MISFET 23a is formed is, for example, a silicon substrate. The substrate 50 includes an n + -type semiconductor substrate 61 and an n - -type epitaxial layer 62 formed on the semiconductor substrate 61. The drain region 63 is formed by the semiconductor substrate 61 and the epitaxial layer 62. The surface of the substrate 50 is formed by the epitaxial layer 62, and the back surface of the substrate 50 is formed by the semiconductor substrate 61. An example of the thickness of the epitaxial layer 62 is 9.5 μm.

[0065] On the surface side of the substrate 50, a source pad 21 is formed, and on the back surface side of the substrate 50, a drain electrode 64 is formed. On the surface side of the active region 29 of the substrate 50, a plurality of trench gate structures 65 are provided. The plurality of trench gate structures 65 are formed in the surface layer portion of the epitaxial layer 62 and include a trench 66 formed by digging down the epitaxial layer 62, and a gate electrode 68 and an embedded electrode 69 embedded in the trench 66 with a gate insulating film 67 interposed therebetween.

[0066] As shown in FIG. 10, the gate electrode 68 and the embedded electrode 69 are separated (insulated) by the gate insulating film 67 in the depth direction of the trench 66. The gate electrode 68 is disposed on the opening side of the trench 66, and the embedded electrode 69 is disposed on the bottom side of the trench 66 rather than the gate electrode 68. An example of the gate insulating film 67 is a silicon oxide film.

[0067] The gate insulating film 67 includes a thick film portion 67a in contact with the embedded electrode 69 and a thin film portion 67b in contact with the gate electrode 68. One surface (the surface on the drain region 63 side) and the opposite surface of the thick film portion 67a of the gate insulating film 67 are formed along the inner wall of the trench 66, and it has a laminated structure in which a silicon oxide film with a low density is laminated on a silicon oxide film with a high density. The thickness T1 of the thick film portion 67a of the gate insulating film 67 is thicker than the thickness T2 of the thin film portion 67b (T2 < T1). The thickness T1 of the thick film portion 67a is thicker than the thickness T3 of the separation portion 67c that separates the gate electrode 68 and the embedded electrode 69 in the gate insulating film 67 (T3 < T1). The thickness T3 of the separation portion 67c is thicker than the thickness T2 of the thin film portion 67b (T2 < T3 < T1). Note that the thickness T1 of the thick film portion 67a, the thickness T2 of the thin film portion 67b, and the thickness T3 of the separation portion 67c can each be arbitrarily changed. For example, the thickness T2 of the thin film portion 67b and the thickness T3 of the separation portion 67c may be equal to each other.

[0068] The gate electrode 68 is made of, for example, polysilicon. A recess 68a that opens toward the embedded electrode 69 is formed at the lower end portion of the gate electrode 68. The upper end portion 69a of the embedded electrode 69 is accommodated in the recess 68a. Thus, the upper end portion 69a of the embedded electrode 69 faces the gate electrode 68 through the thin film portion 67b of the gate insulating film 67. The embedded electrode 69 is made of, for example, polysilicon. In this embodiment, the embedded electrode 69 is electrically floating from the outside by being covered with the thick film portion 67a and the separation portion 67c of the gate insulating film 67. Note that the embedded electrode 69 may have the same potential (ground potential) as the source pad 21. In a cross-sectional view of the embedded electrode 69, the width dimension D1 of the upper end portion 69a is smaller than the width dimension D2 of the portion below the upper end portion 69a (on the back surface side of the substrate 50) in the embedded electrode 69.

[0069] In FIGS. 9 and 10, an example is shown in which the trench 66 is formed substantially perpendicular to the surface of the epitaxial layer 62. However, in the depth direction of the trench 66, a tapered trench 66 may be formed in a cross-sectional view in which the opening width gradually narrows toward the bottom of the trench 66. Also, in FIGS. 9 and 10, an example is shown in which the bottom of the trench 66 has a flat portion parallel to the surface of the epitaxial layer 62. However, the bottom of the trench 66 may be formed in a curved shape outward from the side surface of the trench 66.

[0070] On the sides (both side surfaces) of the trench gate structure 65, an n + -type source region 70, a p - -type body region 71, and a drain region 63 (epitaxial layer 62) are provided in this order in the depth direction from the surface side of the substrate 50. The source region 70, the body region 71, and the drain region 63 are all formed so as to be in contact with the trench gate structure 65, and face the gate electrode 68 with the gate insulating film 67 interposed therebetween. Further, the drain region 63 faces the embedded electrode 69 with the gate insulating film 67 interposed therebetween.

[0071] The body region 71 is shared by one trench gate structure 65 and the other trench gate structure 65 between adjacent trench gate structures 65. The source region 70 is provided so as to be exposed from the surface of the body region 71. The planar shape of the source region 70 corresponds to the planar shape of the channel formation region 72 that serves as a current path. Below the source region 70, the body region 71 that forms the side surface of the trench gate structure 65 is the channel formation region 72. The formation of the channel in the channel formation region 72 is controlled by the trench gate structure 65 (gate electrode 68).

[0072] FIG. 11 is an example of the planar structure of the epitaxial layer 62 of the MISFET 23a. As shown in FIG. 11, in the body region 71 (see FIG. 10) sandwiched between adjacent trench gate structures 65, a plurality of source regions 70 are alternately formed on one side and the other side of the trench gate structure 65. The area of each source region 70 is the same. Thus, in the MISFET 23a of this embodiment, the ratio of the area of the channel formation region 72 per unit area is about 50%.

[0073] Here, the case where the channel formation region 72 exists throughout the region between each trench gate structure 65 is defined as the ratio of the area of the channel formation region 72 per unit area being 100%. Further, the area of the channel formation region 72 is defined as the area of the region that becomes the current path in plan view. Specifically, the area of the channel formation region 72 is defined as the opposing area in which the source region 70 faces the drain region 63 (epitaxial layer 62) with the body region 71 interposed therebetween in plan view. Also, the ratio of the area of the channel formation region 72 per unit area is the ratio of the area of the channel formation region 72 occupying the region defined in advance between the trench gate structures 65. The region defined in advance is a region of a predetermined area obtained by multiplying the width between the trench gate structures 65 and an arbitrary length along the length direction of the trench gate structure 65.

[0074] Also, between the plurality of trench gate structures 65, a p + -type body contact region 73 is formed so as to be exposed from the surface of the portion other than the source region 70 in the body region 71. The body contact region 73 is formed so as to be in contact with the side surface of the trench gate structure 65, and a part thereof faces the gate electrode 68 with the gate insulating film 67 interposed therebetween. In this embodiment, the depth of the body contact region 73 and the depth of the source region 70 are equal to each other.

[0075] Note that the depths of the body contact region 73 and the source region 70 can be arbitrarily changed. In one example, the depth of the body contact region 73 may be deeper than the depth of the source region 70. Also, the body contact region 73 may be omitted from the MISFET 23a. In this case, the body region 71 is exposed from the surface of the epitaxial layer 62.

[0076] Also, as shown in FIG. 9, a DTI (Deep Trench Isolation) structure 90 as an element isolation structure for partitioning the region where the MISFET 23a is formed from other regions is formed in the epitaxial layer 62. For example, the DTI structure 90 is formed in a substantially annular shape in a plan view (hereinafter simply referred to as "plan view") of the surface of the epitaxial layer 62 viewed from the normal direction. The DTI structure 90 has a trench 91 formed by digging down the epitaxial layer 62 and an insulator 92 embedded in the trench 91 with the gate insulating film 67 interposed therebetween. An example of the insulator 92 is polysilicon. Note that the insulator 92 may be silicon oxide. In the present embodiment, an example in which the DTI structure 90 is formed as the element isolation structure has been described, but the element isolation structure may use a diffusion isolation method including an annular p-type diffusion region that partitions the region where the MISFET 23a is formed, that is, a pn connection separation method.

[0077] On the surface of the epitaxial layer 62, an interlayer insulating film 74 is formed. The interlayer insulating film 74 includes at least one of a silicon oxide film and a silicon nitride film. The interlayer insulating film 74 has a laminated structure in which a first interlayer insulating film 75, a second interlayer insulating film 76, a third interlayer insulating film 77, and a fourth interlayer insulating film 78 are laminated in order from the surface side of the epitaxial layer 62. The first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 are formed of an insulator such as silicon oxide or silicon nitride, for example. The first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 may be formed by, for example, USG (HDP-USG: High Density Plasma-CVD-Undoped Silica Glass) by a high density plasma CVD method. The first interlayer insulating film 75 covers the surface of the epitaxial layer 62. The first interlayer insulating film 75 enters a recess 79 formed by the height difference between the upper surface of the gate electrode 68 and the surface of the epitaxial layer 62. The thickness TF1 of the first interlayer insulating film 75 is, for example, 13500 Å, the thickness TF2 of the second interlayer insulating film 76 is, for example, 8000 Å, the thickness TF3 of the third interlayer insulating film 77 is, for example, 13500 Å, and the thickness TF4 of the fourth interlayer insulating film 78 is, for example, 10000 Å.

[0078] On the first interlayer insulating film 75, a first source electrode 80 is formed as a first metal (first metal layer). The first source electrode 80 is an electrode film including one or more metal species selected from the group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The thickness of the first source electrode 80 is, for example, 4000 Å. The first source electrode 80 is electrically connected to the source region 70 and the body contact region 73 via corresponding contacts 81. The first source electrode 80 is covered by the second interlayer insulating film 76.

[0079] On the other hand, a body contact region 73 is formed in the body region 71 between the trench gate structure 65 and the DTI structure 90, while a source region 70 is not formed. Therefore, the contact 81 on the body region 71 between the trench gate structure 65 and the DTI structure 90 is electrically connected to the body contact region 73. A wiring 93 is formed on the first interlayer insulating film 75 so as to be electrically connected to the contact 81. The wiring 93 extends so as to cover the DTI structure 90. A contact 94 is electrically connected to the wiring 93. The contact 94 is connected to the insulator 92. Although not shown in FIG. 9, the wiring 93 is connected to the first source electrode 80.

[0080] On the third interlayer insulating film 77, a second source electrode 82 is formed as a second metal (second metal layer). The second source electrode 82 is an electrode film containing one or more metal species selected from the group including, for example, aluminum (Al), copper (Cu), titanium (Ti), tungsten (W), and tantalum (Ta). The thickness of the second source electrode 82 is, for example, 8000 Å. The second source electrode 82 is electrically connected to the first source electrode 80 via a corresponding contact 83. The outer peripheral portion of the second source electrode 82 is covered by the fourth interlayer insulating film 78.

[0081] A passivation film 84 is formed on the surface of the fourth interlayer insulating film 78. The passivation film 84 contains, for example, at least one of silicon nitride and silicon oxide. The passivation film 84 may be a laminated film including a silicon oxide film and a silicon nitride film formed on the silicon oxide film. The passivation film 84 of the present embodiment is made of a silicon nitride film. The thickness of the passivation film 84 is, for example, 11000 Å.

[0082] The source pad 21 is provided in an opening 85 that penetrates the fourth interlayer insulating film 78 and the passivation film 84. The source pad 21 has an inner peripheral portion 86 that contacts the second source electrode 82 within the opening 85, and an outer peripheral portion 87 that covers the surface of the passivation film 84 over the opening 85. The thickness of the inner peripheral portion 86 of the source pad 21 is, for example, 42000 Å.

[0083] A surface protection film 88 is formed on the surface of the source pad 21. An example of the surface protection film 88 is a film containing polyimide. The surface protection film 88 covers a part of the inner peripheral portion 86 and a part of the outer peripheral portion 87 of the source pad 21. The surface protection film 88 is provided with an opening 89 for connecting the first wire 41 to the source pad 21.

[0084] 〔Structure of Semiconductor Elements Constituting Control Circuit〕 With reference to FIGS. 12 to 17, the structure of the control semiconductor elements that constitute the overcurrent protection circuit 24, the overheat protection circuit 25, and the low-voltage malfunction prevention circuit 26, which are control circuits for controlling the MISFET 23a of the semiconductor device 1, will be described. Examples of the control semiconductor elements include low-voltage CMOS (Complementary MOS) FETs, MOS capacitors, polysilicon resistors, high-voltage P-channel MOSFETs, high-voltage N-channel MOSFETs, and NPN transistors. These control semiconductor elements are provided on the substrate 50 in the same manner as the MISFET 23a. In the following description, when referring to n-type impurities (n-type), a pentavalent element (e.g., phosphorus (P), arsenic (As), etc.) is included as the main impurity, and when referring to p-type impurities (p-type), a trivalent element (e.g., boron (B), indium (In), gallium (Ga), etc.) is included as the main impurity.

[0085] The low-voltage CMOSFET shown in FIG. 12 has a CMOS region 100 in which CMOS transistors are formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 101 is formed as an element isolation structure that partitions the CMOS region 100 from other regions. The DTI structure 101 is formed in a substantially annular shape in a plan view (hereinafter simply referred to as "plan view") as viewed from the normal direction of the surface of the epitaxial layer 62. The DTI structure 101 includes an insulator 101b embedded in a trench 101a formed in the epitaxial layer 62. An example of the insulator 101b is polysilicon. Note that the insulator 101b may be silicon oxide. In the present embodiment, an example in which the DTI structure 101 is formed as an element isolation structure has been described. However, the element isolation structure may use a diffusion isolation method, that is, a pn connection separation method, including an annular p-type diffusion region that partitions the CMOS region 100.

[0086] In the CMOS region 100, a first P-well region 102, which is a p-type high-voltage well region, is formed at a distance from the DTI structure 101. In order to secure a distance between the DTI structure 101 and the first P-well region 102, a second P-well region 103, which is a p-type low-voltage well region, is formed in the surface layer portion of the epitaxial layer 62. The second P-well region 103 is formed in a substantially annular shape so as to be adjacent to the DTI structure 101. When the DTI structure 101 is formed in a stripe shape instead of a substantially annular shape, the second P-well region 103 is formed in a stripe shape so as to be adjacent to each DTI structure 101. The impurity concentration of the second P-well region 103 is higher than the impurity concentration of the first P-well region 102.

[0087] In the surface layer portion of the epitaxial layer 62 within the first P well region 102, a first N well region 104 and a second N well region 105, which are two n-type well regions, are formed. The first N well region 104 is formed so as to surround the second N well region 105. The thickness of the first N well region 104 is thinner than the thickness of the first P well region 102. The thickness of the second N well region 105 is thinner than the thickness of the first N well region 104. The impurity concentration of the first N well region 104 is higher than the impurity concentration of the first P well region 102. The impurity concentration of the second N well region 105 is higher than the impurity concentration of the first N well region 104. In the following description, the thickness refers to the length in the normal direction of the surface of the epitaxial layer 62.

[0088] In the surface layer portion of the epitaxial layer 62 within the second N well region 105, a p-type source region 106, a p-type drain region 107, and an n-type contact region 108 are formed. The source region 106, the drain region 107, and the contact region 108 are formed with intervals therebetween. The source region 106 is formed between the contact region 108 and the drain region 107. The impurity concentrations of the source region 106, the drain region 107, and the contact region 108 are each higher than the impurity concentration of the second N well region 105.

[0089] Also, in the CMOS region 100, a third P-well region 109, which is a p-type low-voltage well region, is formed at an interval from the first N-well region 104 in the surface layer portion of the epitaxial layer 62. The third P-well region 109 is integrated with the second P-well region 103. An n-type source region 110, an n-type drain region 111, and a p-type contact region 112 are formed in the surface layer portion of the third P-well region 109. The source region 110, the drain region 111, and the contact region 112 are formed at intervals from each other. The contact region 112 is formed in the third P-well region 109 near the DTI structure 101 (the second P-well region 103) adjacent to the third P-well region 109. In other words, the contact region 112 is formed in the region of the third P-well region 109 where the second P-well region 103 is integrated. That is, the contact region 112 also serves as the contact region of the second P-well region 103. The source region 110 is formed between the drain region 111 and the contact region 112.

[0090] An insulating film 113 is formed between the surface of the epitaxial layer 62 in the CMOS region 100 and between the trench 101a and the insulator 101b of the DTI structure 101. An example of the insulating film 113 is a silicon oxide film. A first gate electrode 114 facing the second N-well region 105 and a second gate electrode 115 facing the third P-well region 109 are formed on the insulating film 113. Each of the gate electrodes 114, 115 is, for example, polysilicon doped with impurities. Both side surfaces of each of the gate electrodes 114, 115 are covered with sidewalls 116, 117 containing an insulating material such as silicon oxide or silicon nitride.

[0091] On the epitaxial layer 62 within the CMOS region 100, similar to the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order. On the first interlayer insulating film 75, as the first metal, a first source electrode 118, a first drain electrode 119, a first gate electrode (not shown), a second source electrode 120, a second drain electrode 121, a second gate electrode (not shown), a back gate electrode 122, and a ground electrode 123 are formed. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0092] The first source electrode 118 is electrically connected to the source region 106 of the second N-well region 105 via a contact, the first drain electrode 119 is electrically connected to the drain region 107 of the second N-well region 105 via a contact, and the back gate electrode 122 is electrically connected to the contact region 108 of the second N-well region 105 via a contact. In this way, a p-type MOSFET is formed.

[0093] The second source electrode 120 is electrically connected to the source region 110 of the third P-well region 109 via a contact, and the second drain electrode 121 is electrically connected to the drain region 111 of the third P-well region 109 via a contact. In this way, an n-type MOSFET is formed.

[0094] The ground electrode 123 is electrically connected to the contact region 112 of the second P-well region 103 via a contact. The ground electrode 123 is electrically connected to the insulator 101b of the DTI structure 101 via a contact. Also, the ground electrode 123 electrically connected to the contact region 112 of the third P-well region 109 serves as the back gate of the n-type MOSFET formed in the third P-well region 109. In this way, the DTI structure 101, the third P-well region 109, and the first P-well region 102 are at the ground potential.

[0095] On the third interlayer insulating film 77, a third source electrode, a third drain electrode, a third gate electrode, a fourth source electrode, and a fourth gate electrode are formed as second metals (all are not shown). The third source electrode is electrically connected to the first source electrode 118, the third drain electrode is electrically connected to the first drain electrode 119 and the second drain electrode 121, and the third gate electrode is electrically connected to the first gate electrode 114. Also, the fourth source electrode is electrically connected to the second source electrode 120, and the fourth gate electrode is electrically connected to the second gate electrode. In this way, by electrically connecting the first drain electrode 119 and the second drain electrode 121 through the third drain electrode, a CMOS transistor is formed.

[0096] The MOS capacitor shown in FIG. 13 has a capacitor region 130 where the capacitor is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 131 is formed as an element isolation structure that partitions the capacitor region 130 from other regions. The DTI structure 131 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and has a structure in which an insulator 131b is embedded in a trench 131a. An example of the insulator 131b is polysilicon. Note that the insulator 131b may be silicon oxide. In this embodiment, an example in which the DTI structure 131 is formed as the element isolation structure has been described, but the element isolation structure may use a pn junction isolation method including an annular p-type diffusion region that partitions the capacitor region 130.

[0097] In the capacitor region 130, a first P-well region 132 which is a p-type high-voltage well region and a second P-well region 133 which is a p-type low-voltage well region are formed. The first P-well region 132 is formed at a distance from the DTI structure 131. The second P-well region 133 is formed so as to be adjacent to the DTI structure 131 across the first P-well region 132 in order to secure a distance between the DTI structure 131 and the first P-well region 132. The thickness of the second P-well region 133 is thinner than the thickness of the first P-well region 132. The impurity concentration of the second P-well region 133 is higher than the impurity concentration of the first P-well region 132. A p-type contact region 134 is formed in the surface layer portion of the second P-well region 133.

[0098] In the surface layer portion of the epitaxial layer 62 within the first P-well region 132, a first N-well region 135, a second N-well region 136, and a third N-well region 137 which are three n-type well regions are formed. The first N-well region 135 is formed so as to surround the second N-well region 136. The second N-well region 136 is formed so as to surround the third N-well region 137. The thickness of the first N-well region 135 is thinner than the thickness of the first P-well region 132. The thickness of the second N-well region 136 is thinner than the thickness of the first N-well region 135. The thickness of the third N-well region 137 is thinner than the thickness of the second N-well region 136. The impurity concentration of the first N-well region 135 is higher than the impurity concentration of the first P-well region 132. The impurity concentration of the second N-well region 136 is higher than the impurity concentration of the first N-well region 135. The impurity concentration of the third N-well region 137 is higher than the impurity concentration of the second N-well region 136. An n-type contact region 138 is formed in the surface layer portion outside the third N-well region 137 in the second N-well region 136. The impurity concentration of the contact region 138 is higher than the impurity concentration of the second N-well region 136.

[0099] An insulating film 139 is formed between the surface of the epitaxial layer 62 and the trench 131a of the DTI structure 131 and the insulator 131b within the capacitor region 130. An example of the insulating film 139 is a silicon oxide film. A gate electrode 140 is formed on the insulating film 139. The gate electrode 140 is formed so as to cover the entire third N-well region 137 and a part of the second N-well region 136. The gate electrode 140 is, for example, polysilicon doped with impurities. Both end faces of the gate electrode 140 are covered with sidewalls 141 containing an insulating material such as silicon oxide or silicon nitride.

[0100] On the epitaxial layer 62 within the capacitor region 130, a interlayer insulating film 74 and a passivation film 84 are laminated in this order, similar to the MISFET 23a. On the first interlayer insulating film 75, a first electrode 142, a first gate electrode 143, and a ground electrode 144 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0101] The first electrode 142 is electrically connected to the contact region 138 of the second N-well region 136 via a contact, and the first gate electrode 143 is electrically connected to the gate electrode 140 via a contact. The ground electrode 144 is electrically connected to the contact region 134 of the second P-well region 133 via a contact. The ground electrode 144 is electrically connected to the insulator 131b of the DTI structure 131 via a contact. Thus, the DTI structure 131 and the second P-well region 133 are at the ground potential.

[0102] On the third interlayer insulating film 77, a second electrode and a second gate electrode are formed as the second metal (both are not shown). The second electrode is electrically connected to the first electrode 142, and the second gate electrode is electrically connected to the first gate electrode 143.

[0103] The polysilicon resistor shown in FIG. 14 has a resistor region 150 in which a resistor is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 151 is formed as an element isolation structure that partitions the resistor region 150 from other regions. The DTI structure 151 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 151b is embedded in a trench 151a. An example of the insulator 151b is polysilicon. Note that the insulator 151b may be silicon oxide. In this embodiment, an example in which the DTI structure 151 is formed as an element isolation structure has been described, but the element isolation structure may use a pn junction isolation method including an annular p-type diffusion region that partitions the resistor region 150.

[0104] In the resistor region 150, a first P-well region 152 that is a p-type high-voltage well region and a second P-well region 153 that is a p-type low-voltage well region are formed. The first P-well region 152 is formed at a distance from the DTI structure 151. The second P-well region 153 is formed so as to straddle the first P-well region 152 and be adjacent to the DTI structure 151 in order to secure a space between the DTI structure 151 and the first P-well region 152. The thickness of the second P-well region 153 is thinner than the thickness of the first P-well region 152. The impurity concentration of the second P-well region 153 is higher than the impurity concentration of the first P-well region 152. A p-type contact region 154 is formed in the surface layer portion of the second P-well region 153.

[0105] An insulating film 155 is formed on the surface of the epitaxial layer 62 within the resistance region 150 and between the trench 151a of the DTI structure 151 and the insulator 151b. An example of the insulating film 155 is a silicon oxide film. On the insulating film 155, a first polysilicon resistor 156 and a second polysilicon resistor 157 are formed at intervals from each other. The first polysilicon resistor 156 and the second polysilicon resistor 157 face the first P-well region 152. Both side surfaces of the first polysilicon resistor 156 are covered with sidewalls 156a containing an insulating material such as silicon oxide or silicon nitride, and both side surfaces of the second polysilicon resistor 157 are covered with sidewalls 157a in the same manner as the first polysilicon resistor 156. In the present embodiment, the first polysilicon resistor 156 has a low concentration of impurities added to the polysilicon, that is, a high resistance, and the second polysilicon resistor 157 has a low concentration of impurities added to the polysilicon, that is, a low resistance. Note that the number and types of polysilicon resistors formed in the resistance region 150 can be arbitrarily changed. For example, one of the first polysilicon resistor 156 and the second polysilicon resistor 157 may be omitted.

[0106] On the epitaxial layer 62 within the resistance region 150, in the same manner as the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order. On the first interlayer insulating film 75, a ground electrode 158 is formed as a first metal. The ground electrode is an electrode film containing one or a plurality of metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum. The ground electrode 158 is electrically connected to the insulator 151b of the DTI structure 151 and the contact region 154 through a plurality of contacts. Thus, the DTI structure 151, the second P-well region 153, and the first P-well region 152 are at a ground potential.

[0107] The high-voltage N-channel MOSFET shown in FIG. 15 has an NMOS region 160 in which an N-channel MOSFET is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 161 is formed as an element isolation structure that partitions the NMOS region 160 from other regions. The DTI structure 161 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and has a structure in which an insulator 161b is embedded in a trench 161a. An example of the insulator 161b is polysilicon. Note that the insulator 161b may be silicon oxide. In this embodiment, an example in which the DTI structure 161 is formed as an element isolation structure has been described, but the element isolation structure may use a pn junction isolation method including an annular p-type diffusion region that partitions the NMOS region 160.

[0108] In the NMOS region 160, a first P-well region 162, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 161. In order to ensure a distance between the DTI structure 161 and the first P-well region 162, a second P-well region 163, which is a p-type low-voltage well region, is formed in the surface layer portion of the epitaxial layer 62. The second P-well region 163 is formed in a substantially annular shape so as to be adjacent to the DTI structure 161. Note that when the DTI structure 161 is formed in a stripe shape instead of a substantially annular shape, the second P-well region 163 is formed in a stripe shape so as to be adjacent to each DTI structure 161. The impurity concentration of the second P-well region 163 is higher than the impurity concentration of the first P-well region 162.

[0109] In the surface layer portion of the epitaxial layer 62 within the NMOS region 160, an N-well region 164, which is an n-type well region, is formed. The N-well region 164 is formed within the first P-well region 162. The thickness of the N-well region 164 is thinner than the thickness of the first P-well region 162. The impurity concentration of the N-well region 164 is higher than the impurity concentration of the first P-well region 162. An n-type drain region 165 is formed in the surface layer portion of the N-well region 164. The impurity concentration of the drain region 165 is higher than the impurity concentration of the N-well region 164.

[0110] Also, in the NMOS region 160, a third P-well region 166, which is a p-type low-voltage well region, is formed in the surface layer portion of the epitaxial layer 62. The third P-well region 166 is formed at a distance from the N-well region 164. The third P-well region 166 is formed integrally with the second P-well region 163. The thickness of the third P-well region 166 is thinner than the thickness of the first P-well region 162 and the thickness of the N-well region 164. An n-type source region 167 and a p-type contact region 168 are formed in the surface layer portion of the third P-well region 166. The source region 167 and the contact region 168 are formed at a distance from each other. The contact region 168 is formed in the region of the third P-well region 166 where the second P-well region 163 is integrated. That is, it also serves as the contact region of the second P-well region 163.

[0111] An insulating film 169 is formed between the surface of the epitaxial layer 62 and between the trench 161a and the insulator 161b of the DTI structure 161 in the NMOS region 160. An example of the insulating film 169 is a silicon oxide film. A gate electrode 170 is formed on the insulating film 169 so as to face across the third P-well region 166, the first P-well region 162, and the N-well region 164. The gate electrode 170 is, for example, polysilicon doped with impurities. Both side surfaces of the gate electrode 170 are covered with sidewalls 171 containing an insulating material such as silicon oxide or silicon nitride.

[0112] On the epitaxial layer 62 in the NMOS region 160, a interlayer insulating film 74 and a passivation film 84 are laminated in this order, similar to the MISFET 23a. On the first interlayer insulating film 75, a first source electrode 172, a first drain electrode 173, a first gate electrode 174, and a ground electrode 175 are formed as the first metal. These electrodes are electrode films containing one or a plurality of metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0113] The first source electrode 172 is electrically connected to the source region 167, the first drain electrode 173 is electrically connected to the drain region 165, and the first gate electrode 174 is electrically connected to the gate electrode 170. Also, the ground electrode 175 is electrically connected to the contact region 168 of the second P-well region 163 and the insulator 161b of the DTI structure 161 through a plurality of contacts. In this way, the DTI structure 161, the second P-well region 163, and the first P-well region 162 are at the ground potential.

[0114] On the third interlayer insulating film 77, a second source electrode, a second drain electrode, and a second gate electrode are formed as second metal (all are not shown). The second source electrode is electrically connected to the first source electrode 172, the second drain electrode is electrically connected to the first drain electrode 173, and the second gate electrode is electrically connected to the first gate electrode 174. These electrodes are formed of the same material as the electrodes (such as the first source electrode 172) that form the first metal, for example.

[0115] In the high-voltage P-channel MOSFET shown in FIG. 16, a PMOS region 180 in which a P-channel MOSFET is formed is formed. In the epitaxial layer 62 of the substrate 50, a DTI structure 181 is formed as an element isolation structure that partitions the PMOS region 180 from other regions. The DTI structure 181 has the same structure as the DTI structure 101 (see FIG. 12) of the low-voltage CMOSFET, and is a structure in which an insulator 181b is embedded in a trench 181a. An example of the insulator 181b is polysilicon. Note that the insulator 181b may be silicon oxide. In the present embodiment, an example in which the DTI structure 181 is formed as an element isolation structure has been described, but the element isolation structure may use a pn junction isolation method including an annular p-type diffusion region that partitions the PMOS region 180.

[0116] In the PMOS region 180, a P-well region 182, which is a p-type high-voltage well region, and an N-well region 183, which is an n-type well region, are formed in the surface layer portion of the epitaxial layer 62. The P-well region 182 and the N-well region 183 are formed at intervals from the DTI structure 181. The P-well region 182 and the N-well region 183 are formed at intervals from each other. The thickness of the N-well region 183 is thinner than the thickness of the P-well region 182. A p-type drain region 184 is formed in the surface layer portion of the P-well region 182. A p-type source region 185 is formed in the surface layer portion of the N-well region 183.

[0117] In the PMOS region 180, an n-type contact region 186 is formed in the surface layer portion of the epitaxial layer 62. The contact region 186 is formed in a substantially annular shape, at intervals from the P-well region 182 and the DTI structure 181 between the P-well region 182 and the DTI structure 181, and at intervals from the N-well region 183 and the DTI structure 181 between the N-well region 183 and the DTI structure 181.

[0118] An insulating film 187 is formed on the surface of the epitaxial layer 62 in the PMOS region 180 and between the trench 181a and the insulator 181b of the DTI structure 181. An example of the insulating film 187 is a silicon oxide film. A gate electrode 188 facing across the N-well region 183, the epitaxial layer 62, and the P-well region 182 is formed on the insulating film 187. The gate electrode 188 is, for example, polysilicon doped with impurities. Both side surfaces of the gate electrode 188 are covered with sidewalls 189 containing an insulating material such as silicon oxide or silicon nitride.

[0119] On the epitaxial layer 62 in the PMOS region 180, a interlayer insulating film 74 and a passivation film 84 are laminated in this order, similarly to the MISFET 23a. On the first interlayer insulating film 75, a first source electrode 190, a first drain electrode 191, and a first gate electrode 192 are formed as the first metal. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0120] The first source electrode 190 is electrically connected to the source region 185 via a contact, the first drain electrode 191 is electrically connected to the drain region 184 via a contact, and the first gate electrode 192 is electrically connected to the gate electrode 188 via a contact.

[0121] On the third interlayer insulating film 77, a second source electrode, a second drain electrode, and a second gate electrode are formed as the second metal (all are not shown). The second source electrode is electrically connected to the first source electrode 190, the second drain electrode is electrically connected to the first drain electrode 191, and the second gate electrode is electrically connected to the first gate electrode 192. These electrodes are formed of the same material as the electrodes forming the first metal (such as the first source electrode 190).

[0122] The NPN transistor shown in FIG. 17 has a transistor region 200 that forms a bipolar transistor. In the epitaxial layer 62 of the substrate 50, a DTI structure 201 is formed as an element isolation structure that partitions the transistor region 200 from other regions. The DTI structure 201 has the same structure as the DTI structure 101 (see FIG. 12) of a low-voltage CMOSFET, and has a structure in which an insulator 201b is embedded in a trench 201a. An example of the insulator 201b is polysilicon. Note that the insulator 201b may be silicon oxide. In this embodiment, an example in which the DTI structure 201 is formed as an element isolation structure has been described, but the element isolation structure may utilize a pn junction isolation method including an annular p-type diffusion region that partitions the transistor region 200.

[0123] In the transistor region 200, a first P-well region 202, which is a p-type low-voltage well region, is formed at a distance from the DTI structure 201. In order to ensure a distance between the DTI structure 201 and the first P-well region 202, a second P-well region 203, which is a p-type low-voltage well region, is formed in the surface layer portion of the epitaxial layer 62. The second P-well region 203 is formed in a substantially annular shape so as to be adjacent to the DTI structure 201. When the DTI structure 201 is formed in a stripe shape instead of a substantially annular shape, the second P-well region 203 is formed in a stripe shape so as to be adjacent to each DTI structure 201. The impurity concentration of the second P-well region 203 is higher than the impurity concentration of the first P-well region 202. An annular p-type contact region 204 is formed in the surface layer portion of the second P-well region 203. The impurity concentration of the contact region 204 is higher than the impurity concentration of the second P-well region 203.

[0124] In the surface layer portion of the epitaxial layer 62 within the transistor region 200, an N-well region 205, which is an n-type well region, is formed. The N-well region 205 is formed within the first P-well region 202. The thickness of the N-well region 205 is thinner than the thickness of the first P-well region 202. The impurity concentration of the N-well region 205 is higher than the impurity concentration of the first P-well region 202.

[0125] In the surface layer portion of the epitaxial layer 62 within the N-well region 205, a p-type base region 206 is formed. The N-well region 205 is formed so as to surround the base region 206. The thickness of the base region 206 is thinner than the thickness of the N-well region 205. In the surface layer portion of the base region 206, a p-type base contact region 207 and an n-type emitter region 208 are formed. The base contact region 207 and the emitter region 208 are formed at intervals from each other. The impurity concentrations of the base contact region 207 and the emitter region 208 are each higher than the impurity concentration of the N-well region 205. Also, outside the base region 206 in the N-well region 205, an annular n-type collector region 209 is formed. The impurity concentration of the collector region 209 is higher than the impurity concentration of the N-well region 205.

[0126] An insulating film 210 is formed on the surface of the epitaxial layer 62 within the transistor region 200 and between the trench 201a of the DTI structure 201 and the insulator 201b. An example of the insulating film 210 is a silicon oxide film.

[0127] On the epitaxial layer 62 within the transistor region 200, in the same manner as the MISFET 23a, an interlayer insulating film 74 and a passivation film 84 are laminated in this order. On the first interlayer insulating film 75, as the first metal, a first emitter electrode 211, a first collector electrode 212, a first base electrode 213, and a ground electrode 214 are formed. These electrodes are electrode films containing one or more metal species selected from the group including, for example, aluminum, copper, titanium, tungsten, and tantalum.

[0128] The first emitter electrode 211 is electrically connected to the emitter region 208 via a contact. The first collector electrode 212 is electrically connected to the collector region 209 via a contact. The first base electrode 213 is electrically connected to the base contact region 207 via a contact. Also, the ground electrode 214 is electrically connected to the contact region 204 of the second P-well region 203 via a contact. The ground electrode 214 is electrically connected to the insulator 201b of the DTI structure 201 via a plurality of contacts. Thus, the DTI structure 201, the second P-well region 203, and the first P-well region 202 are at the ground potential.

[0129] On the third interlayer insulating film 77, a second emitter electrode, a second collector electrode, and a second base electrode are formed as the second metal (all are not shown). The second emitter electrode is electrically connected to the first emitter electrode 211, the second collector electrode is electrically connected to the first collector electrode 212, and the second base electrode is electrically connected to the first base electrode 213. These electrodes are formed of the same material as the electrodes (such as the first emitter electrode 211) that form the first metal, for example.

[0130] 〔Method of manufacturing a semiconductor device〕 With reference to FIGS. 18 to 19F, a method of manufacturing the semiconductor device 1 will be described. As shown in FIG. 18, the method of manufacturing the semiconductor device 1 includes an element mounting step (step S1), a first wire connection step (step S2), a second wire connection step (step S3), a molding step (step S4), a frame separation step (step S5), and a terminal bending step (step S6).

[0131] In the element mounting process shown in FIG. 19A, first, a frame FL including a lead frame 10 is prepared. The frame FL is configured by connecting a first lead frame 11, a second lead frame 12, and a third lead frame 13 to an outer frame portion FL1, respectively. Further, a first terminal portion 11b of the first lead frame 11 is connected to a second terminal portion 12b of the second lead frame 12 and a third terminal portion 13b of the third lead frame 13 by a connecting portion FL2 (diver). In the frame FL, the first terminal portion 11b is in a state where a first bent portion 11g, an inclined portion 11h, a second bent portion 11i, and a tip portion 11j are already formed. Also, in the frame FL, the second terminal portion 12b and the third terminal portion 13b are provided so as to be at the same position as the tip portion 11j of the first terminal portion 11b. Further, the frame FL is pre-plated with nickel.

[0132] Next, solder SD (not shown in FIG. 19A, see FIG. 3) is applied to each first island portion 11a of the frame FL. Then, a semiconductor element 20 is mounted on each solder SD. In one example, a die bonder device (not shown) picks up the semiconductor element 20 and fixes the semiconductor element 20 on the solder SD of the first island portion 11a.

[0133] In the first wire connection process shown in FIG. 19B, a first wire 41 is connected to a source pad 21 of the semiconductor element 20 and a third island portion 13a of the third lead frame 13 by wedge bonding. Specifically, a wedge bonding device (not shown) that performs wedge bonding first connects the first wire 41 to the source pad 21 (first bonding), and then connects it to the third island portion 13a (second bonding).

[0134] Here, as described with reference to FIGS. 7 and 8, a connection portion 41a of the source pad 21 in the first wire 41 includes the center of gravity position GC of the active region 29 of the semiconductor element 20. At this time, the connection portion 41a is formed so as to extend toward the third island portion 13a of the third lead frame 13 by a wedge bonding device.

[0135]

[0135] In the second wire connection step shown in FIG. 19C, the second wire 42 is connected to the gate pad 22 of the semiconductor element 20 and the second island portion 12a of the second lead frame 12 by wedge bonding.

[0136] In the molding step shown in FIG. 19D, for example, the encapsulating resin 30 is molded by a molding apparatus. In one example, in a state where the assembly manufactured by the second wire connection step is placed in the cavity of the mold of the molding apparatus, the molten epoxy resin is poured into the cavity of the mold. Thereby, the encapsulating resin 30 that encapsulates the semiconductor element 20, the first wire 41, and the second wire 42 (both refer to FIG. 19C) is formed.

[0137] In the frame separation step shown in FIG. 19E, for example, the lead frame 10 is separated from the frame FL (refer to FIG. 19D) by a press molding apparatus. More specifically, the first lead frame 11, the second lead frame 12, and the third lead frame 13 are cut from the outer frame portion FL1 (refer to FIG. 19D), and the connecting portion FL2 (refer to FIG. 19D) that connects the first terminal portion 11b of the first lead frame 11, the second terminal portion 12b of the second lead frame 12, and the third terminal portion 13b of the third lead frame 13 is cut.

[0138]

[0136] In the terminal bending step shown in FIG. 19F, for example, the portions protruding from the encapsulating resin 30 of the second terminal portion 12b of the second lead frame 12 and the third terminal portion 13b of the third lead frame 13 are bent by a press molding apparatus. Through the above steps, the semiconductor device 1 shown in FIG. 1 can be obtained.

[0139] According to this embodiment, the following effects can be obtained. (1-1) The region where the first wire 41 is connected to the source pad 21, that is, the connection portion 41a of the first wire 41, includes the centroid position GC of the active region 29 which is a transistor formation region. According to this configuration, the active clamp tolerance Eac can be improved as compared with the case where the connection portion 41a of the first wire 41 is connected to a location different from the centroid position GC of the active region 29 at the source pad 21.

[0140] (1-2) The connection portion 41a of the first wire 41 extends toward the second island portion 12a of the second lead frame 12. For this reason, although the intermediate portion of the first wire 41 connecting the semiconductor element 20 and the second island portion 12a is bent, the degree of bending can be made small. Therefore, the reliability of the semiconductor device 1 can be enhanced.

[0141] (1-3) A plating layer 14 is formed on the surface of the first island portion 11a of the first lead frame 11. According to this configuration, when solder SD is applied to the first island portion 11a, the wettability of the solder SD decreases, so that it becomes difficult for the solder SD to spread on the surface of the first island portion 11a. For this reason, since the thickness of the solder SD is suppressed from becoming excessively thin, the semiconductor element 20 and the first island portion 11a can be appropriately connected.

[0142] (1-4) The first wire 41 is composed of a material containing aluminum, and the second lead frame 12 is composed of a material containing copper. A plating layer 14 is formed on the surface of the second island portion 12a of the second lead frame 12 to which the first wire 41 is connected. According to this configuration, corrosion of the connection portion between the first wire 41 and the second island portion 12a can be suppressed.

[0143] (1-5) The second wire 42 is composed of aluminum, and the third lead frame 13 is composed of copper. A plating layer 14 is formed on the surface of the third island portion 13a of the third lead frame 13 to which the second wire 42 is connected. According to this configuration, corrosion at the connection portion between the second wire 42 and the third island portion 13a can be suppressed.

[0144] (1-6) The temperature sensor 27 is arranged at the location where heat is most concentrated among the regions outside the source pad 21 in the active region 29 when the semiconductor device 1 is driven. Thereby, the temperature of the semiconductor device 1 can be detected with high precision.

[0145] (1-7) Generally, the linear expansion coefficient of a sealing resin (hereinafter, a comparative sealing resin) for sealing an LSI that does not include a power transistor is 8 ppm / K to 10 ppm / K. And the inventor of the present application conducted a temperature cycle test on a semiconductor device using the comparative sealing resin, for example. In the temperature cycle test, the temperature conditions were changed from -65°C to 150°C over about 1000 cycles. As a result, it was found that pitting corrosion occurred in the first wire connected to the source pad of the semiconductor element and the third island portion of the third lead frame. Note that the same wire as the first wire 41 of the semiconductor device 1 is used as the first wire.

[0146] From this, although the surface of the first wire is protected by a natural oxide film, due to the load being applied to the first wire based on the difference between the linear expansion coefficient of the first wire and the linear expansion coefficient of the sealing resin by the temperature cycle test, the natural oxide film is broken and the chlorine ions in the sealing resin are combined with the first wire. As a result, it is considered that pitting corrosion occurred in the first wire.

[0147] In this regard, in the present embodiment, a material having a linear expansion coefficient greater than 10 ppm / K is used as the encapsulation resin 30. More specifically, an encapsulation resin 30 having a linear expansion coefficient of 12 ppm / K is used. As a result, the difference between the linear expansion coefficient of the first wire 41 and the linear expansion coefficient of the encapsulation resin 30 becomes smaller, so the load on the first wire 41 due to the temperature cycle test becomes smaller. As a result, since the natural oxide film of the first wire 41 is prevented from being broken, the occurrence of pitting corrosion of the first wire 41 can be suppressed.

[0148] On the other hand, in the present embodiment, in order to increase the linear expansion coefficient of the encapsulation resin 30, the blending ratio of the filler is increased. However, if the blending ratio of the filler is excessively increased, the moldability of the encapsulation resin 30 will be excessively reduced. Specifically, when the linear expansion coefficient of the encapsulation resin 30 is 15 ppm / K or more, the moldability of the encapsulation resin 30 will be excessively reduced.

[0149] In this regard, since the encapsulation resin 30 of the present embodiment uses an encapsulation resin 30 having a linear expansion coefficient smaller than 15 ppm / K, a decrease in the moldability of the encapsulation resin 30 can be suppressed. Thus, in the present embodiment, the occurrence of pitting corrosion of the first wire 41 can be suppressed and a decrease in the moldability of the encapsulation resin 30 can be suppressed.

[0150] (1-8) In the MISFET23a, the ratio of the area of the channel formation region 72 per unit area is less than 100%. The ratio of the area of the channel formation region 72 per unit area in the MISFET23a of the present embodiment is about 50%. Therefore, the generation of heat in the active region 29 can be suppressed as compared with the case where the above ratio is 100%. Therefore, the active clamp withstand voltage Eac can be improved.

[0151] (1-9) The surface of the source pad 21 of the MISFET23a is formed in an uneven shape. According to this configuration, the adhesion between the source pad 21 and the encapsulation resin 30 can be improved.

[0152] (Second Embodiment) Referring to FIGS. 20 to 22, the semiconductor device 1 of the second embodiment will be described. The semiconductor device 1 of this embodiment has a different connection structure of the first wire 41 to the source pad 21 as compared with the semiconductor device 1 of the first embodiment. In the following description, the same reference numerals are given to the components common to the semiconductor device 1 of the first embodiment, and the description thereof is omitted. FIGS. 20 and 21 are enlarged plan views showing a part of the substrate 50. In FIG. 20, the active region 29 is shown by a solid line, and the source pad 21 is shown by a two-dot chain line. In FIG. 21, the active region 29 is shown by a broken line, and the source pad 21 is shown by a solid line.

[0153] The inventor of the present application focused on the connection position of the first wire 41 connected to the semiconductor element 20 with respect to the source pad 21 of the active region 29 of the semiconductor device 1 for improving the active clamp withstand voltage Eac of the semiconductor device 1. And the inventor of the present application obtained the finding that when the first wire 41 is connected at two positions of the source pad 21, the active clamp withstand voltage Eac is improved when the first wire 41 is connected to the positions of the source pad 21 corresponding to the centroid positions of the two divided regions obtained by dividing the active region 29 into two divided regions with equal areas. In view of this point, as shown in FIG. 21, in this embodiment, the first wire 41 is connected to the source pad 21 at two connection positions. These two connection positions are the centroid positions GB1 and GB2 of the divided active regions 29 when the area of the active region 29 is bisected.

[0154] Here, the centroid positions GB1 and GB2 of the active region 29 are obtained as follows. As shown in FIG. 20, first, the source pad 21 is divided into two divided regions (the first region RB1 and the second region RB2) having equal areas. As shown in FIG. 20, at least one of the first region RB1 and the second region RB2 may be a region different from a rectangular shape. The first region RB1 shown in FIG. 20 is a region having a convex portion in a rectangular shape. On the other hand, the second region RB2 is a rectangular region.

[0155] Next, the centroid position GB1 of the first region RB1 and the centroid position GB2 of the second region RB2 are obtained. As shown in FIG. 20, since the second region RB2 is rectangular, the centroid position GB2 of the second region RB2 is the intersection of the diagonals of the second region RB2. On the other hand, since the first region RB1 is not rectangular, the first region RB1 is further divided into a first divided region RB11 and a second divided region RB12. Specifically, the region that becomes the rectangular convex portion of the first region RB1 is defined as the first divided region RB11, and the remaining region (rectangular region) of the first region RB1 is defined as the second divided region RB12. Then, the centroid position GB11 of the first divided region RB11 and the centroid position GB12 of the second divided region RB12 are obtained. The centroid position GB11 of the first divided region RB11 is the intersection of the diagonals of the first divided region RB11. The centroid position GB12 of the second divided region RB12 is the intersection of the diagonals of the second divided region RB12. Next, the area SB1 of the first divided region RB11 and the area SB2 of the second divided region RB12 are obtained respectively. Next, on the line segment LB connecting the centroid position GB11 and the centroid position GB12, based on the relationship between the distance DB1 between the centroid position GB11 and the centroid position GB1, the distance DB2 between the centroid position GB12 and the centroid position GB1, the area SB1 of the first divided region RB11, and the area SB2 of the second divided region RB12, the centroid position GB1 of the first region RB1 is obtained. Specifically, the ratio of the distance DB2 to the distance DB1 (DB2 / DB1) is equal to the inverse ratio of the ratio of the area SB2 of the second divided region RB12 to the area SB1 of the first divided region RB11 (SB1 / SB2) (DB2 / DB1 = SB1 / SB2). Thus, by obtaining at least one of the distances DB1 and DB2, the centroid position GB1 of the first region RB1 is obtained. Also, as shown in FIG. 20, the source pad 21 is provided so as to cover the centroid positions GB1 and GB2 (the centroid position GB1 of the first region RB1 and the centroid position GB2 of the second region RB2) of the divided active regions 29 respectively.

[0156] The two chain-dotted regions RY shown in FIG. 20 indicate tool heads (hereinafter referred to as wedge RY) for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the center of gravity position GB1 of the first region RB1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. As a result, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity position GB1 of the first region RB1, as shown in FIG. 21. That is, the first connection portion 41b (connection region) of the first wire 41 to the source pad 21 includes the center of gravity position GB1 of the first region RB1. In the present embodiment, the center position of the first connection portion 41b coincides with the center of gravity position GB1 of the first region RB1. Next, the wedge bonding apparatus separates the wedge RY from the source pad 21 so that the first wire 41 is separated from the source pad 21 (see FIG. 22). Then, the wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the center of gravity position GB2 of the second region RB2 of the active region 29, and connects the first wire 41 to the source pad 21 (see FIG. 22). As a result, the first wire 41 passed through the wedge RY is connected so as to overlap the center of gravity position GB2 of the second region RB2, as shown in FIG. 21. That is, the second connection portion 41c (connection region) of the first wire 41 to the source pad 21 includes the center of gravity position GB2 of the second region RB2. In the present embodiment, the center position of the second connection portion 41c coincides with the center of gravity position GB2 of the second region RB2. Also, as shown in FIG. 22, the portion of the first wire 41 between the first connection portion 41b and the second connection portion 41c is spaced upward from the source pad 21.

[0157] Also, as shown in FIG. 21, the first connection portion 41b and the second connection portion 41c connected to the source pad 21 in the first wire 41 each extend in a direction different from the lateral direction X and the longitudinal direction Y in the plan view of the semiconductor device 1. Specifically, the first connection portion 41b and the second connection portion 41c each extend from the semiconductor element 20 toward the second island portion 12a (see FIG. 2). Note that the direction in which the first connection portion 41b extends and the direction in which the second connection portion 41c extends can each be arbitrarily changed. In one example, the direction in which the first connection portion 41b extends and the direction in which the second connection portion 41c extends may be different from each other.

[0158] As shown in FIG. 21, the two-dot chain line region RS surrounding the first connection portion 41b and the second connection portion 41c of the first wire 41 is a margin considering the variation in the wire diameter of the first wire 41 and the variation in the connection position of the first wire 41 to the source pad 21 by the wedge bonding device. That is, the first connection portion 41b and the second connection portion 41c of the first wire 41 are always positioned within the region RS. In the present embodiment, the region RS includes the vicinity of the intersection of the fifth side 29e and the sixth side 29f of the active region 29. In the present embodiment, the temperature sensor 27 is provided adjacent to the region RS in the plan view of the semiconductor device 1.

[0159] According to the present embodiment, in addition to the effects of the first embodiment, the following effects can be obtained. (2-1) The first wire 41 is connected to the centroid positions GB1 and GB2 of the first region RB1 and the second region RB2, which are two divided regions obtained by dividing the active region 29 into two divided regions having equal areas. Thereby, since the concentration of heat in the active region 29 during the driving of the semiconductor device 1 is reduced, the active clamp tolerance Eac can be improved.

[0160] (Third Embodiment) Referring to FIG. 23, the semiconductor device 1 of the third embodiment will be described. The semiconductor device 1 of this embodiment is different in part of the structure of the MISFET 23a compared with the semiconductor device 1 of the first embodiment. In the following description, the same reference numerals are given to the components common to the semiconductor device 1 of the first embodiment, and the description thereof will be omitted. Also, the differences from the MISFET 23a of the first embodiment will be described in detail below.

[0161] As shown in FIG. 23, at least in a portion of the first source electrode 80 as the first metal layer that faces the source pad 21, one or a plurality of first slits 220 are provided. The first slit 220 penetrates the first source electrode 80 and extends in the direction in which the trench gate structure 65 extends (the depth direction of the paper surface). The first slit 220 of this embodiment faces the trench gate structure 65.

[0162] At least in a portion of the second source electrode 82 as the second metal layer that faces the source pad 21, one or a plurality of second slits 221 are provided. The second slit 221 penetrates the second source electrode 82 and extends in the direction in which the trench gate structure 65 extends.

[0163] The second slit 221 is provided so as to face at least a part of the first slit 220. The width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 can be arbitrarily changed respectively. In this embodiment, the width dimension DS2 of the second slit 221 and the width dimension DS1 of the first slit 220 are equal to each other. Also, in this embodiment, the entire second slit 221 faces the first slit 220.

[0164] The second interlayer insulating film 76 is embedded in the first slit 220. The fourth interlayer insulating film 78 is embedded in the second slit 221. The fourth interlayer insulating film 78 straddles the second slit 221 and covers the periphery of the second slit 221 of the second source electrode 82. Thus, in the semiconductor element 20, support pillars 222 composed of the first interlayer insulating film 75 to the fourth interlayer insulating film 78 are provided at the portions where the first slit 220 and the second slit 221 are provided. The support pillar 222 is formed by laminating the first interlayer insulating film 75, the second interlayer insulating film 76, the third interlayer insulating film 77, and the fourth interlayer insulating film 78 in this order. The upper end portion of the support pillar 222 is covered by the source pad 21. Thereby, the support pillar 222 supports the source pad 21.

[0165] A configuration including such first slit 220 and second slit 221 is preferably provided at least at the periphery of the source pad 21. In the present embodiment, the configuration including the first slit 220 and the second slit 221 is provided entirely around the source pad 21. More specifically, the MISFET 23a is formed by combining a large number of configurations including the first slit 220 and the second slit 221. An example of the configuration including the first slit 220 and the second slit 221 is a configuration in which three trench gate structures 65 and the first slit 220 and the second slit 221 are provided at positions corresponding to one of the three trench gate structures 65. The MISFET 23a is configured by combining configurations including a plurality of first slits 220 and second slits 221.

[0166] The source pad 21 of this embodiment is made of copper (Cu). The thickness of the source pad 21 is preferably about 4 μm or more. Also, the thickness of the source pad 21 is preferably about 20 μm or less. The thickness of the source pad 21 of this embodiment is about 8 μm. The source pad 21 can be formed by copper plating growth. On the surface of the copper constituting the source pad 21, a connection layer 21a including nickel (Ni) plating is formed. The connection layer 21a of this embodiment is formed by nickel palladium (NiPd) plating. Note that the source pad 21 may be an aluminum alloy (for example, AlCu).

[0167] (Operation) The operation of this embodiment will be described. For example, when a semiconductor device is connected to an inductive load and a function of absorbing the energy released from the inductive load when the switching element (MISFET) of the semiconductor device is turned off is required, the active clamp tolerance Eac is known as an index of how much energy accumulated in the inductive load can be absorbed.

[0168] By the way, when the energy applied to the semiconductor device exceeds a predetermined value, the semiconductor device may fail due to a temperature rise. Thus, the active clamp tolerance Eac is mainly determined by the failure of the semiconductor device due to heat. For this reason, for example, when energy is applied to the semiconductor device, a portion that transiently and locally becomes a high temperature occurs on the substrate, and as a result, a failure is likely to occur in that portion, and there is a possibility that the energy cannot be absorbed. This makes it difficult to improve the active clamp tolerance Eac.

[0169] In response to such a problem, in order to absorb the transient energy of the semiconductor device, it is conceivable to change the power electrode pad (source pad) of the semiconductor device to copper having excellent heat dissipation and increase the thickness of the source pad. Thereby, the active clamp tolerance Eac can be improved.

[0170] However, when heat is applied to the source pad during the manufacture of a semiconductor device, the source pad made of copper is more likely to expand compared to a source pad made of aluminum. As a result, in particular, the outer peripheral edge of the source pad presses the interlayer insulating film formed in the source pad against the epitaxial layer. As a result, in the external region of the source pad, for example, the first metal may protrude from the passivation film, and passivation cracks may occur.

[0171] In view of such circumstances, in the present embodiment, a first slit 220 is formed in the first source electrode 80, and a second slit 221 is formed in the second source electrode 82. As a result, even if the first source electrode 80 is deformed, the deformation is interrupted by the first slit 220, and even if the second source electrode 82 is deformed, the deformation is interrupted by the second slit 221. Therefore, the amount of deformation of each of the first source electrode 80 and the second source electrode 82 can be reduced.

[0172] In addition, since a support pillar 222 that supports the source pad 21 so as to connect the first slit 220 and the second slit 221 is formed, the support pillar 222 supports the source pad 21 against deformation due to heat. Therefore, deformation of the first source electrode 80 and the second source electrode 82 can be suppressed. Therefore, the occurrence of passivation cracks can be suppressed.

[0173] According to the present embodiment, in addition to the above actions and effects, the following effects can be obtained. (3-1) For example, when the source pad 21 is made of aluminum, since the source pad 21 is formed by sputtering, it is difficult to make the source pad 21 sufficiently thick. For this reason, it is difficult to increase the heat capacity of the source pad 21, and there is a possibility that heat cannot be sufficiently dissipated when heat is instantaneously applied to the semiconductor device. Therefore, there is room for improvement in sufficiently improving the active clamp tolerance Eac.

[0174] In this regard, in the present embodiment, the source pad 21 is made of electroplated copper. As a result, the thickness of the source pad 21 can be made thicker than that of the source pad 21 made of aluminum. Therefore, since the heat capacity of the source pad 21 can be increased, the active clamp withstand voltage Eac can be improved. In addition, since the source pad 21 can be made thicker, when the first wire 41 is connected to the source pad 21, it is possible to suppress the impact from being transmitted to the interlayer insulating film 74.

[0175] (3-2) Nickel plating is formed on the copper surface of the source pad 21. The first wire 41 is made of aluminum. Thereby, it is possible to suppress the connection portion between the source pad 21 and the first wire 41 from corroding.

[0176] (Fourth Embodiment) With reference to FIGS. 24 to 27K, the semiconductor device 1 of the fourth embodiment will be described. The semiconductor device 1 of the present embodiment has a different structure of the MISFET 23a compared to the semiconductor device 1 of the first embodiment. In the following description, the same reference numerals are given to the components common to the semiconductor device 1 of the first embodiment, and the description thereof will be omitted. In the MISFET 23a of the present embodiment, since the channel formation region 72 is different, for convenience of explanation, in FIGS. 27J and 27K, the interlayer insulating film 74, the first source electrode 80, the second source electrode 82, and the source pad 21 are shown in a simplified manner. In the present embodiment, a configuration including the first source electrode 80, the second source electrode 82, and the source pad 21 is defined as the source metal 230.

[0177] The MISFET 23a of this embodiment has a plurality of functional element formation regions 231 in which the ratio of the area of the channel formation region 72 per unit area is different. In this embodiment, the active region 29 of the MISFET 23a is composed of a plurality of functional element formation regions 231. The plurality of functional element formation regions 231 include a first functional element formation region 232 in which the ratio of the area of the channel formation region 72 per unit area is relatively small, and a second functional element formation region 233 in which the ratio of the area of the channel formation region 72 per unit area is relatively high. Further, the plurality of functional element formation regions 231 of this embodiment include a third functional element formation region 234 in which the ratio of the area of the channel formation region 72 per unit area is larger than that of the first functional element formation region 232 and smaller than that of the second functional element formation region 233.

[0178] Since the ratio of the area of the channel formation region 72 per unit area of the first functional element formation region 232 is smaller than that of the second functional element formation region 233 and the third functional element formation region 234, its heat generation amount is also relatively small. On the other hand, the on-resistance of the first functional element formation region 232 becomes larger than that of the second functional element formation region 233 and the third functional element formation region 234 due to the relatively small channel formation region 72.

[0179] On the contrary, since the ratio of the area of the channel formation region 72 per unit area of the second functional element formation region 233 and the third functional element formation region 234 is larger than that of the first functional element formation region 232, their heat generation amounts are also relatively large. On the other hand, the on-resistance of the second functional element formation region 233 and the third functional element formation region 234 becomes smaller than that of the first functional element formation region 232 due to the relatively large area of the channel formation region 72.

[0180] The relationship of the amount of heat generated in each of the first to third functional element formation regions 232 to 234 is such that the amount of heat generated in the first functional element formation region 232 < the amount of heat generated in the third functional element formation region 234 < the amount of heat generated in the second functional element formation region 233. The relationship of the on-resistance in each of the first to third functional element formation regions 232 to 234 is such that the on-resistance in the second functional element formation region 233 < the on-resistance in the third functional element formation region 234 < the on-resistance in the first functional element formation region 232. Also, the relationship of the active clamp tolerance Eac in each of the first to third functional element formation regions 232 to 234 is such that the active clamp tolerance Eac in the second functional element formation region 233 < the active clamp tolerance Eac in the third functional element formation region 234 < the active clamp tolerance Eac in the first functional element formation region 232.

[0181] In the semiconductor device 1 (MISFET 23a) of the present embodiment, by devising the arrangement pattern of the first functional element formation region 232, the second functional element formation region 233, and the third functional element formation region 234, a semiconductor device 1 is provided that enables both an excellent active clamp tolerance Eac and an on-resistance while suppressing the temperature rise in the entire semiconductor device 1 (semiconductor element 20). In particular, the semiconductor device 1 arranges the first functional element formation region 232 in a portion of the source pad 21 where the temperature is likely to rise, and arranges the second functional element formation region 233 and the third functional element formation region 234 in other portions, thereby attempting to achieve the above object.

[0182] For example, as a region where the temperature is likely to rise in the source pad 21 and the temperature rise should be suppressed, an inner region spaced a predetermined distance inward from the periphery of the source pad 21, a region surrounded by a plurality of channel formation regions 72 (a plurality of functional element formation regions 231), a region not connected to the first wire 41 in a plan view, or a region in which these regions are selectively combined can be exemplified. In these regions, heat is difficult to dissipate and tends to accumulate. In particular, the inner region of the source pad 21 is likely to have its temperature rise and tends to be relatively high compared to other portions.

[0183] Therefore, in the present embodiment, a first functional element formation region 232 is disposed in the inner region of the active region 29, and a second functional element formation region 233 and a third functional element formation region 234 are disposed in the outer region of the active region 29. As a result, the ratio of the area of the channel formation region 72 per unit area gradually increases from the inner side to the outer side of the active region 29.

[0184] In addition, in the active region 29, the portion where the first wire 41 is connected to the source pad 21 radiates heat to the first wire 41 through the source pad 21, so the temperature of the active region 29 is likely to decrease. In view of this point, the portion where the first wire 41 is connected to the source pad 21 is arranged with the second functional element formation region 233 having the largest heat generation amount.

[0185] Hereinafter, the arrangement of the plurality of functional element formation regions 231 will be described in detail. FIGS. 24 and 25 are examples of the arrangement modes of the plurality of functional element formation regions 231, and the size and number of the regions dividing the active region 29 can be arbitrarily changed.

[0186] As shown in FIGS. 24 and 25, the plurality of functional element formation regions 231 include a first functional element formation region unit U1 including a plurality (four in this embodiment) of first functional element formation regions 232, a second functional element formation region unit U2 including a plurality (four in this embodiment) of second functional element formation regions 233, and a third functional element formation region unit U3 including a plurality (four in this embodiment) of third functional element formation regions 234.

[0187] In the present embodiment, the first to third functional element formation region units U1 to U3 are generally rectangular in plan view with the same area, and are arranged so as to tile the active region 29 in a matrix shape (regular grid shape in the vertical and horizontal directions) with a predetermined layout. In other words, the first to third functional element formation region units U1 to U3 are arranged in a predetermined layout within a plurality of rectangular regions partitioning the active region 29 in a matrix shape.

[0188] Specifically, the first to third functional element formation region units U1 to U3 are arranged according to the heat generation amount of each region of the active region 29 when the semiconductor device 1 is driven, which is obtained, for example, by simulation. For example, the second functional element formation region unit U2 is arranged in a region where the heat generation amount is equal to or less than the first threshold value, the first functional element formation region unit U1 is arranged in a region where the heat generation amount is greater than the first threshold value and equal to or greater than the second threshold value, and the third functional element formation region unit U3 is arranged in a region where the heat generation amount is greater than the first threshold value and less than the second threshold value.

[0189] FIG. 24 shows the arrangement modes of the first to third functional element formation region units U1 to U3 in the active region 29 when the first wire 41 is connected to the source pad 21 at one location.

[0190] As shown in FIG. 24, the first functional element formation region unit U1 is provided in a region where heat generation should be suppressed. The first functional element formation region unit U1 is arranged in the inner region of the active region 29. The third functional element formation region unit U3 is provided in a region adjacent to the first functional element formation region unit U1. The second functional element formation region unit U2 is provided in a region adjacent to the third functional element formation region unit U3 and on the opposite side of the first functional element formation region unit U1.

[0191] Also, in a region including the region (the dashed-dotted line region) where the first wire 41 is connected to the source pad 21 in the active region 29, the second functional element formation region unit U2 is provided. The first functional element formation region unit U1 is provided in the region around these second functional element formation region units U2. The third functional element formation region unit U3 is provided in the region around these first functional element formation region units U1.

[0192] FIG. 25 shows the arrangement modes of the first to third functional element formation region units U1 to U3 in the active region 29 when the first wire 41 is connected to the source pad 21 at two locations.

[0193] As shown in FIG. 25, the first functional element formation region unit U1 is provided in a region where heat generation should be suppressed. The first functional element formation region unit U1 is disposed in the inner region of the active region 29. In one example, the first functional element formation region unit U1 is provided in the inner region between two regions (the regions indicated by the dashed-dotted line) where the first wire 41 is connected to the source pad 21 in the active region 29. The third functional element formation region unit U3 is provided in a region adjacent to the first functional element formation region unit U1.

[0194] Also, in a region (the region where the wedge RY is disposed) including the two regions where the first wire 41 is connected to the source pad 21 in the active region 29, the second functional element formation region unit U2 is provided. In the regions around these second functional element formation region units U2, the first functional element formation region units U1 are provided. In the regions around these second functional element formation region units U2, the first functional element formation region units U1 are provided. In the regions around these first functional element formation region units U1, the third functional element formation region units U3 are provided.

[0195] Note that the outer region in the active region 29 is not limited to the arrangement modes of the second functional element formation region unit U2 and the third functional element formation region unit U3 shown in FIGS. 24 and 25, and either one of the second functional element formation region unit U2 and the third functional element formation region unit U3 may be arranged.

[0196] Next, with reference to FIGS. 26A to 26C, the planar structures of the first to third functional element formation region units U1 to U3 will be described. As shown in FIGS. 26A to 26C, in the first to third functional element formation region units U1 to U3, the ratio of the area of the channel formation region 72 occupied per unit area is adjusted, and the layouts of the first to third functional element formation regions 232 to 234 are changed.

[0197] The first functional element formation region unit U1 shown in FIG. 26A includes a plurality of functional element formation regions 231 in which the ratio of the area of the channel formation region 72 per unit area is about 25%. The second functional element formation region unit U2 shown in FIG. 26B includes a plurality of functional element formation regions 231 in which the ratio of the area of the channel formation region 72 per unit area is about 75%. The third functional element formation region unit U3 shown in FIG. 26C includes a plurality of functional element formation regions 231 in which the ratio of the area of the channel formation region 72 per unit area is about 50%.

[0198] As shown in FIGS. 26A to 26C, in the present embodiment, a plurality of channel formation regions 72 are formed in the first to third functional element formation regions 232 to 234 in a layout based on a staggered or zigzag pattern.

[0199] As shown in FIG. 26A, in each first functional element formation region 232 of the first functional element formation region unit U1, a plurality of channel formation regions 72 are arranged in a staggered pattern along the length direction of the trench gate structure 65. In each trench gate structure 65, a plurality of channel formation regions 72 are arranged at intervals alternately on one side surface side and the other side surface side of each trench gate structure 65 along the length direction of the trench gate structure 65. The plurality of channel formation regions 72 are arranged only on one side surface side or the other side surface side in the lateral direction intersecting the trench gate structure 65. With such a configuration, in the first functional element formation region unit U1, the ratio of the area of the channel formation region 72 per unit area is about 25%. In the first functional element formation region unit U1, since the channel formation region 72 is arranged at an interval from other channel formation regions 72 on one side surface side or the other side surface side of the trench gate structure 65, the heat generation sources can be effectively dispersed.

[0200] Further, the channel formation region 72 disposed on one side surface does not face the channel formation region 72 disposed on the other side surface with the trench gate structure 65 interposed therebetween. Therefore, in the lateral direction intersecting the trench gate structure 65, a plurality of heat generation sources do not face each other with the trench gate structure 65 interposed therebetween. As a result, heat generated in one channel formation region 72 can be suppressed from being transmitted to the other channel formation region 72, so that the occurrence of heat interference can be effectively suppressed. Thus, the first functional element formation region unit U1 is configured to be able to effectively suppress a temperature rise.

[0201] As shown in FIG. 26B, each second functional element formation region 233 of the second functional element formation region unit U2 has a configuration in which the source region 70 and the body contact region 73 are interchanged in the configuration shown in FIG. 26A. More specifically, the channel formation region 72 extends along the length direction of the trench gate structure 65. In the lateral direction intersecting the trench gate structure 65, the channel formation region 72 formed on one side of the trench gate structure 65 and the channel formation region 72 formed on the other side of the trench gate structure 65 are integrally formed. As a result, a zigzag channel formation region 72 is formed in each second functional element formation region 233. With such a configuration, in the second functional element formation region unit U2, the ratio of the area of the channel formation region 72 to the unit area is about 75%.

[0202] As shown in FIG. 26C, each third functional element formation region 234 of the third functional element formation region unit U3 has a configuration in which the length of the channel formation region 72 is extended about twice in the length direction of the trench gate structure 65 in the configuration shown in FIG. 26A. With such a configuration, in the third functional element formation region unit U3, the ratio of the area of the channel formation region 72 to the unit area is about 50%. The cross-sectional structure of the first to third functional element formation region units U3 in the present embodiment is substantially the same as the cross-sectional structure of the MISFET23a shown in FIG. 9.

[0203] (Manufacturing Method of MISFET) Referring to FIGS. 27A to 27K, an example of a method for manufacturing the MISFET 23a will be described. FIGS. 27A to 27K are longitudinal sectional views of a portion corresponding to the 27-27 line of FIG. 26A.

[0204] First, as shown in FIG. 27A, a wafer-like substrate 50 including a semiconductor substrate 61 and an epitaxial layer 62 formed on the semiconductor substrate 61 is prepared. Next, as shown in FIG. 27B, a hard mask 240 having a selective opening 241 is formed on the epitaxial layer 62 in a region where the trench 66 is to be formed. Then, by etching through the hard mask 240, the surface layer portion of the epitaxial layer 62 is selectively removed. As a result, a plurality of trenches 66 are formed. After the trenches 66 are formed, the hard mask 240 is removed.

[0205] Next, as shown in FIG. 27C, for example, by a thermal oxidation method, a thermal oxide film 242 made of silicon oxide is formed on the inner wall surface of the trench 66. Next, as shown in FIG. 27D, a polysilicon film 244 as a conductor is deposited on the epitaxial layer 62. The polysilicon film 244 fills the trenches 66 and covers the surface of the epitaxial layer 62. Thereafter, an n-type impurity is implanted into the polysilicon film 244 and diffused by heat treatment (drive-in). Examples of the n-type impurity include phosphorus (P), arsenic (As), etc.

[0206] Next, as shown in FIG. 27E, the polysilicon film 244 is etched. The etching of the polysilicon film 244 is continued until the etching surface reaches the middle of each depth direction of the trench 66. As a result, an embedded electrode 69 made of the remaining polysilicon film 244 is formed in the trench 66.

[0207] Next, as shown in FIG. 27F, a thick gate insulating film 67 located between the opening of the trench 66 and the upper end portion 69a of the embedded electrode 69 is etched. The thick gate insulating film 67 is removed such that a part thereof remains on each inner wall surface of the trench 66. At this time, a part of the upper end portion 69a of the embedded electrode 69 is exposed from the thick gate insulating film 67. In this case, the etching to be performed may be wet etching.

[0208] Next, as shown in FIG. 27G, by subjecting the substrate 50 to thermal oxidation treatment, a thermal oxide film 242 is formed on the exposed side surfaces of the trench 66 and the surface of the substrate 50. At this time, a part of the exposed upper end portion 69a of the embedded electrode 69 is also oxidized to form a thermal oxide film 242. At the upper end portion 69a of the embedded electrode 69, due to the polysilicon into which impurities are introduced, oxidation proceeds more than on the exposed surface side of the trench 66, and as a result, a relatively thick thermal oxide film 242 is formed. In this step, a recess 245 is formed between the upper end portion 69a of the embedded electrode 69 and the side surface of the trench 66 by the thick film portion 67a and the thin film portion 67b of the gate insulating film 67.

[0209] Next, as shown in FIG. 27H, a polysilicon film 246 as a conductor is deposited on the substrate 50. The polysilicon film 246 fills the trench 66 and covers the surface of the substrate 50. The polysilicon film 246 enters the recess 245 in the trench 66 and forms a recess 68a that opens toward the embedded electrode 69 by forming a protruding portion that extends downward between the polysilicon film 246 and the upper end portion 69a of the embedded electrode 69 in the trench 66. Thereafter, impurities are implanted into the polysilicon film 246 and diffused by heat treatment (drive-in). Next, the polysilicon film 246 is etched.

[0210] The etching of the polysilicon film 246 is continued until the etching surface reaches a position slightly inside the trench 66 from the surface of the substrate 50. As a result, gate electrodes 68 each made of the remaining polysilicon film 246 are formed in the trenches 66. In addition, a recess 247 is formed on the gate electrode 68.

[0211] Next, as shown in FIG. 27I, an ion implantation mask (not shown) that selectively opens in the region where the body region 71 is to be formed is formed on the substrate 50. Then, p-type impurities are implanted into the surface layer portion of the epitaxial layer 62 through the ion implantation mask. Thereby, the body region 71 is formed in the surface layer portion of the epitaxial layer 62. After the body region 71 is formed, the ion implantation mask is removed. Next, n-type impurities and p-type impurities are sequentially implanted into the substrate 50. Then, the implanted impurity ions are diffused by heat treatment (drive-in). As a result, n + -type source region 70 and p + -type body contact region 73 are formed. Next, as shown in FIG. 27J, for example, by the CVD method, a silicon nitride film and a silicon oxide film are sequentially deposited. Thereby, the interlayer insulating film 74 is formed.

[0212] Here, the source region 70 is formed by implanting n-type impurities through an ion implantation mask having a selective opening in the region where the source region 70 is to be formed. As a result, in plan view, a source region 70 having a relatively small area ratio per unit area and a source region 70 having a relatively large area ratio per unit area are selectively formed. That is, the first functional element formation region 232 (first functional element formation region unit U1), the second functional element formation region 233 (second functional element formation region unit U2), and the third functional element formation region 234 (third functional element formation region unit U3) are formed.

[0213] Also, the body contact region 73 is formed by implanting p-type impurities through an ion implantation mask having a selective opening in the region where the body contact region 73 is to be formed. Next, the interlayer insulating film 74 is selectively etched by reactive ion etching (RIE) to form the contact hole 248. Then, as shown in FIG. 27K, after the contacts 81 and 83 (not shown in FIG. 27K) are embedded in the contact hole 248, an electrode film (not shown) is formed so as to cover the region on the substrate 50. By patterning this electrode film, the source pad 21 (source metal 230) and the gate pad 22 (see FIG. 5) are formed. Also, an electrode film (not shown) is formed so as to cover the semiconductor substrate 61 of the substrate 50. By patterning this electrode film, the drain electrode 64 is formed. Through the above steps, the semiconductor device 1 (MISFET 23a) is obtained.

[0214] According to this embodiment, the following effects can be obtained. (4-1) In the active region 29, the first functional element formation region unit U1 having a configuration with a small heat generation amount and a large active clamp tolerance Eac is arranged in the region where heat generation should be suppressed. Thereby, the temperature rise in the active region 29 can be suppressed, and it is possible to suppress the region where heat generation in the active region 29 should be suppressed from becoming transiently and locally high temperature. Further, since the first functional element formation region unit U1 is arranged in the active region 29, for example, compared with a configuration in which the active region 29 is composed of the second functional element formation region unit U2 and the third functional element formation region unit U3, it is easier to improve the active clamp tolerance Eac.

[0215] (4-2) In a region other than the region where heat generation is to be suppressed in the active region 29, for example, in an outer region of the active region 29, a second functional element formation region unit U2 or a third functional element formation region unit U3 in which the ratio of the area of the channel formation region 72 per unit area is larger than that of the first functional element formation region unit U1 is arranged. Thereby, since the area of the channel formation region 72 is larger than that of the first functional element formation region unit U1 and a current path with a large area can be secured, even when the first functional element formation region unit U1 is used together, it is possible to suppress a decrease in the current path as viewed from the entire active region 29. Thereby, an increase in the on-resistance of the semiconductor element 20 can be suppressed by using a region other than the region where heat generation is to be suppressed in the active region 29.

[0216] (4-3) In the active region 29, a second functional element formation region unit U2 having a configuration with a large heat generation amount and a small active clamp tolerance Eac is arranged in a region corresponding to a location where the first wire 41 is connected to the source pad 21. According to this configuration, since the heat in the active region 29 moves to the first wire 41 through the source pad 21, the temperature is difficult to rise in the region corresponding to the location where the first wire 41 is connected to the source pad 21 in the active region 29. Therefore, by using the second functional element formation region unit U2 with a large heat generation amount, it is possible to contribute to suppressing an increase in the on-resistance of the semiconductor element 20.

[0217] (4-4) The active region 29 is composed of a first functional element formation region unit U1, a second functional element formation region unit U2, and a third functional element formation region unit U3. Thereby, it becomes easier to adjust the on-resistance and the active clamp tolerance Eac of the semiconductor element 20 as compared with the case where the active region 29 is composed of, for example, two types of functional element formation region units.

[0218] Also, in a part of the active region 29, a third functional element formation region unit U3 is disposed between the first functional element formation region unit U1 and the second functional element formation region unit U2. Thereby, it is possible to suppress a rapid change in the on-resistance and the active clamp withstand voltage Eac.

[0219] (Modification example) The description of each of the above embodiments is an exemplification of the forms that the semiconductor device of the present disclosure can take, and is not intended to limit the form. The semiconductor device of the present disclosure can take, for example, a modification example of each of the above embodiments shown below, and a form in which at least two modification examples that do not contradict each other are combined.

[0220] 〔Combination of embodiments〕 · The second embodiment and the third embodiment may be combined. That is, the structure of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 directly under the source pad 21 of the semiconductor device 1 of the second embodiment may be replaced with the structure of the interlayer insulating film 74, the first source electrode 80, and the second source electrode 82 of the third embodiment.

[0221] · The third embodiment and the fourth embodiment may be combined. That is, the active region 29 of the semiconductor device 1 of the third embodiment may be replaced with a structure having a plurality of functional element formation regions 231 in which the ratio of the area of the channel formation region 72 occupied per unit area is different as in the fourth embodiment.

[0222] 〔Addition of heat dissipation member〕 · In order to improve the active clamp withstand voltage Eac, it is necessary to improve the heat dissipation performance of the semiconductor device 1. Therefore, in each of the above embodiments, by connecting the heat dissipation member 250 to the source pad 21, the heat dissipation performance of the semiconductor device 1 can be improved. As an example, as shown in FIGS. 28A and 28B, a plurality of heat dissipation members 250 are connected to the source pad 21. FIG. 28A shows the arrangement mode of the heat dissipation member 250 when the connection point of the first wire 41 to the source pad 21 is one place, and FIG. 28B shows the arrangement mode of the heat dissipation member 250 when the connection point of the first wire 41 to the source pad 21 is two places.

[0223] As shown in FIGS. 28A and 28B, the plurality of heat dissipation members 250 are connected to the region of the source pad 21 corresponding to the region where heat generation should be suppressed in the active region 29. Specifically described, in FIG. 28A, the plurality of heat dissipation members 250 are connected to the region of the source pad 21 corresponding to the inner region of the active region 29. Specifically, the plurality of heat dissipation members 250 are arranged so as to surround a part of the connection portion 41a (dashed line) of the first wire 41. In order to avoid interference with the first wire 41, no heat dissipation member 250 is arranged in the direction in which the first wire 41 extends.

[0224] In FIG. 28B, it is arranged so as to surround a part of the first connection portion 41b and the second connection portion 41c (both dashed lines) which are the ends of the first wire 41. In order to avoid interference with the first wire 41, no heat dissipation member 250 is arranged in the direction in which the first wire 41 extends. Further, the plurality of heat dissipation members 250 are connected to the region of the source pad 21 corresponding to the inner region of the active region 29, that is, the region between the first connection portion 41b and the second connection portion 41c of the first wire 41 in the active region 29 and the region adjacent to the first wire 41 in the vertical direction Y.

[0225] Such a heat dissipation member 250 is formed by connecting a wire to the source pad 21 by wedge bonding or ball bonding. That is, the shape of the heat dissipation member 250 is the same as the shape of the connection portion when the wire is connected. The heat dissipation member 250 is made of, for example, copper or aluminum. Also, for example, the heat dissipation member 250 may be formed by connecting the first wire 41 to the source pad 21.

[0226] FIG. 29 shows an example of the heat dissipation member 250. The heat dissipation member 250 shown in FIG. 29 is a case where a wire is connected to the source pad 21 by ball bonding. Also, the arrangement modes of the plurality of heat dissipation members 250 in FIGS. 28A and 28B are examples, and the arrangement modes can be arbitrarily changed. For example, the plurality of heat dissipation members 250 may be connected to at least one of the regions of the source pad 21 corresponding to the regions where the plurality of third functional element formation region units U3 in the active region 29 shown in FIGS. 28A and 28B are arranged.

[0227] ·In the above first to third embodiments, one or a plurality of heat dissipation members 250 may be connected on the source pad 21. According to this configuration, since the heat dissipation performance of the semiconductor device 1 is improved through the source pad 21, the active clamp withstand voltage Eac can be improved.

[0228] 〔Connection position of the connection member〕 ·In the above first embodiment, as shown in FIG. 7, the first wire 41 as the connection member and the source pad 21 are connected to each other at a position on the line segment LA connecting the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2. The first wire 41 and the source pad 21 may be connected to each other at two positions, namely, the centroid position GA1 of the first region RA1 and the centroid position GA2 of the second region RA2.

[0229] 〔Shape and centroid position of the active region〕 · In each of the above embodiments, the shape of the active region 29 can be arbitrarily changed. The active region 29 can be changed as follows in (A) to (C) below. The center-of-gravity positions of the active region 29 in (A) to (C) will also be described together.

[0230] (A) As shown in FIGS. 30A and 30B, the shape of the active region 29 is a concave shape. In FIG. 30A, a case where the first wire 41 is connected to the source pad 21 at one location is shown. As shown in FIG. 30A, the active region 29 is divided into a first region RD1 having a rectangular shape with a recess 29x filled therein and a second region RD2 corresponding to the rectangular recess 29x. Next, the center-of-gravity position GD1 of the first region RD1 and the center-of-gravity position GD2 of the second region RD2 are obtained. As shown in FIG. 30A, since the first region RD1 and the second region RD2 are each rectangular, the center-of-gravity position GD1 of the first region RD1 is the intersection of the diagonal lines of the first region RD1, and the center-of-gravity position GD2 of the second region RD2 is the intersection of the diagonal lines of the second region RD2. Next, the area SD1 of the first region RD1 and the area SD2 of the second region RD2 are obtained respectively. Next, on the line segment LD connecting the center-of-gravity position GD1 and the center-of-gravity position GD2, the distance DD1 between the center-of-gravity position GD1 and the center-of-gravity position GD of the active region 29, and the distance DD2 between the center-of-gravity position GD2 and the center-of-gravity position GD of the active region 29, and the area SD1 of the first region RD1 and the area SD2 of the second region RD2 are used to obtain the center-of-gravity position GD of the active region 29. Specifically, the ratio of the distance DD2 to the distance DD1 (DD2 / DD1) is equal to the inverse ratio of the ratio of the area SD2 of the second region RD2 to the area SD1 of the first region RD1 (SD1 / SD2) (DD2 / DD1 = SD1 / SD2). Thus, by obtaining at least one of the distances DD1 and DD2, the center-of-gravity position GD of the active region 29 can be obtained. Also, as shown in FIG. 30A, the source pad 21 is provided so as to cover the center-of-gravity position GD of the active region 29.

[0231] The dashed-dotted line area RX shown in FIG. 30A indicates a tool head for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown) (hereinafter referred to as wedge RX). The wedge bonding apparatus moves the wedge RX so that the wedge RX is located on the center of gravity position GD of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap the center of gravity position GD of the active region 29. That is, the contact area of the first wire 41 with the source pad 21 includes the center of gravity position GD of the active region 29. In FIG. 30A, the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity position GD of the active region 29. In this modification, the contact area (wedge RX) of the first wire 41 with the source pad 21 only needs to include the center of gravity position GD of the active region 29, and the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 may be different from the center of gravity position GD of the active region 29.

[0232] FIG. 31A shows an example of the semiconductor device 1 using the active region 29 of FIG. 30A and the contact area (wedge RX) of the first wire 41 with the source pad 21. As shown in FIG. 31A, a part of the active region 29 is cut out for forming the gate pad 22 as compared with the active region 29 of FIG. 30A, but the point that the center position of the contact area (wedge RX) of the first wire 41 with the source pad 21 coincides with the center of gravity position GD of the active region 29 remains unchanged. Also, as shown in FIG. 31A, the recess 29x of the active region 29 is formed to be recessed in the lateral direction X. The control circuit region 29LG is formed across the notch 29w and the recess 29x in which the gate pad 22 is formed in the active region 29. Further, the temperature sensor 27 is provided at a position adjacent to the bottom surface 29xa of the recess 29x in the vertical direction Y and at the center of the recess 29x in the lateral direction X. As shown in FIG. 31A, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, on the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0233] FIG. 30B shows a case where the first wire 41 is connected to the source pad 21 at two locations. As shown in FIG. 30B, the active region 29 is divided into two regions (the first region RE1 and the second region RE2) having equal areas. As shown in FIG. 30B, the first region RE1 and the second region RE2 are formed in a substantially L shape. Next, the centroid position GE1 of the first region RE1 and the centroid position GE2 of the second region RE2 are obtained. The first region RE1 is divided into a first divided region RE11 and a second divided region RE12, which are two rectangular regions. Then, the centroid position GE11 of the first divided region RE11 and the centroid position GE12 of the second divided region RE12 are obtained. Since the first divided region RE11 is rectangular, the intersection of the diagonals of the first divided region RE11 is the centroid position GE11 of the first divided region RE11. Since the second divided region RE12 is rectangular, the intersection of the diagonals of the second divided region RE12 is the second centroid position GE12 of the divided region RE12. Next, the area SE1 of the first divided region RE11 and the area SE2 of the second divided region RE12 are obtained respectively. Next, on the line segment LE1 connecting the centroid position GE11 and the centroid position GE12, based on the relationship between the distance DE1 between the centroid position GE11 and the centroid position GE1, the distance DE2 between the centroid position GE12 and the centroid position GE1, and the area SE1 of the first divided region RE11 and the area SE2 of the second divided region RE12, the centroid position GE1 of the first region RE1 is obtained. Specifically, the ratio of the distance DE2 to the distance DE1 (DE2 / DE1) is equal to the inverse ratio of the ratio of the area SE2 of the second divided region RE12 to the area SE1 of the first divided region RE11 (SE1 / SE2) (DE2 / DE1 = SE1 / SE2). Thus, by obtaining at least one of the distances DE1 and DE2, the centroid position GE1 of the first region RE1 is obtained. Also, for the second region RE2, in the same way as the method for obtaining the centroid position GE1 of the first region RE1, on the line segment LE2 connecting the centroid position GE21 of the first divided region RE21 and the centroid position GE22 of the second divided region RE22, the centroid position GE2 is obtained based on the area SE21 of the first divided region RE21 and the area SE22 of the second divided region RE22.Also, as shown in FIG. 30B, the source pad 21 is provided so as to cover the respective centroid positions GE1 and GE2 (the centroid position GE1 of the first region RE1 and the centroid position GE2 of the second region RE2) of the divided active regions 29.

[0234] The two dashed-dotted line regions RY shown in FIG. 30B indicate tool heads (hereinafter referred to as wedge RY) for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the centroid position GE1 of the first region RE1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. Thereby, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GB1 of the first region RB1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid position GE1 of the first region RE1. In FIG. 30B, the center position of the first connection portion 41b coincides with the centroid position GE1 of the first region RE1. Next, the wedge bonding apparatus separates the wedge RY from the source pad 21 so that the first wire 41 is separated from the source pad 21. Then, the wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the centroid position GB2 of the second region RB2 of the active region 29, and connects the first wire 41 to the source pad 21. Thereby, the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GE2 of the second region RE2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid position GE2 of the second region RE2. In FIG. 30B, the center position of the second connection portion 41c coincides with the centroid position GE2 of the second region RE2. Note that in this modification, it is sufficient that the first connection portion 41b includes the centroid position GE1 of the first region RE1, and the center position of the first connection portion 41b may be different from the centroid position GE1 of the first region RE1. Also, it is sufficient that the second connection portion 41c includes the centroid position GE2 of the second region RE2, and the center position of the second connection portion 41c may be different from the centroid position GE2 of the second region RE2.

[0235] FIG. 31B shows an example of the semiconductor device 1 using the active region 29 of FIG. 30B and the contact region (wedge RX) to the source pad 21 of the first wire 41. The shape of the active region 29, the shape of the control circuit region 29LG, and the position of the temperature sensor 27 are the same as those in FIG. 31A. As shown in FIG. 31B, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, on the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0236] Also, the position of the temperature sensor 27 is not limited to the positions shown in FIGS. 31A and 31B and can be arbitrarily changed. In one example, as shown in FIG. 31C, the temperature sensor 27 may be provided so as to approach the region where the temperature is highest in the active region 29 during the driving of the semiconductor element 20. More specifically, the active region 29 shown in FIG. 31C has a second recess 29v that is recessed in the lateral direction X from the central portion in the longitudinal direction Y of the bottom surface 29xa of the recess 29x. The control circuit region 29LG has a convex portion 29u that enters the second recess 29v. The temperature sensor 27 is provided at the tip of the convex portion 29u. As shown in FIG. 31C, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, on the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0237] (B) As shown in FIGS. 32A and 32B, the shape of the active region 29 is convex. In FIG. 32A, a case where the first wire 41 is connected to the source pad 21 at one location is shown. As shown in FIG. 32A, the active region 29 is divided into a rectangular first region RF1 excluding the convex portion 29y and a second region RF2 corresponding to the rectangular convex portion 29y. Next, the centroid position GF1 of the first region RF1 and the centroid position GF2 of the second region RF2 are obtained. As shown in FIG. 32A, since the first region RF1 and the second region RF2 are each rectangular, the centroid position GF1 of the first region RF1 is the intersection of the diagonals of the first region RF1, and the centroid position GF2 of the second region RF2 is the intersection of the diagonals of the second region RF2. Next, the area SF1 of the first region RF1 and the area SF2 of the second region RF2 are obtained respectively. Next, on the line segment LF connecting the centroid position GF1 and the centroid position GF2, the distance DF1 between the centroid position GF1 and the centroid position GF of the active region 29, the distance DF2 between the centroid position GF2 and the centroid position GF of the active region 29, and the area SF1 of the first region RF1 and the area SF2 of the second region RF2 are used to obtain the centroid position GF of the active region 29 based on their relationship. Specifically, the ratio of the distance DF2 to the distance DF1 (DF2 / DF1) is equal to the inverse ratio of the ratio of the area SF2 of the second region RF2 to the area SF1 of the first region RF1 (SF1 / SF2) (DF2 / DF1 = SF1 / SF2). Thus, by obtaining at least one of the distances DF1 and DF2, the centroid position GF of the active region 29 can be obtained. Also, as shown in FIG. 32A, the source pad 21 is provided so as to cover the centroid position GF of the active region 29.

[0238] The region RX indicated by the dashed line in FIG. 32A shows a tool head for ultrasonically bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown) (hereinafter referred to as wedge RX). The wedge bonding apparatus moves the wedge RX so that the wedge RX is positioned on the centroid position GF of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap the centroid position GF of the active region 29. That is, the contact region of the first wire 41 with the source pad 21 includes the centroid position GF of the active region 29. In FIG. 32A, the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the centroid position GF of the active region 29. In this modification, it is sufficient that the contact region (wedge RX) of the first wire 41 with the source pad 21 includes the centroid position GF of the active region 29, and the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 may be different from the centroid position GF of the active region 29.

[0239] FIG. 33A shows an example of the semiconductor device 1 using the active region 29 of FIG. 32A and the contact region (wedge RX) to the source pad 21 of the first wire 41. In FIG. 33A, the semiconductor element 20 is provided such that the convex portion 29y of the active region 29 is on the side of the second lead frame 12 and the third lead frame 13 in the vertical direction Y. As shown in FIG. 33A, although a part of the active region 29 is cut out for the arrangement of the temperature sensor 27 as compared with the active region 29 of FIG. 32A, the point that the center position of the contact region (wedge RX) to the source pad 21 of the first wire 41 coincides with the center of gravity position GD of the active region 29 remains unchanged. Also, as shown in FIG. 33A, in the region adjacent to the side opposite to the gate pad 22 side with respect to the convex portion 29y in the active region 29, there is a concave portion 29t formed to be concave in the vertical direction Y. The control circuit region 29LG is arranged in parallel with the active region 29 in the vertical direction Y and is formed so as to surround the convex portion 29y of the active region 29 from the lateral direction X and the vertical direction Y. The control circuit region 29LG has a convex portion 29s that enters the concave portion 29t of the active region 29. The temperature sensor 27 is provided at the tip of the convex portion 29s. As shown in FIG. 33A, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, at a position on the side opposite to the gate pad 22 side in the lateral direction X with respect to the first wire 41.

[0240] FIG. 32B shows a case where the first wire 41 is connected to the source pad 21 at two locations. As shown in FIG. 32B, the active region 29 is divided into two regions (a first region RG1 and a second region RG2) having equal areas. As shown in FIG. 32B, the first region RG1 and the second region RG2 are formed in a substantially L shape. Next, the centroid position GG1 of the first region RG1 and the centroid position GG2 of the second region RG2 are obtained. The first region RG1 is divided into a first divided region RG11 and a second divided region RG12, which are two rectangular regions. Then, the centroid position GG11 of the first divided region RG11 and the centroid position GG12 of the second divided region RG12 are obtained. Since the first divided region RG11 is rectangular, the intersection of the diagonals of the first divided region RG11 is the centroid position GG11 of the first divided region RG11. Since the second divided region RG12 is rectangular, the intersection of the diagonals of the second divided region RG12 is the second centroid position GG12 of the divided region RG12. Next, the area SG1 of the first divided region RG11 and the area SG2 of the second divided region RG12 are obtained respectively. Next, on the line segment LG1 connecting the centroid position GG11 and the centroid position GG12, based on the relationship between the distance DG1 between the centroid position GG11 and the centroid position GG1, the distance DG2 between the centroid position GG12 and the centroid position GG1, and the area SG1 of the first divided region RG11 and the area SG2 of the second divided region RG12, the centroid position GG1 of the first region RG1 is obtained. More specifically, the ratio of the distance DG2 to the distance DG1 (DG2 / DG1) is equal to the inverse ratio of the ratio of the area SG2 of the second divided region RG12 to the area SG1 of the first divided region RG11 (SG1 / SG2) (DG2 / DG1 = SG1 / SG2). Thus, by obtaining at least one of the distances DG1 and DG2, the centroid position GG1 of the first region RG1 is obtained. Also, for the second region RG2, in the same way as the method for obtaining the centroid position GG1 of the first region RG1, on the line segment LG2 connecting the centroid position GG21 of the first divided region RG21 and the centroid position GG22 of the second divided region RG22, the centroid position GG2 is obtained based on the area SG21 of the first divided region RG21 and the area SG22 of the second divided region RG22.Also, as shown in FIG. 32B, the source pad 21 is provided so as to cover the respective centroid positions GG1 and GG2 (the centroid position GG1 of the first region RG1 and the centroid position GG2 of the second region RG2) of the divided active regions 29.

[0241] The two dashed-dotted line regions RY shown in FIG. 32B indicate tool heads (hereinafter referred to as wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the centroid position GG1 of the first region RG1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. Thereby, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GG1 of the first region RG1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid position GG1 of the first region RG1. In FIG. 32B, the center position of the first connection portion 41b coincides with the centroid position GG1 of the first region RG1. Next, the wedge bonding apparatus separates the wedge RY from the source pad 21 so that the first wire 41 is separated from the source pad 21. Then, the wedge bonding apparatus moves the wedge RY so that the wedge RY is positioned on the centroid position GG2 of the second region RG2 of the active region 29, and connects the first wire 41 to the source pad 21. Thereby, the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GG2 of the second region RG2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid position GG2 of the second region RG2. In FIG. 32B, the center position of the second connection portion 41c coincides with the centroid position GG2 of the second region RG2. Note that in this modification, it is sufficient that the first connection portion 41b includes the centroid position GG1 of the first region RG1, and the center position of the first connection portion 41b may be different from the centroid position GG1 of the first region RG1. Also, it is sufficient that the second connection portion 41c includes the centroid position GG2 of the second region RG2, and the center position of the second connection portion 41c may be different from the centroid position GG2 of the second region RG2.

[0242] FIG. 33B shows an example of the semiconductor device 1 using the active region 29 of FIG. 32B and the contact region (wedge RX) to the source pad 21 of the first wire 41. In FIG. 33B, the convex portion 29y of the active region 29 extends in the lateral direction X, and the semiconductor element 20 is provided such that the convex portion 29y is on the side of the second lead frame 12 in the lateral direction X. As shown in FIG. 33B, a part of the active region 29 is cut out for the arrangement of the temperature sensor 27 as compared with the active region 29 of FIG. 32B, but the point that the center position of the contact region (wedge RX) to the source pad 21 of the first wire 41 coincides with the centroid position GD of the active region 29 remains unchanged. Also, as shown in FIG. 33B, in the region adjacent to the side opposite to the gate pad 22 with respect to the convex portion 29y in the active region 29, there is a recess 29r formed to be recessed in the vertical direction Y. The recess 29r is formed to be recessed obliquely toward the third lead frame 13. The control circuit region 29LG is arranged in parallel with the active region 29 in the lateral direction X and is formed so as to surround the convex portion 29y of the active region 29 from the lateral direction X and the vertical direction Y. The gate pad 22 is on the side of the second lead frame 12 rather than the convex portion 29y of the active region 29 in the vertical direction Y and is formed between the control circuit region 29LG and the active region 29 in the lateral direction X. The control circuit region 29LG has a convex portion 29q that enters the recess 29r of the active region 29. The temperature sensor 27 is provided at the tip of the convex portion 29q. As shown in FIG. 33B, the temperature sensor 27 is provided at a position that does not overlap with the first wire 41 in a plan view, that is, at a position between the first wire 41 and the gate pad 22 in the lateral direction X.

[0243] (C) As shown in FIGS. 34A and 34B, the shape of the active region 29 is a shape in which a plurality of rectangular shapes are combined. FIG. 34A shows a case where the first wire 41 is connected to the source pad 21 at one location. As shown in FIG. 34A, the active region 29 is divided into a rectangular first region RH1 and a convex second region RH2. Next, the centroid position GH1 of the first region RH1 and the centroid position GH2 of the second region RH2 are obtained. As shown in FIG. 34A, since the first region RH1 is rectangular, the centroid position GH1 of the first region RH1 is the intersection of the diagonals of the first region RH1. Since the second region RH2 is convex, similar to the active region 29 in FIG. 33A, the second region RH2 is divided into a first divided region RH21 and a second divided region RH22, which are two rectangular regions. Then, the centroid position GH21 of the first divided region RH21 and the centroid position GH22 of the second divided region RH22 are obtained. Since the first divided region RH21 is rectangular, the intersection of the diagonals of the first divided region RH21 is the centroid position GH21 of the first divided region RH21. Since the second divided region RH22 is rectangular, the intersection of the diagonals of the second divided region RH22 is the second centroid position GH22 of the second divided region RH22. Next, the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22 are obtained respectively. Next, on the line segment LH1 connecting the centroid position GH21 and the centroid position GH22, based on the relationship between the distance DH21 between the centroid position GH21 and the centroid position GH2, the distance DH22 between the centroid position GH22 and the centroid position GH2, and the area SH21 of the first divided region RH21 and the area SH22 of the second divided region RH22, the centroid position GH2 of the second region RH2 is obtained. Specifically, the ratio of the distance DH22 to the distance DH21 (DH22 / DH21) is equal to the inverse ratio of the ratio of the area SH22 of the second divided region RH22 to the area SH21 of the first divided region RH21 (SH21 / SH22) (DH22 / DH21 = SH21 / SH22). Thus, by obtaining at least one of the distances DH21 and DH22, the centroid position GH2 of the second region RH2 is obtained.

[0244] Next, on the line segment LH2 connecting the centroid position GH1 of the first region RH1 and the centroid position GH2 of the second region RH2, based on the relationship between the distance DH1 between the centroid position GH1 and the centroid position GH of the active region 29, the distance DH2 between the centroid position GH2 and the centroid position GH of the active region 29, the area SH1 of the first region RH1, and the area SH2 of the second region RH2, the centroid position GH of the active region 29 is obtained. Specifically, the ratio of the distance DH1 to the distance DH2 (DH1 / DH2) is equal to the inverse ratio of the ratio of the area SH2 of the second region RH2 to the area SH1 of the first region RH1 (SH1 / SH2) (DH2 / DH1 = SH1 / SH2). Thus, by obtaining at least one of the distances DH1 and DH2, the centroid position GH of the active region 29 is obtained.

[0245] The region RX indicated by the dashed line in FIG. 34A shows a tool head for ultrasonic bonding the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown) (hereinafter referred to as the wedge RX). The wedge bonding apparatus moves the wedge RX so that the wedge RX is located on the centroid position GD of the active region 29. The end of the first wire 41 passed through the wedge RX is connected so as to overlap the centroid position GH of the active region 29. That is, the contact region of the first wire 41 with the source pad 21 includes the centroid position GH of the active region 29. In FIG. 34A, the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 coincides with the centroid position GH of the active region 29. In this modification, the contact region (wedge RX) of the first wire 41 with the source pad 21 only needs to include the centroid position GH of the active region 29, and the center position of the contact region (wedge RX) of the first wire 41 with the source pad 21 may be a position different from the centroid position GH of the active region 29.

[0246] FIG. 35A shows an example of the semiconductor device 1 using the active region 29 of FIG. 34A and the contact region (wedge RX) to the source pad 21 of the first wire 41. In FIG. 35A, the first region RH1 and the second region RH2 in the active region 29 are arranged in the lateral direction X, and the semiconductor element 20 is provided such that the second divided region RH22 of the second region RH2 is on the side of the second lead frame 12. As shown in FIG. 35A, the gate pad 22 is formed adjacent to the second divided region RH22 on the side opposite to the first region RH1 with respect to the second divided region RH22. Further, the control circuit region 29LG is arranged in parallel with the active region 29 in the longitudinal direction Y, and has a convex portion 29p that enters between the second divided region RH22 and the first region RH1 of the active region 29 in the lateral direction X. The temperature sensor 27 is provided at the tip of the convex portion 29p. As shown in FIG. 35A, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in plan view, that is, at a position on the side of the second lead frame 12 in the longitudinal direction Y with respect to the first wire 41.

[0247] FIG. 34B shows a case where the first wire 41 is connected to the source pad 21 at two locations. As shown in FIG. 34B, the active region 29 is divided into two regions (a first region RJ1 and a second region RJ2) having equal areas. As shown in FIG. 34B, the first region RJ1 is formed in a substantially L shape, and the second region RJ2 is formed in a convex shape. Next, the centroid position GJ1 of the first region RJ1 and the centroid position GJ2 of the second region RJ2 are obtained. The first region RJ1 is divided into a first divided region RJ11 and a second divided region RJ12, which are two rectangular regions. Then, the centroid position GJ11 of the first divided region RJ11 and the centroid position GJ12 of the second divided region RJ12 are obtained. Since the first divided region RJ11 is rectangular, the intersection of the diagonals of the first divided region RJ11 is the centroid position GJ11 of the first divided region RJ11. Since the second divided region RJ12 is rectangular, the intersection of the diagonals of the second divided region RJ12 is the centroid position GJ12 of the divided region RJ12. Next, the area SJ11 of the first divided region RJ11 and the area SJ12 of the second divided region RJ12 are obtained respectively. Next, on the line segment LJ1 connecting the centroid position GJ11 and the centroid position GJ12, based on the relationship between the distance DJ11 between the centroid position GJ11 and the centroid position GJ1, the distance DJ12 between the centroid position GJ12 and the centroid position GJ1, the area SJ11 of the first divided region RJ11, and the area SJ12 of the second divided region RJ12, the centroid position GJ1 of the first region RJ1 is obtained. More specifically, the ratio of the distance DJ12 to the distance DJ11 (DJ12 / DJ11) is equal to the inverse ratio of the ratio of the area SJ12 of the second divided region RJ12 to the area SJ11 of the first divided region RJ11 (SJ11 / SJ12) (DJ12 / DJ11 = SJ11 / SJ12). Thus, by obtaining at least one of the distances DJ11 and DJ12, the centroid position GJ1 of the first region RJ1 is obtained.

[0248] Also, the second region RJ2 is divided into a first divided region RJ21 and a second divided region RJ22, which are two rectangular regions. Then, the centroid position GJ21 of the first divided region RJ21 and the centroid position GJ22 of the second divided region RJ22 are obtained. Since the first divided region RJ21 is rectangular, the intersection point of the diagonals of the first divided region RJ21 is the centroid position GJ21 of the first divided region RJ21. Since the second divided region RJ22 is rectangular, the intersection point of the diagonals of the second divided region RJ22 is the second centroid position GJ22 of the divided region RJ22. Next, the area SJ21 of the first divided region RJ21 and the area SJ22 of the second divided region RJ22 are obtained respectively. Next, on the line segment LJ2 connecting the centroid position GJ21 and the centroid position GJ22, based on the relationship between the distance DJ21 between the centroid position GJ21 and the centroid position GJ2, the distance DJ22 between the centroid position GJ22 and the centroid position GJ2, the area SJ21 of the first divided region RJ21, and the area SJ22 of the second divided region RJ22, the centroid position GJ2 of the second region RJ2 is obtained. More specifically, the ratio of the distance DJ22 to the distance DJ21 (DJ22 / DJ21) is equal to the inverse ratio of the ratio of the area SJ22 of the second divided region RJ22 to the area SJ21 of the first divided region RJ21 (SJ21 / SJ22) (DJ22 / DJ21 = SJ21 / SJ22). Thus, by obtaining at least one of the distances DJ21 and DJ22, the centroid position GJ2 of the second region RJ2 is obtained.

[0249] The two dashed-dotted line regions RY shown in FIG. 34B indicate a tool head (hereinafter referred to as wedge RY) for ultrasonically connecting the first wire 41 to the source pad 21 in a wedge bonding apparatus (not shown). The wedge bonding apparatus moves the wedge RY so that the wedge RY is located on the centroid position GJ1 of the first region RJ1 of the active region 29, and connects the end of the first wire 41 to the source pad 21. Thereby, the end of the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GJ1 of the first region RJ1. That is, the first connection portion 41b of the first wire 41 to the source pad 21 includes the centroid position GJ1 of the first region RJ1. In FIG. 34B, the center position of the first connection portion 41b coincides with the centroid position GJ1 of the first region RJ1. Next, the wedge bonding apparatus separates the wedge RY from the source pad 21 so that the first wire 41 is separated from the source pad 21. Then, the wedge bonding apparatus moves the wedge RY so that the wedge RY is located on the centroid position GJ2 of the second region RJ2 of the active region 29, and connects the first wire 41 to the source pad 21. Thereby, the first wire 41 passed through the wedge RY is connected so as to overlap the centroid position GJ2 of the second region RJ2. That is, the second connection portion 41c of the first wire 41 to the source pad 21 includes the centroid position GJ2 of the second region RJ2. In FIG. 34B, the center position of the second connection portion 41c coincides with the centroid position GJ2 of the second region RJ2. Note that in this modification, the first connection portion 41b only needs to include the centroid position GJ1 of the first region RJ1, and the center position of the first connection portion 41b may be different from the centroid position GJ1 of the first region RJ1. Also, the second connection portion 41c only needs to include the centroid position GJ2 of the second region RJ2, and the center position of the second connection portion 41c may be different from the centroid position GJ2 of the second region RJ2.

[0250] FIG. 35B shows an example of the semiconductor device 1 using the active region 29 of FIG. 34B and the contact region (wedge RX) to the source pad 21 of the first wire 41. The shapes of the active region 29 and the control circuit region 29LG in FIG. 35B, and the position of the temperature sensor 27 are the same as those in FIG. 35A. As shown in FIG. 35B, the temperature sensor 27 is provided at a position that does not overlap the first wire 41 in a plan view, that is, on the side of the second lead frame 12 in the vertical direction Y with respect to the first wire 41.

[0251] 〔Multiple first wires〕 · In the second embodiment, there was one first wire 41, but the number of first wires 41 is not limited to this. For example, as shown in FIG. 36, the semiconductor element 20 and the third lead frame 13 may be connected by two first wires 41A and 41B. In this case, as shown in FIG. 37, when the active region 29 is divided into a first region RB1 and a second region RB2 having the same area as in the second embodiment, the first region RB1 and the second region RB2 are arranged in the vertical direction Y, and the semiconductor element 20 is provided such that the second region RB2 is on the side of the third lead frame 13. The gate pad 22 is formed so as to be adjacent to the end portion of the second region RB2 on the side of the third lead frame 13 in the vertical direction Y in the horizontal direction X. The gate pad 22 is formed on the side of the second lead frame 12 with respect to the second region RB2. The position of the temperature sensor 27 with respect to the active region 29 is the same as in the second embodiment.

[0252] Also, in FIG. 37, the active region 29 is divided into a first region RB1 and a second region RB2 having the same area as in the second embodiment, and the center-of-gravity position GB1 of the first region RB1 and the center-of-gravity position GB2 of the second region RB2 are obtained. As shown in FIG. 37, the first wire 41A is connected to the region of the source pad 21 corresponding to the center-of-gravity position GB1 of the first region RB1, and the first wire 41B is connected to the region of the source pad 21 corresponding to the center-of-gravity position GB2 of the second region RB2. As shown in FIG. 36, the temperature sensor 27 is provided at a position that does not overlap the two first wires 41A and 41B in a plan view. That is, the temperature sensor 27 is located on the side of the second lead frame 12 in the lateral direction X from the first wire 41A and on the side opposite to the gate pad 22 side in the longitudinal direction Y from the first wire 41B.

[0253] 〔Modification Example of the First Connection Member〕 ·In each of the above embodiments, the first wire 41 is used as the first connection member, but the present invention is not limited to this. Instead of the first wire 41 as the first connection member, for example, a connection plate (hereinafter, "clip 45") shown in FIG. 38 may be used. The clip 45 has an element connection portion 46 connected to the semiconductor element 20, a lead connection portion 47 connected to the third island portion 13a of the third lead frame 13, and a connection portion 48 connecting the element connection portion 46 and the lead connection portion 47.

[0254] The element connection portion 46 is connected to the source pad 21 of the semiconductor element 20 by, for example, solder. The element connection portion 46 is formed in a strip shape in a plan view. The element connection portion 46 is formed with a first protrusion 46a and a second protrusion 46b. The first protrusion 46a and the second protrusion 46b are provided so as to be closer to the source pad 21 than other portions of the element connection portion 46. The first protrusion 46a is disposed at a position including the wedge RY including the center-of-gravity position GB1 of the first region RB1, and the second protrusion 46b is disposed at a position including the wedge RY including the center-of-gravity position GB2 of the second region RB2.

[0255] The lead connection part 47 is formed in a rectangular flat plate shape. The lead connection part 47 is connected to the third island part 13a of the third lead frame 13 by solder. The connecting part 48 extends along the vertical direction Y. In FIG. 38, the size of the connecting part 48 in the horizontal direction X is formed to increase as it goes from the lead connection part 47 to the element connection part 46 in the vertical direction Y. The connecting part 48 is bent from each of the element connection part 46 and the lead connection part 47, and is arranged at a position spaced apart from the semiconductor element 20 more than the element connection part 46 and the lead connection part 47 in the thickness direction Z.

[0256] As the material of the clip 45, for example, copper (Cu), aluminum (Al), copper alloy, aluminum alloy, etc. can be used. Substantially the entire surface of the clip 45 is covered with a plating layer. As the material of the plating layer, for example, silver (Ag), nickel (Ni), tin (Sn), alloys containing them, etc. can be used. Note that a plurality of plating layers can also be used. Also, the shape of the clip 45 is not limited to the shape of the clip 45 shown in FIG. 38 and can be arbitrarily changed.

[0257] 〔Structure of MISFET〕 ·In each of the above embodiments, the structure of the MISFET 23a can be arbitrarily changed. In one example, the structure of the MISFET 23a shown in FIG. 39 may be used. The MISFET 23a in FIG. 39 has different gate electrode structures and source pad 21 structures compared to the MISFET 23a in each of the above embodiments.

[0258] As shown in FIG. 39, only the gate electrode 260 is embedded in the trench 66. That is, the MISFET 23a in FIG. 39 has a structure in which the embedded electrode 69 is omitted from the MISFET 23a of each of the above embodiments. According to this configuration, no recess 68a is formed in the gate electrode 260. Also, the depth of the trench 66 can be arbitrarily changed. For example, the trench 66 of the MISFET 23a shown in FIG. 39 may be formed shallower than the depth of the trench 66 of the MISFET 23a of each of the above embodiments. As shown in FIG. 39, the thickness of the body contact region 73 may be greater than the thickness of the source region 70.

[0259] As shown in FIG. 39, the source pad 270 has a plurality of laminated structures. Specifically, the source pad 270 includes a first protective layer 271 covering the epitaxial layer 62 and the interlayer insulating film 74, a first electrode layer 272 covering the first protective layer 271, a second protective layer 273 covering the first electrode layer 272, and a second electrode layer 274 covering the second protective layer 273. Also, a connection layer 275 for connecting the first wire 41 is formed on the second electrode layer 274. The connection layer 275 is formed by nickel palladium (NiPd) alloy plating.

[0260] The first protective layer 271 and the second protective layer 273 are made of, for example, titanium nitride (TiN). The thickness of each of the first protective layer 271 and the second protective layer 273 is thinner than the thickness of each of the first electrode layer 272 and the second electrode layer 274. The first electrode layer 272 and the second electrode layer 274 are made of, for example, aluminum or an aluminum alloy. In one example, the first electrode layer 272 is made of AlSiCu. The second electrode layer 274 is made of AlCu. Note that the first electrode layer 272 and the second electrode layer 274 may be made of copper. Also, the Vickers hardness of each of the first protective layer 271 and the second protective layer 273 is greater than the Vickers hardness of each of the first electrode layer 272 and the second electrode layer 274. Thereby, the first protective layer 271 and the second protective layer 273 are less likely to be deformed compared to the first electrode layer 272 and the second electrode layer 274.

[0261] According to the configuration of the source pad 270 like this, when the first wire 41 is connected to the source pad 270 by, for example, wedge bonding, the stress applied to the gate insulating film 67 due to the force or vibration applied to the source pad 270 can be reduced. Therefore, the occurrence of cracks in the gate insulating film 67 can be suppressed.

[0262] Also, the thickness Tsp of the source pad 270 is 16000 Å or more, and preferably 20000 Å or more. FIG. 40 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the stress (maximum principal stress) applied to the gate insulating film 67 when the first wire 41 is connected to the source pad 270. As can be seen from the graph of FIG. 40, the stress applied to the gate insulating film 67 is reduced as the thickness Tsp of the source pad 270 increases. In particular, when the thickness Tsp is less than 20000 Å, the degree of increase in the stress applied to the gate insulating film 67 increases as the thickness Tsp decreases. On the other hand, when the thickness Tsp is more than 20000 Å, the degree of increase in the stress applied to the gate insulating film 67 is small even if the thickness Tsp decreases.

[0263] FIG. 41 is a graph showing the relationship between the thickness Tsp of the source pad 270 and the TDDB failure time. Here, the TDDB failure time is, for example, the time until the cumulative failure reaches 0.1% in a TDDB (Time Dependent Dielectric Breakdown) test.

[0264] As can be seen from FIG. 41, when the thickness Tsp of the source pad 270 is 8000 Å or more and less than 16000 Å, the stress applied to the gate insulating film 67 increases when the first wire 41 is connected to the source pad 270, and damage occurs to the gate insulating film 67, so that the semiconductor element 20 fails in a short time. On the other hand, when the thickness Tsp of the source pad 21 is 16000 Å or more, particularly in the range where the thickness Tsp is 16000 Å or more and 20000 Å or less, the TDDB failure time rapidly increases as the thickness Tsp increases. That is, the semiconductor element 20 becomes less likely to fail as the thickness Tsp increases in the range of 16000 Å or more and 20000 Å or less. Thus, when the thickness Tsp of the source pad 270 is 16000 Å or more, particularly 20000 Å or more, the semiconductor element 20 becomes less likely to fail.

[0265] 〔Sealing resin〕 ·In each of the above embodiments, an ion trap material containing aluminum (Al) and magnesium (Mg) may be added to the sealing resin 30. According to this configuration, the ion trap material captures chloride ions (Cl - ) in the sealing resin 30, so that it is possible to suppress the chloride ions from binding to the first wire 41 and generating pitting corrosion.

[0266] 〔Lead frame〕 ·In each of the above embodiments, the location where the plating layer 14 is formed on the lead frame 10 can be arbitrarily changed. For example, the plating layer 14 may be partially formed on the lead frame 10. In one example, the plating layer 14 is formed on each of the first island portion 11a of the first lead frame 11, the second island portion 12a of the second lead frame 12, and the third island portion 13a of the third lead frame 13. The plating layer 14 is not formed on at least one of the first terminal portion 11b of the first lead frame 11, the second terminal portion 12b of the second lead frame 12, and the third terminal portion 13b of the third lead frame 13.

[0267] 〔Functional element formation region〕 · In the above first to third embodiments, the ratio of the area of the channel formation region 72 per unit area is not limited to 50%, and can be arbitrarily changed. For example, the ratio of the area of the channel formation region 72 per unit area may be 25% or 75%. The ratio of the area of the channel formation region 72 per unit area is set based on the balance between the active clamp tolerance Eac and the on-resistance. Note that the ratio of the area of the channel formation region 72 per unit area is preferably, for example, 20% or more and 80% or less.

[0268] · In the above fourth embodiment, a second functional element formation region unit U2 with a large heat generation amount may be arranged in a region adjacent to the temperature sensor 27 in the active region 29. Thereby, it is possible to adjust the temperature near the temperature sensor 27 to be the highest in the active region 29.

[0269] · In the above fourth embodiment, the plurality of functional element formation regions 231 are composed of the first to third functional element formation regions 232 to 234, but the types of the plurality of functional element formation regions 231 are not limited thereto. The number of types of the functional element formation regions 231 can be arbitrarily changed. For example, the types of the functional element formation regions 231 may be composed of two types of functional element formation regions, or may be composed of four or more types of functional element formation regions. Also, the ratio of the area of the channel formation region 72 per unit area in the above fourth embodiment was 25%, 50%, or 75%, but it is not limited thereto, and other values (for example, 30%, 60%, 80%, etc.) may be used.

[0270] 〔Application Example of Semiconductor Device 1〕 With reference to FIGS. 42 to 46, a circuit to which the semiconductor device 1 is applied will be illustrated and described. (First Application Example) As shown in FIG. 42, the semiconductor device 1 can constitute an asynchronous rectification type switching power supply circuit 280. The switching power supply circuit 280 includes one semiconductor device 1, an inductor 281, and a smoothing capacitor 282. The switching power supply circuit 280 drives the semiconductor device 1 to generate a desired output voltage Vout from the input voltage Vin.

[0271] (Second Application Example) As shown in FIG. 43, the semiconductor device 1 can constitute a synchronous rectification type switching power supply circuit 290. The switching power supply circuit 290 includes an inverter section 291, an inductor 292, and a smoothing capacitor 293. The inverter section 291 includes an upper switching element 294U and a lower switching element 294L. The source terminal of the upper switching element 294U and the drain terminal of the lower switching element 294L are electrically connected. The gate terminal of the upper switching element 294U and the gate terminal of the lower switching element 294L are connected to a gate drive circuit 295. The switching power supply circuit 290 drives the upper switching element 294U and the lower switching element 294L complementarily (exclusively) to generate a desired output voltage Vout from the input voltage Vin. The semiconductor device 1 can be applied to at least one of the upper switching element 294U and the lower switching element 294L. For example, when the semiconductor device 1 is applied to the lower switching element 294L, the lower switching element 294L in the inverter section 291 and the gate drive circuit that drives the lower switching element 294L in the gate drive circuit 295 are replaced by the semiconductor device 1.

[0272] (Third Application Example) The semiconductor device 1 can be applied to an H-bridge type converter. FIG. 44 shows the circuit configuration of an H-bridge type buck-boost converter circuit (hereinafter simply referred to as "converter circuit 300"), which is an example of an H-bridge type converter.

[0273] The converter circuit 300 includes a first inverter section 301, a second inverter section 302, an input capacitor 303, an output capacitor 304, an inductance 305, and a gate drive circuit 306, and steps up or down the input voltage Vi to the output voltage Vo.

[0274] The first inverter section 301 has an upper switching element 301U and a lower switching element 301L. The source terminal of the upper switching element 301U and the drain terminal of the lower switching element 301L are electrically connected. The first inverter section 301 is connected in parallel with the input capacitor 303. Specifically, the drain terminal of the upper switching element 301U is electrically connected to the first terminal of the input capacitor 303, and the source terminal of the lower switching element 301L is electrically connected to the second terminal of the input capacitor 303.

[0275] The second inverter section 302 has an upper switching element 302U and a lower switching element 302L. The source terminal of the upper switching element 302U and the drain terminal of the lower switching element 302L are electrically connected. The second inverter section 302 is connected in parallel with the output capacitor 304. Specifically, the drain terminal of the upper switching element 302U is electrically connected to the first terminal of the output capacitor 304, and the source terminal of the lower switching element 302L is electrically connected to the second terminal of the output capacitor 304.

[0276] The inductance 305 is connected to the first inverter section 301 and the second inverter section 302. Specifically, the first terminal of the inductance 305 is connected to the connection point between the source terminal of the upper switching element 301U and the drain terminal of the lower switching element 301L in the first inverter section 301. The second terminal of the inductance 305 is connected to the connection point between the source terminal of the upper switching element 302U and the drain terminal of the lower switching element 302L in the second inverter section 302.

[0277] The gate drive circuit 306 is electrically connected to the gate terminals of each of the switching elements 301U, 301L, 302U, and 302L. The gate drive circuit 306 controls the on / off of each of the switching elements 301U, 301L, 302U, and 302L.

[0278] The semiconductor device 1 can be applied to at least one of the switching elements 301U, 301L, 302U, and 302L. For example, when the semiconductor device 1 is applied to the lower switching element 301L of the first inverter section 301, the lower switching element 301L in the first inverter section 301 and the gate drive circuit that drives the lower switching element 301L in the gate drive circuit 306 are replaced with the semiconductor device 1.

[0279] (Fourth application example) The semiconductor device 1 can be applied to the full-bridge type inverter circuit shown in FIG. 45 (hereinafter simply referred to as "inverter circuit 310"). The inverter circuit 310 includes a first inverter section 311, a second inverter section 312, an input capacitor 313, and a gate drive circuit 314, and converts the input voltage Vi into an output voltage Vo between the first inverter section 311 and the second inverter section 312.

[0280] The first inverter section 311 has an upper switching element 311U and a lower switching element 311L. The source terminal of the upper switching element 311U and the drain terminal of the lower switching element 311L are electrically connected. The first inverter section 311 is connected in parallel with the input capacitor 313. More specifically, the drain terminal of the upper switching element 311U is electrically connected to the first terminal of the input capacitor 313, and the source terminal of the lower switching element 311L is electrically connected to the second terminal of the input capacitor 313.

[0281] The second inverter section 312 has an upper switching element 312U and a lower switching element 312L. The source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L are electrically connected. The second inverter section 312 is connected in parallel with the first inverter section 311. More specifically, the drain terminal of the upper switching element 312U is electrically connected to the drain terminal of the upper switching element 311U, and the source terminal of the lower switching element 312L is electrically connected to the source terminal of the lower switching element 311L. The output voltage Vo is defined as the voltage obtained between the connection point of the source terminal of the upper switching element 311U and the drain terminal of the lower switching element 311L and the connection point of the source terminal of the upper switching element 312U and the drain terminal of the lower switching element 312L.

[0282] The gate drive circuit 314 is electrically connected to the gate terminals of the respective switching elements 311U, 311L, 312U, and 312L. The gate drive circuit 314 controls the on / off of the respective switching elements 311U, 311L, 312U, and 312L.

[0283] The semiconductor device 1 can be applied to at least one of the switching elements 311U, 311L, 312U, and 312L. For example, when the semiconductor device 1 is applied to the lower switching element 311L of the first inverter section 311, the lower switching element 311L in the first inverter section 311 and the gate drive circuit in the gate drive circuit 314 that drives the lower switching element 311L are replaced with the semiconductor device 1.

[0284] (Fifth application example) The semiconductor device 1 can be applied to the three-phase AC inverter circuit shown in FIG. 46 (hereinafter, simply referred to as "three-phase inverter circuit 320").

[0285] The three-phase inverter circuit 320 includes a power drive unit 321 electrically connected to the coils of the U-phase, V-phase, and W-phase of a three-phase AC motor (hereinafter simply referred to as "motor 327"), a gate drive circuit 325 that controls the power drive unit 321, and a converter unit 326 connected to the power drive unit 321 and a power supply ES. The converter unit 326 has a positive power terminal EP and a negative power terminal EN.

[0286] The power drive unit 321 controls the power supplied to the coils of the U-phase, V-phase, and W-phase of the motor 327. The power drive unit 321 includes a U-phase inverter unit 322, a V-phase inverter unit 323, and a W-phase inverter unit 324. The U-phase inverter unit 322, the V-phase inverter unit 323, and the W-phase inverter unit 324 are connected in parallel with each other between the positive power terminal EP and the negative power terminal EN.

[0287] The U-phase inverter unit 322 includes an upper switching element 322U and a lower switching element 322L. The drain terminal of the upper switching element 322U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 322U and the drain terminal of the lower switching element 322L are electrically connected. The source terminal of the lower switching element 322L is connected to the negative power terminal EN. A snubber diode 322A is connected in anti-parallel to the upper switching element 322U, and a snubber diode 322B is connected in anti-parallel to the lower switching element 322L. Specifically, the anode of the snubber diode 322A is electrically connected to the source terminal of the upper switching element 322U, and the cathode of the snubber diode 322A is electrically connected to the drain terminal of the upper switching element 322U. The anode of the snubber diode 322B is electrically connected to the source terminal of the lower switching element 322L, and the cathode of the snubber diode 322B is electrically connected to the drain terminal of the lower switching element 322L.

[0288] The V-phase inverter section 323 has an upper switching element 323U and a lower switching element 323L. The drain terminal of the upper switching element 323U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 323U and the drain terminal of the lower switching element 323L are electrically connected. The source terminal of the lower switching element 323L is connected to the negative power terminal EN. A snubber diode 323A is connected in anti-parallel to the upper switching element 323U, and a snubber diode 323B is connected in anti-parallel to the lower switching element 323L. More specifically, the anode of the snubber diode 323A is electrically connected to the source terminal of the upper switching element 323U, and the cathode of the snubber diode 323A is electrically connected to the drain terminal of the upper switching element 323U. The anode of the snubber diode 323B is electrically connected to the source terminal of the lower switching element 323L, and the cathode of the snubber diode 323B is electrically connected to the drain terminal of the lower switching element 323L.

[0289] The W-phase inverter section 324 has an upper switching element 324U and a lower switching element 324L. The drain terminal of the upper switching element 324U is electrically connected to the positive power terminal EP. The source terminal of the upper switching element 324U and the drain terminal of the lower switching element 324L are electrically connected. The source terminal of the lower switching element 324L is connected to the negative power terminal EN. A snubber diode 324A is connected in anti-parallel to the upper switching element 324U, and a snubber diode 324B is connected in anti-parallel to the lower switching element 324L. More specifically, the anode of the snubber diode 324A is electrically connected to the source terminal of the upper switching element 324U, and the cathode of the snubber diode 324A is electrically connected to the drain terminal of the upper switching element 324U. The anode of the snubber diode 324B is electrically connected to the source terminal of the lower switching element 324L, and the cathode of the snubber diode 324B is electrically connected to the drain terminal of the lower switching element 324L.

[0290] The gate drive circuit 325 is electrically connected to the gate terminals of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L, respectively. The gate drive circuit 325 controls the on / off of each of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L.

[0291] The semiconductor device 1 can be applied to at least one of the switching elements 322U, 322L, 323U, 323L, 324U, and 324L. For example, when the semiconductor device 1 is applied to the lower switching element 322L of the U-phase inverter section 322, the lower switching element 322L among the U-phase inverter section 322 and the gate drive circuit that drives the lower switching element 322L among the gate drive circuits 325 are replaced with the semiconductor device 1.

[0292] [Supplementary Note] The technical idea that can be grasped from the above embodiment and the above modification example will be described below. (Supplementary Note 1-1) The active region has a substantially L shape formed by combining a small rectangular first region and a large rectangular second region, and the first wire as a connection member and the source pad are connected to each other at a position on the line segment connecting the center-of-gravity positions of the first region and the second region, a semiconductor device.

[0293] (Supplementary Note 1-2) The semiconductor element includes a transistor, and the semiconductor device includes a second lead frame for controlling the on / off of the transistor and a third lead frame connected to the first wire. The second lead frame is disposed on the first region side, and the third lead frame is disposed on the second region side, the semiconductor device according to Supplementary Note 1-1.

[0294] (Supplementary Note 1-3) The semiconductor element includes a gate pad connected to the second lead frame, and the gate pad is disposed in a rectangular region not occupied by the transistor among the regions surrounded by the extension line of the side (first side) of the first region RA1 and the extension line of the side (fourth side) of the second region. The semiconductor device according to Supplementary Note 1-2.

[0295] (Supplementary Note 1-4) The source pad is also substantially L-shaped, and the source pad is formed across the first region and the second region included in the active region. The source pad is configured such that the first side, which is the farthest from the second region in the source pad, coincides with the position where the gate pad is provided in the lateral direction. The semiconductor device according to Supplementary Note 1-3.

[0296] (Supplementary Note 1-5) The temperature sensor is disposed between the gate pad and the source pad. The semiconductor device according to Supplementary Note 1-3.

[0297] (Supplementary Note 1-6) The first wire and the source pad are connected to each other at two locations, namely, the centroid position of the first region and the centroid position of the second region. The semiconductor device according to Supplementary Note 1-1.

[0298] (Supplementary Note 2-1) A semiconductor device includes a substrate including a transistor formation region in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at one location. The transistor formation region is formed in a concave shape having one concave portion recessed at the center in the vertical direction or one concave portion recessed at the center in the horizontal direction of a rectangle in plan view. The electrode pad is provided so as to cover the centroid of the transistor formation region in the plan view. In the plan view, the connection region where the first connection member is connected to the electrode pad includes the centroid position of the transistor formation region.

[0299] (Supplementary Note 2-2) The semiconductor device according to Supplementary Note 2-1, wherein the center position of the connection region coincides with the centroid position of the transistor formation region.

[0300] (Supplementary Note 2-3) A semiconductor device including a substrate including a transistor formation region in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a first connection member connected to the electrode pad at a plurality of locations, wherein the transistor formation region is formed in a concave shape having one concave portion recessed at the center in the vertical direction or one concave portion recessed at the center in the horizontal direction of a rectangle in plan view, and is divided into a plurality of divided regions having equal areas according to the number of connection locations of the first connection member, the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in the plan view, and in the plan view, the connection region where the first connection member is connected to the electrode pad includes the centroid positions of each of the plurality of divided regions.

[0301] (Supplementary Note 2-4) A semiconductor device including a substrate including a transistor formation region in which a transistor is formed, a semiconductor element having an electrode pad on the transistor formation region, and a plurality of first connection members connected to the electrode pad, wherein the transistor formation region is formed in a concave shape having one concave portion recessed at the center in the vertical direction or one concave portion recessed at the center in the horizontal direction of a rectangle in plan view, and is divided into a plurality of divided regions having equal areas according to the number of the first connection members, the electrode pad is provided so as to cover the centroid of each of the plurality of divided regions in the plan view, and in the plan view, the connection regions where the plurality of first connection members are respectively connected to the electrode pad include the centroid positions of each of the plurality of divided regions.

[0302] (Supplementary Note 2-5) The number of the first connection members is two. When the recess is provided at the center in the longitudinal direction in the transistor formation region, the transistor formation region is divided into the two divided regions by a virtual line extending in the lateral direction at the center in the longitudinal direction. When the recess is provided at the center in the lateral direction, the transistor formation region is divided into the two divided regions by a virtual line extending in the longitudinal direction at the center in the lateral direction. The semiconductor device according to Supplementary Note 4.

[0303] (Supplementary Note 2-6) The semiconductor device according to any one of Supplementary Notes 2-1 to 2-5, further having a control circuit region formed in a region different from the transistor formation region among the semiconductor elements and controlling the current flowing through the semiconductor device.

[0304] (Supplementary Note 2-7) The semiconductor device according to Supplementary Note 2-6, wherein at least a part of the control circuit region is disposed in the recess of the transistor formation region.

[0305] (Supplementary Note 2-8) The semiconductor device according to Supplementary Note 2-6 or 2-7, wherein a temperature sensor is provided in the control circuit region.

[0306] (Supplementary Note 2-9) The semiconductor device according to Supplementary Note 2-8, wherein the temperature sensor is disposed in a portion of the control circuit region that does not overlap with the first connection member in the plan view.

[0307] (Supplementary Note 2-10) The semiconductor device according to Supplementary Note 2-8 or 2-9, wherein the temperature sensor is provided at a location adjacent to the bottom surface of the recess in the control circuit region disposed in the recess.

[0308] (Supplementary Note 2-11) The transistor formation region has a first recess and a second recess as the recesses, the second recess is recessed from the bottom surface of the first recess, at least a part of the control circuit region is located in the second recess, and the temperature sensor is provided at a location within the second recess of the control circuit region. The semiconductor device according to Supplementary Note 2-8 or 2-9.

[0309] (Supplementary Note 2-12) The semiconductor element has a power transistor and a control electrode pad connected to a control terminal of the power transistor, and the control electrode pad is disposed in a region notched at a location different from the recess in the transistor formation region. The semiconductor device according to any one of Supplementary Notes 2-1 to 2-11.

[0310] (Supplementary Note 3-1) A semiconductor element having a substrate including a transistor formation region having a shape other than a square in which a transistor is formed, and an electrode pad on the transistor formation region, A first connection member connected to the electrode pad at one location, and having The electrode pad is provided so as to cover the centroid of the transistor formation region in a plan view thereof, In the plan view, a connection region where the first connection member is connected to the electrode pad includes the centroid position of the transistor formation region Semiconductor device.

[0311] (Supplementary Note 3-2) The center position of the connection region coincides with the centroid position of the transistor formation region The semiconductor device according to Supplementary Note 3-1. (Supplementary Note 4-1) A semiconductor element having a substrate including a transistor formation region having a shape other than a square in which a transistor is formed and a control circuit region provided with a circuit for controlling the transistor, a temperature sensor provided in the control circuit region, and an electrode pad on the transistor formation region, A first connection member connected to the electrode pad, having, The transistor formation region, a first region, a second region having a larger area than the first region, having, The temperature sensor is disposed at a position adjacent to the transistor formation region, The electrode pad is provided so as to cover the respective centroids of the first region and the second region in a plan view thereof, In the plan view, a connection region where the first connection member is connected to the electrode pad includes the centroid position of the transistor formation region Semiconductor device. (Appendix 4-2) The temperature sensor is disposed at a location where heat is most concentrated among regions outside the electrode pad within the control circuit region when the semiconductor device is driven. The semiconductor device according to Appendix 4-1. (Appendix 4-3) The temperature sensor is provided so as to be adjacent to the connection region in the plan view. The semiconductor device according to Appendix 4-1 or 4-2. (Appendix 4-4) having a current sensor for detecting a current flowing through the transistor, The current sensor is disposed between the electrode pad and the control circuit region. The semiconductor device according to any one of Appendices 4-1 to 4-3. (Appendix 4-5) The current sensor is provided within the transistor formation region. The semiconductor device according to Appendix 4-4. (Appendix 4-6) The center position of the connection region coincides with the centroid position of the transistor formation region. The semiconductor device according to any one of Appendices 4-1 to 4-5. (Appendix 4-7) The semiconductor element has a power transistor and a control electrode pad connected to a control terminal of the power transistor. A first lead frame on which the semiconductor element is mounted; A second lead frame to which the other end of a second connection member having one end connected to the control electrode pad is connected; A third lead frame to which the other end of the first connection member having one end connected to the semiconductor element is connected; and has The semiconductor device according to any one of Appendices 4-1 to 4-6. (Appendix 4-8) The first lead frame and the third lead frame are configured to contain copper. The first connection member is configured to contain aluminum. At least one surface of the first lead frame and the third lead frame has a plating layer. The semiconductor device according to Appendix 4-7. (Appendix 4-9) The first lead frame has a first island portion on which the semiconductor element is mounted. A plating layer is provided on the surface of the first island portion on which the semiconductor element is mounted. The semiconductor device according to Appendix 4-8. (Appendix 4-10) The third lead frame has a third island portion to which the first connection member is connected. A plating layer is provided on the surface of the third island portion to which the first connection member is connected. The semiconductor device according to Appendix 4-8 or 4-9. (Appendix 4-11) The second lead frame configured to contain copper has a second island portion to which the second connection member is connected. The second connection member is configured to contain aluminum. A plating layer is provided on the surface of the second island portion to which the second connection member is connected. The semiconductor device according to any one of Appendices 4-7 to 4-10. (Appendix 4-12) The first connection member is connected to the electrode pad by wedge bonding, has a connection portion connected to the electrode pad, In a plan view, the connection portion extends from the semiconductor element toward the third island portion. The semiconductor device according to Supplementary Note 4-10. (Supplementary Note 4-13) A plurality of trenches and a plurality of functional element formation regions including channel formation regions that are arranged along the plurality of trenches and serve as current paths are formed in the substrate. The plurality of functional element formation regions include a first functional element formation region in which the area of the channel formation region per unit area is relatively small, and a second functional element formation region in which the area of the channel formation region per unit area is relatively large. The first functional element formation region is provided in a region where heat generation should be suppressed among the plurality of functional element formation regions. The semiconductor device according to any one of Supplementary Notes 4-1 to 4-12. (Supplementary Note 4-14) The first connection member is electrically connected to the plurality of functional element formation regions. The second functional element formation region is provided in a region where the first connection member is electrically connected among the plurality of functional element formation regions. The semiconductor device according to Supplementary Note 4-13. (Supplementary Note 4-15) The first connection member is connected to the electrode pad at a plurality of locations. The first functional element formation region is provided in a region between adjacent second functional element formation regions among the second functional element formation regions to which the first connection member is connected to the plurality of functional element formation regions. The semiconductor device according to Supplementary Note 4-14. (Supplementary Note 4-16) A metal layer for electrically connecting the functional element formation region and the electrode pad is formed between the functional element formation region and the electrode pad. In the metal layer, at least a portion facing the electrode pad is provided with one or more slits. The semiconductor device according to any one of Appendices 4-13 to 4-15. (Appendix 4-17) The metal layer has a first metal layer and a second metal layer provided so as to be laminated with the first metal layer through a contact electrically connected to the first metal layer. In the first metal layer and the second metal layer, at least a portion facing the electrode pad is respectively provided with one or more slits. The slit of the first metal layer and the slit of the second metal layer face each other in the lamination direction of the first metal layer and the second metal layer. The semiconductor device according to Appendix 4-16. (Appendix 4-18) It has an interlayer insulating film formed on the functional element formation region and covering the first metal layer and the second metal layer. The interlayer insulating film is embedded in the slit of the first metal layer and the slit of the second metal layer. The semiconductor device according to Appendix 4-17. (Appendix 4-19) The electrode pad is composed of copper. The semiconductor device according to any one of Appendices 4-1 to 4-18. (Appendix 4-20) On the surface of the electrode pad, a connection layer for connecting the first connection member is provided. The semiconductor device according to any one of Appendices 4-1 to 4-19. (Appendix 4-21) The thickness of the electrode pad is 16000 Å or more. The semiconductor device according to any one of Appendices 4-1 to 4-20. (Appendix 4-22) The thickness of the electrode pad is 20000 Å or more. The semiconductor device according to Appendix 4-21. (Appendix 4-23) The first connection member is aluminum. having a sealing resin that seals at least the semiconductor element and the first connection member, the linear expansion coefficient of the sealing resin being greater than 10 ppm / K and less than 15 ppm / K The semiconductor device according to any one of Appendices 4-1 to 4-22. (Appendix 4-24) the linear expansion coefficient of the sealing resin being 12 ppm / K The semiconductor device according to Appendix 4-23. (Appendix 4-25) the sealing resin being added with an ion trap material containing aluminum and magnesium The semiconductor device according to Appendix 4-23 or 4-24. (Appendix 4-26) the electrode pad having a first protective layer covering the interlayer insulating film, a first electrode layer covering the first protective layer, a second protective layer covering the first electrode layer, a second electrode layer covering the second protective layer, and the Vickers hardness of each of the first protective layer and the second protective layer being greater than the Vickers hardness of each of the first electrode layer and the second electrode layer The semiconductor device according to any one of Appendices 4-1 to 4-25. (Appendix 4-27) the first electrode layer and the second electrode layer being made of aluminum or an aluminum alloy, the first protective layer and the second protective layer being made of titanium nitride The semiconductor device according to Appendix 4-26. (Appendix 4-28) the first connection member being an aluminum wire wedge-bonded to the electrode pad The semiconductor device according to any one of Appendices 4-1 to 4-27. (Appendix 4-29) the wire diameter of the aluminum wire being 300 μm or more and 400 μm or less The semiconductor device according to Appendix 4-28. (Appendix 4-30) The first connection member is a copper wire wedge-bonded to the electrode pad. The semiconductor device according to any one of Appendices 4-1 to 4-29. (Appendix 4-31) The on-resistance of the semiconductor device is 30 mΩ or less. The semiconductor device according to any one of Appendices 4-1 to 4-30.

Explanation of Signs

[0312] 1... Semiconductor device 11... First lead frame 11a... First island part 12... Second lead frame 12a... Second island part 13... Third lead frame 13a... Third island part 14... Plating layer 20... Semiconductor element 21... Source pad (electrode pad) 21a... Connection layer 22... Gate pad (control electrode pad) 23a... MISFET (power transistor) 27... Temperature sensor 29... Active region (transistor formation region) 30... Encapsulating resin 41... First wire (first connection member) 41a... Connection part 41b... First connection part 41c... Second connection part 42... Second wire (second connection member) 50... Substrate 66... Trench 72... Channel formation region 74... Interlayer insulating film 80... First source electrode (first metal layer, metal layer) 81... Contact 82... Second source electrode (second metal layer, metal layer) 83... Contact 220…First slit 221…Second slit 231…Functional element formation region 232…First functional element formation region 233…Second functional element formation region 270…Source pad (electrode pad) 271…First protective layer 272…First electrode layer 273…Second protective layer 274…Second electrode layer 275…Connection layer GC, GD, GF, GH…Center of gravity position GB1, GE1, GG1, GJ1…Center of gravity position of regions obtained by dividing the transistor formation region into regions of equal area GB2, GE2, GG2, GJ2…Center of gravity position of regions obtained by dividing the transistor formation region into regions of equal area RX, RY…Wedge (connection region)

Claims

1. A semiconductor device having a substrate including a transistor formation region having a shape other than a quadrilateral in which a transistor is formed, and an electrode pad on the transistor formation region, a first bonding wire connected to the electrode pad, and having, wherein the electrode pad is provided so as to cover the center of gravity of the transistor formation region in a plan view thereof, in the plan view, the first bonding wire overlaps the center of gravity of the transistor formation region at a connection point with the electrode pad, a semiconductor device.

2. The semiconductor element includes a DTI structure that partitions the transistor formation region, the transistor is surrounded by the DTI structure in the plan view, The semiconductor device according to claim 1.

3. The DTI structure includes a portion overlapping the electrode pad in the plan view, The semiconductor device according to claim 2.

4. The DTI structure includes an insulator provided inside the DTI structure, a wiring layer connecting the insulator and the electrode pad is disposed in the transistor formation region, The semiconductor device according to claim 3.

5. The wiring layer includes a portion disposed closer to the electrode pad in the transistor formation region, The semiconductor device according to claim 4.

6. The semiconductor device includes a first lead frame on which the semiconductor element is mounted, and a third lead frame to which the first bonding wire is connected, a first terminal portion of the first lead frame constituting an output terminal and a third terminal portion of the third lead frame constituting a ground terminal are disposed on the same side of the semiconductor device in the plan view, The semiconductor device according to claim 1.

7. The semiconductor element includes a gate pad to which a signal for controlling the transistor is input, the gate pad is disposed near a corner of the semiconductor element in the plan view, The semiconductor device according to claim 1.

8. The substrate includes a plurality of side surfaces facing a direction orthogonal to the thickness direction of the semiconductor element and a control circuit region provided with a circuit for controlling the transistor, the plurality of side surfaces include a first side surface disposed closer to the control circuit region and a second side surface disposed on the opposite side of the first side surface in the plan view, the semiconductor element includes a temperature sensor disposed in the control circuit region, In the plan view, the temperature sensor is disposed closer to the first side surface of the substrate. The semiconductor device according to claim 1.

9. The temperature sensor is disposed at a distance from the electrode pad. The semiconductor device according to claim 8.

10. The semiconductor element includes a surface protection film on the surface of the electrode pad. At least a part of the electrode pad is covered by the surface protection film. The semiconductor device according to claim 1.

11. The surface protection film has an opening in the electrode pad. The semiconductor device according to claim 10.

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