Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the formation of voids between a passivation layer and a plating layer.SOLUTION: A semiconductor device has a substrate having a first main surface, an electrode provided on the first main surface, a passivation layer covering the electrode, the passivation layer has openings that expose the first region of the electrode, and the electrode has a sloping surface on the periphery of the first region that slopes in a direction closer to the first main surface as it moves toward the passivation layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

Background Art

[0002] In a semiconductor device, a technique is known in which an opening for exposing an electrode pad is formed in a passivation layer, and a plating layer is formed on the exposed electrode pad (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, voids may occur between a passivation layer and a plating layer.

[0005] An object of the present disclosure is to provide a semiconductor device capable of suppressing the occurrence of voids between a passivation layer and a plating layer.

Means for Solving the Problems

[0006] The semiconductor device of the present disclosure includes a substrate having a first main surface, an electrode provided on the first main surface, and a passivation layer covering the electrode. An opening for exposing a first region of the electrode is formed in the passivation layer, and the electrode has an inclined surface that inclines in a direction approaching the first main surface as it approaches the passivation layer on the outer peripheral portion of the first region.

Effects of the Invention

[0007] According to the present disclosure, the occurrence of voids between a passivation layer and a plating layer can be suppressed.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 10

Embodiments for Carrying Out the Invention

[0009] Embodiments for carrying out the invention will be described below.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. In the following description, the same or corresponding elements are denoted by the same reference numerals, and the same description thereof will not be repeated.

[0011] [1] A semiconductor device according to an aspect of the present disclosure includes a substrate having a first main surface, an electrode provided on the first main surface, and a passivation layer covering the electrode. An opening is formed in the passivation layer to expose a first region of the electrode. The electrode has an inclined surface that inclines in a direction approaching the first main surface as it approaches the passivation layer on an outer peripheral portion of the first region.

[0012] In this case, since the growth direction of the plating layer when growing the plating layer on the electrode includes a direction along the side wall surface of the opening formed in the passivation layer, it is possible to suppress the generation of voids between the passivation layer and the plating layer.

[0013] [2] In [1], the sum of the angle formed by the side wall surface of the opening and the first main surface and the angle formed by the inclined surface and the first main surface may be 70° or more and 110° or less. In this case, the plating layer is likely to grow in a direction along the side wall surface.

[0014] [3] In [1] or [2], the electrode may have a concave portion including the inclined surface. Since the concave portion can be formed by etching the electrode, it is easy to form an inclined surface at a desired position.

[0015] [4] In [3], having a plating layer provided on the electrode, the opening width of the concave portion at the position farthest from the first main surface may be 0.1 times or more and 0.5 times or less the thickness of the plating layer. In this case, the plating layer is likely to grow in a direction along the side wall surface.

[0016] [5] In [3] or [4], having a plating layer provided on the electrode, the depth of the concave portion may be 0.05 times or more and 0.5 times or less the thickness of the plating layer. In this case, while ensuring the sheet resistance of the electrode, it is easy to grow the plating layer in a direction along the side wall surface.

[0017] In [6], [1] or [2], it has a plurality of interlayer insulating films provided on the substrate, the electrode has a convex portion including the inclined surface, and when viewed in plan from a direction perpendicular to the first main surface, the convex portion may be formed at a position covering the interlayer insulating film. The convex portion can be formed by forming the electrode so as to follow the convex shape of the interlayer insulating film. Therefore, etching of the electrode for forming the inclined surface becomes unnecessary.

[0018] 〔7〕 In [6], the angle formed by the straight line connecting the first boundary between the electrode and the passivation layer and the first position of the inclined surface separated from the first boundary by 5 μm in a direction parallel to the first main surface and the first main surface may be 0° or more and 10° or less. In this case, the plating layer is likely to grow in the direction along the side wall surface.

[0019] 〔8〕 In [6] or [7], when viewed in plan from a direction perpendicular to the first main surface, the opening may have a rectangular shape, and the inclined surface may be provided at positions facing two opposite sides of the opening. In this case, it is possible to suppress the generation of voids between the passivation layer and the plating layer at two opposite sides of the opening.

[0020] 〔9〕 In [1] to [8], the substrate may be a silicon carbide substrate. In this case, it is easy to obtain excellent withstand voltage.

[0021] [Details of Embodiments of the Present Disclosure] Hereinafter, embodiments of the present disclosure will be described in detail, but the present disclosure is not limited thereto.

[0022] (First Embodiment) First, the semiconductor device 100 according to the first embodiment will be described. FIG. 1 is a cross-sectional view showing the semiconductor device 100 according to the first embodiment.

[0023] As shown in FIG. 1, the semiconductor device 100 according to the first embodiment mainly includes a silicon carbide substrate 10, a gate insulating film 21, a gate electrode 22, an interlayer insulating film 23, a source electrode 30, a drain electrode 40, a passivation layer 50, and a plating layer 60.

[0024] The silicon carbide substrate 10 is an example of a substrate. When the silicon carbide substrate 10 is used, it is easy to obtain excellent breakdown voltage. The silicon carbide substrate 10 includes a silicon carbide single crystal substrate 11 and a silicon carbide epitaxial layer 12 on the silicon carbide single crystal substrate 11. The silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. The silicon carbide epitaxial layer 12 constitutes the first main surface 1, and the silicon carbide single crystal substrate 11 constitutes the second main surface 2. The silicon carbide single crystal substrate 11 and the silicon carbide epitaxial layer 12 are composed of, for example, polytype 4H hexagonal silicon carbide. The silicon carbide single crystal substrate 11 contains, for example, an n-type impurity such as nitrogen (N) and has an n-type conductivity type. A field effect transistor is formed on the silicon carbide substrate 10 as an example of a semiconductor element.

[0025] The silicon carbide epitaxial layer 12 mainly has a drift region 13, a body region 14, a source region 15, and a contact region 16.

[0026] The drift region 13 contains, for example, an n-type impurity such as nitrogen or phosphorus (P) and has an n-type conductivity type.

[0027] The body region 14 is provided on the drift region 13. The body region 14 contains, for example, a p-type impurity such as aluminum (Al) and has a p-type conductivity type.

[0028] The source region 15 is provided on the body region 14. The source region 15 contains, for example, an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity type. The source region 15 is separated from the drift region 13 by the body region 14. The source region 15 constitutes the first main surface 1.

[0029] The contact region 16 contains p-type impurities such as aluminum and has a p-type conductivity type. The contact region 16 penetrates the source region 15 and contacts the body region 14. The contact region 16 constitutes the first main surface 1.

[0030] On the first main surface 1, a gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided. The side surface 3 penetrates the source region 15 and the body region 14 and reaches the drift region 13. The side surface 3 may be, for example, a surface inclined from the second main surface 2 or a surface perpendicular to the second main surface 2. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is in the drift region 13. The bottom surface 4 is, for example, a plane parallel to the second main surface 2. The gate trench 5 extends, for example, in a first direction parallel to the first main surface 1, and a plurality of gate trenches 5 are arranged in a second direction.

[0031] The gate insulating film 21 is, for example, an oxide film. The gate insulating film 21 is composed of a material containing, for example, silicon dioxide. The gate insulating film 21 contacts the side surface 3 and the bottom surface 4. The gate insulating film 21 contacts the drift region 13 at the bottom surface 4. The gate insulating film 21 contacts each of the source region 15, the body region 14, and the drift region 13 at the side surface 3. The gate insulating film 21 may contact the source region 15 on the first main surface 1.

[0032] The gate electrode 22 is provided on the gate insulating film 21. The gate electrode 22 is composed of, for example, polysilicon containing a conductive impurity. The gate electrode 22 is provided inside the gate trench 5. A part of the gate electrode 22 may be provided on the first main surface 1.

[0033] The interlayer insulating film 23 covers the gate electrode 22. The interlayer insulating film 23 contacts the gate electrode 22 and the gate insulating film 21. The interlayer insulating film 23 is, for example, an oxide film. The interlayer insulating film 23 is composed of a material containing, for example, silicon dioxide. The interlayer insulating film 23 electrically insulates the gate electrode 22 and the source electrode 30 from each other. A part of the interlayer insulating film 23 may be provided inside the gate trench 5.

[0034] Contact holes 24 are formed in the interlayer insulating film 23 and the gate insulating film 21. The contact holes 24 are provided at regular intervals in the second direction. The contact holes 24 are provided such that the gate trench 5 is positioned between adjacent contact holes 24 in the second direction. The contact holes 24 extend along the first direction. Through the contact holes 24, the source region 15 and the contact region 16 are exposed from the interlayer insulating film 23 and the gate insulating film 21. The contact region 16 does not need to be provided over the entire length in the first direction and may be provided periodically. A barrier metal film may be formed to cover the upper surface and the side surface of the interlayer insulating film 23 and the side surface of the gate insulating film 21.

[0035] The source electrode 30 is in contact with the first main surface 1. The source electrode 30 has a contact electrode 31 and a source wiring 32.

[0036] The contact electrode 31 is provided in the contact hole 24. The contact electrode 31 is in contact with the source region 15 and the contact region 16 on the first main surface 1. The contact electrode 31 is made of a material containing, for example, nickel silicide (NiSi). The contact electrode 31 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 31 makes an ohmic contact with the source region 15 and the contact region 16.

[0037] The source wiring 32 is provided on the interlayer insulating film 23 and the contact electrode 31. The source wiring 32 covers the interlayer insulating film 23 and the contact electrode 31. The source wiring 32 has a recess 32A at the outer peripheral portion of the region exposed through the opening 51 described later. The recess 32A has an inclined surface 32S that inclines in a direction approaching the first main surface 1 as it goes toward the passivation layer 50 described later. The inclined surface 32S is located at the outer peripheral portion of the source wiring 32 exposed through the opening 51. The source wiring 32 is made of a material containing, for example, aluminum or copper (Cu). The source wiring 32 may be made of a material containing aluminum and copper. The source wiring 32 is an example of an electrode.

[0038] The drain electrode 40 is in contact with the second main surface 2. The drain electrode 40 is in contact with the silicon carbide single crystal substrate 11 on the second main surface 2. The drain electrode 40 is electrically connected to the drift region 13. The drain electrode 40 is made of a material containing, for example, nickel silicide. The drain electrode 40 may be made of a material containing titanium, aluminum, and silicon. The drain electrode 40 makes an ohmic contact with the silicon carbide single crystal substrate 11.

[0039] The passivation layer 50 contains an organic material. The passivation layer 50 is provided on the source wiring 32. The passivation layer 50 covers the source wiring 32. An opening 51 is formed in the passivation layer 50. When viewed in plan from a direction perpendicular to the first main surface 1, the opening 51 has a rectangular shape. The opening 51 is formed on the source wiring 32. A part of the source wiring 32 is exposed through the opening 51.

[0040] The opening 51 has a side wall surface 51S. The side wall surface 51S may be perpendicular to the first main surface 1 or may be inclined from a plane perpendicular to the first main surface 1. The sum of the angle θ1 formed between the side wall surface 51S and the first main surface 1 and the angle θ2 formed between the inclined surface 32S and the first main surface 1 may be, for example, 70° or more and 110° or less, or may be 85° or more and 95° or less. The closer the sum of the angle θ1 and the angle θ2 is to 90°, the easier it is for the plating layer 60 to grow in the direction along the inclined surface 32S, and the generation of voids between the passivation layer 50 and the plating layer 60 can be suppressed.

[0041] The angle θ1 is the angle formed between the first straight line L1 connecting the first point P1 and the second point P2 and the first main surface 1. The first point P1 is a point where the boundary between the source wiring 32 and the passivation layer 50 is located in a cross section perpendicular to the first direction. The second point P2 is a point that is t1 / 2 away from the interface between the source wiring 32 and the passivation layer 50 of the passivation layer 50 in the direction perpendicular to the first main surface 1 in a cross section perpendicular to the first direction, where t1 is the thickness of the portion of the passivation layer 50 located on the source wiring 32.

[0042] The angle θ2 is the angle formed by the second straight line L2 connecting the third point P3 and the fourth point P4 and the first main surface 1. The third point P3 is the point among the deepest points of the recess 32A that is farthest from the side wall surface 51S in a cross section orthogonal to the first direction. The fourth point P4 is a point that is separated by t2 / 2 in a direction perpendicular to the first main surface 1 from the deepest position of the recess 32A on the inclined surface 32S when the depth of the recess 32A is t2 in a cross section orthogonal to the first direction. The passivation layer 50 includes, for example, a polyimide layer. The passivation layer 50 may be a polyimide layer.

[0043] The plating layer 60 has a nickel (Ni) plating layer 61, a palladium (Pd) plating layer 62, and a gold (Au) plating layer 63. The Ni plating layer 61 is provided on the source wiring 32 so as to fill the recess 32A inside the opening 51. The Ni plating layer 61 is in contact with the upper surface of the source wiring 32, the inner surface of the recess 32A, and a part of the side wall surface 51S. The Pd plating layer 62 is provided on the Ni plating layer 61 inside the opening 51. The Au plating layer 63 is provided on the Pd plating layer 62 inside the opening 51.

[0044] The opening width W1 of the recess 32A at the position farthest from the first main surface 1 may be, for example, 0.1 times or more and 0.5 times or less the thickness D1 of the Ni plating layer 61. In this case, the Ni plating layer 61 easily grows in the direction along the side wall surface 51S. On the other hand, when the opening width W1 becomes smaller than 0.1 times the thickness D1, the inclined surface 32S approaches the side wall surface 51S too much, so that it is difficult for the Ni plating layer 61 to grow from the inclined surface 32S. When the opening width W1 becomes larger than 0.5 times the thickness D1, the growth direction of the Ni plating layer 61 from the inclined surface 32S approaches the growth direction of the Ni plating layer 61 from the upper surface of the source wiring 32, so that it is difficult for the Ni plating layer 61 to grow in the direction along the side wall surface 51S.

[0045] The depth t2 of the recess 32A may be, for example, not less than 0.05 times and not more than 0.5 times the thickness D1 of the Ni plating layer 61. In this case, while ensuring the sheet resistance of the source wiring 32, it is easy to grow the Ni plating layer 61 in the direction along the side wall surface 51S. On the other hand, when the depth t2 becomes less than 0.05 times the thickness D1, it is difficult for the Ni plating layer 61 to grow from the inclined surface 32S. When the depth t2 becomes greater than 0.5 times the thickness D1, the source wiring 32 at the position where the recess 32A is formed becomes thin. For this reason, the sheet resistance of the source wiring 32 may increase, voids may occur in the Ni plating layer 61 when forming the Ni plating layer 61, and ionic impurities derived from the plating solution staying in the voids may invade the source wiring 32, resulting in a decrease in reliability.

[0046] According to the semiconductor device 100 according to the first embodiment, the recess 32A is provided in the outer peripheral portion of the region where the source wiring 32 is exposed through the opening 51, and the recess 32A has an inclined surface 32S that inclines in a direction approaching the first main surface 1 as it goes toward the passivation layer 50. Thereby, since the growth direction of the Ni plating layer 61 when growing the Ni plating layer 61 on the source wiring 32 includes the direction along the side wall surface 51S of the opening 51, it is possible to suppress the generation of voids between the passivation layer 50 and the Ni plating layer 61.

[0047] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. FIGS. 2 to 5 are cross-sectional views showing the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0048] First, as shown in FIG. 2, a silicon carbide substrate 10 is prepared. In preparing the silicon carbide substrate 10, a silicon carbide epitaxial layer 12 is formed on a silicon carbide single crystal substrate 11. Next, a drift region 13, a body region 14, a source region 15, and a contact region 16 are formed in the silicon carbide epitaxial layer 12 by ion implantation or the like. Next, a plurality of gate trenches 5 are formed in the source region 15, the body region 14, and the drift region 13. Next, a gate insulating film 21 is formed in contact with the source region 15, the body region 14, the drift region 13, and the contact region 16. Next, a gate electrode 22 is formed on the gate insulating film 21. Next, an interlayer insulating film 23 is formed so as to cover the gate electrode 22 and be in contact with the gate insulating film 21. Next, a contact hole 24 is formed in the interlayer insulating film 23 and the gate insulating film 21. Next, a contact electrode 31 is formed on the source region 15 and the contact region 16.

[0049] Next, as shown in FIG. 3, a source wiring 32 having a recess 32A is formed. Specifically, a source wiring 32 covering the contact electrode 31 and the interlayer insulating film 23 is formed by a sputtering method or the like. Next, a mask (not shown) having an opening is formed on the region where the recess 32A is to be formed. Next, using the mask, a part of the source wiring 32 is removed by etching. The etching is, for example, wet etching using a mixed chemical solution of phosphoric acid and nitric acid. By the etching, a recess 32A having an inclined surface 32S is formed.

[0050] Next, as shown in FIG. 4, a passivation layer 50 having an opening 51 is formed. Specifically, a passivation layer 50 is formed on the source wiring 32. Next, a mask (not shown) having an opening is formed on the region where the opening 51 is to be formed. Next, using the mask, a part of the passivation layer 50 is removed by etching. The etching is, for example, wet etching using a developer or the like. By the etching, an opening 51 having a side wall surface 51S is formed. The opening 51 is formed such that the side wall surface 51S is located outside the inclined surface 32S.

[0051] Next, as shown in FIG. 5, a plating layer 60 is formed. In forming the plating layer 60, a Ni plating layer 61, a Pd plating layer 62, and an Au plating layer 63 are formed in this order using a plating solution. The Ni plating layer 61 grows along a direction perpendicular to the upper surface of the source wiring 32 as indicated by arrow A1 and also grows along a direction perpendicular to the inclined surface 32S as indicated by arrow A2. In this case, since the growth direction of the Ni plating layer 61 includes a direction along the side wall surface 51S, it is possible to suppress the generation of voids between the passivation layer 50 and the Ni plating layer 61. If voids are generated between the passivation layer 50 and the Ni plating layer 61, the plating solution may accumulate in the voids when forming the Pd plating layer 62 and the Au plating layer 63, resulting in a decrease in reliability. Also, a drain electrode 40 in contact with the silicon carbide single crystal substrate 11 is formed on the second main surface 2.

[0052] In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

[0053] (Second Embodiment) Next, the semiconductor device 200 according to the second embodiment will be described. FIG. 6 is a cross-sectional view showing the semiconductor device 200 according to the second embodiment.

[0054] As shown in FIG. 6, the semiconductor device 200 according to the second embodiment is different from the semiconductor device 100 in that the source wiring 32 has a convex portion 32B. Hereinafter, the description will focus on the differences from the semiconductor device 100.

[0055] The source wiring 32 is provided on the interlayer insulating film 23 and the contact electrode 31. The source wiring 32 covers the interlayer insulating film 23 and the contact electrode 31. The source wiring 32 has a convex portion 32B in a region exposed through the opening 51. When viewed in plan from a direction perpendicular to the first main surface 1, the convex portion 32B is formed at a position covering the interlayer insulating film 23. The convex portion 32B has an inclined surface 32S that slopes in a direction approaching the first main surface 1 as it goes toward the passivation layer 50. The inclined surface 32S is located at the outer peripheral portion of the source wiring 32 exposed through the opening 51. The inclined surface 32S is provided at positions facing two opposite sides of the opening 51. In this case, it is possible to suppress the occurrence of voids between the passivation layer 50 and the plating layer 60 at two opposite sides of the opening 51. The source wiring 32 is made of a material containing, for example, aluminum or copper (Cu). The source wiring 32 may be made of a material containing aluminum and copper. The source wiring 32 is an example of an electrode.

[0056] The sum of the angle θ1 formed between the side wall surface 51S and the first main surface 1 and the angle θ2 formed between the inclined surface 32S and the first main surface 1 may be, for example, 70° or more and 110° or less, or may be 85° or more and 95° or less. The closer the sum of the angle θ1 and the angle θ2 is to 90°, the easier it is for the plating layer 60 to grow in the direction along the inclined surface 32S, and it is possible to suppress the occurrence of voids between the passivation layer 50 and the plating layer 60.

[0057] The angle θ3 formed between the straight line L3 connecting the first point P1 where the boundary between the source wiring 32 and the passivation layer 50 is located and the position P5 of the inclined surface 32S that is 5 μm away from the first point P1 in a direction parallel to the first main surface 1 and the first main surface 1 may be, for example, 0° or more and 10° or less. In this case, the Ni plating layer 61 easily grows in the direction along the side wall surface 51S. On the other hand, when the angle θ3 is greater than 10°, the inclined surface 32S gets too close to the side wall surface 51S, so it is difficult for the Ni plating layer 61 to grow from the inclined surface 32S.

[0058] The height t3 of the convex portion 32B may be, for example, not less than 0.05 times and not more than 0.5 times the thickness D1 of the Ni plating layer 61. In this case, the Ni plating layer 61 can be easily grown in the direction along the side wall surface 51S without causing bonding defects during mounting. On the other hand, when the height t3 is less than 0.05 times the thickness D1, it is difficult for the Ni plating layer 61 to grow from the inclined surface 32S. When the height t3 is greater than 0.5 times the thickness D1, the unevenness of the finished surface after forming the plating layer 60 becomes large, and bonding defects may occur during mounting.

[0059] According to the semiconductor device 200 according to the second embodiment, the convex portion 32B is provided in the region where the source wiring 32 is exposed through the opening 51, and the convex portion 32B has an inclined surface 32S that inclines in a direction approaching the first main surface 1 as it goes toward the passivation layer 50. Thereby, since the growth direction of the Ni plating layer 61 when growing the Ni plating layer 61 on the source wiring 32 includes the direction along the side wall surface 51S of the opening 51, it is possible to suppress the occurrence of voids between the passivation layer 50 and the Ni plating layer 61.

[0060] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. FIGS. 7 to 10 are cross-sectional views showing the method for manufacturing the semiconductor device 200 according to the second embodiment.

[0061] First, as shown in FIG. 7, up to the formation of the contact electrode 31 is performed in the same manner as the method for manufacturing the semiconductor device 100 according to the first embodiment.

[0062] Next, as shown in FIG. 8, a source wiring 32 having a convex portion 32B is formed. Specifically, a source wiring 32 covering the contact electrode 31 and the interlayer insulating film 23 is formed by a sputtering method or the like. At this time, by forming the source wiring 32 so as to follow the convex shape of the interlayer insulating film 23, the convex portion 32B is formed on the upper surface of the source wiring 32. Thereby, the convex portion 32B having the inclined surface 32S is formed. When viewed in plan from a direction perpendicular to the first main surface 1, the convex portion 32B is formed at a position covering the interlayer insulating film 23.

[0063] Next, as shown in FIG. 9, a passivation layer 50 having an opening 51 is formed. Specifically, the passivation layer 50 is formed over the source wiring 32. Next, a mask (not shown) having an opening is formed over the region where the opening 51 is to be formed. Next, using the mask, a portion of the passivation layer 50 is removed by etching. The etching is, for example, wet etching using a developer or the like. By the etching, an opening 51 having sidewall surfaces 51S is formed. The opening 51 is formed such that the sidewall surfaces 51S are positioned outside the inclined surfaces 32S.

[0064] Next, as shown in FIG. 10, a plating layer 60 is formed. In forming the plating layer 60, a Ni plating layer 61, a Pd plating layer 62, and an Au plating layer 63 are formed in this order using a plating solution. The Ni plating layer 61 grows along a direction perpendicular to the upper surface of the source wiring 32 as indicated by arrow A1 and also grows along a direction perpendicular to the inclined surface 32S as indicated by arrow A2. In this case, since the growth direction of the Ni plating layer 61 includes a direction along the sidewall surfaces 51S, it is possible to suppress the generation of voids between the passivation layer 50 and the Ni plating layer 61. If voids are generated between the passivation layer 50 and the Ni plating layer 61, the plating solution may accumulate in the voids when the Pd plating layer 62 and the Au plating layer 63 are formed, resulting in a decrease in reliability. Also, a drain electrode 40 that contacts the silicon carbide single crystal substrate 11 is formed on the second main surface 2.

[0065] In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

[0066] Although the embodiments have been described in detail above, the present invention is not limited to the specific embodiments, and various modifications and changes are possible within the scope described in the claims.

Description of Reference Numerals

[0067] 1 First main surface 2 Second main surface 3 Side surface 4 Bottom surface 5 gate trenches 10 silicon carbide substrate 11 silicon carbide single crystal substrate 12 silicon carbide epitaxial layer 13 drift region 14 body region 15 source region 16 contact region 21 gate insulating film 22 gate electrode 23 interlayer insulating film 24 contact hole 30 source electrode 31 contact electrode 32 source wiring 32A recess 32B protrusion 32S inclined surface 40 drain electrode 50 passivation layer 51 opening 51S side wall surface 60 plating layer 61 Ni plating layer 62 Pd plating layer 63 Au plating layer 100 semiconductor device 200 semiconductor device

Claims

1. A substrate having a first main surface, an electrode provided on the first main surface, a passivation layer covering the electrode, characterized by comprising: an opening exposing a first region of the electrode is formed in the passivation layer, the electrode has an inclined surface that inclines in a direction approaching the first main surface as it approaches the passivation layer at an outer peripheral portion of the first region, a semiconductor device.

2. The sum of the angle formed by the side wall surface of the opening and the first main surface and the angle formed by the inclined surface and the first main surface is 70° or more and 110° or less, The semiconductor device according to claim 1.

3. The electrode has a recess including the inclined surface, The semiconductor device according to claim 1.

4. having a plating layer provided on the electrode, the opening width of the recess at the position farthest from the first main surface is 0.1 times or more and 0.5 times or less the thickness of the plating layer, The semiconductor device according to claim 3.

5. having a plating layer provided on the electrode, the depth of the recess is 0.05 times or more and 0.5 times or less the thickness of the plating layer, The semiconductor device according to claim 3.

6. having a plurality of interlayer insulating films provided on the substrate, the electrode has a convex portion including the inclined surface, when viewed in plan from a direction perpendicular to the first main surface, the convex portion is formed at a position covering the interlayer insulating film, The semiconductor device according to claim 1.

7. The angle formed by a straight line connecting a first boundary between the electrode and the passivation layer and a first position of the inclined surface that is 5 μm away from the first boundary in a direction parallel to the first main surface and the first main surface is 0° or more and 10° or less, The semiconductor device according to claim 6.

8. when viewed in plan from a direction perpendicular to the first main surface, the opening has a rectangular shape, the inclined surface is provided at positions facing two opposing sides of the opening, The semiconductor device according to claim 6.

9. The substrate is a silicon carbide substrate, The semiconductor device according to any one of claims 1 to 8.

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