Nitride semiconductor light-emitting element

Abstract

To provide a nitride semiconductor light-emitting element capable of improving an optical output.SOLUTION: This nitride semiconductor light-emitting element comprises: a substrate 2 including a c surface in which a growth surface 21 has an off-angle θ; an AlN buffer layer 3 made of AlN and formed on the growth surface 21; an n-type semiconductor layer 4 formed on the AlN buffer layer 3; an active layer formed on the n-type semiconductor layer 4 to emit ultraviolet light; and a p-type semiconductor layer formed on the active layer. An upper surface 31 of the AlN buffer layer 3 has a step / terrace structure including a plurality of terraces T2 and a plurality of steps S2 for connecting the terraces T2. An average value of heights H among the steps S2 is 7.1 nm or lower. An average value of widths among the terraces T2 is 350 nm or lower.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a nitride semiconductor light-emitting device.

Background Art

[0002] Patent Document 1 discloses an ultraviolet light-emitting device including a substrate, an underlying layer formed on the substrate, a first cladding layer formed on the underlying layer, a light-emitting layer that emits ultraviolet light formed on the first cladding layer, and a second cladding layer formed on the light-emitting layer. In the ultraviolet light-emitting device described in Patent Document 1, the step height at the interface between the underlying layer and the first cladding layer is set to be 10 nm or more and 60 nm or less.

Prior Art Document

Patent Document

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the ultraviolet light-emitting device described in Patent Document 1, the light output for an example where the step height is relatively small has not been studied.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a nitride semiconductor light-emitting device capable of improving the light output.

Means for Solving the Problems

[0006] To achieve the above object, the present invention provides a nitride semiconductor light-emitting device including a substrate having a growth surface composed of a c-plane with an off-angle, an AlN buffer layer made of AlN formed on the growth surface, an n-type semiconductor layer formed on the AlN buffer layer, an active layer that emits ultraviolet light formed on the n-type semiconductor layer, and a p-type semiconductor layer formed on the active layer. The upper surface of the AlN buffer layer has a step-terrace structure having a plurality of terraces and a plurality of steps connecting the terraces. The average value of the heights of the plurality of steps is 7.1 nm or less, and the average value of the widths of the plurality of terraces is 350 nm or less.

Effects of the Invention

[0007] According to the present invention, it is possible to provide a nitride semiconductor light-emitting device capable of improving the light output.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 5

Figure 6

Modes for Carrying Out the Invention

[0009] [Embodiment] An embodiment of the present invention will be described with reference to FIGS. 1 and 2. Note that the embodiments described below are presented as preferred specific examples for implementing the present invention, and although there are parts that specifically exemplify various technically preferable technical matters, the technical scope of the present invention is not limited to this specific aspect.

[0010] (Nitride semiconductor light-emitting element 1) FIG. 1 is a schematic diagram schematically showing the configuration of the nitride semiconductor light-emitting element 1. In FIG. 1, the dimensional ratio in the stacking direction of each semiconductor layer of the nitride semiconductor light-emitting element 1 (hereinafter, also simply referred to as "light-emitting element 1") does not necessarily match the actual one. Hereinafter, the stacking direction of each semiconductor layer of the light-emitting element 1 (that is, the direction orthogonal to the bottom surface of the substrate 2) is referred to as the vertical direction. Also, on one side in the vertical direction, the side on which each semiconductor layer is grown on the substrate 2 (for example, the upper side in FIG. 1) is defined as the upper side, and the opposite side (for example, the lower side in FIG. 1) is defined as the lower side. Note that the expressions "upper" and "lower" are for convenience and do not limit the posture of the light-emitting element 1 with respect to the vertical direction, for example, when the light-emitting element 1 is in use.

[0011] The light-emitting element 1 constitutes, for example, a light-emitting diode (LED: Light Emitting Diode) or a semiconductor laser (LD: Laser Diode). In this embodiment, the light-emitting element 1 constitutes a light-emitting diode that emits light having a wavelength in the ultraviolet region. In particular, the light-emitting element 1 of this embodiment emits ultraviolet light having a central wavelength of 240 nm or more and 365 nm or less. The light-emitting element 1 can be used, for example, in fields such as sterilization (such as air purification, water purification, etc.), medical treatment (such as phototherapy, measurement / analysis, etc.), and UV curing.

[0012] The light-emitting element 1 sequentially includes an AlN buffer layer 3, an n-type semiconductor layer 4, a composition gradient layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8 on the substrate 2. The light-emitting element 1 also includes an n-side electrode 11 provided on the n-type semiconductor layer 4 and a p-side electrode 12 provided on the p-type semiconductor layer 8.

[0013] As a semiconductor constituting the light-emitting element 1, for example, Al a Ga b In 1-a-b An II-VI group nitride semiconductor represented by N (0 ≤ a ≤ 1, 0 ≤ b ≤ 1, 0 ≤ a + b ≤ 1) can be used. In this embodiment, as the semiconductor constituting the light-emitting element 1, Al c Ga 1-c A binary or ternary group III nitride semiconductor represented by N (0 ≤ c ≤ 1) is used. Some of these group III elements may be replaced with boron (B), thallium (Tl), etc. Further, some of nitrogen may be replaced with phosphorus (P), arsenic (As), antimony (Sb), bismuth (Bi), etc.

[0014] The substrate 2 is made of a material that transmits the light emitted by the active layer 6. The substrate 2 is a sapphire (Al2O3) substrate. FIG. 2 is a schematic cross-sectional view parallel to the vertical direction of the light-emitting element 1 and is a schematic cross-sectional view in which the periphery of the AlN buffer layer 3 is enlarged. The growth surface 21 formed on the upper surface of the substrate 2 is composed of a c-plane having an off-angle θ. The off-angle θ is, for example, 0.2° or more and 1.5° or less, more preferably 1.0° ± 0.3° (that is, 0.7° or more and 1.3° or less). Note that FIG. 2 is merely a schematic diagram, and the shapes of the growth surface 21 of the substrate 2 and the upper surface 31 of the AlN buffer layer 3 may be different from the actual ones.

[0015] The growth surface 21 of the substrate 2 has a step-terrace structure having a plurality of terraces T1 formed on a c-plane having an off-angle θ and a plurality of steps S1 connecting the terraces T1. The step-terrace structure is one in which the terraces T1 and the steps S1 are alternately formed in multiple stages. The substrate 2 is not particularly limited. For example, the substrate 2 may have an off-angle θ of 0.2° and an average terrace width of 60.2 nm, an off-angle θ of 0.6° and an average terrace width of 20.1 nm, an off-angle θ of 1.0° and an average terrace width of 12.0 nm, or an off-angle θ of 1.5° and an average terrace width of 8.0 nm. Further, as the substrate 2, for example, an aluminum nitride (AlN) substrate or an aluminum gallium nitride (AlGaN) substrate may be used.

[0016] The AlN buffer layer 3 is formed on the substrate 2. The AlN buffer layer 3 is formed of undoped aluminum nitride. An undoped semiconductor layer means a semiconductor layer in which impurities are not intentionally added during the formation of the semiconductor layer, and a semiconductor layer containing a trace amount of impurities inevitably contained is also regarded as an undoped semiconductor layer.

[0017] The AlN buffer layer 3 is formed by step-flow growth, and the upper surface 31 of the AlN buffer layer 3 has a step-terrace structure having a plurality of terraces T2 inclined with respect to a virtual plane orthogonal to the vertical direction and a plurality of steps S2 connecting the terraces T2 to each other.

[0018] On the upper surface 31 of the AlN buffer layer 3, the average value of the height H of the step S2 is 7.1 nm or less, and the average value of the width of the terrace T2 is 350 nm or less. As a result, the active layer 6 formed using the AlN buffer layer 3 as an underlying layer is appropriately planarized, and the monochromaticity of the light emitted from the active layer 6 is improved. It is presumed that the light output in the desired wavelength band of the light-emitting element 1 is improved. The height H of the step S2 is the length of the step S2 in the vertical direction. The width of the terrace T2 is the length of the terrace T2 in the direction in which the terrace T2 and the step S2 are continuous (for example, the left-right direction in FIG. 2) among the directions orthogonal to the vertical direction. Hereinafter, the average value of the height H of the step S2 on the upper surface 31 of the AlN buffer layer 3 is also referred to as the "average step height", and the average value of the width W of the terrace T2 on the upper surface 31 of the AlN buffer layer 3 is also referred to as the "average terrace width".

[0019] The average step height is preferably less than 7.0 nm, and the average terrace width is more preferably 325 nm or less. Further, from the viewpoint of causing step-flow growth in the AlN buffer layer 3, the average step height is preferably 5.0 nm or more, and the average terrace width is preferably 250 nm or more.

[0020] The average step height can be calculated, for example, as follows. First, the surface shape of the AlN buffer layer 3 is measured using an atomic force microscope (AFM). Then, at least one cross-sectional profile is extracted from the measured AFM image along both the direction in which the terraces T2 and steps S2 are continuous and the vertical direction. Then, the average value of the height H of the steps S2 is obtained by dividing the sum of the heights H of the plurality of steps S2 appearing in the at least one extracted cross-sectional profile by the number of steps S2.

[0021] Also, the average terrace width can be obtained, for example, by dividing the sum of the widths of the terraces T2 appearing in the at least one cross-sectional profile extracted as described above by the number of terraces T2.

[0022] Note that, on the AlN buffer layer 3, an undoped Al p Ga 1-p buffer layer made of N (0 ≦ p ≦ 1) may be included.

[0023] The n-type semiconductor layer 4 is formed on the AlN buffer layer 3. The n-type semiconductor layer 4 is, for example, an n-type cladding layer formed of Al q Ga 1-q N (0 ≦ q ≦ 1) doped with an n-type impurity. In this embodiment, silicon (Si) is used as the n-type impurity. The same applies to semiconductor layers containing an n-type impurity other than the n-type semiconductor layer 4. Note that, as the n-type impurity, germanium (Ge), selenium (Se), tellurium (Te), or the like may be used. The Al composition ratio q of the n-type semiconductor layer 4 is, for example, 45% or more and 65% or less.

[0024] The shape of the upper surface of the n-type semiconductor layer 4 follows the shape of the upper surface 31 of the AlN buffer layer 3. At this time, up to a predetermined film thickness, the shape of the upper surface of the n-type semiconductor layer 4 becomes flatter as the film thickness increases. However, when the film thickness of the n-type semiconductor layer 4 exceeds the predetermined film thickness, it is considered that the change in the shape of the upper surface of the n-type semiconductor layer 4 due to the increase in the film thickness is substantially eliminated. Since the n-type semiconductor layer 4 is a semiconductor layer that causes energization, it is formed with a relatively large film thickness (for example, 1 μm or more) so as to be energizable. However, the film thickness usually adopted in the n-type semiconductor layer 4 is larger than the predetermined film thickness. In this embodiment, the film thickness of the n-type semiconductor layer 4 is, for example, 1600 nm or more and 3600 nm or less. The n-type semiconductor layer 4 may have a single-layer structure or a multilayer structure.

[0025] The composition gradient layer 5 is formed on the n-type semiconductor layer 4. The composition gradient layer 5 is composed of Al r Ga 1-r N (0 ≦ r ≦ 1). The Al composition ratio at each position in the vertical direction of the composition gradient layer 5 increases as the position is higher. Note that the composition gradient layer 5 may include a region where the Al composition ratio does not increase as it goes upward in, for example, a very small part of the vertical direction (for example, a region within 5% of the entire vertical direction of the composition gradient layer 5).

[0026] It is preferable that the Al composition ratio at the lower end of the composition gradient layer 5 is substantially the same as the Al composition ratio at the upper end of the n-type semiconductor layer 4 adjacent to the lower side of the composition gradient layer 5 (for example, the difference is within 5%). Also, it is preferable that the Al composition ratio at the upper end of the composition gradient layer 5 is substantially the same as the Al composition ratio at the lower end of the barrier layer 61 adjacent to the upper side of the composition gradient layer 5 (for example, the difference is within 5%). Silicon is doped in the composition gradient layer 5. The silicon concentration of the composition gradient layer 5 is, for example, 5.0 × 10 18 atoms / cm 3 or more and 5.0 × 10 19 atoms / cm 3 or less.

[0027] The active layer 6 is formed on the composition gradient layer 5. The active layer 6 of this embodiment has a multiple quantum well structure having a plurality of well layers 621 and 622. The bandgap of the active layer 6 is adjusted so that it can emit ultraviolet light with a central wavelength of 240 nm or more and 365 nm or less. When the active layer 6 is a multiple quantum well structure as in this embodiment, from the viewpoint of improving the light output, the central wavelength of the ultraviolet light emitted by the active layer 6 is preferably 250 nm or more and 300 nm or less, and more preferably 260 nm or more and 290 nm or less. In this embodiment, the active layer 6 has three barrier layers 61 and three well layers 621 and 622, and the barrier layers 61 and the well layers 621 and 622 are alternately laminated. In the active layer 6, the barrier layer 61 is located at the lower end, and the well layer 622 is located at the upper end.

[0028] Each barrier layer 61 is formed of Al s Ga 1-s N (0 < s ≦ 1). The Al composition ratio s of each barrier layer 61 is, for example, 75% or more and 95% or less. Also, the film thickness of each barrier layer 61 is, for example, 2 nm or more and 50 nm or less.

[0029] The well layers 621 and 622 are formed of Al t Ga 1-t N (0 < t < 1). The Al composition ratio t of each well layer 621 and 622 is smaller than the Al composition ratio s of the barrier layer 61 (that is, t < s).

[0030] The three well layers 621 and 622 are different in configuration between the bottom well layer 621 which is the bottommost well layer arranged at the lowermost side and the upper well layers 622 which are the two well layers other than the bottom well layer 621. For example, the film thickness of the bottom well layer 621 is 1 nm or more greater than the film thickness of each of the two upper well layers 622, and the Al composition ratio of the bottom well layer 621 is 2% or more greater than the Al composition ratio of each of the two upper well layers 622. In this embodiment, the upper well layer 622 has a film thickness of 2 nm or more and 4 nm or less and an Al composition ratio of 25% or more and 45% or less, and the bottom well layer 621 has a film thickness of 4 nm or more and 6 nm or less and an Al composition ratio of 35% or more and 55% or less. The difference in film thickness between the film thickness of the bottom well layer 621 and each upper well layer 622 can be 2 nm or more and 4 nm or less.

[0031] By making the Al composition ratio of the bottom well layer 621 greater than the Al composition ratio of the upper well layer 622, the crystallinity of the bottom well layer 621 is improved. This is because the difference in Al composition ratio between the bottom well layer 621 and the n-type semiconductor layer 4 becomes smaller. By improving the crystallinity of the bottom well layer 621, the crystallinity of each semiconductor layer of the active layer 6 formed upward from the bottom well layer 621 is also improved. As a result, the mobility of carriers in the active layer 6 is improved and the light output is improved. Such an effect is more remarkable as the film thickness of the bottom well layer 621 increases, but the film thickness of the bottom well layer 621 is designed to be equal to or less than a predetermined value from the viewpoint of suppressing an increase in the electrical resistance value of the entire light-emitting element 1.

[0032] In addition, in this embodiment, although an example in which the active layer 6 has a multiple quantum well structure with three well layers 621 and 622 is shown, the present invention is not limited thereto, and a multiple quantum well structure having two or four or more well layers may be used. Further, the active layer 6 may have a single quantum well structure having only one well layer.

[0033] The electron blocking layer 7 is formed on the active layer 6. The electron blocking layer 7 has a role of improving the electron injection efficiency into the active layer 6 by suppressing the occurrence of an overflow phenomenon in which electrons leak from the active layer 6 to the p-type semiconductor layer 8 side (hereinafter also referred to as the electron blocking effect). The electron blocking layer 7 has a stacked structure in which a first layer 71 and a second layer 72 are stacked in order from the lower side.

[0034] The first layer 71 is provided on the active layer 6. The first layer 71 is made of, for example, Al u Ga 1-u N (0 ≤ u ≤ 1). The Al composition ratio u of the first layer 71 is, for example, 90% or more, and in this embodiment, it is composed of aluminum nitride. The film thickness of the first layer 71 is, for example, 0.5 nm or more and 5.0 nm or less.

[0035] The second layer 72 is made of, for example, Al v Ga 1-v N (0 < v < 1). The Al composition ratio v of the second layer 72 is smaller than the Al composition ratio t of the first layer 71 (that is, v < t), and is, for example, 70% or more and 90% or less. The film thickness of the second layer 72 is larger than the film thickness of the first layer 71, and is, for example, 15 nm or more and 100 nm or less.

[0036] Since a semiconductor layer with a larger Al composition ratio has a larger electrical resistance value, if the film thickness of the first layer 71 with a relatively high Al composition ratio is made too large, it will cause an excessive increase in the overall electrical resistance value of the light-emitting element 1. Therefore, it is preferable to make the film thickness of the first layer 71 somewhat small. On the other hand, if the film thickness of the first layer 71 is made small, the probability that electrons tunnel through the first layer 71 from the lower side to the upper side can increase. Therefore, in the light-emitting element 1 of this embodiment, by forming the second layer 72 on the first layer 71, the overall electron blocking layer 7 is suppressed from being tunneled through by electrons.

[0037] Each of the first layer 71 and the second layer 72 can be an undoped layer, a layer containing n-type impurities, a layer containing p-type impurities, or a layer containing both n-type and p-type impurities. As the p-type impurity, magnesium (Mg) can be used, but in addition to magnesium, zinc (Zn), beryllium (Be), calcium (Ca), strontium (Sr), barium (Ba), carbon (C), etc. may also be used. The same applies to semiconductor layers containing other p-type impurities. When each electron blocking layer 7 contains impurities, the impurities contained in each electron blocking layer 7 may be contained in the entire electron blocking layer 7 or may be contained in a part of each electron blocking layer 7. In this embodiment, the entire electron blocking layer 7 is an undoped layer.

[0038] The p-type semiconductor layer 8 is formed on the electron blocking layer 7. The p-type semiconductor layer 8 has a smaller Al composition ratio than the electron blocking layer 7 and is Al doped with p-type impurities w Ga 1-w N (0 ≦ w ≦ 1). In this embodiment, the p-type semiconductor layer 8 has a p-type cladding layer 81 and a p-type contact layer 82 in order from the bottom.

[0039] The p-type cladding layer 81 is provided so as to be in contact with the upper surface of the electron blocking layer 7. The Al composition ratio of the p-type cladding layer 81 can be smaller than the Al composition ratio of the semiconductor layer adjacent to the p-type cladding layer 81 in the electron blocking layer 7 (that is, the second layer 72) and larger than the Al composition ratio of the p-type contact layer 82. The film thickness of the p-type cladding layer 81 is, for example, 9 nm or more and 105 nm or less.

[0040] The p-type contact layer 82 is the layer to which the p-side electrode 12 described later is connected, and is doped with a high concentration of p-type impurities. The p-type contact layer 82 is configured such that the Al composition ratio is low (for example, 10% or less) in order to achieve an ohmic contact with the p-side electrode 12, and from this viewpoint, it is preferably formed of p-type gallium nitride (GaN). Since the p-type contact layer 82 with a low Al composition ratio can absorb the ultraviolet light emitted from the active layer 6, the film thickness of the p-type contact layer 82 is preferably 50 nm or less, more preferably 25 nm or less. Also, from the viewpoint of suppressing the occurrence of shorts, the film thickness of the p-type contact layer 82 is preferably 5 nm or more.

[0041] The n-side electrode 11 is formed on the exposed surface 41 exposed upward from the active layer 6 in the n-type semiconductor layer 4. The n-side electrode 11 can be, for example, a multilayer film in which titanium (Ti), aluminum, titanium, and titanium nitride (TiN) are sequentially laminated on the n-type semiconductor layer 4. Also, when the light-emitting element 1 is flip-chip mounted as described later, the n-side electrode 11 may be formed of a material capable of reflecting the ultraviolet light emitted by the active layer 6.

[0042] The p-side electrode 12 is formed on the upper surface of the p-type semiconductor layer 8. The p-side electrode 12 can be composed of, for example, rhodium (Rh). In this embodiment, the p-side electrode 12 is a reflective electrode having a reflectivity of 50% or more, preferably 60% or more, at the central wavelength of the light emitted by the active layer 6, but is not limited thereto.

[0043] The light-emitting element 1 can be used by being flip-chip mounted on a package substrate (not shown). That is, the light-emitting element 1 has the side on which the n-side electrode 11 and the p-side electrode 12 are provided in the vertical direction facing the package substrate side, and each of the n-side electrode 11 and the p-side electrode 12 is mounted on the package substrate via a gold bump or the like. For the flip-chip mounted light-emitting element 1, light is extracted from the substrate 2 side (i.e., the lower side). Note that the present invention is not limited to this, and the light-emitting element 1 may be mounted on the package substrate by wire bonding or the like. Further, in the present embodiment, the light-emitting element 1 is a so-called horizontal light-emitting element in which both the n-side electrode 11 and the p-side electrode 12 are provided on the upper side of the light-emitting element 1. However, the present invention is not limited to this, and a vertical light-emitting element may be used. The vertical light-emitting element is a light-emitting element in which an active layer is sandwiched between an n-side electrode and a p-side electrode.

[0044] (Method for manufacturing the light-emitting element 1) Next, an example of the method for manufacturing the light-emitting element 1 of the present embodiment will be described. In the present embodiment, an AlN buffer layer 3, an n-type semiconductor layer 4, a composition gradient layer 5, an active layer 6, an electron blocking layer 7, and a p-type semiconductor layer 8 are sequentially epitaxially grown on a disk-shaped substrate 2 by metal organic chemical vapor deposition (MOCVD). That is, in the present embodiment, a disk-shaped substrate 2 is placed in the chamber, and each semiconductor layer is formed on the substrate 2 by introducing a source gas of each semiconductor layer formed on the substrate 2 into the chamber. As the source gas for epitaxially growing each semiconductor layer, trimethylaluminum (TMA) can be used as an aluminum source, trimethylgallium (TMG) can be used as a gallium source, ammonia (NH3) can be used as a nitrogen source, tetramethylsilane (TMSi) can be used as a silicon source, and biscyclopentadienylmagnesium (Cp2Mg) can be used as a magnesium source.

[0045] Incidentally, the MOCVD method is sometimes called the Metal Organic Vapor Phase Epitaxy (MOVPE). Also, when epitaxially growing each semiconductor layer on the substrate 2, other epitaxial growth methods such as Molecular Beam Epitaxy (MBE) and Hydride Vapor Phase Epitaxy (HVPE) can also be used.

[0046] In the manufacturing method of the light-emitting element 1 of this embodiment, the manufacturing conditions are designed such that the average step height on the upper surface 31 of the AlN buffer layer 3 is 7.1 nm or less and the average terrace width is 350 nm or less. For example, when the growth rate of the AlN buffer layer 3 is increased, the average step height tends to decrease. Adjustment of the growth rate of the AlN buffer layer 3 can be achieved, for example, by adjusting the growth temperature in the AlN buffer layer 3, the supply amount of the source gas, etc. The appropriate values of each manufacturing condition can vary depending on other manufacturing conditions and also depending on the manufacturing apparatus used. Also, the shape of the upper surface 31 of the AlN buffer layer 3 is affected not only by the growth rate but also by the shape of the growth surface 21 of the substrate 2. As described above, by appropriately adjusting the factors affecting the upper surface 31 of the AlN buffer layer 3, the AlN buffer layer 3 is grown in step-flow and its upper surface 31 is formed into the shape described above.

[0047] After forming each semiconductor layer on the disk-shaped substrate 2, a mask is formed on a part of the p-type semiconductor layer 8, that is, on a site other than the exposed surface 41 of the n-type semiconductor layer 4. Then, the region where the mask is not formed is removed by etching from the upper surface of the p-type semiconductor layer 8 to the middle of the n-type semiconductor layer 4 in the vertical direction. Thereby, an exposed surface 41 that is exposed upward is formed in the n-type semiconductor layer 4. After the formation of the exposed surface 41, the mask is removed.

[0048] Next, an n-side electrode 11 is formed on the exposed surface 41 of the n-type semiconductor layer 4, and a p-side electrode 12 is formed on the p-type semiconductor layer 8. The n-side electrode 11 and the p-side electrode 12 may be formed by a well-known method such as an electron beam evaporation method or a sputtering method. By cutting the thus completed product into desired dimensions, a plurality of light-emitting elements 1 as shown in FIG. 1 are manufactured from one wafer.

[0049] (Operations and Effects of the Embodiment) In the light-emitting element 1 of this embodiment, the upper surface 31 of the AlN buffer layer 3 has a step-and-terrace structure having a plurality of terraces T2 and a plurality of steps S2 connecting the terraces T2. And on the upper surface 31 of the AlN buffer layer 3, the average step height is 7.1 nm or less, and the average terrace width is 350 nm or less. Therefore, the light output of the light-emitting element 1 can be improved. This is presumably because the active layer 6 formed with the AlN buffer layer 3 as the underlying layer is appropriately planarized, and the monochromaticity of the light emitted from the active layer 6 is improved, resulting in an improvement in the light output in the desired wavelength band of the light-emitting element 1. These numerical values are supported by the experimental examples described later.

[0050] Also, the average step height is less than 7.0 nm. Therefore, the light output of the light-emitting element 1 can be further improved. These numerical values are supported by the experimental examples described later.

[0051] Also, the average terrace width is 325 nm or less. Therefore, the light output of the light-emitting element 1 can be further improved. These numerical values are supported by the experimental examples described later.

[0052] Also, the light-emitting element 1 further has a composition gradient layer 5 in which the Al composition ratio increases as the position is closer to the active layer 6 between the n-type semiconductor layer 4 and the active layer 6. Therefore, since the crystallinity of the active layer 6 is improved, the light output is more likely to be further improved in combination with the planarization of the active layer 6 by setting the average step height to 7.1 nm or less and the average terrace width to 350 nm or less as described above.

[0053] Further, in the light-emitting element 1, the p-side electrode 12 is a reflective electrode, and the film thickness of the p-type contact layer 82 is 50 nm or less. That is, the light-emitting element 1 of this embodiment has a configuration in which ultraviolet light emitted from the active layer 6 toward the p-side electrode 12 is reflected by the p-side electrode 12 and extracted from the substrate 2 side. When having such a configuration, the phase difference between the direct-emitted light directly emitted from the active layer 6 toward the substrate 2 side and the reflected-emitted light reflected by the p-side electrode 12 and extracted from the substrate 2 side is designed so that they reinforce each other and interfere. However, when the flatness of the interface of each semiconductor layer is poor, light scattering is likely to occur at the interface of each semiconductor layer. As a result, it is difficult for the phases of the direct-emitted light and the reflected-emitted light to be aligned, and there is a risk that the improvement of the light output is impaired. On the other hand, in the light-emitting element 1 of this embodiment, as described above, since the average step height on the upper surface 31 of the AlN buffer layer 3 is 7.1 nm or less and the average terrace width is 350 nm or less, it is considered that each semiconductor layer formed on the AlN buffer layer 3 also has a smaller step height and terrace width (that is, improved flatness). Therefore, in the light-emitting element 1 of this embodiment, the occurrence of light scattering at the interface of each semiconductor layer is suppressed, and the phases of the direct-emitted light and the reflected-emitted light are likely to be aligned. As a result, it becomes easier to improve the light output.

[0054] As described above, according to this embodiment, a nitride semiconductor light-emitting element capable of improving the light output can be provided.

[0055] [Experimental Example] This experimental example is an example in which the light output of wafers when the average step height and average terrace width on the upper surface of the AlN buffer layer are variously changed are evaluated. Among the names of the components used in this experimental example, those the same as the names used in the previously described embodiments represent the same components as those in the previously described embodiments unless otherwise specified.

[0056] In this experimental example, wafers according to Examples 1 to 5 and Comparative Examples 1 to 3 were prepared. As shown in Table 1 below, the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3 have the same basic structure as the light-emitting elements in the embodiments. The differences between Examples 1 to 5 and Comparative Examples 1 to 3 are the average step height and the average terrace width, which will be described in detail later. Table 1 shows the basic configuration common to the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3.

[0057]

Table 1

[0058] The Al composition ratio of each layer described in Table 1 is a value estimated from the secondary ion intensity of Al measured by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry). In addition, the column of the Al composition ratio of the composition gradient layer in Table 1 indicates that the Al composition ratio at each position in the vertical direction of the composition gradient layer gradually increases from 55% to 85% from the lower end to the upper end of the composition gradient layer. In the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3, a substrate with a c-plane having an off-angle of 1.0° ± 0.3° as the growth surface was used.

[0059] In addition, for the wafers according to Examples 1 to 5 and Comparative Examples 1 to 3, the average step height and the average terrace width were calculated. These calculation methods will be described below.

[0060] The average step height was calculated as follows. First, wafers grown to the AlN buffer layer under the same manufacturing conditions as those of each of Examples 1 to 5 and Comparative Examples 1 to 3 were prepared. Next, the shape of the upper surface of the AlN buffer layer of each wafer was measured by AFM. The AFM image of the upper surface of the AlN buffer layer of the wafer grown under the same manufacturing conditions as Example 1 is shown in FIG. 3A, and the AFM image of the upper surface of the AlN buffer layer of the wafer grown under the same manufacturing conditions as Comparative Example 1 is shown in FIG. 4A. In this example, a 5 μm square range was measured at the central position of the upper surface of each wafer.

[0061] Next, in each of the obtained AFM images, cross-sectional profiles were acquired at five arbitrary locations along both the vertical direction and the direction in which terraces and steps are continuous. The cross-sectional profile at the dashed-dotted line in Fig. 3A is shown in Fig. 3B, and the cross-sectional profile at the dashed-dotted line in Fig. 4A is shown in Fig. 4B.

[0062] Then, from the five cross-sectional profiles obtained from each AFM image, the height H of all the steps S2 that appeared was measured and averaged to calculate the average step height. In Fig. 3B, even extremely small steps appear, and such extremely small steps are also counted as one step.

[0063] Also, the average terrace width was calculated by measuring the width W of all the terraces T2 that appeared in the five cross-sectional profiles obtained from each AFM image and taking the average. In this experimental example, in the cross-sectional profiles shown in Figs. 3B and 4B, the length in the horizontal direction (i.e., among the directions orthogonal to the vertical direction, the direction in which terraces and steps are continuous) between the upper convex vertices located on both the left and right sides of the terrace T2 was regarded as the width W of the terrace T2. In Fig. 3B, even extremely small terraces appear, and such extremely small terraces are also counted as one terrace.

[0064] In Figs. 3B and 4B, the terraces that appear at both the left and right ends are interrupted in the middle, and the exact width of the entire terrace cannot be measured. Thus, for terraces that appear only partially, they were ignored when calculating the average terrace width. The same applies when steps appear at both the left and right ends and the steps are interrupted in the middle.

[0065] The average step height and average terrace width related to Examples 1 to 5 and Comparative Examples 1 to 3 calculated as described above are shown in Table 2. In Table 2, the light output of the wafers related to Examples 1 to 5 and Comparative Examples 1 to 3 is also described, which will be described later.

[0066]

Table 2

[0067] As shown in Table 2, Examples 1 to 5 satisfy that the average step height is 7.1 nm or less and the average terrace width is 350 nm or less, and Comparative Examples 1 to 3 have an average step height exceeding 7.1 nm and an average terrace width exceeding 350 nm.

[0068] Then, in each of Examples 1 to 5 and Comparative Examples 1 to 3, a current of 20 mA was passed in the on-wafer state, and the optical output was measured. The optical output of each of Examples 1 to 5 and Comparative Examples 1 to 3 was measured by a photodetector installed on the lower side (i.e., the substrate side) of each of Examples 1 to 5 and Comparative Examples 1 to 3. The relationship between the average step height and the optical output is shown in FIG. 5, and the relationship between the average terrace width and the optical output is shown in FIG. 6. Note that the emission wavelengths of Examples 1 to 5 and Comparative Examples 1 to 3 were 260 nm or more and 290 nm or less.

[0069] As can be seen from Table 2, FIG. 5, and FIG. 6, Examples 1 to 5 with an average step height of 7.1 nm or less and an average terrace width of 350 nm or less can obtain a higher optical output compared to Comparative Examples 1 to 3 with an average step height exceeding 7.1 nm and an average terrace width exceeding 350 nm.

[0070] Further, as in Examples 1 to 4, by setting the average step height to less than 7.0 nm, the optical output can be further increased. Also, as the average step height increases, the average terrace width tends to increase, and from the viewpoint of setting the average step height to less than 7.0 nm, the average terrace width is preferably 325 nm or less.

[0071] (Summary of the Embodiment) Next, regarding the technical idea grasped from the above-described embodiments, it will be described by referring to the reference numerals and the like in the embodiments. However, each reference numeral and the like in the following description are not limited to the members that specifically show the components in the claims in the embodiments.

[0072] [1] The first embodiment of the present invention includes a substrate 2 composed of a c-plane with a growth surface 21 having an off-angle θ, an AlN buffer layer 3 made of AlN formed on the growth surface 21, an n-type semiconductor layer 4 formed on the AlN buffer layer 3, an active layer 6 that emits ultraviolet light formed on the n-type semiconductor layer 4, and a p-type semiconductor layer 8 formed on the active layer 6. The upper surface 31 of the AlN buffer layer 3 has a step-terrace structure having a plurality of terraces T2 and a plurality of steps S2 connecting the terraces T2. The average value of the height H of the plurality of steps S2 is 7.1 nm or less, and the average value of the width W of the plurality of terraces T2 is 350 nm or less. This is the nitride semiconductor light-emitting device 1. Thereby, the light output of the nitride semiconductor light-emitting device 1 can be improved.

[0073] [2] The second embodiment of the present invention is that, in the first embodiment, the average value of the height H of the plurality of steps S2 is less than 7.0 nm. Thereby, the light output of the nitride semiconductor light-emitting device 1 can be further improved.

[0074] [3] The third embodiment of the present invention is that, in the first or second embodiment, the average value of the width W of the plurality of terraces T2 is 325 nm or less. Thereby, the light output of the nitride semiconductor light-emitting device 1 can be further improved.

[0075] [4] The fourth embodiment of the present invention is that, in any one of the first to third embodiments, a composition gradient layer 5 with a higher Al composition ratio as the position is closer to the active layer 6 side is further provided between the n-type semiconductor layer 4 and the active layer 6. Thereby, the light output of the nitride semiconductor light-emitting device 1 can be further improved.

[0076] [5] In the fifth embodiment of the present invention, in any one of the first to fourth embodiments, a reflective electrode 12 is further provided on the p-type semiconductor layer 8 to reflect the light emitted from the active layer 6, the p-type semiconductor layer 8 has a p-type contact layer 82 made of p-type GaN, and the film thickness of the p-type contact layer 82 is 50 nm or less. Thereby, the light output of the nitride semiconductor light-emitting device 1 can be further improved.

[0077] (Appendix) As described above, the embodiments of the present invention have been described. However, the above-described embodiments do not limit the invention according to the claims. It should also be noted that not all combinations of the features described in the embodiments are essential means for solving the problems of the invention. In addition, the present invention can be appropriately modified and implemented without departing from its gist. For example, a configuration in which the configurations of the above embodiments are appropriately combined may be adopted.

Explanation of Reference Numerals

[0078] 1... Nitride semiconductor light-emitting device 12... p-side electrode (reflective electrode) 2... Substrate 21... Growth surface 3... AlN buffer layer 31... Upper surface 4... n-type semiconductor layer 5... Composition gradient layer 6... Active layer 8... p-type semiconductor layer 82... p-type contact layer H... Height of step S2... Step T2... Terrace θ... Off-angle of substrate

Claims

1. A substrate composed of a c-plane having a growth surface with an off-angle, an AlN buffer layer made of AlN formed on the growth surface, an n-type semiconductor layer formed on the AlN buffer layer, an active layer that emits ultraviolet light formed on the n-type semiconductor layer, and a p-type semiconductor layer formed on the active layer, and the upper surface of the AlN buffer layer has a step-terrace structure having a plurality of terraces and a plurality of steps connecting the terraces, an average value of heights of the plurality of steps is 7.1 nm or less, an average value of widths of the plurality of terraces is 350 nm or less, a nitride semiconductor light-emitting device.

2. The average value of the heights of the plurality of steps is less than 7.0 nm, The nitride semiconductor light-emitting device according to Claim 1.

3. The average value of the widths of the plurality of terraces is 325 nm or less, The nitride semiconductor light-emitting device according to Claim 2.

4. Further comprising a composition gradient layer in which an Al composition ratio increases as a position on the active layer side between the n-type semiconductor layer and the active layer, The nitride semiconductor light-emitting device according to Claim 1 or 2.

5. Further comprising a reflective electrode formed on the p-type semiconductor layer and reflecting light emitted from the active layer, the p-type semiconductor layer has a p-type contact layer made of p-type GaN, a film thickness of the p-type contact layer is 50 nm or less, The nitride semiconductor light-emitting device according to Claim 1 or 2.

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