Inspection device, inspection method, and program

Abstract

To provide an inspection device, an inspection method, and a program that can reduce the number of steps required for operation inspection of a circuit including a transistor while ensuring accuracy of the operation inspection.SOLUTION: An inspection device of an embodiment is for performing operation inspection of a circuit including a transistor. The inspection device of the embodiment includes: a standard calculation unit that calculates an electrical standard of the transistor based on information related to specifications of the transistor; and a standard determination unit that determines whether an inspection data group, including temporal data of a current value flowing through the transistor and a voltage value applied to the transistor within a predetermined time range, satisfies the electrical standard, and outputs data in the inspection data group that is determined not to satisfy the electrical standard.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Embodiments of the present invention relate to a verification apparatus, a verification method, and a program.

Background Art

[0002] When designing a circuit including transistors, it is necessary to verify whether the circuit can operate without the transistors being damaged or deteriorated. As this verification method, for example, a double logarithmic graph showing a safe operating area (SOA: Safe Operating Area) (electrical standard) described in a transistor data sheet is compared with each data of the current value flowing through the transistor and the voltage value applied to the transistor obtained by simulation or the like, and a method of determining whether each data is included in the safe operating area is exemplified. However, when an operator manually performs the verification method, it may require a lot of man-hours. On the other hand, for example, it is also conceivable that the operator inputs the conditions of the safe operating area into a computer or the like and automatically performs the above verification method. However, in this case, since the condition setting of the safe operating area is entrusted to the operator, there is a risk that accurate verification cannot be performed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a verification apparatus, a verification method, and a program that can reduce the man-hours required for the operation verification while ensuring the accuracy of the operation verification of a circuit including transistors.

Means for Solving the Problems

[0005] The verification device according to the embodiment is a verification device that verifies the operation of a circuit including transistors. The verification device according to the embodiment includes a standard calculation unit that calculates the electrical standard of the transistor based on information regarding the specifications of the transistor, and a standard determination unit that determines whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range satisfies the electrical standard, and outputs data determined not to satisfy the electrical standard among the verification data group.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

MODE FOR CARRYING OUT THE INVENTION

[0007] Hereinafter, a verification apparatus, a verification method, and a program according to an embodiment will be described with reference to the drawings.

[0008] FIG. 1 is a block diagram showing the configuration of the verification apparatus 100 of the present embodiment. The verification apparatus 100 of the present embodiment shown in FIG. 1 is an apparatus for verifying the operation of a circuit 40 including a transistor 50. FIG. 2 is a diagram showing an example of the circuit 40 whose operation is verified by the verification apparatus 100. As shown in FIG. 2, the circuit 40 includes a transistor 50. In the example of FIG. 2, the transistor 50 is a field effect transistor (FET: Field Effect Transistor) having a gate 51, a drain 52, and a source 53. In the circuit 40, a resistor 61 is connected to the gate 51. A gate voltage is applied to the gate 51 via the resistor 61. The circuit 40 is provided with a resistor 62 connecting the gate 51 and the source 53. In the circuit 40, the source 53 is grounded.

[0009] The verification apparatus 100 is, for example, a computer. A program for causing the verification apparatus 100, which is a computer, to execute the verification method of the present embodiment is installed in the verification apparatus 100. As shown in FIG. 1, the verification apparatus 100 includes an arithmetic unit 10, an operation unit 20, and a display unit 30. The operation unit 20 is a part for an operator to operate the verification apparatus 100. The operation unit 20 is, for example, a keyboard and a mouse. By operating the operation unit 20, the operator can input various data to the arithmetic unit 10 and cause the arithmetic unit 10 to start an operation. The display unit 30 is a part capable of displaying the operation result of the arithmetic unit 10. The display unit 30 is, for example, a display. Note that when the verification apparatus 100 is a smart device such as a smartphone or a tablet terminal, the screen of the smart device may be the operation unit 20 and the display unit 30.

[0010] The arithmetic unit 10 is, for example, a processor such as a CPU (Central Processing Unit) in which a program capable of executing the verification method of the present embodiment is installed. The arithmetic unit 10 executes the verification method of the present embodiment for verifying the operation of the circuit 40. The arithmetic unit 10 includes a storage unit 11, a data determination unit 12, a standard calculation unit 13, a standard determination unit 14, and a waveform generation unit 15.

[0011] The memory unit 11 is a part where various data are stored. The memory unit 11 is realized by a memory medium such as, for example, RAM (Random Access Memory), ROM (Read Only Memory), HDD (Hard Disk Drive), and flash memory. The memory unit 11 stores data input by an operator via the operation unit 20, data of a file read by the operator via the operation unit 20, and the like.

[0012] The memory unit 11 has a verification data storage unit 11a and a specification data storage unit 11b. The verification data storage unit 11a is a part where a verification data group DG including data of the current value flowing through the transistor 50 and the voltage value applied to the transistor 50 at each time within a predetermined time range TR when the circuit 40 is driven is stored. In the present embodiment, the verification data group DG is a data group obtained by simulation. Note that the method for acquiring the verification data group DG by simulation is not particularly limited, and any known method can be adopted. The plurality of data included in the verification data group DG are sampling data Sd acquired at a predetermined sampling period. The sampling period is, for example, 0.1 microsecond or more. In the present embodiment, the voltage value of the sampling data Sd is the voltage applied between the drain 52 and the source 53, that is, the drain-source voltage V ds value. In the present embodiment, the current value of the sampling data Sd is the current flowing from the drain 52 to the source 53, that is, the drain current I d value.

[0013] FIG. 3 is a diagram showing an example of the verification data group DG as a time waveform. In the example of FIG. 3, the verification data group DG including the value of the drain current I d and the value of the drain-source voltage V ds of the transistor 50 within a predetermined time range TR from time t1 to time t6 is shown. The upper graph in FIG. 3 is the drain current I with respect to time t dIt is a graph showing the change of. The lower graph in FIG. 3 is the voltage V between the drain and the source with respect to time t ds It is a graph showing the change of. In the upper graph of FIG. 3, the horizontal axis is time t and the vertical axis is the drain current I d is. In the lower graph of FIG. 3, the horizontal axis is time t and the vertical axis is the voltage V between the drain and the source ds is. The verification data group DG includes current data Di and voltage data Dv. The current data Di and the voltage data Dv each have a plurality of sampling data Sd

[0014] In the example of the verification data group DG shown in FIG. 3, the time range TR has a first section P1, a second section P2, a third section P3, a fourth section P4, and a fifth section P5. The first section P1, the second section P2, the third section P3, the fourth section P4, and the fifth section P5 are provided continuously in this order in time. The first section P1 and the fifth section P5 are off sections in which the transistor 50 is in the off state. The second section P2 is a turn-on section in which the transistor 50 switches from the off state to the on state. The third section P3 is an on section in which the transistor 50 is in the on state. The fourth section P4 is a turn-off section in which the transistor 50 switches from the on state to the off state. The first section P1 is the section between time t1 and time t2. The second section P2 is the section between time t2 and time t3. The third section P3 is the section between time t3 and time t4. The fourth section P4 is the section between time t4 and time t5. The fifth section P5 is the section between time t5 and time t6. The width of the time in the second section P2, which is the turn-on section, is larger than the width of the time in the fourth section P4, which is the turn-off section

[0015] The specification data storage unit 11b is a part that stores information regarding the specifications of the transistor 50. The information regarding the specifications of the transistor 50 includes numerical values in a specification sheet on which various numerical values indicating the specifications of the transistor 50 are described, numerical values that can be read from a graph indicating the specifications of the transistor 50, and the like. The graph indicating the specifications of the transistor 50 includes a graph indicating the safe operating area (SOA) 70 of the transistor 50, and a graph indicating the change in the transient thermal resistance rth with respect to the pulse width tw of the pulse current applied to the transistor 50, and the like.

[0016] FIG. 4 is a diagram showing an example of a log-log graph indicating the safe operating area 70 of the transistor 50. In FIG. 4, the horizontal axis represents the drain-source voltage V ds and the vertical axis represents the drain current I d . The safe operating area 70 is an electrical specification of the transistor 50 indicating the range of the drain current I d and the range of the drain-source voltage V ds within which the transistor 50 can be safely used without being destroyed or degraded. The log-log graph indicating the safe operating area 70 is described in a data sheet indicating the specifications of the transistor 50. The safe operating area 70 shown in FIG. 4 is an area surrounded by a current limit area 71, a voltage limit area 72, an on-resistance limit area 73, a thermal limit area 74, and a secondary breakdown area 75, that is, the hatched area in FIG. 4. When a point determined from the value of the drain current I d and the value of the drain-source voltage V ds of the transistor 50 when the circuit 40 operates is plotted on the graph of FIG. 4, if the plotted point is within the safe operating area 70, the circuit 40 can be operated without destroying or degrading the transistor 50.

[0017] The current limit area 71 is an area determined from the rated value of the drain current I d . That is, the value of the drain current I d indicated by the area line of the current limit area 71 in FIG. 4 is the drain current I dis the rated value. The voltage limit region 72 is a region determined from the rated value of the drain-source voltage V ds . That is, the value of the drain-source voltage V ds indicated by the region line of the voltage limit region 72 in FIG. 4 is the rated value of the drain-source voltage V ds .

[0018] The on-resistance limit region 73 is a region determined from the maximum value of the on-resistance of the transistor 50. The on-resistance of the transistor 50 is the resistance value between the drain 52 and the source 53 when a voltage equal to or higher than the threshold value is applied to the gate 51 of the transistor 50 and the transistor 50 is turned on. The thermal limit region 74 is a region determined from the allowable loss P d of the transistor 50. The allowable loss P d is the maximum power consumption that does not exceed the temperature at which the performance of the transistor 50 can be maintained, and corresponds to the rated power of the transistor 50. The thermal limit region 74 is set within a range that can prevent the transistor 50 from being destroyed by heat.

[0019] The second breakdown region 75 is a region determined based on the second breakdown that occurs in the transistor 50. The second breakdown that occurs in the transistor 50 is a phenomenon in which current concentrates in the channel of the transistor 50 due to a decrease in the channel resistance as the temperature of the transistor 50 increases. More specifically, when the temperature of the transistor 50 rises, the threshold voltage of the gate 51 decreases, causing the channel resistance to decrease, and current concentrates in the channel with the decreased resistance, resulting in second breakdown. When second breakdown occurs and current concentrates in the channel, the temperature of the transistor 50 further rises, and the threshold voltage of the gate 51 further decreases. As a result, more current concentrates in the channel, and there is a risk that the transistor 50 will be destroyed.

[0020] Each region line shown by a solid line in FIG. 4 indicates, for example, each region when a direct current flows through the transistor 50. The safe operating region 70 changes depending on whether the current flowing through the transistor 50 is a direct current or a pulse current. Further, the safe operating region 70 also changes depending on the pulse width tw of the pulse current flowing through the transistor 50. Each region line of the current limit region 71, the thermal limit region 74, and the secondary breakdown region 75 shown by a broken line in FIG. 4 indicates a region when a pulse current flows through the transistor 50. In FIG. 4, the safe operating region 70 when a pulse current flows through the transistor 50 is a region surrounded by the current limit region 71, the thermal limit region 74, and the secondary breakdown region 75 shown by a broken line, and the voltage limit region 72 and the on-resistance limit region 73 shown by a solid line. From FIG. 4, it is confirmed that the range of the safe operating region 70 changes between the case where a direct current flows through the transistor 50 and the case where a pulse current flows through the transistor 50. The safe operating region 70 when a direct current flows through the transistor 50 is narrower than the safe operating region 70 when a pulse current flows through the transistor 50. The voltage limit region 72 and the on-resistance limit region 73 do not change depending on, for example, the current flowing through the transistor 50.

[0021] A double logarithmic graph showing the safe operating region 70 described in the data sheet indicating the specifications of the transistor 50 shows the safe operating region 70 when a direct current flows through the transistor 50 and the safe operating region 70 when a pulse current flows through the transistor 50. Regarding the safe operating region 70 when a pulse current flows through the transistor 50, a plurality of safe operating regions 70 with different pulse widths tw are shown in the double logarithmic graph showing the safe operating region 70 of the transistor 50. The plurality of safe operating regions 70 when a pulse current flows through the transistor 50 include, for example, the safe operating regions 70 when the pulse width tw is 10 milliseconds, 1 millisecond, 100 microseconds, and 10 microseconds.

[0022] FIG. 5 shows the transient thermal resistance r with respect to the pulse width tw of the pulse current applied to the transistor 50 thIt is a diagram showing an example of a graph indicating the change of th th . The graph in Fig. 5 is a log-log graph. In Fig. 5, the horizontal axis represents the pulse width tw [seconds], and the vertical axis represents the transient thermal resistance r th [℃ / W]. The transient thermal resistance r

[0023] is the thermal resistance in the time range affected by the heat capacity. The change in the transient thermal resistance r d changes, for example, according to the duty ratio of the pulse current applied to the transistor 50. ds ch c d ds ch c d d d d d c Stored in the specification data storage unit 11b are the rated value of the drain current I d flowing through the transistor 50, the rated value of the drain-source voltage V ds applied to the transistor 50, the maximum value of the on-resistance of the transistor 50, the channel temperature T ch of the transistor 50, and the case temperature T c of the transistor 50. The rated value of the drain current I d flowing through the transistor 50, the rated value of the drain-source voltage V ds applied to the transistor 50, the maximum value of the on-resistance of the transistor 50, the channel temperature T ch of the transistor 50, and the case temperature T c of the transistor 50 are, for example, numerical values that can be read from the specification sheet of the transistor 50.

[0024] The rated value of the drain current I d stored in the specification data storage unit 11b includes the rated value when the drain current I d flowing through the transistor 50 is a direct current and the rated value when the drain current I d flowing through the transistor 50 is a pulse current. The rated value when the drain current I d flowing through the transistor 50 is a pulse current may be provided for each pulse current with a plurality of pulse widths tw. Note that, for example, when the rated value of the drain current I d is not described in the specification sheet, the rated value may be read from the log-log graph showing the safe operating area 70 of the transistor 50 shown in Fig. 4. The case temperature T cis the temperature of the case of the transistor 50. The case temperature T c is, for example, the standard case temperature T described in the specification of the transistor 50 c1 and the case temperature T that is assumed to be reached as the temperature of the transistor 50 rises c The maximum value of and are stored in the specification data storage unit 11b. The case temperature T c1 is, for example, 25°C. Note that in the specification data storage unit 11b, instead of the case temperature T c the ambient temperature T of the transistor 50 a may be stored.

[0025] In the specification data storage unit 11b, transient thermal resistances r corresponding to a plurality of pulse widths tw th are stored. The value of the transient thermal resistance r th The value of can be read from the graph showing the change in the transient thermal resistance r with respect to the pulse width tw shown in FIG. 5. For example, in FIG. 5, when a pulse current with a pulse width tw of 0.001 seconds flows through the transistor 50, the transient thermal resistance r th is the value r1. In the specification data storage unit 11b, the transient thermal resistance r corresponding to the direct current th is the value r1. The value of the transient thermal resistance r corresponding to the direct current th is stored. The value of the transient thermal resistance r corresponding to the direct current th The value of can also be read from the graph showing the change in the transient thermal resistance r with respect to the pulse width tw shown in FIG. 5. Specifically, when the pulse width tw becomes larger than a certain size and the value of the transient thermal resistance r th no longer changes, the value of the transient thermal resistance r th is read as the value of the transient thermal resistance r corresponding to the direct current th th th In FIG. 5, when the pulse width tw is 0.1 seconds or more, the transient thermal resistance r th becomes constant. For example, in FIG. 5, when the pulse width tw is 10 seconds, the value r2 of the transient thermal resistance r th can be used as the value of the transient thermal resistance r corresponding to the direct current th The value r2 is, for example, a value larger than the value r1.

[0026] In the specification data storage unit 11b, the drain currents I at any two points on the region line indicating the secondary yield region 75 d and the values of the drain-source voltages V ds are stored. Each of these values can be read from the double logarithmic graph showing the safe operating region 70 of the transistor 50 shown in FIG. 4. For example, in the specification data storage unit 11b, the drain current I at the point 75a shown in FIG. 4 d and the value of the drain-source voltage V ds and the drain current I at the point 75b shown in FIG. 4 d and the value of the drain-source voltage V ds are stored.

[0027] The data determination unit 12 is a part that determines which of the plurality of sections CL the sampling data Sd included in the verification data group DG belongs to. The plurality of sections CL are sections corresponding to a plurality of safe operating regions 70 according to the pulse application time of the pulse current applied to the transistor 50, that is, the pulse width tw. In the present embodiment, the plurality of sections CL are determined based on the magnitude of the slope of the time change of the drain current I d in the verification data group DG. Specifically, in the example shown in FIG. 3, the plurality of sections CL include a first section CL1, a second section CL2, and a third section CL3.

[0028] The first section CL1 is a section where the slope of the time change of the drain current I d is greater than or equal to the value α and less than or equal to the value β. The value α is a negative value, and the value β is a positive value. The absolute value of the value α and the absolute value of the value β may be the same as each other or different from each other. The second section CL2 is a section where the slope of the time change of the drain current I d is greater than the value β. The third section CL3 is a section where the drain current I dis a section where the slope of the time change is smaller than the value α. In the example of FIG. 3, the first section P1, the third section P3, and the fifth section P5 are included in the first classification CL1. The second section P2 is included in the second classification CL2. The fourth section P4 is included in the third classification CL3. That is, the second classification CL2 is the classification CL of the sampling data Sd included in the turn-on section. The third classification CL3 is the classification CL of the sampling data Sd included in the turn-off section. The first classification CL1 is the classification CL of the sampling data Sd included in the section other than the turn-on section and the turn-off section. The absolute value of the slope of the drain current I d in the first classification CL1 is smaller than the absolute value of the slope of the drain current I d in the second classification CL2 and the third classification CL3. The value α is the determination value of the slope at the time of turn-off (fall time). The value β is the determination value of the slope at the time of turn-on (rise time).

[0029] Note that, for example, when the time width of the second section P2, which is the turn-on section, is relatively large, the second section P2 may be regarded as a section corresponding to the case where a direct current flows through the transistor 50 and classified into the first classification CL1.

[0030] In sections where the drain current I d and the drain-source voltage V ds change, such as the second section P2 and the fourth section P4, the time width of each section can be regarded as the pulse width tw of the pulse current applied to the transistor 50. Here, in the section where the drain current I d and the drain-source voltage V ds change, the larger the absolute value of the slope of the drain current I d , the smaller the time width of the section, and the smaller the absolute value of the slope of the drain current I d , the larger the time width of the section. Therefore, by calculating the magnitude of the slope of the drain current I d , the drain current I dIt is possible to determine what pulse current with what pulse width tw is applied.

[0031] The data determination unit 12 calculates the slope of the time change of the drain current I in the verification data group DG. In the present embodiment, the data determination unit 12 calculates the slope for each sampling data Sd included in the verification data group DG. Specifically, the data determination unit 12 calculates, for example, the drain current I of the sampling data Sd using the sampling data Sd before and after the sampling data Sd for which the slope is calculated. d The differential value dI / dt, which is the differential value obtained by differentiating the drain current I of the sampling data Sd, is calculated as the slope in the sampling data Sd. The data determination unit 12 determines to which of the plurality of sections CL each sampling data Sd included in the verification data group DG corresponds based on the calculated value of the slope. In the following description, the slope of the time change of the drain current I in the verification data group DG may be referred to as the slope dI / dt. d / dt d / dt d The slope of the time change of the drain current I in the verification data group DG is sometimes referred to as the slope dI / dt. d / dt

[0032] The specification calculation unit 13 is a part that calculates the electrical specifications of the transistor 50 based on information regarding the specifications of the transistor 50. In the present embodiment, the specification calculation unit 13 calculates the safe operating region 70 of the transistor 50 as the electrical specification of the transistor 50. Specifically, the specification calculation unit 13 derives functions representing the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the second breakdown region 75 based on numerical values regarding the specifications of the transistor 50, and calculates the safe operating region 70 as the electrical specification. In the present embodiment, the specification calculation unit 13 uses the rated current value of the transistor 50, that is, the rated value of the drain current I, and the rated voltage value of the transistor 50, that is, the rated value of the drain-source voltage V, and the maximum value of the on-resistance of the transistor 50, and the allowable loss P of the transistor 50, and the drain current I related to the second breakdown of the transistor 50. d The rated value of the drain current I, and the rated voltage value of the transistor 50, that is, the rated value of the drain-source voltage V, and the maximum value of the on-resistance of the transistor 50, and the allowable loss P of the transistor 50, and the drain current I related to the second breakdown of the transistor 50. ds The rated value of the drain-source voltage V, and the maximum value of the on-resistance of the transistor 50, and the allowable loss P of the transistor 50, and the drain current I related to the second breakdown of the transistor 50. d The allowable loss P of the transistor 50, and the drain current I related to the second breakdown of the transistor 50. dvalue and the drain-source voltage V ds Based on the value of ds and the value of the drain-source voltage V, the electrical standard, i.e., the safe operating area 70, is calculated. In the following description, the safe operating area 70 calculated by the standard calculation unit 13 is referred to as the safe operating area 70S.

[0033] In the present embodiment, the standard calculation unit 13 can calculate the electrical standard corresponding to each of the plurality of sections CL, i.e., the safe operating area 70S. In the present embodiment, the standard calculation unit 13 calculates the safe operating area 70A corresponding to the first section CL1, the safe operating area 70B corresponding to the second section CL2, and the safe operating area 70C corresponding to the third section CL3. The safe operating area 70A in the first section CL1 corresponds to the safe operating area when a direct current flows through the transistor 50. The safe operating areas 70B and 70C in the second section CL2 and the third section CL3 correspond to the safe operating area when a pulse current flows through the transistor 50. The safe operating area 70B in the second section CL2 corresponds to the safe operating area when the pulse width tw of the pulse current flowing through the transistor 50 is larger than that in the safe operating area 70C in the third section CL3. Since the plurality of safe operating areas 70S calculated by the standard calculation unit 13 are divided based on the time (pulse width tw) during which current flows through the transistor 50, it can be said that the plurality of electrical standards calculated by the standard calculation unit 13 include the time standard of the transistor 50.

[0034] The current limit region 71 sets the drain current as I d and, when the rated value of the drain current I d is I r is represented by I d =I r The standard calculation unit 13 can derive a function representing the current limit region 71 by substituting the rated value of the drain current I r stored in the specification data storage unit 11b into I d in the above formula.

[0035] The voltage limit region 72 sets the drain-source voltage as V ds and the drain-source voltage Vds When the rated value is V r , it is represented by V ds = V r . The specification calculation unit 13 can derive a function representing the voltage limit region 72 by substituting the rated value of the drain-source voltage V r stored in the specification data storage unit 11b into V ds in the formula.

[0036] The on-resistance limit region 73 sets the drain current as I d , the drain-source voltage as V ds , and the maximum value of the on-resistance as R ds . When this is the case, I d = V ds / (R ds ). The specification calculation unit 13 can derive a function representing the on-resistance limit region 73 by substituting the maximum value of the on-resistance stored in the specification data storage unit 11b into R ds in the formula.

[0037] The thermal limit region 74 sets the drain current as I d , the drain-source voltage as V ds , and the allowable loss as P d . When this is the case, I d = P d / V ds . The allowable loss P d is represented by P ch = (T c - T th ) / r d when the channel temperature is T ch , the case temperature is T c , and the transient thermal resistance is r th . The specification calculation unit 13 can derive a function representing the thermal limit region 74 by substituting the values of the channel temperature T ch , the case temperature T c , and the transient thermal resistance r th stored in the specification data storage unit 11b into these formulas. Note that when the allowable loss P d is described in the specification sheet of the transistor 50, the allowable loss P d described in the specification sheetStore the numerical value in the specification data storage unit 11b, and use the stored value as the allowable loss P d and it may be used as the value of

[0038] The secondary breakdown region 75 has a drain current of I d and, when the drain-source voltage is V ds is represented by the following equation (1).

[0039] [Number] However, I d1 is the drain current I d at any point on the region line indicating the secondary breakdown region 75 in the double logarithmic graph of the safe operating region 70 described in the data sheet of the transistor 50, and V ds1 is the drain-source voltage V ds at the said any point. I d2 is the drain current I d at another arbitrary point on the region line indicating the secondary breakdown region 75 in the double logarithmic graph of the safe operating region 70 described in the data sheet of the transistor 50, and V ds2 is the drain-source voltage V ds at the said another arbitrary point.

[0040] The specification calculation unit 13 can derive a function representing the secondary breakdown region 75 by substituting the values of the drain current I d and the drain-source voltage V ds at any two points on the region line indicating the secondary breakdown region 75, which are stored in the specification data storage unit 11b, into the above equation (1). In this embodiment, the value of the drain current I d1 at the point 75a shown in FIG. 4 is substituted into I d , and the value of the drain-source voltage V ds1 at the point 75a is substituted into V ds . The value of the drain current I d2 at the point 75b shown in FIG. 4 is substituted into I d , and the drain-source voltage V ds2 at the point 75b is substituted into Vds The value of

[0041] Based on each function that defines the above-described safe operating region 70S, the specification calculation unit 13 creates a data table according to each sampling data Sd included in the verification data group DG. The specification calculation unit 13 determines the drain current I in the current limit region 71 corresponding to the value of the drain-source voltage V between each drain and source of each sampling data Sd ds of the value, that is, the data group of the rated value of the drain current I stored in the specification data storage unit 11b, and creates a data table of the current limit region 71. The specification calculation unit 13 determines the drain-source voltage V in the voltage limit region 72 corresponding to the value of the drain current I of each sampling data Sd d of the value, that is, the data group of the rated value of the drain-source voltage V stored in the specification data storage unit 11b, and creates a data table of the voltage limit region 72. d of the value, and creates a data table of the voltage limit region 72. d of the value, that is, the data group of the rated value of the drain-source voltage V stored in the specification data storage unit 11b, and creates a data table of the voltage limit region 72. ds of the value, that is, the data group of the rated value of the drain-source voltage V stored in the specification data storage unit 11b, and creates a data table of the voltage limit region 72. ds of the value, that is, the data group of the rated value of the drain-source voltage V stored in the specification data storage unit 11b, and creates a data table of the voltage limit region 72.

[0042] Among the functions that define the safe operating region 70S, the specification calculation unit 13 substitutes the value of the drain-source voltage V of each sampling data Sd included in the verification data group DG into the function having I d and V ds as variables, that is, the function representing the on-resistance limit region 73, the function representing the thermal limit region 74, and the function representing the secondary breakdown region 75, and creates data tables of the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 corresponding to each sampling data Sd, respectively. ds of each sampling data Sd included in the verification data group DG, and creates data tables of the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 corresponding to each sampling data Sd, respectively. ds of each sampling data Sd included in the verification data group DG, and creates data tables of the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 corresponding to each sampling data Sd, respectively.

[0043] The specification calculation unit 13 plots each value of the created data table on a double logarithmic graph, and creates a double logarithmic graph of the safe operating region 70S corresponding to the safe operating region 70 described in the data sheet of the transistor 50. In the present embodiment, the specification calculation unit 13 creates a double logarithmic graph of the safe operating region 70S corresponding to each of the plurality of sections CL.

[0044] FIG. 6 is a diagram showing an example of a double logarithmic graph of a safe operating region 70A corresponding to a first section CL1 created by the standard calculation unit 13. FIG. 7 is a diagram showing an example of a double logarithmic graph of a safe operating region 70B corresponding to a second section CL2 created by the standard calculation unit 13. FIG. 8 is a diagram showing an example of a double logarithmic graph of a safe operating region 70C corresponding to a third section CL3 created by the standard calculation unit 13. In FIGS. 6 to 8, the horizontal axis represents the drain-source voltage V ds and the vertical axis represents the drain current I d . In FIGS. 6 to 8, the region lines of the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 are schematically shown as straight lines. However, in reality, the region lines indicating each region are created based on the values of the plotted data table. As shown in FIGS. 6 to 8, the voltage limit region 72 and the on-resistance limit region 73 are the same in the safe operating region 70S of any section CL.

[0045] The standard calculation unit 13 adjusts the electrical standard based on the temperature related to the transistor 50. The temperature related to the transistor 50 may be any temperature related to the transistor 50, which may be the temperature at any location of the transistor 50 or the temperature around the transistor 50. In the present embodiment, the standard calculation unit 13 adjusts the thermal limit region 74 and the secondary breakdown region 75 among the regions defining the safe operating region 70S based on the case temperature T c of the transistor 50. Specifically, the standard calculation unit 13 adjusts the thermal limit region 74 and the secondary breakdown region 75 by adjusting the value of the allowable loss P d .

[0046] FIG. 9 is a diagram showing an example of a graph showing the change in the allowable loss P c with respect to the case temperature T d of the transistor 50. In FIG. 9, the horizontal axis represents the case temperature T c and the vertical axis represents the allowable loss P d . In the example of FIG. 9, the case temperature T c is the standard case temperature Tc1 In the above region, the allowable loss P d decreases linearly as the case temperature T c increases. From this relationship, when the case temperature T c is calculated as the standard case temperature T c1 and the allowable loss is P d1 , and the channel temperature is T ch , when the case temperature T c is the case temperature T c1 higher than the case temperature T c2 and the allowable loss P d2 calculated as T d2 =P d1 ×(T ch -T c2 ) / (T ch -T c1 ). The case temperature T c2 is, for example, the maximum value of the case temperature T c expected to be reached as the temperature of the transistor 50 increases. As an example, the case temperature T c2 is 120°C or the like.

[0047] The standard calculation unit 13 can adjust the thermal limit region 74 when the case temperature T d is the case temperature T d1 by changing the allowable loss P d2 from the allowable loss P c to the allowable loss P c1 . c c2 d1 d2

[0048] The standard calculation unit 13 multiplies the right side of the above formula (1) representing the secondary yield region 75 by the ratio of the allowable loss P d1 to the allowable loss P d2 to adjust the secondary yield region 75 when the case temperature T c is the case temperature T c1 to the secondary yield region 75 when the case temperature T c is the case temperature T c2It can be adjusted to the secondary breakdown region 75 when [conditions are met]. Specifically, the standard calculation unit 13 can obtain a function of the adjusted secondary breakdown region 75 according to the following formula (2).

[0049]

Equation

[0050] FIG. 10 is a diagram showing an example when the double logarithmic graph of the safe operating region 70B corresponding to the second section CL2 is adjusted. In FIG. 10, the horizontal axis is the drain-source voltage V ds and the vertical axis is the drain current I d . As shown in FIG. 10, when the case temperature T c increases from the case temperature T c1 to a case temperature T c1 higher than the case temperature T c2 , the values of the drain current I d in the thermal limit region 74 and the secondary breakdown region 75 decrease, and the safe operating region 70B becomes narrower. In this way, the standard calculation unit 13 can perform temperature derating on the safe operating region 70S.

[0051] The specification determination unit 14 determines whether the verification data group DG satisfies the electrical specifications calculated by the specification calculation unit 13. In the present embodiment, the specification determination unit 14 determines whether each sampling data Sd of the verification data group DG is included in the safe operating region 70S calculated by the specification calculation unit 13. More specifically, the specification determination unit 14 plots the sampling data Sd classified into a plurality of sections CL on the double logarithmic graph of the safe operating region 70S created by the specification calculation unit 13 for each of the plurality of sections CL, and determines whether each sampling data Sd is included in the safe operating region 70S of the plotted double logarithmic graph. That is, in the present embodiment, the specification determination unit 14 determines the sampling data Sd using the safe operating region 70S corresponding to each section CL according to which section CL the sampling data Sd to be determined is included in. In other words, the specification determination unit 14 automatically changes the electrical specifications used for the verification data group DG according to the section CL determined by the data determination unit 12.

[0052] When the sampling data Sd is included in all of the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the secondary yield region 75 that define the safe operating region 70S, the specification determination unit 14 determines that the sampling data Sd is included in the safe operating region 70S and that the sampling data Sd satisfies the electrical specifications of the transistor 50. When the sampling data Sd is not included in one or more of the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the secondary yield region 75, the specification determination unit 14 determines that the sampling data Sd is not included in the safe operating region 70S and that the sampling data Sd does not satisfy the electrical specifications of the transistor 50. The specification determination unit 14 outputs the sampling data Sd determined not to satisfy the electrical specifications among the verification data group DG to the waveform generation unit 15.

[0053] That the sampling data Sd is included in the current limit region 71 means that the drain current I of the sampling data Sd d has a value equal to the drain current I of the region line of the current limit region 71 d, that is, the drain current I d means that it is smaller than the rated value. That the sampling data Sd is included in the voltage limit region 72 means that the drain-source voltage V ds of the sampling data Sd has a value smaller than the drain-source voltage V ds of the region line of the voltage limit region 72, that is, smaller than the rated value of the drain-source voltage V ds . That the sampling data Sd is included in the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 means that, for the drain-source voltage V ds of the sampling data Sd, the value of the drain current I d of the sampling data Sd is smaller than the value of the drain current I d at each region line of the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75.

[0054] FIG. 11 is a diagram showing an example in which sampling data Sd determined to be the first section CL1 is plotted on a log-log graph of the safe operating region 70A of the first section CL1. FIG. 12 is a diagram showing an example in which sampling data Sd determined to be the second section CL2 is plotted on a log-log graph of the safe operating region 70B of the second section CL2. FIG. 13 is a diagram showing an example in which sampling data Sd determined to be the third section CL3 is plotted on a log-log graph of the safe operating region 70C of the third section CL3. FIG. 14 is a diagram showing an example in which sampling data Sd determined to be the second section CL2 is plotted on a log-log graph of the adjusted safe operating region 70B of the second section CL2.

[0055] In FIGS. 11 to 14, the horizontal axis is the drain-source voltage V ds , and the vertical axis is the drain current I d . Note that in FIGS. 11 to 14, the region lines of the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 are schematically shown as straight lines, but in reality, the region lines indicating each region are created based on the values of the plotted data table.

[0056] In FIGS. 11 to 14, each safe operation region 70S, that is, sampling data Sd that satisfies each electrical standard is indicated by a white circle, and sampling data Sd that does not satisfy each electrical standard is indicated by a black circle. The standard determination unit 14 outputs the sampling data Sd determined not to satisfy the electrical standard to the waveform generation unit 15. Note that the standard determination unit 14 may output each log-log graph in which the sampling data Sd is plotted to the display unit 30 and cause the display unit 30 to display it. Further, the standard determination unit 14 may indicate all the sampling data Sd with plots of the same color in each log-log graph to be displayed on the display unit 30.

[0057] The waveform generation unit 15 is the drain current I in the verification data group DG d and the drain-source voltage V ds to generate a time waveform W. Specifically, the waveform generation unit 15 plots each sampling data Sd included in the verification data group DG stored in the verification data storage unit 11a on the time axis, and the drain current I d and the drain-source voltage V ds to generate a time waveform W. The waveform generation unit 15 displays the sampling data Sd that does not satisfy the electrical standard output from the standard determination unit 14 among the verification data group DG on the created time waveform W.

[0058] FIG. 15 is a diagram showing an example of the time waveform W generated by the waveform generation unit 15. The upper graph in FIG. 15 is a graph showing the time waveform Wi of the drain current I d . The lower graph in FIG. 15 is a graph showing the time waveform Wd of the drain-source voltage V ds . In the upper graph of FIG. 15, the horizontal axis is time t, and the vertical axis is the drain current I d . In the lower graph of FIG. 15, the horizontal axis is time t, and the vertical axis is the drain-source voltage V dsIt is as follows. As shown in FIG. 15, the waveform generation unit 15 emphasizes and displays sampling data Sd that does not meet the electrical standard on each time waveform Wi, Wd. In the example of FIG. 15, sampling data Sd that meets the electrical standard is indicated by white circles, and sampling data Sd that does not meet the electrical standard is indicated by black circles. The waveform generation unit 15 outputs the created time waveform W to the display unit 30 and causes the display unit 30 to display it. As a result, the operator can confirm which part of the verification data group DG is outside the safe operating region 70S of the transistor 50, that is, does not meet the electrical standard.

[0059] Next, a verification method using the verification device 100 will be described. FIG. 16 is a flowchart showing an example of the calculation procedure in the calculation unit 10. FIG. 17 is a flowchart showing an example of the processing procedure in the data determination unit 12. FIG. 18 is a flowchart showing an example of the processing procedure in the standard calculation unit 13. FIG. 19 is a flowchart showing an example of the processing procedure in the standard determination unit 14. FIG. 20 is a flowchart showing an example of the processing procedure in the waveform generation unit 15.

[0060] As shown in FIG. 16, when information on the specifications of the transistor 50 and the verification data group DG are input to the calculation unit 10 via the operation unit 20 (step S11), the calculation unit 10 determines which of the plurality of sections CL each sampling data Sd of the verification data group DG belongs to (step S12), and calculates the safe operating region 70S, that is, the electrical standard, for each of the plurality of sections CL (step S13).

[0061] Note that the calculation unit 10 may sequentially perform step S12 and step S13, and in that case, either step S12 or step S13 may be performed first. Also, in the case where a determination of a transistor 50 having the same specifications has been made prior to this verification, if the information on the specifications of the transistor 50 input last time is stored in the storage unit 11, the input of the information on the specifications of the transistor 50 in step S11 may be omitted.

[0062] Step S12 is performed by the data decision unit 12. As shown in FIG. 17, the data decision unit 12 calculates the drain current I d The time waveform is, for example, similar to the time waveform shown in the upper graph of FIG. 3. The data decision unit 12 creates a time waveform of the drain current I d The time waveform of is differentiated for each sampling data Sd, and the slope of the time change dI d In this way, the verification method of the present embodiment calculates the gradient dI d This includes calculating / dt.

[0063] The data judgment unit 12 calculates the slope dI d It is determined whether or not / dt satisfies a first predetermined condition (step S23). The first predetermined condition is the slope dI d / dt is smaller than the above-mentioned value α or larger than the above-mentioned value β. d If / dt does not satisfy the first predetermined condition (step S23: NO), the data judgment unit 12 judges that the sampling data Sd falls into the first category CL1 (step S25).

[0064] On the other hand, the calculated slope dI d When / dt satisfies the first predetermined condition (step S23: YES), the data judgment unit 12 d It is determined whether or not / dt satisfies a second predetermined condition (step S24). The second predetermined condition is the slope dI d / dt is greater than the above-mentioned value β. The calculated slope dI d When / dt satisfies the second predetermined condition (step S24: YES), the data judgment unit 12 judges that the sampling data Sd falls into the second section CL2 (step S26). dWhen / dt does not satisfy the second predetermined condition (step S24: NO), the data determination unit 12 determines that the sampling data Sd corresponds to the third category CL3 (step S27). The data determination unit 12 performs the above-described determination for all the sampling data Sd included in the verification data group DG, and determines to which category CL each sampling data Sd corresponds. Thus, the verification method of the present embodiment is such that each sampling data Sd included in the verification data group DG has a slope dI d includes determining to which of a plurality of categories CL divided based on the magnitude of / dt the sampling data Sd corresponds.

[0065] Step S13 is performed in the standard calculation unit 13. As shown in FIG. 18, the standard calculation unit 13 derives a safe operating region 70S, that is, a function representing an electrical standard, based on information regarding the specifications of the transistor 50 (step S31). In the present embodiment, the standard calculation unit 13 derives a function representing the safe operating region 70S for each of the plurality of categories CL. Specifically, the standard calculation unit 13 derives functions representing the current limit region 71, the voltage limit region 72, the on-resistance limit region 73, the thermal limit region 74, and the secondary breakdown region 75 as described above. That is, the verification method of the present embodiment includes calculating an electrical standard based on the rated current value of the transistor 50, the rated voltage value of the transistor 50, the maximum value of the on-resistance of the transistor 50, the allowable loss P of the transistor d and the current value and voltage value related to the secondary breakdown of the transistor 50.

[0066] Based on the derived function, the specification calculation unit 13 creates a data table of the safe operating region 70S according to each sampling data Sd of the verification data group DG (step S32). In the present embodiment, the specification calculation unit 13 creates a data table of the safe operating region 70S for each of the plurality of sections CL. The specification calculation unit 13 creates a double logarithmic graph of the safe operating region 70S from the created data table (step S33). In the present embodiment, the specification calculation unit 13 creates a double logarithmic graph of the safe operating region 70S for each of the plurality of sections CL. The double logarithmic graph of the safe operating region 70S created by the specification calculation unit 13 in step S33 is, for example, the graph shown in FIGS. 6 to 8 described above.

[0067] Note that, for example, when an instruction to perform temperature derating is input to the verification device 100 by an operator, in step S13, the specification calculation unit 13 adjusts the electrical specifications as shown in FIG. 10 described above based on the case temperature T of the transistor 50. c Based on this.

[0068] As described above, the verification method of the present embodiment includes calculating the electrical specifications of the transistor 50 based on the information regarding the specifications of the transistor 50, calculating the electrical specifications corresponding to each of the plurality of sections CL, and adjusting the electrical specifications based on the temperature regarding the transistor 50.

[0069] As shown in FIG. 16, after performing steps S12 and S13, the arithmetic unit 10 determines whether each sampling data Sd is included in the safe operation region 70S for each of the plurality of sections CL (step S14). Step S14 is performed in the standard determination unit 14. As shown in FIG. 19, in step S14, the standard determination unit 14 reads the double logarithmic graph of the safe operation region 70S created by the standard calculation unit 13 in accordance with the section CL determined by the data determination unit 12 (step S41). As shown in FIGS. 11 to 14, the standard determination unit 14 plots the sampling data Sd included in the section CL determined by the data determination unit 12 on the double logarithmic graph (step S42). The standard determination unit 14 determines whether the plotted sampling data Sd is included in the safe operation region 70S (step S43). If the sampling data Sd is included in the safe operation region 70S, the standard determination unit 14 similarly determines the next sampling data Sd (step S45). On the other hand, if the sampling data Sd is not included in the safe operation region 70S, the standard determination unit 14 outputs the sampling data Sd to the waveform generation unit 15 (step S44) and similarly determines the next sampling data Sd (step S45).

[0070] The standard determination unit 14 performs step S14 until the determination of all the sampling data Sd included in the verification data group DG is completed. The standard determination unit 14 may perform the determination of the sampling data Sd in any order as long as the determination is performed for all the sampling data Sd. The standard determination unit 14 may perform the determination of the sampling data Sd for each of the plurality of sections CL, or may sequentially determine one by one the sampling data Sd included in the verification data group DG in chronological order.

[0071] As described above, the verification method of the present embodiment includes determining whether a verification data group DG including sampling data Sd at each time of a current value flowing through the transistor 50 and a voltage value applied to the transistor 50 within a predetermined time range TR satisfies electrical standards, outputting sampling data Sd determined not to satisfy the electrical standards among the verification data group DG, and automatically changing the electrical standards used for the determination of the verification data group DG according to the determined section CL.

[0072] As shown in FIG. 16, after performing step S14, the arithmetic unit 10 generates a time waveform W in which sampling data Sd not included in the safe operating region 70S is displayed, and displays it on the display unit 30 (step S15). Step S15 is performed in the waveform generation unit 15. As shown in FIG. 20, in step S15, the waveform generation unit 15 generates the time waveform W of the verification data group DG as shown in FIG. 15 described above, and displays it on the display unit 30 (step S51). The waveform generation unit 15 highlights and displays the sampling data Sd not included in the safe operating region 70S on the time waveform W (step S52). In step S52, the waveform generation unit 15, for example, changes the color of the sampling data Sd not included in the safe operating region 70S with respect to the sampling data Sd included in the safe operating region 70S and plots it on the time waveform W, thereby highlighting and displaying the sampling data Sd not included in the safe operating region 70S on the time waveform W. Thus, the verification method of the present embodiment includes generating a time waveform W of the current value and the voltage value in the verification data group DG, and displaying sampling data Sd not satisfying the electrical standards among the verification data group DG on the time waveform W.

[0073] Thereby, the operation verification by the verification device 100 is completed. By looking at the time waveform W displayed on the display unit 30, the operator can easily confirm which part of the verification data group DG plotted on the time axis is not included in the safe operating region 70S, that is, does not satisfy the electrical standards.

[0074] At least a part of the functions of each component of the above-described arithmetic unit 10 is realized, for example, by a processor such as a CPU executing a program stored in the storage unit 11, that is, software. Note that at least a part of the functions of each component of the arithmetic unit 10 may be realized by hardware including a circuit unit such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit), or may be realized by cooperation between software and hardware.

[0075] According to the present embodiment, the verification device 100 is a verification device that verifies the operation of the circuit 40 including the transistor 50, and includes a standard calculation unit 13 that calculates the electrical standard (safe operation region 70S) of the transistor 50 based on information regarding the specifications of the transistor 50, and the current value (drain current I d value) flowing through the transistor 50 and the voltage value (drain-source voltage V dsA standard determination unit 14 determines whether a verification data group DG including sampling data Sd at each time of a value) satisfies electrical standards, and outputs sampling data Sd determined not to satisfy the electrical standards among the verification data group DG. Therefore, simply by an operator inputting information regarding the specifications of the transistor 50 to the verification device 100, the electrical standards of the transistor 50 are automatically calculated, and sampling data Sd that does not satisfy the electrical standards among the verification data group DG is output. As a result, the operator can easily verify whether each sampling data Sd of the verification data group DG satisfies the electrical standards of the transistor 50 only by inputting to the verification device 100 several minimum necessary numerical values that can be easily read from a specification sheet or the like, without the operator himself / herself inputting the electrical standards of the transistor 50 to the verification device 100. Therefore, unlike the case where the operator himself / herself inputs the electrical standards of the transistor 50, the accuracy of the electrical standards used for the determination of the verification data group DG is guaranteed. Thereby, while guaranteeing the accuracy of the operation verification of the circuit 40 including the transistor 50, the man-hours required for the operation verification can be reduced.

[0076] Further, the verification data group DG includes sampling data Sd at each time of a current value flowing through the transistor 50 and a voltage value applied to the transistor 50 within a predetermined time range TR. Therefore, by knowing which sampling data Sd of the verification data group DG does not satisfy the electrical standards of the transistor 50, the operator can easily grasp at which location on the time axis the current value flowing through the transistor 50 and the voltage value applied to the transistor 50 do not satisfy the electrical standards when the circuit 40 operates within the predetermined time range TR. As a result, the operator can easily investigate the cause why the operation of the circuit 40 does not satisfy the electrical standards of the transistor 50, and can easily take measures for the operation of the circuit 40 to satisfy the electrical standards of the transistor 50. Therefore, the design of the circuit 40 including the transistor 50 can be facilitated.

[0077] Further, according to the present embodiment, the verification device 100 is the drain current I in the verification data group DGd Calculate the slope dI of the time change of the value of d / dt, and determine which of the plurality of sections CL into which each sampling data Sd included in the verification data group DG is classified based on the magnitude of the slope dI d / dt. It includes a data determination unit 12. The standard calculation unit 13 can calculate the electrical standards corresponding to each of the plurality of sections CL. The standard determination unit 14 automatically changes the electrical standard used for the determination of the verification data group DG according to the section CL determined by the data determination unit 12. As described above, when the drain current I d changes, the slope dI of the time change of the value of the drain current I d d The larger the absolute value of / dt, the shorter the length of the period during which the drain current I d changes, and the smaller the absolute value of the slope dI of the time change of the value of the drain current I d d / dt, the longer the length of the period during which the drain current I d changes. Therefore, by dividing each sampling data Sd into a plurality of sections CL according to the slope dI d / dt and determining each sampling data Sd using the electrical standards corresponding to each section CL, it is possible to determine whether each sampling data Sd satisfies the electrical standards according to the pulse application time applied to the transistor 50. Therefore, the determination of the verification data group DG can be performed more accurately and preferably.

[0078] Also, according to the present embodiment, based on the rated current value of the transistor 50, the rated voltage value of the transistor 50, the maximum value of the on-resistance of the transistor 50, the allowable loss P d of the transistor 50, and the current value and voltage value related to secondary breakdown of the transistor 50, the electrical standards are calculated. Therefore, the standard calculation unit 13 can preferably and easily calculate the safe operating region 70S as the electrical standard.

[0079] Also, according to the present embodiment, the standard calculation unit 13 uses the case temperature T as the temperature related to the transistor 50 c ​​Adjust the electrical standard based on this. Therefore, for example, when it is predicted that the temperature of the transistor 50 will be higher than normal during the operation of the circuit 40, by inputting the predicted temperature into the verification device 100, the electrical standard can be adjusted according to the predicted temperature, that is, temperature derating can be performed. Thereby, the operation verification of the circuit 40 including the transistor 50 can be performed more accurately.

[0080] Also, according to the present embodiment, the verification device 100 includes a waveform generation unit 15 that generates a time waveform W of the current value and the voltage value in the verification data group DG. The waveform generation unit 15 displays the sampling data Sd that does not satisfy the electrical standard among the verification data group DG on the time waveform W. Therefore, the operator can more preferably grasp at which location on the time axis in the verification data group DG the electrical standard of the transistor 50 is not satisfied by looking at the time waveform W displayed on the display unit 30.

[0081] Each effect of the verification device 100 described above is also an effect obtained in the same way for a verification method including a method corresponding to each configuration of the verification device 100.

[0082] According to at least one embodiment described above, the verification device is a verification device that performs operation verification of a circuit including a transistor. The verification device includes a standard calculation unit that calculates the electrical standard of the transistor based on information regarding the specifications of the transistor, and a standard determination unit that determines whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range satisfies the electrical standard, and outputs the data determined not to satisfy the electrical standard among the verification data group. By having these, while ensuring the accuracy of the operation verification of the circuit including the transistor, the man-hours required for the operation verification can be reduced.

[0083] If the specification calculation unit calculates the electrical specifications of the transistor based on the information regarding the specifications of the transistor, it may have any configuration. The electrical specifications may be specifications outside the safe operating region as long as they are specifications that enable the operation verification of the circuit including the transistor. The specification calculation unit may calculate the electrical specifications of the transistor based on the information regarding the specifications of the transistor by a method other than the above-described embodiments. The specification calculation unit may calculate the electrical specifications without using any one or more of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and the current value and voltage value regarding secondary breakdown of the transistor.

[0084] The data determination unit may calculate the slope of the time change of the voltage value in the verification data group and determine to which of a plurality of sections each data belongs. The number of sections divided based on the magnitude of the slope of the time change of the current value or voltage value is not particularly limited as long as it is two or more. The plurality of sections may be divided based on the magnitude of the slope of the time change of the current value or voltage value and the length of the period during which the magnitude of the slope continues continuously. For example, when the transistor is in the on state, the magnitude of the slope becomes a value close to almost zero. However, when the length of the period during which such a slope continues continuously is small to a certain extent or more, the period during which the transistor is in the on state may be determined as the period corresponding to the case where a pulse current flows through the transistor. The plurality of sections may not be provided. The waveform generation unit may generate a time waveform of only one of the current value and the voltage value in the verification data group. The method for the waveform generation unit to display the data that does not satisfy the electrical specifications on the time waveform is not particularly limited.

[0085] The verification device may not include a storage unit. In this case, the verification device may read information regarding the specifications of the transistor and the verification data group from a storage unit such as a server installed separately from the verification device via network communication or the like. The type of transistor whose operation is verified by the verification device and verification method of the embodiment is not particularly limited. The transistor may be a transistor other than a field effect transistor such as a bipolar transistor.

[0086] The verification device, verification method, and program of the embodiment include the following appended aspects. (Appended Note 1) A verification device for verifying the operation of a circuit including a transistor, a standard calculation unit that calculates the electrical standard of the transistor based on information regarding the specifications of the transistor, a standard determination unit that determines whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range satisfies the electrical standard, and outputs data determined not to satisfy the electrical standard among the verification data group, A verification device comprising: (Appended Note 2) A data determination unit that calculates the slope of the time change of the current value or the voltage value in the verification data group, and determines to which of a plurality of sections into which each data included in the verification data group is classified based on the magnitude of the slope, the standard calculation unit is capable of calculating the electrical standard corresponding to each of the plurality of sections, The verification device according to Appended Note 1, wherein the standard determination unit automatically changes the electrical standard used for the determination of the verification data group according to the section determined by the data determination unit. (Appended Note 3) The specification calculation unit calculates the electrical specification based on at least one of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and the current value and the voltage value related to secondary breakdown of the transistor. The verification device according to Appendix 1 or Appendix 2. (Appendix 4) The specification calculation unit adjusts the electrical specification based on the temperature related to the transistor. The verification device according to any one of Appendices 1 to 3. (Appendix 5) It includes a waveform generation unit that generates at least one of the time waveforms of the current value and the voltage value in the verification data group. The waveform generation unit displays data that does not meet the electrical specification among the verification data group on the time waveform. The verification device according to any one of Appendices 1 to 4. (Appendix 6) A verification method for performing operation verification of a circuit including a transistor, calculating the electrical specification of the transistor based on information related to the specifications of the transistor; determining whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range meets the electrical specification; outputting data determined not to meet the electrical specification among the verification data group; A verification method including the above. (Appendix 7) calculating the slope of the time change of the current value or the voltage value in the verification data group; determining which of a plurality of sections divided based on the magnitude of the slope each data included in the verification data group corresponds to; calculating the electrical specification corresponding to each of the plurality of sections; automatically changing the electrical specification used for the determination of the verification data group according to the determined section; A verification method according to Appendix 6, including the above. (Appendix 8) The verification method according to Appendix 6 or Appendix 7, including calculating the electrical standard based on at least one of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and the current value and the voltage value related to the second breakdown of the transistor. (Appendix 9) The verification method according to any one of Appendices 6 to 8, including adjusting the electrical standard based on the temperature related to the transistor. (Appendix 10) Generating at least one of the time waveforms of the current value and the voltage value in the verification data group; Displaying the data that does not meet the electrical standard in the verification data group on the time waveform; The verification method according to any one of Appendices 6 to 9, including the above. (Appendix 11) A program for causing a computer to execute the verification method according to any one of Appendices 6 to 10.

[0087] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are also included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0088] 12... Data determination unit, 13... Standard calculation unit, 14... Standard determination unit, 15... Waveform generation unit, 40... Circuit, 50... Transistor, 100... Verification device, CL... Division, DG... Verification data group, dI d / dt... Slope, I d ... Drain current (current), V ds…Drain-source voltage (voltage), Pd, Pd1, Pd2... Allowable loss, TR... Time range, W, Wd, Wi... Time waveform

Claims

1. A verification device for verifying the operation of a circuit including a transistor, comprising: a standard calculation unit that calculates the electrical standard of the transistor based on information regarding the specifications of the transistor; a standard determination unit that determines whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range satisfies the electrical standard, and outputs data determined not to satisfy the electrical standard among the verification data group; A verification device comprising the above.

2. A data determination unit that calculates the slope of the time change of the current value or the voltage value in the verification data group, and determines to which of a plurality of sections into which each data included in the verification data group is classified based on the magnitude of the slope; the standard calculation unit is capable of calculating the electrical standard corresponding to each of the plurality of sections; The verification device according to claim 1, wherein the standard determination unit automatically changes the electrical standard used for determination of the verification data group according to the section determined by the data determination unit.

3. The verification device according to claim 1, wherein the standard calculation unit calculates the electrical standard based on at least one of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and the current value and the voltage value related to secondary breakdown of the transistor.

4. The verification device according to claim 1, wherein the standard calculation unit adjusts the electrical standard based on the temperature related to the transistor.

5. A waveform generation unit that generates at least one of the time waveforms of the current value and the voltage value in the verification data group; The waveform generation unit displays data not satisfying the electrical standard among the verification data group on the time waveform. The verification device according to any one of claims 1 to 4.

6. A verification method for verifying the operation of a circuit including a transistor, comprising: calculating the electrical standard of the transistor based on information regarding the specifications of the transistor; determining whether a verification data group including data for each time of the current value flowing through the transistor and the voltage value applied to the transistor within a predetermined time range satisfies the electrical standard; Outputting data determined not to meet the electrical standard among the verification data group; A verification method including this.

7. Calculating the slope of the time change of the current value or the voltage value in the verification data group; Determining which of a plurality of sections into which each data included in the verification data group is classified based on the magnitude of the slope the data belongs to; Calculating the electrical standard corresponding to each of the plurality of sections; Automatically changing the electrical standard used for the determination of the verification data group according to the determined section; The verification method according to claim 6, including this.

8. Calculating the electrical standard based on at least one of the rated current value of the transistor, the rated voltage value of the transistor, the maximum value of the on-resistance of the transistor, the allowable loss of the transistor, and the current value and the voltage value related to the second breakdown of the transistor, the verification method according to claim 6.

9. The verification method according to claim 6, including adjusting the electrical standard based on the temperature related to the transistor.

10. Generating at least one time waveform of the current value and the voltage value in the verification data group; Displaying data that does not meet the electrical standard among the verification data group on the time waveform; The verification method according to any one of claims 6 to 9, including this.

11. A program for causing a computer to execute the verification method according to any one of claims 6 to 9.

Images