Power supply circuit

Abstract

To provide a power supply circuit capable of supplying a stable constant voltage in accordance with a change in a load current due to the operation of a load circuit to which power is supplied.SOLUTION: A power supply circuit 10a supplies a DC voltage to an output node No to which a load circuit 100 that becomes an active state or an inactive state in accordance with an enable signal EN is connected. An error amplifier 12 outputs a voltage obtained by amplifying a voltage difference between a voltage Vout at the output node and the predefined value of the DC voltage. An output transistor 15 supplies, to the output node No, a current that changes in accordance with an output voltage from a first error amplifier. A current supply circuit 20 is configured to: supply a DC current to the output node No when the load circuit 100 is in an active state; and stop the current supply when the load circuit 100 is in an inactive state.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a power supply circuit.

Background Art

[0002] As a power supply circuit that outputs a desired voltage required by a system, a digital circuit, an analog circuit, etc. from an externally supplied voltage, a regulator circuit is widely known. In particular, when obtaining a low output voltage with respect to the supply voltage, a linear regulator typified by a low dropout regulator (LDO) circuit is used.

[0003] In an LDO circuit, there is a concern that the output voltage with respect to the power supply destination greatly fluctuates due to a large amount of load current being drawn from the output transistor by the operation of the circuit at the power supply destination.

[0004] To address this problem, Japanese Patent Application Laid-Open No. 3-158912 (Patent Document 1) describes a circuit configuration that changes the amount of current (operating current) flowing through an error amplifier in an LDO circuit in accordance with an increase or decrease in load current as an LDO circuit for suppressing fluctuations in the output voltage.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] In the LDO circuit disclosed in Patent Document 1, by adjusting the operating speed (slew rate) of the error amplifier in accordance with the load current, the amount of fluctuation in the output voltage can be suppressed to a certain level or less within a wide load current range.

[0007] However, in the configuration of Patent Document 1, in order to monitor the load current amount, a path for constantly flowing a current amount proportional to the load current amount is provided inside the error amplifier, so there is a concern that the power consumption will increase. Further, since the current amount of the error amplifier changes according to the load current amount, there is also a concern that it will be relatively difficult to ensure stability.

[0008] The present disclosure has been made to solve such problems, and an object of the present disclosure is to provide a power supply circuit capable of supplying a stable constant voltage in response to fluctuations in the load current accompanying the operation of a load circuit of a power supply destination.

Means for Solving the Problems

[0009] In one aspect of the present disclosure, a power supply circuit is provided. The power supply circuit supplies a DC voltage to an output node to which a load circuit that becomes an operating state or a stationary state according to the logic level of an enable signal is connected. The power supply circuit includes a first error amplifier, a first output transistor, and a current supply circuit. The first error amplifier outputs a voltage obtained by amplifying the voltage difference between the voltage of the output node and the specified value of the DC voltage. The first output transistor supplies a current that changes according to the output voltage of the first error amplifier to the output node. The current supply circuit supplies a DC current to the output node during the operating state of the load circuit, while stopping the current supply during the stationary state of the load circuit.

Effects of the Invention

[0010] According to the present disclosure, it is possible to provide a configuration of a power supply circuit capable of supplying a stable constant voltage in response to fluctuations in the load current accompanying the operation of a load circuit of a power supply destination.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0012] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the drawings. In the following, the same or corresponding parts in the drawings are denoted by the same reference numerals, and the description thereof will not be repeated in principle.

[0013] Embodiment 1. (Explanation of Comparative Example) First, a power supply circuit according to a comparative example will be described with reference to FIG. 1.

[0014] Referring to FIG. 1, the power supply circuit 10♯ according to the comparative example is composed of an LDO circuit according to the prior art, and includes an error amplifier 12, an output transistor 15, and a voltage dividing circuit 17. The power supply circuit 10♯ supplies an output voltage Vout to an output node No to which a load circuit 100 is connected. A smoothing capacitor 105 for stabilizing the output voltage Vout may be connected to the output node No.

[0015] The voltage dividing circuit 17 has resistor elements R1 and R2 connected in series between the output node No and the GND node Ns that supplies the ground voltage Vss. The voltage dividing circuit 17 outputs a divided voltage Vdv (Vdv = kv·Vout) according to a voltage division ratio kv (kv < 1.0) determined by the resistance values of the resistor elements R1 and R2.

[0016] The output transistor 15 is connected between the power supply node Np to which the input voltage Vin is supplied and the output node No, and its gate (control electrode) receives the output voltage of the error amplifier 12. The output transistor 15 is composed of, for example, a P-type field effect transistor (hereinafter simply referred to as "P-type transistor").

[0017] The error amplifier 12 outputs a voltage obtained by amplifying the voltage difference between the divided voltage Vdv input to the non-inverting input terminal and the reference voltage Vref input to the inverting input terminal. The reference voltage Vref is represented by the product of the specified value (Vo*) of the output voltage Vout and the voltage division ratio kv (Vref = Vo*·kv). Therefore, the error amplifier 12 outputs a voltage obtained by amplifying the voltage difference between the output voltage Vout and its specified value Vo*. Note that the error amplifier 12 may be powered by the input voltage Vin, or may be powered by a voltage from a control power supply or the like different from the input voltage Vin.

[0018] The load circuit 100 is set to an operating state or a stationary state (non-operating state) according to the enable signal EN. For example, during the H level period of the enable signal EN, the load circuit 100 operates with the output voltage Vout of the power supply circuit 10♯ as the power supply voltage. On the other hand, during the L level period of the enable signal EN, the load circuit 100 is in a stationary state. The load circuit 100 consumes a load current Ild1 in the operating state.

[0019] As the load circuit 100 operates, when the output voltage Vout becomes lower than the specified value Vo*, the divided voltage Vdv becomes lower than the reference voltage Vref, causing the output voltage of the error amplifier 12 to decrease. As a result, the output transistor 15 composed of P-type transistors has a large gate-source voltage and conducts (turns on). Thereby, a current for increasing the output voltage Vout is supplied from the power supply node Np to the output node No by the output transistor 15.

[0020] On the other hand, when the output voltage Vout is higher than the specified value Vo*, the divided voltage Vdv becomes higher than the reference voltage Vref, causing the output voltage of the error amplifier 12 to increase. As a result, the output transistor 15 has a small gate-source voltage and turns off. Thereby, the current supply from the output transistor 15 to the output node No is cut off.

[0021] The power supply circuit 10# (LDO circuit) responds to a decrease in the output voltage Vout due to the load current by controlling the amount of current of the output transistor 15 by feedback of the divided voltage Vdv. That is, even if the output voltage Vout decreases below the specified value Vo*, the output voltage Vout can return to the specified value Vo* by the negative feedback operation of the LDO circuit following after a certain time.

[0022] However, if the change in the load current is too rapid with respect to the response speed determined by the characteristics of the error amplifier 12 and the output transistor 15, the output voltage Vout may fluctuate.

[0023] Here, in the configuration of FIG. 1, in addition to the load circuit 100 performing an intermittent operation of repeating an operating state and a stationary state in response to the enable signal EN, it is assumed that a load current Ild0 is constantly supplied from the output node No to another load circuit (not shown).

[0024] In this case, in response to the enable signal EN changing from the L level to the H level, the load current consumed from the output node No increases rapidly. Accordingly, in order to suppress fluctuations in the output voltage Vout, it becomes necessary to rapidly increase the amount of current of the output transistor 15. On the other hand, if the size of the output transistor 15 is increased in order to increase the response speed, there is a risk that the phase stability in the negative feedback operation will be impaired due to an increase in the gate capacitance of the output transistor 15 and the parasitic capacitance between the gate and drain.

[0025] For this reason, if a configuration is adopted in which the operating current of the error amplifier 12 is changed according to the load current amount as in Patent Document 1, in addition to circuit complexity, as described above, there are concerns about an increase in power consumption due to constantly monitoring the load current amount and a decrease in operating stability due to a change in the current amount of the error amplifier 12.

[0026] (Power supply circuit according to Embodiment 1) In Embodiment 1, a configuration example of a power supply circuit including a load circuit that operates intermittently according to an enable signal EN at the power supply destination, which eliminates the concerns described in the comparative example, will be described.

[0027] FIG. 2 is a circuit block diagram for explaining a configuration example of the power supply circuit 10a according to Embodiment 1.

[0028] As shown in FIG. 2, the power supply circuit 10a includes an LDO circuit 11 and a current supply circuit 20. The configuration and operation of the LDO circuit 11 are the same as those of the power supply circuit (comparative example) 10# in FIG. 1. That is, the LDO circuit 11 does not have a mechanism for making the operating current of the error amplifier 12 variable as in Patent Document 1. Regarding the output transistor 15, it is also possible to configure it with an N-type field effect transistor (hereinafter, also simply referred to as an "N-type transistor"). In this case, the polarity of the input of the error amplifier 12 is reversed, and the divided voltage Vdv is input to the inverting input terminal while the reference voltage Vref is input to the non-inverting input terminal. The error amplifier 12 corresponds to an example of the "first error amplifier", and the output transistor 15 corresponds to an example of the "first output transistor".

[0029] Also, the load circuit 100 and the smoothing capacitor 105 are the same as those in FIG. 1. Also in FIG. 2, in addition to the load circuit 100, other load circuits (not shown) may be connected. As a result, when the enable signal EN changes from the L level to the H level, the current supplied by the power supply circuit 10a rapidly increases from the level corresponding to the load current Ild0 to the level corresponding to the sum of the load currents Ild0 and Ild1. Also, the load circuit 100 may be either an analog circuit or a digital circuit as long as its operating state and standby state are controlled by the enable signal EN.

[0030] The current supply circuit 20 is configured as a current source that executes or stops the supply of the current Ics in conjunction with the operating state and standby state of the load circuit 100. The current Ics can be set to be equivalent to the load current Ild1 by estimating the load current Ild1 during the operation of the load circuit 100.

[0031] FIG. 3 shows a circuit diagram for explaining a configuration example of the current supply circuit 20.

[0032] Referring to FIG. 3, the current supply circuit 20 includes a current supply transistor 22, a switch 23, and a voltage fixing transistor 24. The current supply transistor 22 is connected between a voltage node Nc that supplies the power supply voltage Vc and an output node No. The voltage fixing transistor 24 is connected between the voltage node Nc and the gate of the current supply transistor 22. The enable signal EN is input to the gate of the voltage fixing transistor 24.

[0033] The current supply transistor 22 and the voltage fixing transistor 24 can be constituted by a P-type transistor or an N-type transistor, but in the example of FIG. 3, they are constituted by P-type transistors. A bias voltage Vbias, which is a constant voltage, is input to the gate of the current supply transistor 22 via the switch 23. The current Ics of the current supply transistor 22 can be adjusted by the bias voltage Vbias. When the constant voltage (bias voltage Vbias) is input to the gate, the current supply transistor 22 can constitute an example of a "constant current source".

[0034] The switch 23 is arranged to form or cut off the supply path of the bias voltage Vbias to the gate of the current supply transistor 22. The switch 23 and the voltage fixing transistor 24 are turned on and off according to an enable signal EN common to the load circuit 100. When the load circuit 100 is in an operating state, the switch 23 is turned on and the voltage fixing transistor 24 is turned off. On the other hand, when the load circuit 100 is in a stationary state, the switch 23 is turned off and the voltage fixing transistor 24 is turned on, so that the gate of the current supply transistor 22 is fixed to the power supply voltage Vc and the current supply transistor 22 maintains an off state.

[0035] When the current supply transistor 22 is constituted by an N-type transistor, the voltage fixing transistor 24 can be configured to input the ground voltage Vss to the gate of the current supply transistor 22 during the off period (L-level period) of the enable signal EN. Also, the voltage node Nc may be common to the power supply node Np, and in this case, Vc = Vin.

[0036] During the ON period (H level) of the enable signal, a current Ics set to be equal to the load current Ild1 of the load circuit 100 is output to the output node No by the current supply transistor 22. On the other hand, during the OFF period (L level) of the enable signal, the current supply by the current supply transistor 22 is stopped (Ics = 0). In this way, the current supply circuit 20 can turn on and off (execute / stop) the supply of current to the output node No by the current supply transistor 22 operating as a constant current source according to the enable signal EN. That is, the switch 23 and the voltage fixing transistor 24 can constitute an embodiment of the "first on-off control mechanism".

[0037] As a result, according to the power supply circuit according to the first embodiment, since the current consumption during the operation of the load circuit 100 can be supplied by the current supply circuit 20, it is possible to prevent the output current required by the LDO circuit 11 (output transistor 15) from fluctuating rapidly at the start of the operation of the load circuit 100. Therefore, the fluctuation amount of the output voltage Vout can be suppressed and a stable constant voltage can be supplied.

[0038] Further, compared with a configuration (comparative example) in which the current supply circuit 20 is not arranged, the amount of current supplied by the output transistor 15 can be reduced, so the size of the output transistor 15 can be reduced. Also, the fluctuation amount of the output voltage Vout can be suppressed without increasing the operating current of the error amplifier 12 as in Patent Document 1. As a result, it is also possible to improve the stability of the LDO circuit 11 and suppress the power consumption.

[0039] In addition, in a situation where a large current is required to flow instantaneously other than at the start of the operation of the load circuit 100, since stability and current accuracy are not required, the gate-source voltage of the output transistor 15 is increased by the output voltage of the error amplifier 12, and the output transistor 15 is operated in the linear region, thereby enabling correspondence to the current supply to the output node No.

[0040] Embodiment 2. FIG. 4 is a circuit block diagram for explaining a configuration example of the power supply circuit 10b according to Embodiment 2.

[0041] As shown in FIG. 4, the power supply circuit 10b includes an LDO circuit 11 similar to that in FIG. 2, a current supply circuit 25, a voltage monitoring circuit 50, and a control circuit 60. That is, the power supply circuit 10b is different from the power supply circuit 10a (FIG. 2) in that it includes a current supply circuit 25 instead of the current supply circuit 20, and further includes a voltage monitoring circuit 50 and a control circuit 60.

[0042] The voltage monitoring circuit 50 is connected to the output node No and generates a detection signal VR1 for detecting a decrease in the output voltage Vout. The detection signal VR1 indicates whether the output voltage Vout is lower than a determination voltage Vjd set lower than a specified value Vo* of the output voltage Vout. When Vo≧Vjd, it is set to the L level, while when Vo<Vjd, it is set to the H level.

[0043] The control circuit 60 generates a control signal SR for adjusting the current Ics supplied from the current supply circuit 70 based on the detection signal VR1 from the voltage monitoring circuit 50. For example, a 1-bit control signal SR is generated to have the same signal level as the detection signal VR1.

[0044] The current supply circuit 25 receives the control signal SR from the control circuit 60 in addition to the enable signal EN similar to that of the current supply circuit 20. The current supply circuit 25 has a function of a "variable current source" that changes the current Ics supplied to the output node No according to the control signal SR.

[0045] FIG. 5 is a circuit diagram for explaining a configuration example of the current supply circuit 25.

[0046] Referring to FIG. 5, the current supply circuit 25 includes, in addition to the current supply transistor 22, the switch 23, and the voltage fixing transistor 24, which are the same as those in FIG. 3, a gate voltage control circuit 27. In the current supply circuit 25 of FIG. 5, the gate voltage of the current supply transistor 22 transmitted via the switch 23 is variably controlled by the gate voltage control circuit 27.

[0047] The gate voltage control circuit 27 includes a P-type transistor 26 connected between the voltage node Nc and the node Ng, and a variable resistance element Rx connected between the node Ng and the GND node Ns. The transistor 26 is diode-connected, and the voltage of the node Ng (gate voltage Vgc) connected to the gate of the transistor 26 is determined by the voltage drop amount generated in the variable resistance element Rx by the current flowing through the transistor 26. The variable resistance element Rx is configured such that the resistance value Rx changes in a plurality of steps according to the control signal SR. Hereinafter, the resistance value of the variable resistance element Rx is also denoted as Rx.

[0048] The switch 23 is connected between the node Ng and the gate of the current supply transistor 22. The switch 23 and the voltage fixing transistor 24 are turned on and off according to the same enable signal EN as that of the load circuit 100 as in FIG. 3. That is, the switch 23 is turned on during the operation state of the load circuit 100, while it is turned off during the stationary state of the load circuit 100. During the on period of the switch 23, that is, during the operation state of the load circuit 100, the gate voltage Vgc of the node Ng becomes the gate voltage of the current supply transistor 22.

[0049] Each of the current supply transistor 22 and the voltage fixing transistor 24 can be configured by a P-type transistor or an N-type transistor in the same manner as in the first embodiment, and similarly, the transistor 26 can also be configured by a P-type transistor or an N-type transistor. In the example of FIG. 5, the current supply transistor 22, the voltage fixing transistor 24, and the transistor 26 are all configured by P-type transistors.

[0050] During the standby period of the load circuit 100 when the enable signal EN is at the L level, the current supply transistor 22 is turned off, so no current is output (Ics = 0). In contrast, during the operation period of the load circuit 100 when the enable signal EN is at the H level, the current Ics supplied by the current supply circuit 25 changes according to the control signal SR (detection signal VR1).

[0051] Specifically, as an initial setting, the resistance value of the variable resistance element Rx is set to Ra. When the output voltage Vout drops below a certain determination voltage Vjd1 (SR = VR1 = H level), the resistance value of the variable resistance element Rx is decreased from Ra to Rb. As a result, as the gate voltage Vgc of the transistor 26 drops, the gate voltage of the current supply transistor 22, which is connected to the gate of the transistor 26 via the switch 23 (on), also drops. Thereby, the current Ics supplied by the current supply transistor 22 increases.

[0052] For example, the characteristics of the transistor 26 and the resistance value Ra of the variable resistance element Rx (when SR = VR1 = L level) can be designed according to the characteristics of the current supply transistor 22 so that a gate voltage Vgc that results in Ics = Ild1 is generated. In this way, when the detection signal VR1 is at the L level (Vout < Vjd), the current supply circuit 25 can supply a current amount I1 that estimates the load current Ild1 during the operation of the load circuit 100, similar to the current supply circuit 20 (Figure 3).

[0053] On the other hand, when the actual load current Ild1 of the load circuit 100 is greater than I1, causing the output voltage Vout to drop below the determination voltage Vjd, the gate voltage Vgc of the transistor 26 drops in response to the change in the detection signal VR1. Accordingly, the gate voltage of the current supply transistor 22 drops, so the current Ics supplied by the current supply circuit 25 can increase from I1 to I2. Thereby, the output voltage Vout can be restored toward the specified value Vo*.

[0054] Note that the control circuit 60 may generate the control signal SR with multiple bits to change the resistance value of the variable resistor element Rx in three or more steps. In this case, the current Ics can be changed in three or more steps. For example, in response to the detection signal VR1 changing from the L level to the H level, the first bit of the control signal SR is set to the H level to decrease the resistance value of the variable resistor element Rx to Rb. After a certain time has elapsed, if the state where Vo < Vjd (SR1 = H level) continues, the second bit of the control signal SR can be further changed from the L level to the H level. When the second bit changes to the H level, by further decreasing the resistance value of the variable resistor element Rx to Rc (Rx = Rc, Rc < Rb), the current Ics from the current supply circuit 25 can be further increased.

[0055] Also, the voltage monitoring circuit 50 may further generate a detection signal VR2 for further detecting an overrise of the output voltage Vout. For example, when the output voltage Vout rises above the upper limit voltage Vmax (Vmax > Vo*), the detection signal VR2 changes from the L level to the H level.

[0056] When the detection signal VR2 is at the H level (Vo ≥ Vjd), the control circuit 60 can control the gate voltage control circuit 27 so that the gate voltage Vgc rises toward the power supply voltage Vc in order to decrease the current Ics of the current supply transistor 22. For example, the variable resistor element Rx is configured such that the resistance value increases from Ra according to other bits of the control signal SR that are set to the same signal level as the detection signal VR2. In this way, when the output voltage Vout rises above the upper limit voltage Vmax, by decreasing the current Ics from the current supply circuit 25 (preferably, Ics = 0), it is possible to avoid the output voltage Vout rising further.

[0057] As described above, according to the power supply circuit according to Embodiment 2, during the operation of the load circuit 100, by monitoring the output voltage Vout, the current Ics by the current supply circuit 25 can be changed corresponding to the consumption current (load current Ild1) of the load circuit 100. Thereby, since the excess or deficiency of the current Ics with respect to the actual consumption current of the load circuit 100 can be compensated, in addition to the effects in Embodiment 1, the constant voltage supply can be further stabilized by further suppressing the fluctuation of the output voltage Vout.

[0058] In the configuration of FIG. 5, the current supply transistor 22 may be constituted by an N-type transistor. In this case, since the current Ics increases as the gate voltage Vgc is higher, it is necessary to appropriately change the description content above so as to increase the resistance value of the variable resistance element Rx under the condition of increasing the current Ics. Also, as described above, it is also possible to constitute the transistor 26 by an N-type transistor connected in diode configuration.

[0059] Embodiment 3. FIG. 6 is a circuit block diagram for explaining a configuration example of the power supply circuit 10c according to Embodiment 3.

[0060] As shown in FIG. 6, the power supply circuit 10c includes an LDO circuit 11 similar to that in FIG. 2 and a current supply circuit 30. The current supply circuit 30 includes a switch 23, an error amplifier 32, an output transistor 35, and a voltage fixing transistor 36.

[0061] Similar to the error amplifier 12, for the error amplifier 32, the divided voltage Vdv from the voltage dividing circuit 17 is input to the non-inverting input terminal, and the reference voltage Vref is input to the inverting input terminal. An enable signal EN is input to the error amplifier 32. The error amplifier 32 operates in the same manner as the error amplifier 12 during the on period (H level period) of the enable signal EN. On the other hand, during the off period (L level period) of the enable signal EN, the error amplifier 32 stops operating and enters a state (standby state) in which power consumption is significantly reduced.

[0062] The output transistor 35 is composed of P-type transistors in the same manner as the output transistor 15, and is electrically connected between the voltage node Nc and the output node No. The voltage fixing transistor 36 is connected between the voltage node Nc and the gate of the output transistor 35. An enable signal EN is input to the gate of the voltage fixing transistor 36.

[0063] Similar to the output transistor 15 described in the first embodiment, the output transistor 35 can also be composed of N-type transistors. In this case, the voltage fixing transistor 36 can be configured to input the ground voltage Vss to the gate of the output transistor 35 during the off period (L-level period) of the enable signal EN.

[0064] In FIG. 6, the error amplifier 32 corresponds to an embodiment of the "second error amplifier", and the output transistor 35 corresponds to an embodiment of the "first output transistor".

[0065] In FIG. 6, the switch 23 that is turned on and off according to the enable signal EN is connected between the output node of the error amplifier 32 and the gate of the output transistor 35. During the on period of the switch 23, the output voltage of the error amplifier 32 is input to the gate of the output transistor 35.

[0066] Thereby, the current supply circuit 30 can turn on and off (execute / stop) the supply of current to the output node No by the output transistor 35 according to the enable signal EN. That is, an embodiment of the "second on-off control mechanism" can be configured by the switch 23 and the voltage fixing transistor 36.

[0067] Each of the error amplifier 12 of the LDO circuit 11 and the error amplifier 32 of the current supply circuit 30 does not have a mechanism for variably adjusting the operating current online. On the other hand, the operating current Ip2 of the error amplifier 32 is set to be smaller than the operating current Ip1 of the error amplifier 12 (Ip1 > Ip2).

[0068] Thus, in the power supply circuit according to the third embodiment, in response to a rapid current change such as at the start of operation of the load circuit 100 (when the enable signal EN changes from L to H level), the LDO circuit 11 can handle it, and for a current supply that cannot be covered by the LDO circuit 11, it can be handled by the current supply circuit 30 with a low operating speed of the error amplifier 35. As a result, the same effect as in the second embodiment can be achieved without arranging the voltage monitoring circuit 50.

[0069] In addition, in the first to third embodiments, an example in which a single load circuit 100 that operates intermittently in response to the enable signal EN is connected to the output node No has been described, but the number of load circuits 100 is not particularly limited.

[0070] FIG. 7 shows a circuit block diagram for explaining a modification of the connection of the load circuit to the power supply circuit according to the third embodiment.

[0071] In the configuration example of FIG. 7, a plurality of load circuits 100, 101 that become operational or stationary states in response to a common enable signal EN are connected to the output node No, and receive a supply of consumption current from the same power supply circuit 10c as in FIG. 6.

[0072] Even in a configuration where a plurality of load circuits are connected to the output node No, the current supply circuit 30 can operate according to the enable signal EN as in the third embodiment, so the same effect as in the third embodiment can be obtained.

[0073] Similarly, in the configurations of the first and second embodiments (FIGS. 2 and 4), even when a plurality of load circuits that operate in response to a common enable signal are connected to the output node No, the current supply circuits 20 and 25 can operate as described in the first and second embodiments, so the same effect as in the first and second embodiments can be obtained.

[0074] Embodiment 4. In Embodiment 4, a configuration of a power supply circuit for supplying current to a plurality of load circuits that operate according to different enable signals will be described.

[0075] FIG. 8 is a circuit block diagram for explaining a configuration example of the power supply circuit according to Embodiment 4.

[0076] As shown in FIG. 8, the power supply circuit 10d according to Embodiment 4 supplies current to load circuits 100 and 101 that are connected to an output node No and operate according to separate enable signals EN1 and EN2. The specified value of the power supply voltage of the load circuits 100 and 101 is Vo*.

[0077] The load circuit 100 enters an operating state and consumes a load current Ild1 during the H-level period of the enable signal EN1, while entering a stationary state during the L-level period of the enable signal EN1. Similarly, the load circuit 101 enters an operating state and consumes a load current Ild2 during the H-level period of the enable signal EN2, while entering a stationary state during the L-level period of the enable signal EN2.

[0078] The power supply circuit 10d includes an LDO circuit 11 similar to the power supply circuit 10a, a control circuit 65, and a current supply circuit 70. The control circuit 65 generates control signals SRa and SRb for changing the current Ics supplied from the current supply circuit 70 based on the enable signals EN1 and EN2. The current supply circuit 70 has a function of a "variable current source" that changes the current Ics supplied to the output node No according to the enable signals EN1 and EN2.

[0079] FIG. 9 is a circuit diagram for explaining a first configuration example of the current supply circuit 70 (FIG. 8).

[0080] As shown in FIG. 9, the current supply circuit 70 can be configured to include a switch 23, a voltage fixing transistor (P-type) 24, and a P-type transistor 26, which are the same as the current supply circuit 25 shown in FIG. 5, and a gate voltage control circuit 27 including the P-type transistor 26 and the variable resistance element Rx.

[0081] The switch 23 and the voltage-fixing transistor 24 are turned on and off according to the control signal SRa. The control signal SRa is set to the L level by the control circuit 65 when both the enable signals EN1 and EN2 are at the L level. On the other hand, when at least one of the enable signals EN1 and EN2 is at the H level, the control signal SRa is set to the H level.

[0082] Therefore, when both the load circuits 100 and 101 are in the stationary state (EN1 = EN2 = L), the switch 23 is turned off, and the power supply voltage Vc is input to the gate of the current supply transistor 22, so that the current supplied from the current supply circuit 70 becomes zero (Ics = 0).

[0083] On the contrary, when at least one of the load circuits 100 and 101 is in the operating state, the switch 23 is turned on and the voltage-fixing transistor 24 is turned off, so that the current Ics corresponding to the gate voltage Vgc generated by the gate voltage control circuit 27 is supplied to the output node No by the current supply transistor 22.

[0084] The resistance value (Rx) of the variable resistance element Rx changes according to the control signal SRb from the control circuit 65. For example, when the consumption currents of the load circuits 100 and 101 are equal (Ild1 = Ild2), the resistance value Rx can be changed in two steps with the control signal SRb as a 1-bit signal.

[0085] That is, when one of the enable signals EN1 and EN2 is at the H level, the control signal SRb can be set to the L level to make Rx = Ra, while when both the enable signals EN1 and EN2 are at the H level, the control signal SRb can be set to the H level to make Rx = Rz (Rz > Ra). As described in the second embodiment, the smaller the resistance value Rx, the lower the gate voltage Vgc, and thus the larger the current Ics by the current supply transistor 22.

[0086] The characteristics of the transistor 26 and the resistance value Ra (SRb = L level) of the variable resistor element Rx can be designed such that a gate voltage Vgc of about Ics = Ild1 (Ild2) is generated according to the characteristics of the current supply transistor 22. Similarly, the resistance value Rz (SRb = H level) of the variable resistor element Rx can be designed such that a gate voltage Vgc of about Ics = Ild1 + Ild2 is generated.

[0087] Note that when the current consumptions of the load circuits 100 and 101 are not equal, it is preferable to change the resistance value Rx in three steps by using the control signal SRb as a multi-bit signal. In this case, the multi-bit control signal SRb is set to show different values when EN1 = H level and EN2 = L level and when EN2 = H level and EN2 = L level. Then, the resistance value Rx when EN1 = H level and EN2 = L level is designed such that a gate voltage Vgc is generated so that Ics = Ild1 of the current supply transistor 22. On the other hand, the resistance value Rx when EN2 = H level and EN2 = L level is designed such that a gate voltage Vgc is generated so that Ics = Ild2.

[0088] As a result, when EN1 = H level and EN2 = L level, the current Ics from the current supply circuit 70 corresponds to the load current Ild1, and when EN1 = L level and EN2 = H level, the current Ics corresponds to the load current Ild2. Also, when EN1 = EN2 = H level, the resistance value Rx can be designed such that a gate voltage Vgc is generated so that Ics = Ild1 + Ild2.

[0089] As a result, according to the power supply circuit according to the fourth embodiment, in a configuration in which current is supplied to a plurality of load circuits that operate according to individual enable signals, the same effects as those of the first embodiment can be enjoyed.

[0090] FIG. 10 is a circuit diagram for explaining a second configuration example of the current supply circuit 70 (FIG. 8).

[0091] Referring to FIG. 10, the current supply circuit 70 includes current sources 71a and 71b having a function of turning on and off (executing / stopping) the supply of current according to a signal, similar to the current supply circuit 20 of FIG. 3. The current sources 71a and 71b are connected in parallel to the output node No.

[0092] As described above, in the configuration example of FIG. 10, the current sources (71a, 71b) are connected in parallel to the output node No for the number of enable signals (EN1, EN2).

[0093] The current source 71a is turned on and off according to the enable signal EN1. When EN1 = L level, the supply of current is stopped, while when EN1 = H level, the supply of current is executed. The output current of the current source 71a is designed to be equivalent to the estimated value of the load current Ild1 of the load circuit 100.

[0094] Similarly, the current source 71b is turned on and off according to the enable signal EN2. When EN2 = L level, the supply of current is stopped, while when EN2 = H level, the supply of current is executed. The output current of the current source 71b is designed to be equivalent to the estimated value of the load current Ild2 of the load circuit 101.

[0095] As a result, when EN1 = EN2 = L level, the current sources 71a and 71b are turned off, so the current Ics from the current supply circuit 70 becomes 0. When EN1 = H level and EN2 = L level, the current Ics is equivalent to the load current Ild1. When EN1 = L level and EN2 = H level, the current Ics is equivalent to the load current Ild2. Also, when EN1 = EN2 = H level, the current Ics is equivalent to the load current Ild1 + Ild2.

[0096] Therefore, even when using the current supply circuit 70 of the configuration example of FIG. 10, similar to the configuration example of FIG. 9, the current Ics from the current supply circuit 70 can be changed according to the enable signals EN1 and EN2, so the effects according to the above-described Embodiment 4 can be enjoyed similarly.

[0097] In addition, in Embodiment 4 (Figs. 8 to 10), current supply to a plurality of load circuits that operate according to two enable signals was described. However, a configuration for supplying current to a plurality of load circuits that operate according to three or more enable signals can be similarly applied. Specifically, by increasing the number of steps of the resistance value of the variable resistance element Rx in the configuration of Fig. 9, or the number of pairs of current sources and switches connected in parallel in the configuration of Fig. 10 in accordance with the number of enable signals, the effects described in Embodiment 4 can be enjoyed in current supply to a plurality of load circuits that operate according to an arbitrary number of enable signals.

[0098] Embodiment 5. FIG. 11 is a circuit block diagram for explaining a configuration example of the power supply circuit 10e according to Embodiment 5.

[0099] As shown in FIG. 11, the power supply circuit 10e includes an LDO circuit 11 and a current supply circuit 40. The current supply circuit 40 includes k (k: natural number) current supply transistors 42 and an inverter circuit 44 for on / off control of the k current supply transistors 42. The k (k: natural number) current supply transistors 42 are connected between the voltage node Nc and the output node No. When k ≥ 2, the k current supply transistors 42 are connected in parallel between the voltage node Nc and the output node No. The current supply transistor 42 is constituted by a P-type transistor in the example of FIG. 11.

[0100] The inverter circuit 44 inputs the logical inversion signal of the enable signal EN to the gates of the k current supply transistors (P-type) 42. Therefore, the k current supply transistors 42 are turned on during the operation state of the load circuit 100 (EN = H level), while being turned off during the stationary state of the load circuit 100 (EN = L level).

[0101] Note that the current supply transistor 42 may be constituted by an N-type transistor. In this case, a signal having the same logical level as the enable signal EN1 is input to the gate of the current supply transistor 42 (N-type).

[0102] As is well known, the current Ids (drain-source current) supplied by the current supply transistor 42 when it is on depends on the on-resistance Ron shown in Equation (1) when it is on in the linear region. On the other hand, when it is on in the saturation region, the current Ids of the current supply transistor 42 is shown in Equation (2).

[0103] Ron = 1 / (β / (Vgs - Vt)) …(1) Ids = (β / 2)·(Vgs - Vt) 2 …(2) In Equations (1) and (2), Vt is the threshold voltage and Vgs is the gate-source voltage. Also, the gain factor β is represented by the following Equation (3) using the gate width (channel width) W, gate length (channel length) L, average surface mobility μ of carriers, and gate capacitance Cox per unit area of the transistor.

[0104] β = (W / L)·μ·Cox …(3) In the power supply circuit 10e according to Embodiment 5, the current supply transistor 42 constituting the current supply circuit 40 is configured using a transistor in a region 60 manufactured under the same process conditions as the transistor 110 constituting the load circuit 100.

[0105] Since the process conditions are the same, some or all of the parameter values constituting the gain factor β are common between the current supply transistor 42 and the transistor 110. As a result, by appropriately setting the number (k) of the current supply transistors 42 according to the number of transistors 110 that consume current in parallel during the operation of the load circuit 100, the current supply circuit 40 can supply a current Ics balanced with the consumption current (load current Ild1) of the load circuit 100 to the output node No even if it is not configured as a variable current source. As a result, it is possible to enjoy the same effect as in Embodiment 1 with a simple circuit configuration by combining the transistor (current supply transistor 42) and the inverter circuit 44.

[0106] Regarding Embodiment 5 as well, by appropriately modifying the circuit configuration according to the number of load circuits and the number of enable signals, the same effects can be achieved.

[0107] Regarding the plurality of embodiments described above, including combinations not mentioned in the specification, it is also confirmed that within the range where no inconsistency or contradiction occurs, the configurations described in each embodiment can be appropriately combined as planned from the initial stage of the application.

[0108] Also, in this embodiment, it is assumed that a case where another load circuit (load current Ild0) different from the load circuit 100 is constantly supplied to the output node No. However, in a case where the load circuit 100 is activated from a state where the load current Iid = 0, or in a case where only the load circuit 100 (or load circuits 100, 101) is connected to the output node No and no other load circuit is connected, the power supply circuits according to Embodiments 1 to 5 can be applied. Even in these cases, the operating current of the load circuit 100 (or load circuits 100, 101) can be supplied while supplying a stable constant voltage to the output node No by the power supply circuits 10a to 10e that operate according to the enable signals EN (EN1, EN2).

[0109] <Supplementary Note> The above-described embodiments and modified examples include the following technical ideas. [Configuration 1] A power supply circuit (10a to 10e) that supplies a DC voltage to an output node (No) to which a load circuit (100) that becomes an operating state or a stationary state according to the logic level of an enable signal (EN) is connected, a first error amplifier (12) that outputs a voltage obtained by amplifying the voltage difference between the voltage (Vout) of the output node and the specified value (Vo*) of the DC voltage; a first output transistor (15) that supplies a current that changes according to the output voltage of the first error amplifier to the output node; A power supply circuit comprising a current supply circuit (20, 25, 30, 40, 70) that supplies a direct current to the output node during the operating state of the load circuit while stopping the current supply during the stationary state of the load circuit. [Configuration 2] The current supply circuit (20) A constant current source (22) that generates the direct current, A first on-off control mechanism (23, 24) that turns on the supply of the direct current from the constant current source to the output node according to the logic level of the enable signal during the operating state of the load circuit while turning it off during the stationary state of the load circuit, the power supply circuit (10a) according to Configuration 1. [Configuration 3] The current supply circuit (25) is a variable current source in which the direct current changes according to the voltage of the output node, The power supply circuit Further includes a voltage monitoring circuit (50) that monitors the voltage of the output node, The variable current source is configured to increase the direct current when the voltage monitoring circuit detects that the voltage (Vout) of the output node has dropped below a predetermined determination voltage (Vjd) as compared to when the voltage of the output node is higher than the determination voltage, the power supply circuit (10b) according to Configuration 1. [Configuration 4] The current supply circuit (25) is a variable current source in which the direct current changes according to the voltage of the output node, The power supply circuit Further includes a voltage monitoring circuit (50) that monitors the voltage of the output node, The variable current source is configured to decrease the direct current when the voltage monitoring circuit detects that the voltage (Vout) of the output node has risen above a predetermined upper limit voltage (Vmax) as compared to when the voltage of the output node is lower than the upper limit voltage, the power supply circuit (10b) according to Configuration 1 or 3. [Configuration 5] The current supply circuit (30) A second error amplifier (32) that amplifies the voltage difference between the voltage (Vout) of the output node and the specified value (Vo*); A second output transistor (35) that supplies a current that changes according to the output voltage of the second error amplifier to the output node (No); A second on / off control mechanism (23, 36) that turns on the current supply to the output node by the second output transistor according to the logic level of the enable signal during the operation state of the load circuit and turns it off during the stationary state of the load circuit; The power supply circuit (10c) according to Configuration 1, wherein the operating current of the second error amplifier (32) is smaller than the operating current of the first error amplifier (12). [Configuration 6] A plurality of the load circuits (100, 101) that each enter the operation state or the stationary state according to the logic levels of separate plurality of enable signals (EN1, EN2) are connected to the output node (No); The power supply circuit (10d) according to Configuration 1, wherein the current supply circuit (70) is configured to operate as a variable current source in which the direct current changes according to the combination of the logic levels of the plurality of enable signals. [Configuration 7] The current supply circuit includes A plurality of current sources (71a, 71b) that are respectively arranged corresponding to the plurality of enable signals (EN1, EN2) and are connected in parallel to the output node (No); The power supply circuit (10d) according to Configuration 6, wherein each of the plurality of current sources is configured to execute or stop the supply of current according to the logic level of the corresponding enable signal among the plurality of enable signals. [Configuration 8] The current supply circuit (40) includes A current supply transistor (42) that supplies the direct current to the output node when turned on by turning on during the operation state of the load circuit (100) and turning off during the stationary state of the load circuit; The current supply transistor is the power supply circuit (10e) according to Configuration 1, which is manufactured under the same process conditions as the transistor (110) constituting the load circuit.

[0110] The embodiments disclosed this time should be considered to be illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Explanation of Reference Numerals

[0111] 10a to 10e power supply circuits, 11 LDO circuits, 12, 32 error amplifiers, 15, 35 output transistors, 17 voltage dividing circuits, 20, 25, 30, 40, 70 current supply circuits, 22, 42 current supply transistors, 24, 36 voltage fixing transistors, 23 switches, 26 transistors, 27 gate voltage control circuits, 44 inversion circuits, 50 voltage monitoring circuits, 60, 65 control circuits, 71a, 71b current sources, 100, 101 load circuits, 105 smoothing capacitors, 110 transistors (load circuits), EN, EN1, EN2 enable signals, Ild0, Ild1, Ild2 load currents, Ip1, Ip2 operating currents (error amplifiers), No output nodes, Np power supply nodes, Ns GND nodes, R1 to R3 resistance elements, Rx variable resistance elements, SR, SRa, SRb control signals, VR1, VR2 detection signals, Vbias bias voltages, Vc power supply voltages, Vdv divided voltages, Vgc gate voltages, Vjd determination voltages, Vo* specified values (output voltages), Vout output voltages, Vref reference voltages, Vss ground voltages.

Claims

1. A power supply circuit that supplies a DC voltage to an output node to which a load circuit that becomes an operating state or a stationary state according to the logic level of an enable signal is connected, a first error amplifier that outputs a voltage obtained by amplifying the voltage difference between the voltage of the output node and a specified value of the DC voltage; a first output transistor that supplies a current that changes according to the output voltage of the first error amplifier to the output node; and a current supply circuit that supplies a DC current to the output node during the operating state of the load circuit and stops current supply during the stationary state of the load circuit. A power supply circuit.

2. The current supply circuit, a constant current source that generates the DC current, and a first on / off control mechanism that turns on the supply of the DC current from the constant current source to the output node according to the logic level of the enable signal during the operating state of the load circuit and turns off the supply during the stationary state of the load circuit. The power supply circuit according to claim 1.

3. The current supply circuit is a variable current source in which the DC current changes according to the voltage of the output node, The power supply circuit, further includes a voltage monitoring circuit that monitors the voltage of the output node, and the variable current source is configured to increase the DC current when it is detected by the voltage monitoring circuit that the voltage of the output node has dropped below a predetermined determination voltage, as compared with when the voltage of the output node is higher than the determination voltage. The power supply circuit according to claim 1.

4. The current supply circuit is a variable current source in which the DC current changes according to the voltage of the output node, The power supply circuit, further includes a voltage monitoring circuit that monitors the voltage of the output node, and the variable current source is configured to decrease the DC current when it is detected by the voltage monitoring circuit that the voltage of the output node has risen above a predetermined upper limit voltage, as compared with when the voltage of the output node is lower than the upper limit voltage. The power supply circuit according to claim 1.

5. The current supply circuit, a second error amplifier that outputs a voltage obtained by amplifying the voltage difference between the voltage of the output node and the specified value; and a second output transistor that supplies a current that changes according to the output voltage of the second error amplifier to the output node. A second on-off control mechanism that turns on the current supply to the output node by the second output transistor according to the logic level of the enable signal during the operation state of the load circuit and turns off during the standby state of the load circuit is included. The power supply circuit according to claim 1, wherein the operating current of the second error amplifier is smaller than the operating current of the first error amplifier.

6. A plurality of the load circuits that are respectively in the operation state or the standby state according to the logic levels of a plurality of separate enable signals are connected to the output node. The power supply circuit according to claim 1, wherein the current supply circuit is configured to operate as a variable current source in which the DC current changes according to the combination of the logic levels of the plurality of enable signals.

7. The current supply circuit includes a plurality of current sources that are respectively arranged corresponding to the plurality of enable signals and are connected in parallel to the output node. The power supply circuit according to claim 6, wherein each of the plurality of current sources is configured to execute or stop the supply of current according to the logic level of the corresponding enable signal among the plurality of enable signals.

8. The current supply circuit includes a current supply transistor that supplies the DC current to the output node when turned on by turning on during the operation state of the load circuit and turning off during the standby state of the load circuit. The power supply circuit according to claim 1, wherein the current supply transistor is manufactured under the same process conditions as the transistor constituting the load circuit.

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