Arithmetic processing circuit

Abstract

To reduce power consumption of a digital filter.SOLUTION: An arithmetic processing circuit includes: a first core row in which a plurality of arithmetic cores 101 to 104 are arranged in a row; a second core row in which a plurality of arithmetic cores 111 to 114 are arranged in a row; an enable control unit 20 that generates a first enable signal and a second enable signal for controlling a clock signal: a first semiconductor switch 141 that supplies a clock signal to the plurality of arithmetic cores 111 to 114 while the first enable signal is input; and a second semiconductor switch 142 that supplies a clock signal to the plurality of arithmetic cores 111 to 114 while the second enable signal is input.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to an arithmetic processing circuit that operates in synchronization with a clock signal.

Background Art

[0002] In a digital filter, it has been proposed to execute various filter processes by connecting a plurality of arithmetic cores to each other to perform predetermined operation control (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the digital filter described in Patent Document 1, there is a problem that power consumption increases because a clock signal is supplied even to an arithmetic core that is not operating.

[0005] The present invention has been made in view of the above problems, and an object thereof is to provide an arithmetic processing circuit capable of reducing power consumption of a digital filter.

Means for Solving the Problems

[0006] The arithmetic processing circuit according to the first aspect of the present invention includes a first core column in which a plurality of arithmetic cores are arranged in a row, a second core column in which a plurality of arithmetic cores different from the first core column are arranged in a row, an enable control unit that generates a first enable signal and a second enable signal for controlling a clock signal, and a first semiconductor switch for switching whether to supply the clock signal to the plurality of arithmetic cores arranged in the first core column, the first semiconductor switch supplying the clock signal to the plurality of arithmetic cores while the first enable signal is input, and a second semiconductor switch for switching whether to supply the clock signal to the plurality of arithmetic cores arranged in the second core column, the second semiconductor switch supplying the clock signal to the plurality of arithmetic cores while the second enable signal is input.

[0007] The first semiconductor switch may input the logical product of the first enable signal and the clock signal to the plurality of arithmetic cores arranged in the first core column, and the second semiconductor switch may input the logical product of the second enable signal and the clock signal to the plurality of arithmetic cores arranged in the second core column. The arithmetic processing circuit may further include a filter control unit that generates control information for operating the first core column and the second core column as a finite impulse response filter.

Advantages of the Invention

[0008] According to the present invention, there is an effect of reducing the power consumption of the digital filter.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Modes for Carrying Out the Invention

[0010] Figures 1 and 2 show the configuration of the arithmetic processing circuit 100 of the present embodiment. Figure 1 shows an overview of the arithmetic processing circuit 100. The arithmetic processing circuit 100 is constituted by, for example, a processor and digital circuits. The arithmetic processing circuit 100 operates as a digital filter such as a Finite Impulse Response (FIR) filter. The arithmetic processing circuit 100 includes a filter bank 10, an enable control unit 20, and a filter control unit 30.

[0011] The filter bank 10 includes a plurality of arithmetic cores arranged in series or in parallel. The arithmetic core includes an adder, a multiplier, or a delay element. The arithmetic core has, for example, a function of performing a multiply-accumulate operation or a function of delaying a signal. Hereinafter, a plurality of arithmetic cores arranged in a row are also referred to as a core row. The filter bank 10 includes a plurality of core rows. A clock signal is supplied to the filter bank 10, and the plurality of arithmetic cores operate in synchronization with this clock signal. In the arithmetic processing circuit 100, when operating as an FIR filter, a clock signal is not supplied to the arithmetic cores that are not in use in the filter bank 10, so that power consumption can be reduced.

[0012] Figure 2 shows a detailed configuration of the filter bank 10. The filter bank 10 includes a first core row in which a plurality of arithmetic cores 101 to 104 and the like are arranged in a row, a second core row in which a plurality of arithmetic cores 111 to 114 and the like different from the first core row are arranged in a row, a third core row in which a plurality of arithmetic cores 121 to 124 and the like are arranged in a row, a fourth core row in which a plurality of arithmetic cores 131 to 134 and the like are arranged in a row, and semiconductor switches 141 to 144. In Figure 2, some of the arithmetic cores are omitted. The filter bank 10 is not limited to the example including the first to fourth core rows, and may include any number of core rows of two or more.

[0013] In FIG. 2, the numbers in the circuit blocks of the arithmetic cores indicate the addresses of the arithmetic cores. For example, in the address (3, 2) in the circuit block of arithmetic core 113, the right number "2" indicates that arithmetic core 113 belongs to the second core column, and the left number "3" indicates that arithmetic core 113 is arranged third in the order closest to the second semiconductor switch 142 in the second core column.

[0014] The semiconductor switches 141 to 144 switch whether to supply a clock signal to the corresponding core column. The first semiconductor switch 141 switches whether to supply a clock signal to the arithmetic cores 101 to 104 arranged in the first core column. The first semiconductor switch 141 supplies a clock signal to the plurality of arithmetic cores 101 to 104 while the first enable signal is input from the enable control unit 20. The first semiconductor switch 141 does not supply a clock signal to any of the plurality of arithmetic cores 101 to 104 when the first enable signal is not input from the enable control unit 20.

[0015] The second semiconductor switch 142 switches whether to supply a clock signal to the arithmetic cores 111 to 114 arranged in the second core column. The second semiconductor switch 142 supplies a clock signal to the plurality of arithmetic cores 111 to 114 while the second enable signal is input from the enable control unit 20. The second semiconductor switch 142 does not supply a clock signal to any of the plurality of arithmetic cores 111 to 114 when the second enable signal is not input from the enable control unit 20. The third semiconductor switch 143 switches whether to supply a clock signal to the arithmetic cores 121 to 124 arranged in the third core column, similar to the first semiconductor switch 141 and the second semiconductor switch 142. The fourth semiconductor switch 144 switches whether to supply a clock signal to the arithmetic cores 131 to 134 arranged in the fourth core column, similar to the first semiconductor switch 141 and the second semiconductor switch 142.

[0016] In the example of FIG. 2, the semiconductor switches 141 to 144 are AND circuits. The first semiconductor switch 141 inputs the logical product of the first enable signal and the clock signal to the plurality of arithmetic cores 101 to 104 arranged in the first core column. For example, when a high-level first enable signal is input and the clock signal is at a high level, the first semiconductor switch 141 inputs a high-level signal, which is the logical product of the first enable signal and the clock signal, to the plurality of arithmetic cores 101 to 104. When a high-level first enable signal is input and the clock signal is at a low level, the first semiconductor switch 141 inputs a low-level signal, which is the logical product of the first enable signal and the clock signal, to the plurality of arithmetic cores 101 to 104. On the other hand, when a high-level first enable signal is not input, that is, when the first enable signal is at a low level, the first semiconductor switch 141 inputs a low-level signal, which is the logical product of the first enable signal and the clock signal, to the plurality of arithmetic cores 101 to 104 regardless of whether the clock signal is at a high level or a low level. The second semiconductor switch 142 inputs the logical product of the second enable signal and the clock signal to the plurality of arithmetic cores 111 to 114 arranged in the second core column, in the same manner as the first semiconductor switch 141. Since the third semiconductor switch 143 and the fourth semiconductor switch 144 are the same as the first semiconductor switch 141 and the second semiconductor switch 142, the description thereof is omitted.

[0017] The enable control unit 20 generates a first enable signal for controlling the clock signal supplied to the first core column. The enable control unit 20 generates a second enable signal for controlling the clock signal supplied to the second core column. The enable control unit 20 generates a third enable signal and a fourth enable signal for controlling the clock signals supplied to the third core column and the fourth core column, respectively.

[0018]

[0019] ​More specifically, the enable control unit 20 respectively acquires information indicating the addresses of a plurality of arithmetic cores used to operate as a FIR filter from the filter control unit 30. Based on the acquired information indicating the addresses of the arithmetic cores, the enable control unit 20 inputs an enable signal to a semiconductor switch corresponding to a core column including the arithmetic cores used to operate as a FIR filter. The enable control unit 20 does not input an enable signal to a semiconductor switch corresponding to a core column that does not include the arithmetic cores used to operate as a FIR filter.

[0020] As an example, assume that in order to operate as a FIR filter, the arithmetic core 101 at address (1, 1), the arithmetic core 102 at address (2, 1), the arithmetic core 111 at address (1, 2), the arithmetic core 112 at address (2, 2), the arithmetic core 121 at address (1, 3), and the arithmetic core 122 at address (2, 3) are used. At this time, the enable control unit 20 inputs a first enable signal to a first semiconductor switch 141 corresponding to a first core column including the arithmetic core 101 at address (1, 1) and the arithmetic core 102 at address (2, 1) used to operate as a FIR filter.

[0021] The enable control unit 20 inputs a second enable signal to a second semiconductor switch 142 corresponding to a second core column including the arithmetic core 111 at address (1, 2) and the arithmetic core 112 at address (2, 2) used to operate as a FIR filter. The enable control unit 20 inputs a third enable signal to a third semiconductor switch 143 corresponding to a third core column including the arithmetic core 121 at address (1, 3) and the arithmetic core 122 at address (2, 3) used to operate as a FIR filter. On the other hand, since the enable control unit 20 does not use any of the arithmetic cores 131 to 134 arranged in the fourth core column for operating as a FIR filter, the enable control unit 20 does not input an enable signal to a fourth semiconductor switch 144 corresponding to the fourth core column.

[0022] The filter control unit 30 in FIG. 1 generates control information for operating a plurality of core columns, such as a first core column and a second core column, as FIR filters. This control information includes information such as the tap length and the number of stages of the FIR filter. The filter control unit 30 specifies the addresses of a plurality of arithmetic cores used in this FIR filter respectively. The filter control unit 30 outputs the generated control information to the filter group 10. The filter control unit 30 outputs information indicating the addresses of the specified arithmetic cores to the enable control unit 20.

[0023] [Effect of the arithmetic processing circuit 100 of the present embodiment] According to the arithmetic processing circuit 100 of the present embodiment, when operating as an FIR filter, the enable control unit 20 does not supply a clock signal to arithmetic cores that are not used among the plurality of arithmetic cores in the filter group 10. For this reason, the arithmetic processing circuit 100 can reduce power consumption.

[0024] As described above, the present invention has been described using embodiments. However, the technical scope of the present invention is not limited to the scope described in the above embodiments, and various modifications and changes are possible within the scope of the gist. For example, all or part of the device can be configured by functionally or physically dispersing and integrating it in any unit. Also, new embodiments resulting from any combination of a plurality of embodiments are included in the embodiments of the present invention. The effects of the new embodiments resulting from the combination have the effects of the original embodiments combined.

[0025] For example, in the above description, an AND circuit is exemplified as an element that performs a logical product operation, but the element that performs a logical product operation may be another circuit such as an OR circuit.

Explanation of reference numerals

[0026] 10 Filter group 20 Enable control unit 30 Filter control unit 100 Arithmetic processing circuit 101 Arithmetic core 102 Arithmetic core 103 Arithmetic core 104 arithmetic cores 111 arithmetic cores 112 arithmetic cores 113 arithmetic cores 114 arithmetic cores 121 arithmetic cores 122 arithmetic cores 123 arithmetic cores 124 arithmetic cores 131 arithmetic cores 132 arithmetic cores 133 arithmetic cores 134 arithmetic cores 141 First semiconductor switch 142 Second semiconductor switch 143 Third semiconductor switch 144 Fourth semiconductor switch

Claims

1. a first core column in which a plurality of arithmetic cores are arranged in a row; a second core column in which a plurality of arithmetic cores different from the first core column are arranged in a row; an enable control unit that generates a first enable signal and a second enable signal for controlling a clock signal; a first semiconductor switch for switching whether to supply the clock signal to the plurality of arithmetic cores arranged in the first core column, the first semiconductor switch supplying the clock signal to the plurality of arithmetic cores while the first enable signal is input; a second semiconductor switch for switching whether to supply the clock signal to the plurality of arithmetic cores arranged in the second core column, the second semiconductor switch supplying the clock signal to the plurality of arithmetic cores while the second enable signal is input; An arithmetic processing circuit comprising:

2. The first semiconductor switch inputs a logical product of the first enable signal and the clock signal to the plurality of arithmetic cores arranged in the first core column; The second semiconductor switch inputs a logical product of the second enable signal and the clock signal to the plurality of arithmetic cores arranged in the second core column; The arithmetic processing circuit according to claim 1.

3. Further comprising a filter control unit that generates control information for operating the first core column and the second core column as finite impulse response filters; The arithmetic processing circuit according to claim 1 or 2.

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