Semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a semiconductor device in which decrease in reliability can be suppressed.SOLUTION: A semiconductor device including a first semiconductor element and a second semiconductor element is formed on a substrate. The first semiconductor element includes a first multilayer body in which a Si layer and a SiGe layer are stacked, a first source-drain region formed at a side surface of the first multilayer body in a gate length direction, a first gate electrode formed over the first multilayer body and at a side surface thereof in a gate width direction through a first gate insulating film, and an insulating film region formed between the SiGe layer and the first source-drain region.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] In a semiconductor device having a nanosheet FET (Field Effect Transistor), an input / output Tr. (Transistor) for an input / output device is required in the vicinity of a logic device using the nanosheet FET. The input / output Tr. needs to operate at a voltage higher than that of the nanosheet FETs constituting the logic device. For this reason, when attempting to form the input / output Tr. with nanosheet FETs, it is necessary to make the gate insulating film thicker than conventional ones. However, with conventional methods for manufacturing nanosheet FETs, it is difficult to form a gate insulating film with a sufficient thickness to withstand high voltages.

[0003] As a method for manufacturing a thick gate insulating film compatible with the method for manufacturing a nanosheet FET, a semiconductor device has been proposed in which an element capable of withstanding high-voltage operation by a special fin FET (FinFET) structure is formed on the same wafer as the nanosheet FET (see Patent Document 1). This semiconductor device has an EG-FET (Extended Gate Field Effect Transistor) serving as the input / output Tr. composed of a FinFET in which a stacked structure of Si and SiGe is processed. And an SG-FET (Suspended Gate Field Effect Transistor) for a logic device is formed of a normal nanosheet FET (NS-FET). Since the input / output Tr. has a FinFET shape in this structure, a thick gate insulating film can be applied independently of the gate insulating film of the logic device. As a result, this semiconductor device can ensure the required current characteristics even when the gate voltage is high.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

SUMMARY OF THE INVENTION

PROBLEMS TO BE SOLVED BY THE INVENTION

[0005] However, in the semiconductor device having the configuration described in Patent Document 1 above, both Si and SiGe laminated under the gate electrode are in contact with the source region and the drain region. In this structure, when a gate voltage (Vg) is applied to the pFET, first, the FET in the SiGe layer region with a smaller bandgap is turned on, and an inversion layer is formed in the SiGe layer with a smaller |Vth|. Therefore, when the gate voltage (Vg) further increases and the FET in the Si layer region is turned on, in the Id-Vg characteristics, a characteristic bend (hump) deviating from a smooth curve occurs. When having such Id-Vg characteristics, the reliability of the semiconductor device may decrease.

[0006] In order to solve the above-described problems, the present invention provides a semiconductor device and a method of manufacturing a semiconductor device capable of suppressing a decrease in reliability.

MEANS FOR SOLVING THE PROBLEMS

[0007] The semiconductor device of the present invention includes a first semiconductor element and a second semiconductor element on a substrate. The first semiconductor element includes a first laminate in which a Si layer and a SiGe layer are laminated, a first source / drain region formed on a side surface in the gate length direction of the first laminate, a first gate electrode formed above the first laminate and on a side surface in the gate width direction via a first gate insulating film, and an insulating film region formed between the SiGe layer and the first source / drain region. And the second semiconductor element includes a second laminate in which a Si layer and a second gate electrode are laminated, and a second source / drain region formed on a side surface in the gate length direction of the second laminate. Further, the second gate electrode is formed via a second gate insulating film between the Si layers and above the second laminate.

[0008] Further, the semiconductor device of the present invention has a structure in which a first semiconductor device including a first semiconductor element and a second semiconductor element is stacked on a first substrate, and a second semiconductor device including a third semiconductor element and a fourth semiconductor element is stacked on a second substrate. The first semiconductor element and the third semiconductor element include a first stacked body in which an Si layer and an SiGe layer are stacked, a first source / drain region formed on a side surface in the gate length direction of the first stacked body, a first gate electrode formed above the first stacked body and on a side surface in the gate width direction via a first gate insulating film, and an insulating film region formed between the SiGe layer and the first source / drain region. The second semiconductor element and the fourth semiconductor element include a second stacked body in which an Si layer and a second gate electrode are stacked via a gate insulating film, and a second source / drain region formed on a side surface in the gate length direction of the second stacked body. The second gate electrode is formed via a second gate insulating film between the Si layers and above the second stacked body.

[0009] Also, a method for manufacturing the semiconductor device of the present invention includes a step of forming an Si / SiGe stacked body formed by stacking an Si layer and an SiGe layer, a step of etching the Si / SiGe stacked body to form a first stacked body and a second stacked body, a step of selectively etching the SiGe layer exposed on the side surfaces in the gate length direction of the first stacked body and the second stacked body to form a recess in the side surface of the SiGe layer with respect to the side surface of the Si layer, a step of forming an insulating film region in the recess, a step of forming a first source / drain region on the side surface in the gate length direction of the first stacked body and a second source / drain region on the side surface in the gate length direction of the second stacked body, a step of forming a first gate insulating film and a first gate electrode above the first stacked body and on the side surface in the gate width direction, a step of selectively removing the SiGe layer from the second stacked body, and a step of forming a second gate insulating film and a second gate electrode between the Si layers of the second stacked body and above the second stacked body.

Effect of the Invention

[0010] According to the present invention, it is possible to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in reliability.

Brief Description of the Drawings

[0011]

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Embodiments for Carrying Out the Invention

[0012] Hereinafter, examples of embodiments for carrying out the present invention will be described, but the present invention is not limited to the following examples. Note that the description will be made in the following order. 1. Outline of the Conventional Semiconductor Device 2. First Embodiment of the Semiconductor Device 3. Manufacturing Method of the Semiconductor Device 4. Other Embodiments of the Semiconductor Device

[0013] 〈1. Outline of the Conventional Semiconductor Device〉 [Configuration of the Conventional Semiconductor Device] As a conventional semiconductor device, mainly the configuration and problems of the semiconductor device described in Patent Document 1 mentioned above will be explained. FIG. 1 shows the configuration of the conventional semiconductor device. Note that FIG. 1 shows only a cross-sectional view in the gate length direction of the semiconductor device.

[0014] The semiconductor device shown in FIG. 1 includes an EG-FET (Extended Gate Field Effect Transistor) serving as an input / output device and an SG-FET (Suspended Gate Field Effect Transistor) for logic devices on a substrate 305. The EG-FET and the SG-FET are formed adjacent to each other on the substrate 305 via a STI (Shallow Trench Isolation) 310. The EG-FET serving as the input / output device is composed of a FinFET in which a stacked structure of Si and SiGe is processed. The SG-FET (Suspended Gate Field Effect Transistor) for logic devices is formed of a normal nanosheet FET (NS-FET).

[0015] The EG-FET serving as the input / output device includes a nanosheet stack for an EG pillar in which Si and SiGe nanosheets are stacked, source / drain regions 390a and 390c formed on both sides of the nanosheet stack, an EG gate insulating film 325a formed on the nanosheet stack, an EG gate electrode 335a formed on the EG gate insulating film 325a, and sidewall spacers 330c and 330e formed on the EG gate insulating film 325a and around the EG gate electrode 335a. In addition, each nanosheet layer constituting the nanosheet stack and the source / drain regions 390a and 390c are formed on a first dielectric layer 330a. The nanosheet laminate for the EG pillar includes a first barrier layer 340a, a first semiconductor layer 350a, a third barrier layer 340c, a third semiconductor layer 360a, a fifth barrier layer 340e, a fifth semiconductor layer 350c, a seventh barrier layer 340g, a seventh semiconductor layer 360c, a ninth barrier layer 340i, a ninth semiconductor layer 350e, an eleventh barrier layer 340k, and an eleventh semiconductor layer 360e laminated thereon. Here, in the nanosheet layer, the third semiconductor layer 360a, the seventh semiconductor layer 360c, and the eleventh semiconductor layer 360e are formed of an Si nanosheet layer. Also, the first semiconductor layer 350a, the fifth semiconductor layer 350c, and the ninth semiconductor layer 350e are formed of an SiGe nanosheet layer. And these semiconductor layers are laminated via the third barrier layer 340c, the fifth barrier layer 340e, the seventh barrier layer 340g, the ninth barrier layer 340i, and the eleventh barrier layer 340k.

[0016] The SG-FET serving as a logic device includes an SG pillar in which an Si nanosheet layer and a metal electrode are laminated, source / drain regions 390b and 390d formed on both sides of the nanosheet layer, an SG gate insulating film 325b formed on the SG pillar, an SG gate electrode 335b formed on the SG gate insulating film 325b, and sidewall spacers 330d and 330f formed around the SG gate insulating film 325b and the SG gate electrode 335b thereon. Also, each nanosheet layer, metal electrode, and source / drain regions 390b and 390d constituting the SG pillar are formed on a second dielectric layer 330b. The SG pillar includes a first metal electrode 335e, a second semiconductor layer 360b, a second metal electrode 335d, a fourth semiconductor layer 360d, a third metal electrode 335c, and a sixth semiconductor layer 360f laminated thereon. Further, the first metal electrode 335e is surrounded by the inner spacers 315a, 315b and the IL (Interfacial Layer) layers 325g, 325h. The second metal electrode 335d is surrounded by the inner spacers 315c, 315d and the IL layers 325e, 325f. The third metal electrode 335c is surrounded by the inner spacers 315e, 315f and the IL layers 325c, 325d.

[0017] [Equivalent Circuit Diagram of Conventional Input / Output Device] In the semiconductor device having the above configuration, the EG-FET serving as an input / output device has an eleventh semiconductor layer 360e made of a Si nanosheet layer formed directly under the EG gate electrode 335a and a ninth semiconductor layer 350e made of a SiGe nanosheet layer, both of which are in contact with the source / drain regions 390a, 390c. Therefore, the equivalent circuits of the EG gate electrode 335a, the eleventh semiconductor layer 360e, the ninth semiconductor layer 350e, and the source / drain regions 390a, 390c in the EG-FET can be shown as in FIG. 2.

[0018] In FIG. 2, Tr_1 is the eleventh semiconductor layer 360e made of a Si nanosheet layer, and Tr_2 is the ninth semiconductor layer 350e made of a SiGe nanosheet layer. Also, the source / drain regions 390a, 390c of Tr_1 are R1_s and R1_d, and the source / drain regions 390a, 390c of Tr_2 are R2_s and R2_d. Also, let the gate threshold voltage (Vth) of the eleventh semiconductor layer 360e (Tr_1) made of a Si nanosheet layer be |Vth_1|, and the gate threshold voltage (Vth) of the ninth semiconductor layer 350e (Tr_2) made of a SiGe nanosheet layer be |Vth_2|.

[0019] When the EG-FET is a p-channel FET (pFET), assuming the same gate insulating film thickness, it is known that [|Vth_2| < |Vth_1|] due to the difference in the band gaps between Si and SiGe. Therefore, in the equivalent circuit of the EG-FET shown in FIG. 2, Tr_1 and Tr_2 with different gate threshold voltages (Vth) are connected in parallel.

[0020] [Id-Vg Characteristics of Conventional Semiconductor Devices] The Id-Vg characteristics when the EG-FET is a pFET are shown in FIG. 3. In the Id-Vg characteristics shown in FIG. 3, when a gate voltage (Vg) is applied and the gate voltage exceeds |Vth_2|, the FET of Tr_2 composed of the SiGe layer region with a low gate threshold voltage turns on, and current flows only through Tr_2. And this state continues in the region where [|Vth_2| < Vg < |Vth_1|]. Then, when the gate voltage exceeds |Vth_1|, the FET of Tr_1 composed of the Si layer region with a high gate threshold voltage turns on, and current also flows through Tr_1. Therefore, the pFET type EG-FET shows Id-Vg characteristics only by Tr_2 when the gate voltage is less than |Vth_1|, but shows Id-Vg characteristics by the sum of Tr_1 and Tr_2 when the gate voltage exceeds |Vth_1|. For this reason, a sharp change occurs in the Id-Vg characteristics at the boundary of |Vth_1|, and a characteristic bend (hump) occurs in the curve of the Id-Vg characteristics. If such a characteristic hump occurs in the Id-Vg characteristics, there may be problems in a circuit that performs a specific operation, and the reliability of the semiconductor device may decrease.

[0021] When the EG-FET is an n-channel FET (nFET), it is known that |Vth_1| of Tr_1 and |Vth_2| of Tr_2 are almost the same. Therefore, in the equivalent circuit of the EG-FET shown in FIG. 2, Tr_1 and Tr_2 with almost the same gate threshold voltage (Vth) are connected in parallel. The Id-Vg characteristics when the EG-FET is an nFET are shown in FIG. 4. In the Id-Vg characteristics shown in FIG. 4, in the region where [|Vth_2|~|Vth_1|<Vg], in both Tr_1 and Tr_2, the channel of the FET is in the off state. Therefore, in this region, no on-current flows through the entire EG-FET. On the other hand, when it enters the region of [|Vth_2|~|Vth_1|≦Vg], in both the channel of the SiGe layer of Tr_2 and the channel of the Si layer of Tr_1, the nFETs are inverted almost simultaneously. Therefore, when the EG-FET is an nFET, no hump occurs.

[0022] 〈2. First Embodiment of Semiconductor Device〉 Hereinafter, a specific embodiment of the semiconductor device of the present invention will be described. FIGS. 5, 6, and 7 show schematic configuration diagrams of the semiconductor device of the first embodiment. [Configuration of Semiconductor Device] FIG. 5 is a plan view (top view) of the semiconductor device. FIG. 6 is a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5. Further, FIG. 7 is a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 5.

[0023] The semiconductor device 10 shown in FIG. 5 includes a first semiconductor element 100 and a second semiconductor element 200 on a substrate 11. The first semiconductor element 100 is an input / output Tr. serving as an input / output device. The first semiconductor element 100 serving as an input / output device is composed of a FinFET in which a stacked structure of Si and SiGe is processed. The second semiconductor element 200 is a nanosheet FET serving as a logic device.

[0024] As shown in FIG. 5, the first semiconductor element 100 includes a gate electrode 112 (first gate electrode) formed on the substrate 11, a source region 108, and a drain region 109 (first source / drain region). The second semiconductor element 200 includes a gate electrode 212 (second gate electrode) formed on the substrate 11, a source region 208, and a drain region 209 (second source / drain region).

[0025] Also, as shown in FIG. 5, the gate length of the first semiconductor element 100 is larger than that of the second semiconductor element 200. Since the first semiconductor element 100 is an input / output Tr for an input / output device, the voltage applied to the gate electrode 112 is higher than that of the second semiconductor element 200. For this reason, in order to suppress the through-current between the source region 108 and the drain region 109, so-called punch-through, it is preferable that the first semiconductor element 100 has a larger gate length than the second semiconductor element 200. On the other hand, for the second semiconductor element 200 serving as a logic device, it is preferable to form a shorter gate length in order to improve the switching speed.

[0026] Also, as shown in FIGS. 6 and 7, the first semiconductor element 100 is composed of a FinFET including a first laminate in which Si layers 101, 102, 103, 104 and SiGe layers 105, 106, 107 are laminated. The second semiconductor element 200 is composed of a GAA (Gate All Around) FET including a second laminate in which Si layers 201, 202, 203, 204 and gate electrodes 205, 206, 207 are laminated. The Si layers 101, 102, 103, 104 of the first semiconductor element 100 and the Si layers 201, 202, 203, 204 of the second semiconductor element 200 are both composed of nanosheet layers. The first semiconductor element 100 and the second semiconductor element 200 are entirely sealed by an insulating layer 18 on the substrate 11.

[0027] The first semiconductor element 100 has the bottom Si layer 101 on a PTS (punch through stopper) layer 13 formed on the uppermost layer of the substrate 11. The first semiconductor element 100 has a first laminate having a laminated structure of [Si layer 101 / SiGe layer 105 / Si layer 102 / SiGe layer 106 / Si layer 103 / SiGe layer 107 / Si layer 104] including the Si layer 101.

[0028] In the cross-sectional view in the gate length direction shown in FIG. 6, the first semiconductor element 100 includes a source region 108 and a drain region 109 on the side surface of a first stacked body of Si layers 101, 102, 103, 104 and SiGe layers 105, 106, 107. The Si layers 101, 102, 103, 104 are connected to the source region 108 and the drain region 109. An inner spacer 110 (first inner spacer) made of an insulating film region is formed between the SiGe layers 105, 106, 107 and the source region 108 and the drain region 109. Therefore, the side surfaces of the SiGe layers 105, 106, 107 are recessed toward the center of the first semiconductor element 100 by the amount of the inner spacer 110 with respect to the Si layers 101, 102, 103, 104. And the side surfaces of the SiGe layers 105, 106, 107 are not directly connected to the source region 108 and the drain region 109. Note that the first semiconductor element 100 shown in FIG. 6 shows a configuration in which an inner spacer 110 is formed between both the SiGe layers 105, 106, 107 and the source region 108 and the drain region 109. However, in the first semiconductor element 100, it is sufficient that the inner spacer 110 is formed between either one of the SiGe layers 105, 106, 107 and the source region 108 or the drain region 109. If the inner spacer 110 is formed in at least either one of them, direct carrier movement between the SiGe layers 105, 106, 107, the source region 108, and the drain region 109 can be suppressed. For this reason, even when a gate voltage is applied to the first semiconductor element 100 and a channel is formed in the SiGe layers 105, 106, 107, carrier movement between the source region 108 and the drain region 109 can be suppressed.

[0029] Also, in the cross-sectional view in the gate length direction shown in FIG. 6, the first semiconductor element 100 includes a gate insulating film 111 (first gate insulating film) and an insulating film 117 thinner than the gate insulating film 111 above the uppermost Si layer 104. The gate insulating film 111 is formed at the central portion of the Si layer 104, and the insulating film 117 is formed around the gate insulating film 111. Further, the gate insulating film 111 is formed to have a greater thickness than the insulating film 117 and the gate insulating film 211 (second gate insulating film) of the second semiconductor element 200 described later. Thereby, in the first semiconductor element 100 which is the input / output Tr. of the input / output device, a sufficient thickness of the gate insulating film 111 can be ensured to withstand a high voltage.

[0030] A gate electrode 112 is formed on the gate insulating film 111. A sidewall 116 of the gate electrode 112 is formed on the insulating film 117. The gate electrode 112 is formed from a high-k (high dielectric constant) material layer 113, a first metal layer 114, and a second metal layer 115. The gate electrode 112 has its bottom surface and side surfaces, that is, the contact surfaces with the gate insulating film 111 and the sidewall 116 covered by the thin film high-k material layer 113. Then, the first metal layer 114 is filled inside the high-k material layer 113, and further, the second metal layer 115 is filled in the upper central portion of the first metal layer 114. An insulating layer 12 is formed on the side surfaces of the sidewall 116, and the side surfaces of the source region 108 and the drain region 109. The insulating layer 12 covers the side surfaces of the first semiconductor element 100, the side surfaces of the second semiconductor element 200, and the upper surface of the substrate 11.

[0031] In the cross-sectional view in the gate length direction shown in FIG. 6, the second semiconductor element 200 has a bottommost Si layer 201 on a PTS layer 13 formed on the uppermost layer of the substrate 11. And the second semiconductor element 200 has a second laminate composed of a laminate structure of [Si layer 201 / gate electrode 205 / Si layer 202 / gate electrode 206 / Si layer 203 / gate electrode 207 / Si layer 204] including the Si layer 201.

[0032] Also, in the cross-sectional view in the gate length direction shown in FIG. 6, the second semiconductor element 200 includes a gate insulating film 211 and an insulating film 217 above the uppermost Si layer 204. The gate insulating film 211 is formed at the central portion of the Si layer 204, and the insulating film 217 is formed around the gate insulating film 211. The gate insulating film 211 is formed thinner than the gate insulating film 111 of the first semiconductor element 100. A gate electrode 212 is formed on the gate insulating film 211. A sidewall 216 of the gate electrode 212 is formed on the insulating film 217. The gate electrode 212 is formed of a high-k dielectric material layer 213, a first metal layer 214, and a second metal layer 215. The gate electrode 212 includes a thin high-k dielectric material layer 213 that covers the bottom surface and the side surface, that is, the contact surfaces with the gate insulating film 211 and the sidewall 216. The first metal layer 214 is filled in the high-k dielectric material layer 213, and the second metal layer 215 is filled in the upper central portion of the first metal layer 214.

[0033] A gate insulating film 211 is formed between the gate electrodes 205, 206, 207 and the Si layers 201, 202, 203, 204. The gate insulating film 211 is formed only between the gate electrodes 205, 206, 207 and the Si layers 201, 202, 203, 204. The second semiconductor element 200 includes a source region 208 and a drain region 209 on the side surface of the second laminate of the Si layers 201, 202, 203, 204 and the gate electrodes 205, 206, 207. The Si layers 201, 202, 203, 204 are connected to the source region 208 and the drain region 209. An inner spacer 210 (second inner spacer) made of an insulating film region is formed between the gate electrodes 205, 206, 207 and the source region 208 and the drain region 209. For this reason, the gate electrodes 205, 206, 207 and the source region 208 and the drain region 209 are not directly connected. Also, an inner spacer 210 made of an insulating film region is formed between the gate insulating film 211 and the source region 208 and the drain region 209.

[0034] Also, the gate electrodes 205, 206, 207 formed between the Si layers 201, 202, 203, 204 are formed of a high-k dielectric material layer 213 and a first metal layer 214. The gate electrodes 205, 206, 207 include a thin-film high-k dielectric material layer 213 that covers the contact surfaces with the gate insulating film 211 and the inner spacers 210. And the first metal layer 214 is filled inside the high-k dielectric material layer 213. The first metal layer 214 is continuously formed with the gate electrodes 205, 206, 207 and the gate electrode 212 (see FIG. 7). Therefore, in the cross-sectional view in the gate length direction shown in FIG. 6, the Si layers 202, 203, 204 except for the lowermost Si layer 201 are covered by the surrounding gate electrodes 205, 206, 207 and the gate electrode 212. And the gate electrodes 205, 206, 207 and the gate electrode 212 are formed via the gate insulating film 211 between the layers of the Si layers 201, 202, 203, 204 and above the second laminate. That is, in the second semiconductor element 200, the entire cross-section in the gate length direction of the Si layers 202, 203, 204 that serve as the channel portion is surrounded by the gate electrodes 205, 206, 207, 212. An insulating layer 12 is formed on the side surfaces of the sidewalls 216, and the side surfaces of the source region 208 and the drain region 209. The insulating layer 12 is continuously formed via the upper surface of the substrate 11 from the side surface of the first semiconductor element 100 to the side surface of the second semiconductor element 200.

[0035] In the cross-sectional view in the gate width direction shown in FIG. 7, STI (Shallow Trench Isolation) 14 is formed as an element isolation region on the surface of the substrate 11. The STI 14 is composed of an insulating film 15 embedded in the substrate 11, an insulating film 16 formed on the insulating film 15, and an insulating layer 17 embedded on the insulating film 16. The STI 14 is formed between the first semiconductor element 100 and the second semiconductor element 200. Further, the STI 14 is formed outside the regions where the first laminate of the Si layers 101, 102, 103, 104 and the SiGe layers 105, 106, 107 of the first semiconductor element 100, and the Si layers 201, 202, 203, 204 of the second semiconductor element 200 are formed.

[0036] In the cross-sectional view in the gate width direction shown in FIG. 7, the first semiconductor element 100 has a gate insulating film 111 that covers the side surfaces and the upper surface of the laminated structure of the Si layers 101, 102, 103, 104 and the SiGe layers 105, 106, 107. In the cross-sectional view in the gate width direction, the side surfaces of the Si layers 101, 102, 103, 104 and the SiGe layers 105, 106, 107 are formed as the same surface without a step between the layers. Also, in the cross-sectional view in the gate width direction, the first semiconductor element 100 has a gate electrode 112 that covers the side surface and the upper surface of the gate insulating film 111. The gate electrode 112 has a thin-film high-k dielectric material layer 113 that covers the contact surfaces with the gate insulating film 111, the STI 14, and the insulating layer 12. Then, the first metal layer 114 is filled inside the high-k dielectric material layer 113, and further, the second metal layer 115 is filled in the upper center of the first metal layer 114.

[0037] Also, in the cross-sectional view in the gate width direction shown in FIG. 7, the second semiconductor element 200 has the bottom Si layer 201 on the PTS layer 13 formed on the uppermost layer of the substrate 11. The upper surface and the side surface of the Si layer 201 are covered by the gate insulating film 211. Furthermore, in the cross-sectional view in the gate width direction shown in FIG. 7, the second semiconductor element 200 has Si layers 202, 203, 204 laminated via the high-k dielectric material layer 213 and the first metal layer 214 that constitute the gate electrode 212 above the Si layer 201. The Si layers 202, 203, 204 are each surrounded by the gate insulating film 211. And the periphery of the gate insulating film 211 is covered by the high-k dielectric material layer 213. The high dielectric constant material layer 213 covers the entire contact surface of the gate insulating film 211 and the gate electrode 212, as well as the side and bottom surfaces of the gate electrode 212. A first metal layer 214 is filled inside the high dielectric constant material layer 213, and a second metal layer 215 is filled in the upper center of the first metal layer 214.

[0038] [Equivalent circuit diagram of semiconductor device] Next, in the semiconductor device 10 shown in FIGS. 5 - 7 described above, an equivalent circuit diagram of the first semiconductor element 100 serving as an input / output device is shown in FIG. 8. As shown in FIG. 6, in the first semiconductor element 100, an Si layer 104 composed of a nanosheet layer formed directly under the gate electrode 112 is in contact with the source region 108 and the drain region 109. On the other hand, an SiGe layer 107 formed directly under the gate electrode 112 is not in contact with the source region 108 and the drain region 109 due to the presence of the inner spacer 110. Therefore, the equivalent circuits of the gate electrode 112, the Si layer 104, the SiGe layer 107, the source region 108, and the drain region 109 in the first semiconductor element 100 can be shown as in FIG. 8.

[0039] In FIG. 8, Tr_1 is a FET including the Si layer 104. Tr_2 is a FET including the SiGe layer 107. Also, R1_s is the source region 108, and R1_d is the drain region 109. Also, let the gate threshold voltage (Vth) of the FET (Tr_1) including the Si layer 104 be |Vth_1|, and the gate threshold voltage (Vth) of the FET (Tr_2) including the SiGe layer 107 be |Vth_2|.

[0040] As shown in FIG. 6, the SiGe layer 107 is not in contact with the source region 108 and the drain region 109. Therefore, also in the equivalent circuit shown in FIG. 8, Tr_2 is not directly connected to R1_s and R1_d. And, as shown in FIG. 6, the SiGe layer 107 is configured to be connected to the source region 108 and the drain region 109 via an inversion layer formed in the Si layer 104. For this reason, also in the equivalent circuit shown in FIG. 8, the source / drain of Tr_2 is connected inside (under the gate electrode) the source / drain of Tr_1 and is connected to R1_s and R1_d via the source / drain of Tr_1. Thus, unlike the conventional EG-FET in which Tr_1 and Tr_2 shown in FIG. 2 are connected in parallel, in the first semiconductor element 100, since Tr_2 is not directly in contact with the source / drain D, Tr_2 is connected to the source / drain region only after the inversion layer of Tr_1 is formed.

[0041] [Id-Vg Characteristics of Semiconductor Device] The Id-Vg characteristics when the first semiconductor element 100 is a pFET are shown in FIG. 9. In the Id-Vg characteristics shown in FIG. 9, when a gate voltage (Vg) is applied and the gate voltage exceeds |Vth_2|, an inversion layer is formed in the SiGe layer 107. However, no inversion layer is formed in the Si layer 104 and the channel of Tr_1 remains in the off state. For this reason, even when an inversion layer is formed in the SiGe layer 107, Tr_2 does not turn on as a parasitic transistor and no current flows through Tr_2. As a result, in the first semiconductor element 100, it can be considered that no on-current flows overall.

[0042] Then, when the gate voltage exceeds |Vth_1|, an inversion layer is formed in the Si layer 104 having a high gate threshold voltage, the FET of Tr_1 turns on, and current also flows through Tr_1. At this time, since Tr_2 (SiGe layer 107) is disposed in contact with Tr_1 (Si layer 104), when the channel of Tr_1 becomes on state, carriers gradually flow also through Tr_2 in which inversion has already occurred and a channel has been formed.

[0043] Therefore, even when the gate voltage is less than |Vth_2|, the first semiconductor element 100 of the pFET exhibits Id-Vg characteristics dependent on Tr_1. When the gate voltage exceeds |Vth_2|, although the Id-Vg characteristics are affected by the inversion layer formed in the SiGe layer 107, no current flows through the first semiconductor element 100 because Tr_1 is in the off state, and the Id-Vg characteristics remain as a smooth curve. Furthermore, when the gate voltage exceeds |Vth_1|, Tr_1 turns on, and carriers are also injected into the parallel SiGe layer 107 to act as a channel. For this reason, the first semiconductor element 100 of the pFET has a lower overall channel resistance than Tr_1 alone, and a large current can be obtained. As a result, in the first semiconductor element 100 of the pFET, the Id characteristic rises without the occurrence of a characteristic bend (hump) in the curve of the Id-Vg characteristics.

[0044] Also, the Id-Vg characteristics when the first semiconductor element 100 is an nFET are shown in FIG. 10. In the Id-Vg characteristics shown in FIG. 10, in the region of [|Vth_2| ~ |Vth_1| > Vg], the FET channels are in the off state in both Tr_1 and Tr_2. Therefore, no on-current flows through the entire EG-FET in this region. On the other hand, when it becomes the region of [|Vth_2| ~ |Vth_1| ≤ Vg], the nFETs invert almost simultaneously in both the channel of the SiGe layer of Tr_2 and the channel of the Si layer of Tr_1. For this reason, in the first semiconductor element 100 of the nFET, the Id characteristic rises without the occurrence of a characteristic bend (hump) in the curve of the Id-Vg characteristics.

[0045] Therefore, in the semiconductor device 10 described above, the Id characteristic rises without the occurrence of a characteristic bend (hump) in the curve of the Id-Vg characteristics. For this reason, the semiconductor device 10 can suppress the occurrence of defects even in a circuit that performs a specific operation, and can suppress a decrease in reliability.

[0046] 〈3. Manufacturing Method of Semiconductor Device〉 Next, the manufacturing method of the semiconductor device 10 shown in FIGS. 5-7 described above will be explained. Figures 11 - 41 show the manufacturing process diagrams of the semiconductor device 10. In the manufacturing process of the semiconductor device 10 shown in Figures 11 - 41, on the left side (a) of the drawing, a cross-sectional view along line A - A (a cross-sectional view in the gate length direction) of the semiconductor device shown in Figure 5 is shown, and on the right side (b) of the drawing, a cross-sectional view along line B - B (a cross-sectional view in the gate width direction) is shown.

[0047] First, as shown in Figure 11, impurities are implanted into the outermost surface of the substrate 11 to form a PTS layer 13 having a gentle concentration gradient from the surface of the substrate 11 toward the inside. When forming the PTS layer 13 as p-type, boron is implanted as an impurity, and when forming the PTS layer 13 as n-type, phosphorus is implanted as an impurity.

[0048] Next, as shown in Figure 12, an Si layer 19, an SiGe layer 20, an Si layer 21, an SiGe layer 22, an Si layer 23, an SiGe layer 24, and an Si layer 25 are stacked on the substrate 11. The formation of the Si layers 19, 21, 23, 25 and the SiGe layers 20, 22, 24 uses epitaxial growth of Si and SiGe. The Si layers 19, 21, 23, and 25 are formed to have a thickness of about 5 nm, for example. Also, the SiGe layers 20, 22, and 24 are formed to have a thickness of about 10 - 15 nm.

[0049] Next, as shown in Figure 13, hard mask layers 26 and 27 are formed on the Si layer 25. The hard mask layer 26 is formed of, for example, SiN or the like. For the formation of the hard mask layer 27, for example, SiO2 or the like is used. Further, the hard mask layers 26 and 27 are patterned into a predetermined shape. The patterning of the hard mask layers 26 and 27 first involves laminating and forming the hard mask layer 26 and the hard mask layer 27 over the entire surface of the Si layer 25. Then, a resist layer (not shown) is formed over the hard mask layer 27. The formed resist layer is exposed and developed using a photomask with a pattern formed thereon to be patterned. Then, using the patterned resist layer as a mask, the hard mask layers 26 and 27 are etched to form a predetermined pattern in the hard mask layers 26 and 27. The pattern of the hard mask layers 26 and 27 here is formed in the shape of the stacked bodies of the Si layers 101, 102, 103, 104 in the first semiconductor element 100 and the stacked bodies of the Si layers 201, 202, 203, 204 in the second semiconductor element 200.

[0050] Next, as shown in FIG. 14, using the patterned hard mask layers 26 and 27, the stacked body of the Si layer 19, SiGe layer 20, Si layer 21, SiGe layer 22, Si layer 23, SiGe layer 24, and Si layer 25 is etched to form the Si / SiGe stacked body 28. Further, the surface of the substrate 11 is etched to a predetermined depth. For the etching of the Si layer, SiGe layer, and the substrate 11, for example, reactive ion etching (RIE) is used.

[0051] Next, as shown in FIG. 15, after removing the hard mask layer 27, an insulating film 15 is formed to cover the side surfaces of the Si / SiGe stacked body 28, the side surfaces and upper surface of the hard mask layer 26, and the surface of the substrate 11 and the side surface of the PTS layer 13. Further, an insulating film 16 is formed to cover the insulating film 15. The insulating film 15 is formed of, for example, SiO2. The insulating film 16 is formed of, for example, SiN. Also, for the formation of the insulating films 15 and 16, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. are used.

[0052] Next, as shown in FIG. 16, after depositing the insulating layer 17 on the entire surface of the substrate 11, the insulating layer 17 is polished and planarized until the upper surface of the hard mask layer 26 is exposed. For the formation of the insulating layer 17, for example, SiO2 is used. For the deposition of the insulating layer 17, for example, CVD or the like is used. Also, for polishing and planarizing the insulating layer 17, chemical mechanical polishing (CMP) or the like is used.

[0053] Next, the hard mask layer 26, the insulating films 15 and 16 formed on the side surfaces of the Si / SiGe laminate 28, and the insulating layer 17 formed on the side surfaces of the Si / SiGe laminate 28 are removed. The removal of the insulating films 15 and 16 and the insulating layer 17 is performed until the same height as the surface of the PTS layer 13 formed on the surface of the substrate 11. As a result, as shown in FIG. 17, the upper surface and the side surfaces of the Si / SiGe laminate 28 are exposed, and the STI 14 is formed by the insulating films 15 and 16 and the insulating layer 17 having the same height as the upper surface of the PTS layer 13. For the removal of the hard mask layer 26, the insulating films 15 and 16, and the insulating layer 17, anisotropic etching such as RIE is used.

[0054] Next, as shown in FIG. 18, a dummy gate insulating film 30 is formed to cover the side surfaces and the upper surface of the Si / SiGe laminate 28 and the upper surface of the STI 14. Further, after depositing a dummy gate layer 31 covering the dummy gate insulating film 30, the dummy gate layer 31 is polished and planarized. For the formation of the dummy gate insulating film 30, for example, SiO2 is used. For the formation of the dummy gate layer 31, polysilicon (p-Si), amorphous silicon (α-Si), or the like is used. Also, for the formation of the dummy gate insulating film 30 and the deposition of the dummy gate layer 31, for example, CVD or the like is used. For the polishing of the dummy gate layer 31, for example, CMP or the like is used.

[0055] Next, hard mask layers 32 and 33 are formed on the dummy gate layer 31. The hard mask layer 32 is formed of, for example, SiN or the like. For the formation of the hard mask layer 33, for example, SiO2 or the like is used. Then, as shown in FIG. 19, the hard mask layers 32 and 33 are patterned into a predetermined shape. The patterning of the hard mask layers 32 and 33 first involves laminating and forming the hard mask layer 32 and the hard mask layer 33 on the entire surface of the dummy gate layer 31. Then, a resist layer (not shown) is formed on the hard mask layer 32 and the hard mask layer 33. The formed resist layer is exposed and developed using a photomask with a pattern formed thereon to be patterned. Then, using the patterned resist layer as a mask, the hard mask layers 32 and 33 are etched to form a predetermined pattern in the hard mask layers 32 and 33. The patterns of the hard mask layers 32 and 33 here are formed in the shapes of the gate electrode 112 in the first semiconductor element 100 and the gate electrode 212 in the second semiconductor element 200.

[0056] Next, as shown in FIG. 20, the dummy gate layer 31 is etched using the patterned hard mask layers 32 and 33. Thereby, a dummy gate 34 is formed in the first semiconductor element 100. Further, a dummy gate 35 is formed in the second semiconductor element 200. Here, the dummy gate 34 is formed in the same shape as the gate electrode 112 of the first semiconductor element 100. Similarly, the dummy gate 35 is formed in the same shape as the gate electrode 212 of the second semiconductor element 200. For the etching of the dummy gate layer 31, for example, Reactive Ion Etching (RIE) is used.

[0057] Next, as shown in FIG. 21, sidewalls 116 are patterned on the side surfaces of the dummy gate 34 of the first semiconductor element 100 and the hard mask layers 32 and 33. Further, sidewalls 216 are formed on the side surfaces of the dummy gate 35 of the second semiconductor element 200 and the hard mask layers 32 and 33. Further, the Si / SiGe stack 28 and the dummy gate insulating film 30 are etched using the dummy gates 34 and 35, the hard mask layer 33, and the sidewalls 116 and 216 as masks.

[0058] The patterning of the sidewalls 116 is as follows: First, a material layer (such as SiN) that constitutes the sidewalls 116 and 216 is formed on the entire surface of the substrate 11 with a predetermined thickness. Then, anisotropic etching such as RIE is performed on the formed material layer so that the sidewalls 116 and 216 remain on the side surfaces of the dummy gates 34 and 35 and the hard mask layers 32 and 33. The thickness of the material layer to be formed is adjusted according to the thickness of the sidewalls 116 and 216 to be left on the side surfaces of the dummy gates 34 and 35 and the hard mask layers 32 and 33. The sidewall 116 is formed in the range where the stack of the Si layers 101, 102, 103, and 104 of the first semiconductor element 100 is formed. Also, the sidewall 216 is formed in the range where the stack of the Si layers 201, 202, 203, and 204 of the second semiconductor element 200 is formed. By etching the Si / SiGe stack 28 and the dummy gate insulating film 30, an independent first stack 36 composed of a stack of the Si layer 101, the SiGe layer 20, the Si layer 102, the SiGe layer 22, the Si layer 103, the SiGe layer 24, and the Si layer 104 is formed in the first semiconductor element 100. Similarly, an independent second stack 37 composed of a stack of the Si layer 201, the SiGe layer 20, the Si layer 202, the SiGe layer 22, the Si layer 203, the SiGe layer 24, and the Si layer 204 is formed in the second semiconductor element 200.

[0059] Next, in the first stack 36 shown in FIG. 21, the side surfaces of the SiGe layers 20, 22, and 24 exposed in the gate length direction are selectively etched to partially remove the side surfaces of the SiGe layers 20, 22, and 24. As a result, as shown in FIG. 22, the SiGe layers 105, 106, and 107 are formed, and recesses 38 with respect to the side surfaces of the Si layers 101, 102, 103, and 104 are formed on the side surfaces of the SiGe layers 105, 106, and 107. Therefore, a step due to the recess 38 is formed between the side surfaces of the SiGe layers 105, 106, and 107 and the side surfaces of the Si layers 101, 102, 103, and 104. Similarly, in the second laminate 37 shown in FIG. 21, the side surfaces of the SiGe layers 20, 22, 24 exposed in the gate length direction are selectively etched to partially remove the side surfaces of the SiGe layers 20, 22, 24. As a result, as shown in FIG. 22, recesses 39 with respect to the side surfaces of the Si layers 201, 202, 203, 204 are formed on the side surfaces of the SiGe layers 20, 22, 24. Therefore, a step due to the recess 39 is formed between the side surfaces of the SiGe layers 20, 22, 24 and the side surfaces of the Si layers 201, 202, 203, 204. At this time, the side surfaces in the gate width direction are covered by the dummy gates 34, 35. Therefore, the side surfaces of the SiGe layers 20, 22, 24 in the gate width direction are not etched. For the etching of the SiGe layers 20, 22, 24, for example, isotropic etching such as atomic layer etching (ALE), quasi-ALE, or selective vapor etching is used. These methods have selectivity of Si with respect to SiGe and reverse selectivity of SiGe with respect to Si during the etching process. Therefore, these methods can selectively etch the side surfaces of the SiGe layers 20, 22, 24 of the first laminates 36, 37 to form the recesses 38, 39. The depth of the recesses 38, 39 is adjusted in consideration of the thickness of the inner spacer 110 of the first semiconductor element 100 and the thickness of the inner spacer 210 of the second semiconductor element 200.

[0060] Next, as shown in FIG. 23, an insulating layer 40 is formed to selectively cover the first laminates 36, 37, the dummy gates 34, 35, the hard mask layers 32, 33, and the sidewalls 116, 216. The insulating layer 40 is formed as follows. First, a resist layer (not shown) that opens around the first laminate 36, the dummy gate 34, the hard mask layers 32, 33, the sidewalls 116, 216, and these is patterned. Then, SiN or the like is laminated using CVD or the like. Further, the resist layer and the SiN on the resist layer are removed.

[0061] Next, anisotropic etching such as RIE is performed to remove the insulating layer 40 exposed from the side surfaces of the first stacked bodies 36 and 37. That is, the insulating layer 40 of the portions protruding from the Si layers 101, 102, 103, and 104 is removed. As a result, as shown in FIG. 24, the inner spacer 110 as an insulating film region remains in the concave portion 38 on the side surface of the SiGe layers 105, 106, and 107. Also, the insulating layer 40 of the portions protruding from the Si layers 201, 202, 203, and 204 is removed. As a result, as shown in FIG. 24, the inner spacer 210 as an insulating film region remains in the concave portion 39 on the side surface of the SiGe layers 20, 22, and 24.

[0062] Next, as shown in FIG. 25, a source region 108 and a drain region 109 are formed on the side surface of the first stacked body 36. Also, a source region 208 and a drain region 209 are formed on the side surface of the second stacked body 37. The source regions 108 and 208 and the drain regions 109 and 209 are formed, for example, using epitaxial growth of the Si layers 101, 102, 103, 104 and the Si layers 201, 202, 203, 204. Also, when forming the source regions 108 and 208 and the drain regions 109 and 209 by epitaxial growth of the Si layers, impurities are implanted. For example, when forming the first semiconductor element 100 as p-type, boron is implanted as an impurity, and when forming it as n-type, phosphorus is implanted as an impurity. Similarly, when forming the second semiconductor element 200 as p-type, boron is implanted as an impurity, and when forming it as n-type, phosphorus is implanted as an impurity.

[0063] Next, as shown in FIG. 26, an insulating layer 12 is formed on the entire surface of the substrate 11. The insulating layer 12 is formed of, for example, SiN. Also, for forming the insulating layer 12, CVD is used. Furthermore, as shown in FIG. 27, an insulating layer 18 is formed on the entire surface of the substrate 11. The insulating layer 18 is deposited up to a position higher than the insulating layer 12 formed on the hard mask layers 32 and 33. The insulating layer 18 is formed of, for example, SiO2. Also, for forming the insulating layer 18, CVD is used, for example.

[0064] Next, as shown in FIG. 28, the surface is polished from above the insulating layer 18 using CMP or the like to expose the hard mask layer 32 and the sidewalls 116, 216. As a result, the hard mask layer 33, the insulating layer 12, and the sidewalls 116, 216 formed above the hard mask layer 32 are removed.

[0065] Next, the hard mask layer 32, the sidewalls 116, 216 on the side portions of the hard mask layer 32, and the insulating layer 12 are selectively removed. The hard mask layer 32, the sidewalls 116, 216, and the insulating layer 12 are formed of, for example, SiN. Therefore, a chemical such as hydrogen fluoride that can selectively wet-etch SiN with respect to SiO and Si is used to selectively etch the hard mask layer 32, the sidewalls 116, 216, and the insulating layer 12. As a result, as shown in FIG. 29, the dummy gates 34, 35 are exposed while the shape of the insulating layer 18 remains.

[0066] Next, the dummy gates 34, 35 are removed. As a result, as shown in FIG. 30, the dummy gate insulating film 30 is exposed. For the removal of the dummy gates 34, 35, for example, plasma etching or the like that can selectively etch the polysilicon (p-Si) or amorphous silicon (α-Si) constituting the dummy gates 34, 35 is used.

[0067] Next, as shown in FIG. 31, the entire surface on the substrate 11 is filled with the insulating layer 18, and after planarizing the surface of the insulating layer 18, a resist layer 42 that opens only the inside of the insulating layer 12 of the second semiconductor element 200 is patterned. Further, using the resist layer 42 as a mask, the insulating layer 18 is etched to expose the insulating layer 12 and the second laminate 37. When etching the insulating layer 18, the dummy gate insulating film 30 of the second semiconductor element 200 is also removed together. The insulating layer 18 is formed of, for example, SiO2. Planarization of the insulating layer 18 uses CMP or the like. For etching the insulating layer 18 and the dummy gate insulating film 30, RIE or the like is used.

[0068] Next, the resist layer 42 is removed, and the SiGe layers 20, 22, 24 of the second laminate 37 of the second semiconductor element 200 are selectively etched. As a result, as shown in FIG. 32, the spaces between the Si layers 201, 202, 203, 204 of the second semiconductor element 200 are exposed. For the removal of the resist layer 42, plasma etching or the like is used. For the selective etching of the SiGe layers 20, 22, 24, for example, dry etching with a mixed gas containing hydrogen fluoride and oxygen or wet etching with a mixed solution of hydrogen fluoride and hydrogen peroxide is used.

[0069] Next, as shown in FIG. 33, a gate insulating film 211 is formed over the entire surface, and further, a high-k dielectric material layer 213 is formed on the gate insulating film 211. The gate insulating film 211 is formed, for example, by thermal oxidation of the exposed surfaces of the Si layers 201, 202, 203, 204. The high-k dielectric material layer 213 is formed of, for example, hafnium dioxide (HfO2), hafnium oxynitride (HfON), or the like. For the formation of the high-k dielectric material layer 213, for example, ALD (Atomic Layer Deposition) or the like is used.

[0070] Next, as shown in FIG. 34, the first metal layer 214 is filled on the high-k dielectric material layer 213, and further, the second metal layer 215 is filled on the first metal layer 214. The first metal layer 214 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium, or the like. The second metal layer 215 is formed of, for example, tungsten (W) or the like. For the formation of the first metal layer 214 and the second metal layer 215, for example, CVD is used.

[0071] Next, as shown in FIG. 35, the first metal layer 214 and the second metal layer 215 above the sidewall 216 are removed. For the removal of the first metal layer 214 and the second metal layer 215, for example, CMP and RIE are used. Thereby, a gate electrode 212 composed of the high-k dielectric material layer 213, the first metal layer 214, and the second metal layer 215 is formed in the second semiconductor element 200.

[0072] Next, as shown in FIG. 36, the entire surface on the substrate 11 is embedded with the insulating layer 18, and after planarizing the surface of the insulating layer 18, an opening is made in the formation region of the gate electrode of the first semiconductor element 100. For example, a resist layer for opening the formation region of the gate electrode is patterned on the insulating layer 18. Further, using the resist layer as a mask, the insulating layer 18 is etched to expose the insulating layer 12 and the first laminate 36. When etching this insulating layer 18, the dummy gate insulating film 30 of the first semiconductor element 100 and a part of the insulating layer 12 in the gate width direction are removed together. For planarizing the insulating layer 18, CMP or the like is used. For etching the insulating layer 18 and the dummy gate insulating film 30, RIE or the like is used. For removing the resist layer, plasma etching or the like is used.

[0073] Next, as shown in FIG. 37, a gate insulating film 111 is formed on the exposed surface of the first laminate 36, and further, a high-k dielectric material layer 113 is formed on the entire surface of the substrate 11. For forming the gate insulating film 111, for example, generation of an Si layer by epitaxial growth of the Si layers 101, 102, 103, 104 and thermal oxidation of the generated Si layer are used. The high-k dielectric material layer 113 is formed of, for example, hafnium dioxide (HfO2), hafnium oxynitride (HfON), or the like. For forming the high-k dielectric material layer 113, for example, CVD or the like is used.

[0074] Next, as shown in FIG. 38, the first metal layer 114 is filled on the high-k dielectric material layer 113, and further, the second metal layer 115 is filled on the first metal layer 114. The first metal layer 114 is formed of, for example, tungsten nitride (WN), tantalum nitride (TaN), titanium nitride (TiN), niobium, or the like. The second metal layer 115 is formed of, for example, tungsten (W) or the like. For forming the first metal layer 114 and the second metal layer 115, for example, CVD is used.

[0075] Next, as shown in FIG. 39, the high-k dielectric material layer 113, the first metal layer 114, and the second metal layer 115 above the insulating layer 18 are removed. For removing the high-k dielectric material layer 113, the first metal layer 114, and the second metal layer 115, for example, CMP is used.

[0076] Next, as shown in FIG. 40, the high dielectric constant material layer 113, the first metal layer 114, and the second metal layer 115 above the sidewall 116 are removed. For example, RIE is used to remove the high dielectric constant material layer 113, the first metal layer 114, and the second metal layer 115. Thereby, a gate electrode 112 composed of the high dielectric constant material layer 113, the first metal layer 114, and the second metal layer 115 is formed on the first semiconductor element 100.

[0077] Next, an insulating layer 18 is formed on the entire surface of the substrate 11 and the surface is planarized. For example, CVD is used to form the insulating layer 18. For example, CMP is used to planarize the insulating layer 18. Thereby, as shown in FIG. 41, the first semiconductor element 100 and the second semiconductor element 200 are sealed by the insulating layer 18. Through the above steps, the semiconductor device 10 in which the first semiconductor element 100 and the second semiconductor element 200 shown in FIGS. 6 and 7 are formed on the substrate 11 can be manufactured.

[0078] 〈4. Other Embodiments of the Semiconductor Device〉 Next, as another embodiment of the semiconductor device, the configuration of the semiconductor devices of the second to fifth embodiments will be described. The second to fifth semiconductor devices described below have the same configuration as the semiconductor device of the above-described first embodiment. Therefore, the description of the same configuration as that of the semiconductor device of the above-described first embodiment will be omitted.

[0079] [Semiconductor Device of the Second Embodiment] FIGS. 42 and 43 show the configuration of the semiconductor device of the second embodiment. FIG. 42 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5. Further, FIG. 43 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 5. The semiconductor device 50 shown in FIGS. 42 and 43 has a configuration in which a first semiconductor device 51 and a second semiconductor device 52 having the same configuration as the semiconductor device 10 shown in FIGS. 5 and 6 described above are stacked in the vertical direction (stacking direction of the Si layers).

[0080] The first semiconductor device 51 laminated on the upper layer includes, on a substrate 55 (first substrate), a first semiconductor element 150 composed of FinFETs serving as input / output devices, and a second semiconductor element 152 composed of GAAFETs serving as logic devices. Further, the second semiconductor device 52 laminated on the lower layer includes, on a substrate 11 (second substrate), a third semiconductor element 151 composed of FinFETs serving as input / output devices, and a fourth semiconductor element 153 composed of GAAFETs serving as logic devices.

[0081] In the semiconductor device 50 configured as described above, for example, the upper first semiconductor element 150 and the second semiconductor element 152 are formed as pFETs, and the lower third semiconductor element 151 and the fourth semiconductor element 153 are formed as nFETs. The semiconductor device 50 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 51 including the first semiconductor element 150 and the second semiconductor element 152 on the substrate 55 and a second semiconductor device 52 including the third semiconductor element 151 and the fourth semiconductor element 153 formed on the substrate 11 are laminated.

[0082] [Semiconductor Device of the Third Embodiment] FIG. 44 and FIG. 45 show the configuration of the semiconductor device of the third embodiment. FIG. 44 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5. Further, FIG. 45 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 5. The semiconductor device 60 shown in FIG. 44 and FIG. 45 has a configuration in which a first semiconductor device 61 and a second semiconductor device 62 are laminated in the vertical direction (stacking direction of Si layers).

[0083] The upper first semiconductor device 61 has a configuration obtained by removing the first semiconductor element 100 from the semiconductor device 10 shown in FIGS. 5 and 6 described above. Therefore, the first semiconductor device 61 includes, on a substrate 65 (first substrate), a second semiconductor element 162 which is a GAAFET serving as a logic device. The lower second semiconductor device 62 has the same configuration as the semiconductor device 10 shown in FIGS. 5 and 6 described above. Therefore, the second semiconductor device 62 laminated on the lower layer includes, on a substrate 11 (second substrate), a third semiconductor element 161 composed of FinFETs serving as input / output devices, and a fourth semiconductor element 163 composed of GAAFETs serving as logic devices.

[0084] In the semiconductor device 60 having the above configuration, for example, the upper second semiconductor element 162 is formed as a pFET, and the lower third semiconductor element 161 and fourth semiconductor element 163 are formed as nFETs. The semiconductor device 60 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 61 including a second semiconductor element 152 on a substrate 65 and a second semiconductor device 62 including a third semiconductor element 161 and a fourth semiconductor element 163 formed on a substrate 11 are laminated.

[0085] [Semiconductor Device of the Fourth Embodiment] FIGS. 46 and 47 show the configuration of the semiconductor device of the fourth embodiment. FIG. 46 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5. Further, FIG. 47 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 5. The semiconductor device 70 shown in FIGS. 46 and 47 has a configuration in which a first semiconductor device 71 and a second semiconductor device 72 are laminated in the vertical direction (the stacking direction of the Si layers).

[0086] The upper first semiconductor device 71 has the same configuration as the semiconductor device 10 shown in FIGS. 5 and 6 described above. Therefore, the first semiconductor device 71 laminated on the upper layer includes, on a substrate 75 (first substrate), a first semiconductor element 170 composed of FinFETs serving as input / output devices, and a second semiconductor element 172 composed of GAAFETs serving as logic devices. The lower second semiconductor device 72 has a configuration obtained by removing the first semiconductor element 100 from the semiconductor device 10 shown in FIGS. 5 and 6 described above. Therefore, the second semiconductor device 72 laminated on the lower layer includes a fourth semiconductor element 173, which is a GAAFET serving as a logic device, on a substrate 11 (second substrate).

[0087] In the semiconductor device 70 having the above configuration, for example, the upper first semiconductor element 170 and the second semiconductor element 172 are formed as pFETs, and the lower fourth semiconductor element 173 is formed as an nFET. The semiconductor device 70 can form a CFET (Complementary Field Effect Transistor: 3D sequential integration) in which a first semiconductor device 71 including the first semiconductor element 170 and the second semiconductor element 172 on a substrate 75 and a second semiconductor device 72 including the fourth semiconductor element 173 formed on the substrate 11 are laminated.

[0088] [Semiconductor Device of the Fifth Embodiment] FIGS. 48 and 49 show the configuration of the semiconductor device of the fourth embodiment. FIG. 48 corresponds to a cross-sectional view taken along line A-A (cross-sectional view in the gate length direction) of the semiconductor device shown in FIG. 5. Further, FIG. 49 corresponds to a cross-sectional view taken along line B-B (cross-sectional view in the gate width direction) of the semiconductor device shown in FIG. 5. The semiconductor device 80 shown in FIGS. 48 and 49 has a configuration in which a first semiconductor device 81 and a second semiconductor device 82 having the same configuration as the semiconductor device 10 shown in FIGS. 5 and 6 described above are laminated in the vertical direction (stacking direction of Si layers). In the semiconductor device 80 of the fifth embodiment, the first semiconductor device 81 and the second semiconductor device 82 are face-to-face connected by bonding electrodes 92, 94 and bonding electrodes 97, 99 formed on the surfaces opposite to their respective substrates 85 (first substrate) and substrate 11 (second substrate).

[0089] The first semiconductor device 81 laminated on the upper layer includes, on a substrate 85, a first semiconductor element 180 which is an input / output Tr. serving as an input / output device, and a second semiconductor element 182 which is a GAAFET serving as a logic device. Further, the first semiconductor device 81 includes, on the surface of an insulating layer 18, a bonding electrode 92 and a bonding electrode 94. The gate electrode 112 of the first semiconductor element 180 is electrically connected to the bonding electrode 92 through a through electrode 91 penetrating the insulating layer 18. The gate electrode 212 of the second semiconductor element 182 is electrically connected to the bonding electrode 94 through a through electrode 93 penetrating the insulating layer 18.

[0090] The second semiconductor device 82 laminated on the lower layer includes, on a substrate 11, a third semiconductor element 181 which is an input / output Tr. serving as an input / output device, and a fourth semiconductor element 183 which is a GAAFET serving as a logic device. Further, the second semiconductor device 82 includes, on the surface of the insulating layer 18, a bonding electrode 97 and a bonding electrode 99. The gate electrode 112 of the third semiconductor element 181 is electrically connected to the bonding electrode 97 through a through electrode 96 penetrating the insulating layer 18. The gate electrode 212 of the fourth semiconductor element 183 is electrically connected to the bonding electrode 99 through a through electrode 98 penetrating the insulating layer 18.

[0091] The through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99 are formed of copper (Cu) or the like. The formation of the through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99 is, for example, first, to form openings in the insulating layer 18 using a patterned resist layer as a mask. Further, copper is filled into the openings using CVD or the like to form the through electrodes 91, 93, 96, 98 and the bonding electrodes 92, 94, 97, 99. Further, CMP or the like is used to polish and planarize the surfaces of the insulating layer 18 and the bonding electrodes 92, 94, 97, 99. Then, the formed bonding electrodes 92, 94, 97, 99 are heated in a state of being brought into contact with each other face to face to bond the bonding electrodes 92, 94, 97, 99 to each other.

[0092] The semiconductor device 80 with the above configuration forms, for example, the upper first semiconductor element 180 and the second semiconductor element 182 as pFETs, and forms the lower third semiconductor element 181 and the fourth semiconductor element 183 as nFETs. By this method, a structure can be formed that facilitates BSPDN (BackSide Power Delivery Network) and the like.

[0093] Note that the present invention is not limited to the configuration described in the above embodiment examples, and various modifications and changes can be made without departing from the configuration of the present invention.

Explanation of Reference Numerals

[0094] 10, 50, 60, 62, 70, 80 semiconductor device, 11, 55, 65, 75, 85, 305 substrate, 12, 15, 16, 117, 217 insulating film, 13 PTS layer, 14, 310 STI, 17, 18, 40 insulating layer, 19, 21, 23, 25, 101, 102, 103, 104, 201, 202, 203, 204 Si layer, 20, 22, 24, 105, 106, 107 SiGe layer, 26, 27, 32, 33 hard mask layer, 28 Si / SiGe stack, 30 dummy gate insulating film, 31 dummy gate layer, 34, 35 dummy gate, 36 first stack, 37 second stack, 38, 39 recess, 42 resist layer, 51, 61, 71, 81 first semiconductor device, 52, 62, 72, 82 second semiconductor device, 153, 163, 173, 183 fourth semiconductor element, 91, 93, 96, 98 through electrode, 92, 94, 97, 99 bonding electrode, 100, 150, 170, 180 first semiconductor element, 108, 208 source region, 109, 209 drain region, 110, 210, 315a, 315b, 315c, 315d, 315e, 325f inner spacer, 111, 211 gate insulating film, 112, 205, 206, 207, 212 gate electrode, 113, 213 high-k material layer, 114, 214 first metal layer, 115, 215 second metal layer, 116, 216 sidewall, 151, 161, 181 third semiconductor element, 152, 162, 172, 182, 200 second semiconductor element, 325a EG gate insulating film, 325b SG gate insulating film, 325c, 325d, 325e, 325f, 325g, 325h IL layer, 330a first dielectric layer, 330b second dielectric layer, 330c, 330d, 330e,330f Sidewall Spacer, 335a EG Gate Electrode, 335b SG Gate Electrode, 335c Third Metal Electrode, 335d Second Metal Electrode, 335e First Metal Electrode, 340a First Barrier Layer, 340c Third Barrier Layer, 340e Fifth Barrier Layer, 340g Seventh Barrier Layer, 340i Ninth Barrier Layer, 340k Eleventh Barrier Layer, 350a First Semiconductor Layer, 350c Fifth Semiconductor Layer, 350e Ninth Semiconductor Layer, 360a Third Semiconductor Layer, 360b Second Semiconductor Layer, 360c Seventh Semiconductor Layer, 360d Fourth Semiconductor Layer, 360e Eleventh Semiconductor Layer, 360f Sixth Semiconductor Layer, 390a, 390b, 390c, 390d Source / Drain Region

Claims

1. A semiconductor device including a first semiconductor element and a second semiconductor element on a substrate, wherein the first semiconductor element includes: a first stacked body in which an Si layer and an SiGe layer are stacked; a first source / drain region formed on a side surface in the gate length direction of the first stacked body; a first gate electrode formed via a first gate insulating film above the first stacked body and on a side surface in the gate width direction; an insulating film region formed between the SiGe layer and the first source / drain region; and the second semiconductor element includes: a second stacked body in which an Si layer and a second gate electrode are stacked; a second source / drain region formed on a side surface in the gate length direction of the second stacked body; and the second gate electrode is formed via a second gate insulating film between layers of the Si layer and above the second stacked body, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the SiGe layer is connected to the first source / drain region via the Si layer and the insulating film region. The semiconductor device according to claim 1.

3. The semiconductor device according to claim 1, wherein the first gate insulating film of the first semiconductor element is thicker than the second gate insulating film of the second semiconductor element. The semiconductor device according to claim 1.

4. The semiconductor device according to claim 1, wherein the first semiconductor element has a larger gate length than the second semiconductor element. The semiconductor device according to claim 1.

5. The semiconductor device according to claim 1, wherein the first gate electrode and the second gate electrode are composed of a metal layer and a high-k dielectric layer, and the high-k dielectric layer is in contact with the first gate insulating film and the second gate insulating film. The semiconductor device according to claim 1.

6. The semiconductor device according to claim 1, wherein the first semiconductor element is either a p-channel FET (Field Effect Transistor) or an n-channel FET. The semiconductor device according to claim 1.

7. A semiconductor device having a structure in which a first semiconductor device including a first semiconductor element and a second semiconductor element on a first substrate and a second semiconductor device including a third semiconductor element and a fourth semiconductor element on a second substrate are stacked, wherein the first semiconductor element and the third semiconductor element include: a first stacked body in which an Si layer and an SiGe layer are stacked; a first source / drain region formed on a side surface in the gate length direction of the first stacked body; a first gate electrode formed via a first gate insulating film above the first stacked body and on a side surface in the gate width direction; It has the SiGe layer and an insulating film region formed between the first source / drain regions. The second semiconductor element and the fourth semiconductor element have a second laminate in which an Si layer and a second gate electrode are laminated via a gate insulating film, and a second source / drain region formed on a side surface in the gate length direction of the second laminate. The second gate electrode is formed via a second gate insulating film between layers of the Si layer and above the second laminate. Semiconductor device. **Claim 8** The SiGe layer is in contact with the first source / drain region via the Si layer and the insulating film region. The semiconductor device according to claim 7. **Claim 9** The first semiconductor device and the second semiconductor device are joined by joining electrodes formed on the first substrate and the second substrate, the first semiconductor element and the third semiconductor element are electrically connected by the joining electrodes, and the second semiconductor element and the fourth semiconductor element are electrically connected by the joining electrodes. The semiconductor device according to claim 7. **Claim 10** A step of forming an Si / SiGe laminate by laminating an Si layer and an SiGe layer; a step of etching the Si / SiGe laminate to form a first laminate and a second laminate; a step of selectively etching the SiGe layer exposed on side surfaces in the gate length direction of the first laminate and the second laminate to form a recess in the side surface of the SiGe layer with respect to the side surface of the Si layer; a step of forming an insulating film region in the recess; a step of forming a first source / drain region on a side surface in the gate length direction of the first laminate and a second source / drain region on a side surface in the gate length direction of the second laminate; a step of forming a first gate insulating film and a first gate electrode above the first laminate and on side surfaces in the gate width direction; a step of selectively removing the SiGe layer from the second laminate; and a step of forming a second gate insulating film and a second gate electrode between layers of the Si layer of the second laminate and above the second laminate. Method for manufacturing a semiconductor device.

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