Operational amplifier

Abstract

To provide an operational amplifier capable of easily reducing an input offset voltage or fluctuation of the input offset voltage.SOLUTION: Trimming resistors Rt1 and Rt2 to which current from a current source 41 is diverted are connected in series between the connection point of resistors R1 and R2 and the connection point of resistors R3 and R4. Trimming resistors Rt3 and Rt4 to which current from a current source 42 is diverted are connected in series between the connection point of resistors R5 and R6 and the connection point of resistors R7 and R8. The current supplied from at least one of the current source 41 and the current source 42 can be turned on and off.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to an operational amplifier.

Background Art

[0002] Conventionally, an operational amplifier shown in FIG. 12 has been proposed (for example, Patent Document 1). As shown in FIG. 12, the operational amplifier 100 includes a PNP circuit 2 composed of differential transistors Q1 and Q2 that can operate even when the non-inverting input voltage is near the negative power supply voltage VEE, and a differential transistor Q3 that can operate even when the non-inverting input voltage is near the positive power supply voltage VCC. , and an NPN circuit 3 composed of Q4. According to the operational amplifier 100 shown in FIG. 12, the non-inverting input voltage can be set in a wide range from near the negative power supply voltage VEE to the positive power supply voltage VCC.

[0003] In order to adjust the input offset voltage of the above-described operational amplifier 100, the resistors connected in series to the differential transistors Q1 and Q2 are composed of trimming resistors Rt11 and Rt12, and the resistors connected in series to the differential transistors Q3 and Q4 are composed of trimming resistors Rt13 and Rt14. can be considered. The above-described operational amplifier 100 can be switched between three operating states depending on the non-inverting input range: (1) an operating state in which only the PNP circuit 2 operates, (2) an operating state in which only the NPN circuit 3 operates, and (3) an operating state in which both the PNP circuit 2 and the NPN circuit 3 operate. Also conceivable is a configuration that switches between two operating states, the operating state of (1) and the operating state of (2).

[0004] In this case, for example, after adjusting the trimming resistors Rt11 and Rt12 so that the input offset voltage becomes 0 V in the operating state of (1), the trimming resistors Rt13 and Rt14 are adjusted so that the input offset voltage becomes 0 V in the operating state of (2). However, due to the adjustment of the trimming resistors Rt13 and Rt14, the input offset voltage in the operating state of (1) fluctuates and does not become 0 V. For this reason, there has been a problem that it is difficult to reduce fluctuations in the input offset voltage and the input offset voltage itself.

Prior Art Documents

Patent Document

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention has been made in view of the above circumstances, and an object thereof is to provide an operational amplifier that can easily reduce fluctuations in the input offset voltage or the input offset voltage.

Means for Solving the Problems

[0007] In order to achieve the above object, the operational amplifier according to the present invention is characterized by the following [1] to [8]. [1] A first current circuit, A first differential transistor and a second differential transistor whose emitters or sources are commonly connected and that shunt the current from the first current circuit, A first resistor and a second resistor connected in series between the collector or drain of the first differential transistor and a first power supply terminal to which a first power supply voltage is supplied, A first amplifier circuit having a third resistor and a fourth resistor connected in series between the collector or drain of the second differential transistor and the first power supply terminal, A second current circuit, A third differential transistor and a fourth differential transistor whose emitters or sources are commonly connected and that shunt the current from the second current circuit, and which have opposite polarities to the first differential transistor and the second differential transistor, A fifth resistor and a sixth resistor connected in series between the collector or drain of the third differential transistor and a second power supply terminal to which a second power supply voltage is supplied, A second amplifier circuit having a seventh resistor and an eighth resistor connected in series between the collector or drain of the fourth differential transistor and the second power supply terminal; A third current circuit; A first adjustable resistor and a second adjustable resistor, which are connected in series between the connection point of the first resistor and the second resistor and the connection point of the third resistor and the fourth resistor, and through which the current from the third current circuit is shunted; A fourth current circuit; A third adjustable resistor and a fourth adjustable resistor, which are connected in series between the connection point of the fifth resistor and the sixth resistor and the connection point of the seventh resistor and the eighth resistor, and through which the current from the fourth current circuit is shunted; The current supplied from at least one of the third current circuit and the fourth current circuit is provided so as to be turn-on and turn-off capable, which is an operational amplifier. [2] In the operational amplifier according to [1], A fifth current circuit; A fifth adjustable resistor and a sixth adjustable resistor, which are connected in series between the connection point of the first resistor and the second resistor and the connection point of the third resistor and the fourth resistor, or between the connection point of the fifth resistor and the sixth resistor and the connection point of the seventh resistor and the eighth resistor, and through which the current from the fifth current circuit is shunted; The fifth adjustable resistor and the sixth adjustable resistor are connected in parallel with the first adjustable resistor and the second adjustable resistor, or the third adjustable resistor and the fourth adjustable resistor, which is an operational amplifier. [3] In the operational amplifier according to [2], When the input common-mode voltage range in which only the first amplifier circuit is operable is a first voltage range, the input common-mode voltage range in which both the first amplifier circuit and the second amplifier circuit are operable is a second voltage range, and the input common-mode voltage range in which only the second amplifier circuit is operable is a third voltage range, The third current circuit has its current turned on only when the input common-mode voltage is one of the first voltage range to the third voltage range. The fourth current circuit has its current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage range in which the third current circuit is turned on among the first voltage range to the third voltage range. The fifth current circuit has its current turned on when the input common-mode voltage is in the first voltage range to the third voltage range, or has its current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage ranges in which the third current circuit and the fourth current circuit are turned on among the first voltage range to the third voltage range. It is an operational amplifier. [4] In the operational amplifier according to [1], The first resistor connected to the first differential transistor side and the third resistor connected to the second differential transistor side are composed of a fifth adjustable resistor and a sixth adjustable resistor with adjustable resistance values. It is an operational amplifier. [5] In the operational amplifier according to [1] or [4], When the input common-mode voltage range in which only the first amplification circuit is operable is defined as the first voltage range, the input common-mode voltage range in which both the first amplification circuit and the second amplification circuit are operable is defined as the second voltage range, and the input common-mode voltage range in which only the second amplification circuit is operable is defined as the third voltage range, The third current circuit has its current turned on only when the input common-mode voltage is one of the first voltage range to the third voltage range. The fourth current circuit has its current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage range in which the third current circuit is turned on among the first voltage range to the third voltage range. It is an operational amplifier. [6] In the operational amplifier according to [1], When the input non-inverting voltage is within a predetermined fourth voltage range, supply current from the first current circuit to the first differential transistor and the second differential transistor, and cut off the current supplied from the second current circuit to the third differential transistor and the fourth differential transistor. A switching unit that supplies current from the second current circuit to the third differential transistor and the fourth differential transistor and cuts off the current supplied from the first current circuit to the first differential transistor and the second differential transistor when the input non-inverting voltage is within a predetermined fifth voltage range. It is an operational amplifier. [7] In the operational amplifier according to [6], The third current circuit has current turned on only when the input non-inverting voltage is within the fourth voltage range. The fourth current circuit has current turned on only when the input non-inverting voltage is within the fifth voltage range. It is an operational amplifier. [8] In the operational amplifier according to [6], The second current circuit forms a current mirror circuit and has a fifth transistor connected in diode connection and a sixth transistor that folds back the current flowing through the fifth transistor. The fifth transistor is connected in series to the first current circuit. The sixth transistor is connected between the emitter or source of the third differential transistor and the fourth differential transistor and the first power supply terminal. The switching unit is connected between the first current circuit and the fifth transistor. The fourth current circuit forms a current mirror circuit with the fifth transistor and has a seventh transistor that folds back the current flowing through the fifth transistor. The seventh transistor is connected between the connection point of the third adjustment resistor and the fourth adjustment resistor and the first power supply terminal. The first current circuit forms a current mirror circuit together with an eighth transistor to which current is supplied from a current source, and has a ninth transistor that folds back the current flowing through the eighth transistor. The third current circuit forms a current mirror circuit together with the eighth transistor, and has a tenth transistor that folds back the current flowing through the eighth transistor. The tenth transistor is connected between the connection point of the first adjustment resistor and the second adjustment resistor and the second power supply terminal. It is an operational amplifier.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide an operational amplifier that can easily reduce fluctuations in the input offset voltage or the input offset voltage.

[0009] The present invention has been briefly described above. Furthermore, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

[0011] Specific embodiments of the present invention will be described below with reference to the respective drawings.

[0012] (First Embodiment) First, the first embodiment will be described with reference to FIG. 1. The operational amplifier 1 shown in FIG. 1 is a circuit that amplifies an input voltage input between two input terminals T11 and T12 and outputs it from between nodes A and B. The operational amplifier 1 includes a PNP circuit 2 (= first amplifier circuit), an NPN circuit 3 (= second amplifier circuit) having a polarity opposite to that of the PNP circuit 2, transistors Q51 to Q54, trimming resistors Rt1 to Rt4 (= first to fourth adjustment resistors), a current source 41 (= third current circuit), and a current source 42 (= fourth current circuit). The PNP circuit 2 is a circuit that can amplify even when the common-mode input voltage of the input voltage is near the negative power supply voltage VEE (= first power supply voltage). The NPN circuit 3 is a circuit that can amplify even when the common-mode input voltage of the input voltage is near the positive power supply voltage (= second power supply voltage) VCC.

[0013] The PNP circuit 2 includes a differential transistor Q1 (= first differential transistor), a differential transistor Q2 (= second differential transistor), resistors R1 to R4, and a current source 21 (= first current circuit). The emitters of the differential transistors Q1 and Q2 are commonly connected. The bases of the differential transistors Q1 and Q2 are connected to the two input terminals T11 and T12 described above, respectively. The differential transistors Q1 and Q2 are composed of PNP bipolar transistors.

[0014] The resistors R1 (= first resistor) and R2 (= second resistor) are serially connected between the collector of the differential transistor Q1 and a negative power supply terminal T21 (= first power supply terminal) to which a negative power supply voltage VEE is supplied. The resistors R3 (= third resistor) and R4 (= fourth resistor) are serially connected between the collector of the differential transistor Q2 and the negative power supply terminal T21. In this embodiment, the resistor R1 and the resistor R3 are provided with the same resistance value, and the resistor R2 and the resistor R4 are provided with the same resistance value. Also, the resistance values of the resistors R1 and R3 are set higher than the resistance values of the resistors R2 and R4.

[0015] The current source 21 is connected between the emitters of the differential transistors Q1 and Q2 and a positive power supply terminal T22 (= second power supply terminal) to which a positive power supply voltage VCC is supplied. The current source 21 supplies a current I1 to the differential transistors Q1 and Q2.

[0016] The NPN circuit 3 includes a differential transistor Q3 (= third differential transistor), a differential transistor Q4 (= fourth differential transistor), resistors R5 to R8, and a current source 22 (= second current circuit). The emitters of the differential transistors Q3 and Q4 are commonly connected. The bases of the differential transistors Q3 and Q4 are connected to the two input terminals T11 and T12 described above, respectively. The differential transistors Q3 and Q4 are composed of NPN bipolar transistors having a polarity opposite to that of the differential transistors Q1 and Q2.

[0017] Resistors R5 (= fifth resistor) and R6 (= sixth resistor) are connected in series between the collector of differential transistor Q3 and the positive power supply terminal T22. Resistors R7 (= seventh resistor) and R8 (= eighth resistor) are connected in series between the collector of differential transistor Q4 and the positive power supply terminal T22. In this embodiment, resistor R5 and resistor R7 are provided with the same resistance value, and resistor R6 and resistor R8 are provided with the same resistance. Also, the resistance values of resistors R5 and R7 are set higher than the resistance values of resistors R6 and R8.

[0018] Current source 22 is connected between the emitters of differential transistors Q3 and Q4 and the negative power supply terminal T21. Current source 22 supplies current I2 to differential transistors Q3 and Q4.

[0019] Transistors Q51 and Q52 are connected in cascode between the collector of differential transistor Q1 and the collector of differential transistor Q3. Transistor Q51 is composed of a PNP bipolar transistor, with its emitter connected to the collector of differential transistor Q3 and its collector connected to the collector of transistor Q52. Transistor Q52 is composed of an NPN bipolar transistor, with its emitter connected to the collector of differential transistor Q1.

[0020] Transistors Q53 and Q54 are connected in cascode between the collector of differential transistor Q2 and the collector of differential transistor Q4. Transistor Q53 is composed of a PNP bipolar transistor, with its emitter connected to the collector of differential transistor Q4 and its collector connected to the collector of transistor Q54. Transistor Q54 is composed of an NPN bipolar transistor, with its emitter connected to the collector of differential transistor Q2.

[0021] The bases of transistors Q51 and Q53 are connected to each other and a bias voltage is supplied. The bases of transistors Q52 and Q54 are connected to each other and a bias voltage is supplied.

[0022] According to the above configuration, since the sum of the collector currents of the differential transistors Q1 and Q2 is made constant by the current source 21, the collector current ratio of the differential transistors Q1 and Q2 becomes a value corresponding to the input voltage input between the input terminals T11 and T12. Also, since the sum of the collector currents of the differential transistors Q3 and Q4 is made constant by the current source 22, the collector current ratio of the differential transistors Q3 and Q4 becomes a value corresponding to the input voltage input between the input terminals T11 and T12. Therefore, a voltage obtained by amplifying the input voltage input between the input terminals T11 and T12 is generated between the node A provided at the connection point of the transistors Q51 and Q52 and the node B provided at the connection point of the transistors Q53 and Q54.

[0023] The trimming resistors Rt1 to Rt4 and the current sources 41 and 42 are provided to reduce the input offset voltage of the operational amplifier 1. The trimming resistors Rt1 to Rt4 can have their resistance values adjusted by trimming. The trimming resistors Rt1 and Rt2 are connected in series between the connection point of the resistors R1 and R2 and the connection point of the resistors R3 and R4. The trimming resistor Rt1 is connected to the connection point of the resistors R1 and R2, and the trimming resistor Rt2 is connected to the connection point of the resistors R3 and R4.

[0024] The current source 41 is connected between the positive power supply terminal T22 and the connection point of the trimming resistors Rt1 and Rt2. The current source 41 supplies the current I3 to the trimming resistors Rt1 and Rt2. By adjusting the resistance values of the trimming resistors Rt1 and Rt2, the current ratio flowing through the trimming resistors Rt1 and Rt2 can be adjusted, and thus the potentials of the nodes A and B can be adjusted.

[0025] The trimming resistors Rt3 and Rt4 are connected in series between the connection point of the resistors R5 and R6 and the connection point of the resistors R7 and R8. The current source 42 is connected between the negative power supply terminal T21 and the connection point of the trimming resistors Rt3 and Rt4. The current source 42 supplies the current I4 to the trimming resistors Rt3 and Rt4. By adjusting the resistance values of the trimming resistors Rt3 and Rt4, the current ratio flowing through the trimming resistors Rt3 and Rt4 can be adjusted, and thus the potentials of the nodes A and B can be adjusted.

[0026] Next, the adjustment of the input offset voltage by the trimming resistors Rt1 and Rt2 will be described with reference to FIG. 2. Before trimming, as shown in FIG. 2(A), it is assumed that the trimming resistors Rt1 and Rt2 are provided with the same resistance value Rt. When the trimming resistors Rt1 and Rt2 have the same resistance value Rt, as shown by the arrow in FIG. 2(A), currents approximately equal to each other are supplied from the current source 41 to the trimming resistors Rt1 and Rt1.

[0027] As shown in FIG. 2(B), the trimming resistor Rt1 is set to a resistance value Rt, and the trimming resistor Rt2 is set to a resistance value Rt + ΔR. That is, the resistance value Rt + ΔR of the trimming resistor Rt2 is set higher than the resistance value Rt of the trimming resistor Rt1. As a result, as shown by the arrow in FIG. 2(B), the current flowing from the current source 41 to the trimming resistor Rt1 becomes larger than the current flowing through the trimming resistor Rt2, the potential of node A becomes higher, and the potential of node B becomes lower.

[0028] Conversely to FIG. 2(B), by trimming, the trimming resistor Rt2 is set to a resistance value Rt, and the trimming resistor Rt1 is set to a resistance value Rt + ΔR. That is, the resistance value Rt + ΔR of the trimming resistor Rt1 is set higher than the resistance value Rt of the trimming resistor Rt2. As a result, the current flowing from the current source 41 to the trimming resistor Rt2 becomes larger than the current flowing through the trimming resistor Rt1, the potential of node B becomes higher, and the potential of node A becomes lower.

[0029] Also, when the current I3 flowing from the current source 41 to the trimming resistors Rt1 and Rt2 is cut off, the midpoint of the combined resistance value (= 2Rt + ΔR) of the trimming resistors Rt1 and Rt2 becomes the virtual ground point in the differential operation, and the influence of the input offset voltage by the trimming resistors Rt1 and Rt2 can be eliminated.

[0030] Similarly, if the resistance value of trimming resistor Rt3 is made higher than the resistance value of trimming resistor Rt4, the current flowing through trimming resistor Rt4 will be greater than the current flowing through trimming resistor Rt3, the potential of node A will increase, and the potential of node B will decrease. Also, if the resistance value of trimming resistor Rt4 is made higher than the resistance value of trimming resistor Rt3, the current flowing through trimming resistor Rt3 will be greater than the current flowing through trimming resistor Rt4, the potential of node B will increase, and the potential of node A will decrease.

[0031] Also, when the current I4 flowing from current source 42 to trimming resistors Rt3 and Rt4 is cut off, the midpoint of the combined resistance value (= 2Rt + ΔR) of trimming resistors Rt3 and Rt4 becomes the virtual ground point in the differential operation, and the influence of the input offset voltage caused by trimming resistors Rt3 and Rt4 can be eliminated.

[0032] Next, the operation of the operational amplifier 1 of the first embodiment with the above-described configuration will be described with reference to FIG. 3. As shown in FIG. 3, the input common-mode voltage of the input voltage has voltage ranges A1 to A3 (= first to third voltage ranges). Voltage range A1 is an input common-mode voltage range in which only the PNP circuit 2 can operate and the NPN circuit 3 cannot operate. In voltage range A1, in the NPN circuit 3, the base-emitter voltage becomes too low and the differential transistors Q3 and Q4 cannot turn on and cannot operate. Voltage range A2 is an input common-mode voltage range in which both the PNP circuit 2 and the NPN circuit 3 can operate. Voltage range A3 is an input common-mode voltage range in which only the NPN circuit 3 can operate and the PNP circuit 2 cannot operate. In voltage range A3, in the PNP circuit 2, the base-emitter voltage becomes too low and the differential transistors Q1 and Q2 cannot turn on and cannot operate.

[0033] That is, in the operational amplifier 1 of the present embodiment, when the input common-mode voltage is in voltage range A1, only the PNP circuit 2 operates to amplify the input voltage, when in voltage range A2, both the PNP circuit 2 and the NPN circuit 3 operate to amplify the input voltage, and when in voltage range A3, only the NPN circuit 3 operates to amplify the input voltage.

[0034] Therefore, before trimming the trimming resistors Rt1 to Rt4, as shown by the dotted line in Fig. 3, the input offset voltage is different for each of the voltage ranges A1 to A3. Thus, as an example, when the input non-inverting voltage is in the voltage range A1, the current source 41 is turned on to supply current to the trimming resistors Rt1 and Rt2, and the current source 42 is turned off to cut off the current to the trimming resistors Rt3 and Rt4. The trimming resistors Rt1 and Rt2 are trimmed so that the input offset voltage in the voltage range A1 is equal to the input offset voltage in the voltage range A2. At this time, since the current source 42 is cut off, there is no influence of the input offset voltage caused by the trimming resistors Rt3 and Rt4.

[0035] In the voltage range A3, the current source 42 is turned on to supply current to the trimming resistors Rt3 and Rt4, and the current source 41 is turned off to cut off the current to the trimming resistors Rt1 and Rt2. The trimming resistors Rt3 and Rt4 are trimmed so that the input offset voltage in the voltage range A3 is equal to the input offset voltage in the voltage range A2. At this time, since the current source 41 is cut off, there is no influence of the input offset voltage caused by the trimming resistors Rt1 and Rt2.

[0036] In the voltage range A2, the current sources 41 and 42 are turned off to cut off the current to the trimming resistors Rt1 to Rt4. There is no influence of the input offset voltage caused by the trimming resistors Rt1 to Rt4. By the above operations, the variation in the input offset voltage can be suppressed and made constant over the voltage ranges A1 to A3.

[0037] According to the above-described embodiment, by turning on and off the current sources 41 and 42, the variation in the input offset voltage caused by the trimming resistors Rt1 to Rt4 can be eliminated. Therefore, the trimming resistors Rt1 to Rt4 can be easily adjusted so that the input offset voltage becomes constant.

[0038] Incidentally, even when resistors R1 to R4 are trimming resistors, the input offset voltage can be adjusted. However, the resistance values of resistors R1 to R4 need to be set low in order to widen the operating range of differential transistors Q1 and Q2, and the input offset voltage cannot be adjusted with high precision. On the other hand, according to the present embodiment, trimming resistors Rt1 and Rt2 are provided between the connection point of resistors R1 and R2 and the connection point of resistors R3 and R4. For this reason, there are no restrictions on the resistance values of trimming resistors Rt1 and Rt2, and the input offset voltage can be adjusted with high precision. Similarly, trimming resistors Rt3 and Rt4 can also adjust the input offset voltage with high precision.

[0039] Also, according to the above-described embodiment, the resistance values of resistors R1 and R3 are set higher than the resistance values of resistors R2 and R4. The resistance values of resistors R5 and R7 are set higher than the resistance values of resistors R6 and R8. Thereby, fluctuations in the impedance of the signal line due to trimming of trimming resistors Rt1 to Rt4 can be suppressed.

[0040] Note that according to the above-described first embodiment, current source 41 is turned on only when the voltage range is A1, and current source 42 is turned on only when the voltage range is A3, but this is not restrictive. Current source 41 may be turned on only when the voltage range is A2. Current source 42 is turned on only in one of the remaining voltage ranges A1 and A3 excluding voltage range A2 in which current source 41 is turned on among voltage ranges A1 to A3. Trimming resistors Rt1 to Rt4 are adjusted so as to be constant at the input offset voltage in the voltage range in which both current sources 41 and 42 are turned off.

[0041] Also, current source 41 may be turned on only when the voltage range is A3. In this case, current source 42 is turned on only in one of the remaining voltage ranges A1 and A2 excluding voltage range A3 in which current source 41 is turned on among voltage ranges A1 to A3. Trimming resistors Rt1 to Rt4 are adjusted so as to be constant at the input offset voltage in the voltage range in which both current sources 41 and 42 are turned off.

[0042] (Second Embodiment) Next, the operational amplifier 1B of the second embodiment will be described with reference to FIG. 4. In FIG. 4, the same reference numerals are given to the parts equivalent to the operational amplifier 1 shown in FIG. 1 described in the above-described first embodiment, and the detailed description thereof will be omitted. The second embodiment is a circuit example that further concretizes the first embodiment. The operational amplifier 1B of the second embodiment includes a PNP circuit 2, an NPN circuit 3, transistors Q51 to Q54, trimming resistors Rt1 to Rt4, current circuits 41B and 42B, transistors Q81 and Q82 for controlling the current circuits 41B and 42B, and voltage sources 51 and 52.

[0043] Since the PNP circuit 2, the NPN circuit 3, the transistors Q51 to Q54, and the trimming resistors Rt1 to Rt4 are the same as those in the above-described first embodiment, the detailed description thereof will be omitted here.

[0044] The current circuit 41B has transistors Q61 and Q62 that form a current mirror circuit. The transistors Q61 and Q62 are composed of PNP-type bipolar transistors. The emitter of the transistor Q61 is connected to the positive power supply terminal T22, and the base and collector are connected. The base and collector of the transistor Q61 are connected to the current source 22 via the transistor Q81 described later. The emitter of the transistor Q62 is connected to the positive power supply terminal T22, the base is connected to the base and collector of the transistor Q61, and the collector is connected to the connection point of the trimming resistors Rt1 and Rt2.

[0045] The current circuit 42B has transistors Q71 and Q72 which form a current mirror circuit. The transistors Q71 and Q72 are composed of NPN bipolar transistors. The emitter of transistor Q71 is connected to the negative power supply terminal T21, and its base - collector is connected. The base - collector of transistor Q71 is connected to the current source 21 via a transistor Q82 described later. The emitter of transistor Q72 is connected to the negative power supply terminal T21, its base is connected to the base - collector of transistor Q71, and its collector is connected to the connection point of trimming resistors Rt3 and Rt4.

[0046] Transistor Q81 is composed of an NPN bipolar transistor. The emitter of transistor Q81 is connected to the current source 22, its collector is connected to the base - collector of transistor Q61, and its base is connected to the voltage source 51.

[0047] Transistor Q82 is composed of a PNP bipolar transistor. The emitter of transistor Q82 is connected to the current source 21, its collector is connected to the base - collector of transistor Q71, and its base is connected to the voltage source 52.

[0048] The voltage source 51 is connected between the base of transistor Q81 and the negative power supply terminal T21, and supplies a voltage V1 to the base of transistor Q81. The voltage source 52 is connected between the base of transistor Q82 and the positive power supply terminal T22, and supplies a voltage (VCC - V2) to the base of transistor Q82.

[0049] According to the above-described second embodiment, as the common-mode input voltage VICM, when (VEE + V1)> VICM, transistor Q81 is turned on and transistor Q82 is turned off. When (VEE + V1) is set to the upper limit value of voltage range A1, in voltage range A1, transistor Q81 is turned on and transistor Q82 is turned off. When transistor Q81 is turned on, the current I2 from current source 22 is folded back by transistors Q61 and Q62, and the current I3 from current circuit 41B is supplied to trimming resistors Rt1 and Rt2. When transistor Q82 is turned off, the current supplied from current circuit 42B to trimming resistors Rt3 and Rt4 is cut off.

[0050] When (VCC - V2)<VICM, transistor Q82 is turned on and transistor Q81 is turned off. When (VCC - V2) is set to the lower limit value of voltage range A3, in voltage range A3, transistor Q82 is turned on and transistor Q81 is turned off. When transistor Q82 is turned on, the current I1 from current source 21 is folded back by transistors Q71 and Q72, and the current I4 from current circuit 42B is supplied to trimming resistors Rt3 and Rt4. When transistor Q81 is turned off, the current supplied from current circuit 41B to trimming resistors Rt1 and Rt2 is cut off.

[0051] When (VEE + V1)<VICM<(VCC - V2), transistors Q81 and Q82 are turned off. That is, in voltage range A2, transistors Q81 and Q82 are turned off. When transistors Q81 and Q82 are turned off, the current flowing from current circuits 41B and 42B to trimming resistors Rt1 to Rt4 is cut off.

[0052] With the above configuration, current circuits 41B and 42B can be controlled according to voltage ranges A1 to A3. Also, in voltage range A1, the current of current source 22 of non-operating NPN circuit 3 can be folded back and supplied to trimming resistors Rt1 and Rt2. In voltage range A3, the current of current source 21 of non-operating PNP circuit 2 can be folded back and supplied to trimming resistors Rt3 and Rt4.

[0053] (Third Embodiment) Next, the operational amplifier 1C of the third embodiment will be described with reference to FIG. 5. In FIG. 5, the same reference numerals are given to the parts equivalent to the operational amplifier 1B shown in FIG. 4 described in the above-described second embodiment, and the detailed description thereof will be omitted. In the third embodiment, the current source 21 is also used as a third current circuit that supplies current to the trimming resistors Rt1 and Rt2. The current source 22 is also used as a fourth current circuit that supplies current to the trimming resistors Rt3 and Rt4.

[0054] Also, contrary to the second embodiment, in the operational amplifier 1C of the third embodiment, when the non-inverting input voltage is in the voltage range A1, current is supplied to the trimming resistors Rt3 and Rt4, and the current to the trimming resistors Rt1 and Rt2 is cut off. When the non-inverting input voltage is in the voltage range A3, current is supplied to the trimming resistors Rt1 and Rt2, and the current to the trimming resistors Rt3 and Rt4 is cut off.

[0055] As shown in FIG. 5, the operational amplifier 1C includes a PNP circuit 2, an NPN circuit 3, transistors Q51 to Q54, trimming resistors Rt1 to Rt4, transistors Q81C and Q82C, and voltage sources 51C and 52C. Since the PNP circuit 2, the NPN circuit 3, the transistors Q51 to Q54, and the trimming resistors Rt1 to Rt4 are the same as those in the first embodiment, the detailed description thereof will be omitted here.

[0056] The transistor Q81C is composed of an NPN-type bipolar transistor. The emitter of the transistor Q81C is connected to the current source 22, the collector is connected to the connection point of the trimming resistors Rt3 and Rt4, and the base is connected to the voltage source 51C.

[0057] The transistor Q82C is composed of a PNP-type bipolar transistor. The emitter of the transistor Q82C is connected to the current source 21, the collector is connected to the connection point of the trimming resistors Rt1 and Rt2, and the base is connected to the voltage source 52C.

[0058] The voltage source 51C is connected between the base of the transistor Q81C and the negative power supply terminal T21, and supplies the voltage V1 to the base of the transistor Q81C. The voltage source 52C is connected between the base of the transistor Q82C and the positive power supply terminal T22, and supplies the voltage (VCC - V2) to the base of the transistor Q82C.

[0059] Similar to the second embodiment, (VEE + V1) is set to the upper limit value of the voltage range A1, and (VCC - V2) is set to the lower limit value of the voltage range A3. Thereby, when the in-phase input voltage is in the voltage range A1, the transistor Q81C is turned on and the transistor Q82C is turned off. When the transistor Q81C is turned on, the current I4 from the current source 22 is supplied to the trimming resistors Rt3 and Rt4. When the transistor Q82C is turned off, the current supplied from the current source 21 to the trimming resistors Rt1 and Rt2 is cut off. The trimming resistors Rt3 and Rt4 are trimmed so that the input offset voltage in the voltage range A1 is equal to the input offset voltage in the voltage range A2.

[0060] When the in-phase input voltage is in the voltage range A3, the transistor Q82C is turned on and the transistor Q81C is turned off. When the transistor Q82C is turned on, the current I3 from the current source 21 is supplied to the trimming resistors Rt1 and Rt2. When the transistor Q81C is turned off, the current supplied from the current source 22 to the trimming resistors Rt3 and Rt4 is cut off. The trimming resistors Rt1 and Rt2 are trimmed so that the input offset voltage in the voltage range A3 is equal to the input offset voltage in the voltage range A2.

[0061] When the in-phase input voltage is in the voltage range A2, the transistors Q81C and Q82C are turned off. When the transistors Q81C and Q82C are turned off, the current flowing from the current sources 21 and 22 to the trimming resistors Rt1 to Rt4 is cut off. The third embodiment can also obtain the same effects as the first and second embodiments.

[0062] (Fourth Embodiment) Next, the operational amplifier 1D of the fourth embodiment will be described with reference to FIG. 6. In FIG. 6, the same reference numerals are given to the parts equivalent to the operational amplifier 1 shown in FIG. 1 described in the above-described first embodiment, and the detailed description thereof will be omitted. In the first embodiment, in the operational amplifier 1, only the PNP circuit 2 operates in the voltage range A1, both the PNP circuit 2 and the NPN circuit 3 operate in the voltage range A2, and only the NPN circuit 3 operates in the voltage range A3. The operational amplifier 1D of the fourth embodiment cuts off the current I2 supplied to the differential transistors Q3 and Q4 in the voltage ranges A1 and A2, operates only the PNP circuit 2 in the voltage ranges A1 and A2, and operates only the NPN circuit 3D in the voltage range A3. For this reason, as shown by the dotted line in FIG. 7, before trimming the trimming resistors Rt1 to Rt4, the input offset voltage in the voltage ranges A1 and A2 is different from the input offset voltage in the voltage range A3. The input offset voltage in the voltage range A1 is equal to the input offset voltage in the voltage range A2.

[0063] The operational amplifier 1D of the fourth embodiment includes a PNP circuit 2, an NPN circuit 3D, transistors Q51 to Q54, trimming resistors Rt1 to Rt4, current sources 41 and 42, a voltage source 52, and a transistor Q82.

[0064] Since the PNP circuit 2, the transistors Q51 to Q54, the trimming resistors Rt1 to Rt4, and the current sources 41 and 42 are equivalent to those in the above-described first embodiment, the detailed description thereof will be omitted here.

[0065] The NPN circuit 3D includes differential transistors Q3 and Q4, resistors R5 to R8, and a current circuit 22D. Since the differential transistors Q3 and Q4 and the resistors R5 to R8 are equivalent to those in the above-described first embodiment, the detailed description thereof will be omitted here.

[0066] The current circuit 22D has transistors Q5 (= the fifth transistor) and Q6 (= the sixth transistor) which form a current mirror circuit. The transistors Q5 and Q6 are composed of NPN bipolar transistors. The emitter of transistor Q5 is connected to the negative power supply terminal T21, the base-collector is connected and diode-connected. The base-collector of transistor Q5 is connected to the current source 21 via a transistor Q82 (= switching section) described later. The emitter of transistor Q6 is connected to the negative power supply terminal T21, the base is connected to the base-collector of transistor Q5, and the collector is connected to the emitters of differential transistors Q3 and Q4.

[0067] Transistor Q82 is composed of a PNP bipolar transistor. The emitter of transistor Q82 is connected to the current source 21, the collector is connected to the base-collector of transistor Q5, and the base is connected to the voltage source 52. The voltage source 52 is connected between the base of transistor Q82 and the positive power supply terminal T22 and supplies a voltage (VCC - V2) to the base of transistor Q82.

[0068] Next, the operation of the operational amplifier 1D of the fourth embodiment with the above-described configuration will be described with reference to FIG. 7. The voltage (VCC - V2) is set to the lower limit value of the voltage range A3. When the non-inverting input voltage is within the voltage range A3, transistor Q82 turns on and supplies current to differential transistors Q3 and Q4, and the NPN circuit 3D amplifies the input voltage. Since the current to differential transistors Q1 and Q2 is cut off when transistor Q82 turns on, the PNP circuit 2 cannot operate. When the non-inverting input voltage is within the voltage ranges A1 and A2, transistor Q82 turns off, the current to differential transistors Q3 and Q4 is cut off, and the NPN circuit 3D cannot operate. Only the PNP circuit 2 operates to amplify the input voltage.

[0069] In the voltage ranges A1 and A2, the operational amplifier 1D supplies current from the current source 41 to the trimming resistors Rt1 and Rt2, and cuts off the current from the current source 42 to the trimming resistors Rt3 and Rt4. The trimming resistors Rt1 and Rt2 are trimmed so that the input offset voltage in the voltage ranges A1 and A2 becomes 0V. At this time, since the current source 42 is cut off, there is no influence on the input offset voltage due to the trimming resistors Rt3 and Rt4.

[0070] In the voltage range A3, the current source 42 supplies current to the trimming resistors Rt3 and Rt4, and cuts off the current from the current source 41 to the trimming resistors Rt1 and Rt2. The trimming resistors Rt3 and Rt4 are trimmed so that the input offset voltage in the voltage range A3 becomes 0V. At this time, since the current source 41 is cut off, there is no influence on the input offset voltage due to the trimming resistors Rt1 and Rt2. By the above operations, the input offset voltage can be suppressed to approximately 0V and made constant over the voltage ranges A1 to A3.

[0071] In the fourth embodiment, the current source 41 is turned on only in the case of the voltage ranges A1 and A2, and the current source 42 is turned on only in the case of the voltage range A3, but this is not restrictive. The current source 42 may be turned on in all the voltage ranges A1 to A3. Also, the current source 42 may be turned on only in the case of the voltage ranges A1 and A2, and the current source 41 may be turned on only in the case of the voltage range A3 or in all the voltage ranges A1 to A3.

[0072] Also, in the fourth embodiment, the voltage (VCC - V2) is set to the lower limit value of the voltage range A3. That is, the fourth voltage range in which only the PNP circuit 2 operates is set to the voltage ranges A1 and A2, and the fifth voltage range in which only the NPN circuit 3D operates is set to the voltage range A3, but this is not restrictive. The upper limit value of the fourth voltage range and the lower limit value of the fifth voltage range can be arbitrarily determined in the voltage range A2.

[0073] (Fifth Embodiment) Next, the operational amplifier 1E of the fifth embodiment will be described with reference to FIG. 8. In FIG. 8, parts equivalent to those of the operational amplifier 1D shown in FIG. 6 described in the above-described fourth embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted. The operational amplifier 1E of the fifth embodiment supplies the current supplied from one current source (not shown) to the differential transistors Q1 to Q4 and the trimming resistors Rt1 to Rt4 by folding it back with a current mirror circuit.

[0074] The operational amplifier 1E of the fifth embodiment includes a PNP circuit 2E, an NPN circuit 3D, transistors Q51 to Q54, trimming resistors Rt1 to Rt4, current circuits 41E and 42E, a voltage source 52, and a transistor Q82.

[0075] The PNP circuit 2E includes differential transistors Q1 and Q2, resistors R1 to R4, and a current circuit 21E. Since the differential transistors Q1 and Q2 and the resistors R1 to R4 have already been described in the fourth embodiment, detailed descriptions thereof are omitted here. The current circuit 21E is composed of a transistor Q9 (= the ninth transistor) that forms a current mirror circuit together with a transistor (not shown; corresponding to the eighth transistor) through which the current I1 supplied from the current source flows. The transistor Q9 is composed of a PNP bipolar transistor, the base of which is connected to the base-collector of a transistor not shown, the emitter of which is connected to the positive power supply terminal T22, and the collector of which is connected to the emitters of the differential transistors Q1 and Q2. The transistor Q9 folds back the current I1 flowing through the transistor not shown and supplies it to the differential transistors Q1 and Q2.

[0076] Since the NPN circuit 3D, the transistors Q51 to Q54, and the trimming resistors Rt1 to Rt4 have already been described in the fourth embodiment, detailed descriptions thereof are omitted here.

[0077] The current circuit 41E is composed of a transistor Q10 (= the tenth transistor) that forms a current mirror circuit together with a transistor (not shown) through which a current I1 flows. The transistor Q10 is composed of a PNP bipolar transistor. The base of the transistor Q10 is connected to the base-collector of a transistor (not shown) and the base of the transistor Q9. The emitter of the transistor Q10 is connected to the positive power supply terminal T22, and the collector is connected to the connection point of the trimming resistors Rt1 and Rt2. Similar to the transistor Q9, the transistor Q10 folds back the current I1 flowing through the transistor (not shown) and supplies the current I3 to the trimming resistors Rt1 and Rt2.

[0078] The current circuit 42E is composed of a transistor Q7 (= the seventh transistor). The transistor Q7 is composed of an NPN bipolar transistor. The base of the transistor Q7 is connected to the base-collector of the transistor Q5, the emitter is connected to the negative power supply terminal T21, and the collector is connected to the connection point of the trimming resistors Rt3 and Rt4. Since the voltage source 52 and the transistor Q82 have been described in the above-described fourth embodiment, detailed description thereof is omitted here.

[0079] Next, the operation of the operational amplifier 1E of the fifth embodiment having the above-described configuration will be described. The voltage (VCC - V2) is set to the lower limit value of the voltage range A3. When the input non-inverting voltage is within the voltage range A3, the transistor Q82 is turned on, current is supplied to the differential transistors Q3 and Q4, and the NPN circuit 3D amplifies the input voltage. The PNP circuit 2E cannot operate. When the input non-inverting voltage is within the voltage ranges A1 and A2, the transistor Q82 is turned off, the current to the differential transistors Q3 and Q4 is cut off, and the NPN circuit 3D cannot operate. Only the PNP circuit 2E operates to amplify the input voltage.

[0080] The operational amplifier 1E always (i.e., when the input voltage range is within the voltage ranges A1 to A3), has current supplied from the current circuit 41E to the trimming resistors Rt1 and Rt2. In contrast, when the input voltage range is within the voltage ranges A1 and A2, as described above, the transistor Q82 turns off, and the current to the trimming resistors Rt3 and Rt4 is cut off. When the input voltage range is within the voltage range A3, as described above, the transistor Q82 turns on, and current is supplied to the trimming resistors Rt3 and Rt4.

[0081] Therefore, the trimming resistors Rt1 and Rt2 are adjusted so that the input offset voltage for the voltage ranges A1 and A2 becomes 0V. When the input offset voltage is as shown in FIG. 7, the input offset voltage of the trimming resistors Rt1 to Rt4 before trimming adjustment is 1mV. The trimming resistors Rt1 and Rt2 are adjusted so that the input offset voltage decreases by -1mV.

[0082] Also, the trimming resistors Rt3 and Rt4 are adjusted so that the input offset voltage for the voltage range A3 becomes 0V. When the input offset voltage is as shown in FIG. 7, the input offset voltage of the trimming resistors Rt1 to Rt4 before trimming adjustment is -1mV. After trimming adjustment of the trimming resistors Rt1 and Rt2, the input offset voltage for the voltage range A3 becomes -2mV. Therefore, the trimming resistors Rt3 and Rt4 are adjusted so that the input offset voltage increases by +2mV. By the above operations, the input offset voltage can be suppressed to approximately 0V and made constant across the voltage ranges A1 to A3.

[0083] According to the fifth embodiment described above, the current circuits 21E, 22D, 41E, and 42E supply current by folding back the current I1 supplied from one current source. Therefore, the electrical characteristics of the currents supplied from the current circuits 21E, 22D, 41E, and 42E can be made the same. If the current circuits 21E, 22D, 41E, and 42E have the same electrical characteristics, even if the current I1 fluctuates due to environmental dependence or the like, the fluctuations are canceled out and do not affect the input offset voltage.

[0084] (Sixth Embodiment) Next, the operational amplifier 1F of the sixth embodiment will be described with reference to FIG. 9. In FIG. 9, the same reference numerals are given to the parts equivalent to the operational amplifier 1 shown in FIG. 1 described in the first embodiment above, and the detailed description thereof will be omitted. The differences between the first embodiment and the sixth embodiment are that, in addition to the PNP circuit 2, the NPN circuit 3, the transistors Q51 to Q54, the trimming resistors Rt1 to Rt4, and the current sources 41 and 42, trimming resistors Rt5 and Rt6 and a current source 43 (= the fifth current circuit) are provided.

[0085] Since the PNP circuit 2, the NPN circuit 3, the transistors Q51 to Q54, the trimming resistors Rt1 to Rt4, and the current sources 41 and 42 are equivalent to those in the first embodiment, the detailed description thereof will be omitted here.

[0086] The trimming resistors Rt5 and Rt6 are connected in parallel with the trimming resistors Rt1 and Rt2 between the connection point of the resistors R1 and R2 and the connection point of the resistors R3 and R4. The current source 43 is connected between the positive power supply terminal T22 and the connection point of the trimming resistors Rt5 and Rt6.

[0087] Next, the operation of the operational amplifier 1F of the sixth embodiment having the above-described configuration will be described with reference to FIG. 10. In the operational amplifier 1F of this embodiment, in the voltage range A2, a current I5 is supplied from the current source 43 to the trimming resistors Rt5 and Rt6, and the currents from the current sources 41 and 42 to the trimming resistors Rt1 to Rt4 are cut off. The trimming resistors Rt5 and Rt6 are trimmed so that the input offset voltage in the voltage range A2 becomes equal to 0V.

[0088] In the case of the input offset voltage as shown in FIG. 10, in the voltage range A2 before trimming of the trimming resistors Rt1 to Rt6 as indicated by the dotted line, the input offset voltage is -0.8 mV. The trimming resistors Rt5 and Rt6 are adjusted to increase the input offset voltage by +0.8 mV and make it 0V as indicated by the dashed-dotted line.

[0089] In voltage range A1, the operational amplifier 1F supplies current from current sources 41 and 43 to trimming resistors Rt1, Rt2, Rt5, and Rt6, and cuts off the current from current source 42 to trimming resistors Rt3 and Rt4. The trimming resistors Rt1 and Rt2 are adjusted so that the input offset voltage in voltage range A1 becomes 0V.

[0090] When the input offset voltage is as shown in Fig. 10, as indicated by the dashed-dotted line, after adjusting the trimming resistors Rt5 and Rt6, the input offset voltage in voltage range A1 is -0.5mV. The trimming resistors Rt1 and Rt2 are adjusted to increase the input offset voltage by +0.5mV as indicated by the solid line and make it 0V.

[0091] In voltage range A3, the operational amplifier 1F supplies current from current sources 42 and 43 to trimming resistors Rt3, Rt4, Rt5, and Rt6, and cuts off the current from current source 41 to trimming resistors Rt1 and Rt2. The trimming resistors Rt3 and Rt4 are adjusted so that the input offset voltage in voltage range A3 becomes 0V.

[0092] When the input offset voltage is as shown in Fig. 10, as indicated by the dashed-dotted line, after adjusting the trimming resistors Rt5 and Rt6, the input offset voltage in voltage range A3 is +2.0mV. The trimming resistors Rt3 and Rt4 are adjusted to decrease the input offset voltage by -2.0mV as indicated by the solid line and make it 0V. Through the above operations, the input offset voltage can be reduced to approximately 0V across voltage ranges A1 to A3.

[0093] Note that according to the sixth embodiment, current source 41 is turned on only in the case of voltage range A1, and current source 42 is turned on only in the case of voltage range A3, but it is not limited to this. Current source 41 may be turned on only in the case of voltage range A2. Current source 42 is turned on only in one of the remaining voltage ranges A1 and A3 excluding voltage range A2 in which current source 41 is turned on among voltage ranges A1 to A3.

[0094] Further, the current source 41 may be turned on only when the voltage range is A3. In this case, the current source 42 is turned on only when the voltage range is one of the remaining voltage ranges A1 and A2 excluding the voltage range A3 in which the current source 41 is turned on among the voltage ranges A1 to A3. Also, although the current source 43 was on in all the voltage ranges A1 to A3, the current source 43 may be turned on only when the voltage range is the remaining voltage range excluding the voltage ranges in which the current sources 41 and 42 are turned on among the voltage ranges A1 to A3.

[0095] (Seventh Embodiment) Next, the operational amplifier 1G of the seventh embodiment will be described with reference to FIG. 11. The difference between the first embodiment and the seventh embodiment lies in the configuration of the PNP circuit 2G. The PNP circuit 2G of the seventh embodiment uses trimming resistors Rt5G and Rt6G instead of the resistors R1 and R3. Since the configurations other than the trimming resistors Rt5G and Rt6G are the same as those of the first embodiment, detailed description thereof will be omitted here.

[0096] Next, the operation of the operational amplifier 1G of the seventh embodiment having the above-described configuration will be described with reference to FIG. 10. In FIG. 10, read "trimming resistor Rt5G" and "trimming resistor Rt6G" instead of "trimming resistor Rt5" and "trimming resistor Rt6". The operational amplifier 1G of this embodiment cuts off the current from the current sources 41 and 42 to the trimming resistors Rt1 to Rt4 in the voltage range A2. The trimming resistors Rt5G and Rt6G are trimmed so that the input offset voltage in the voltage range A2 becomes equal to 0V.

[0097] When the input offset voltage is as shown in FIG. 10, the input offset voltage is -0.8 mV in the voltage range A2. The trimming resistors Rt5G and Rt6G are adjusted to increase the input offset voltage by +0.8 mV and make it 0V as shown by the dashed-dotted line.

[0098] In voltage range A1, operational amplifier 1G supplies current from current source 41 to trimming resistors Rt1 and Rt2, and cuts off the current from current source 42 to trimming resistors Rt3 and Rt4. The trimming resistors Rt1 and Rt2 are adjusted so that the input offset voltage in voltage range A1 becomes 0V.

[0099] In the case shown in FIG. 10, after adjusting the trimming resistors Rt5G and Rt6G, the input offset voltage in voltage range A1 is -0.5 mV. The trimming resistors Rt1 and Rt2 are adjusted to increase the input offset voltage by +0.5 mV as shown by the solid line to make it 0V.

[0100] In voltage range A3, operational amplifier 1G supplies current from current source 42 to trimming resistors Rt3 and Rt4, and cuts off the current from current source 41 to trimming resistors Rt1 and Rt2. The trimming resistors Rt3 and Rt4 are adjusted so that the input offset voltage in voltage range A3 becomes 0V.

[0101] In the case shown in FIG. 10, as shown by the dashed-dotted line, after adjusting the trimming resistors Rt5G and Rt6G, voltage range A3 is +2.0 mV. The trimming resistors Rt3 and Rt4 are adjusted to decrease the input offset voltage by -2.0 mV as shown by the solid line to make it 0V. By the above operations, the input offset voltage can be reduced over voltage ranges A1 to A3.

[0102] When the operational amplifier 1G is not fast, the current I1 does not have to be large. Therefore, the resistance values of the trimming resistors Rt5G and Rt6G can be somewhat large, and the trimming accuracy does not decrease.

[0103] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the materials, shapes, dimensions, numbers, arrangement locations, etc. of the respective components in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

[0104] In the above-described embodiment, the transistor was composed of bipolar transistors, but it is not limited to this. A field-effect transistor may be used instead of the bipolar transistor. In this case, "PNP type", "PNP" can be read as "P channel", "NPN type", "NPN" as "N channel", "base" as "gate", "emitter" as "source", and "collector" as "drain" for explanation.

Explanation of Signs

[0105] 1,1B~1G operational amplifier 2,2E,2G PNP circuit (first amplification circuit) 3,3D NPN circuit (second amplification circuit) 21 current source (first current circuit, third current circuit) 21E current circuit (first current circuit) 22 current source (second current circuit, fourth current circuit) 22D current circuit (second current circuit) 41 current source (third current circuit) 41B,41E current circuit (third current circuit) 42 current source (fourth current circuit) 43 current source (fifth current circuit) A1~A3 voltage range (first to third voltage ranges) Q1 differential transistor (first differential transistor) Q2 differential transistor (second differential transistor) Q3 differential transistor (third differential transistor) Q4 differential transistor (fourth differential transistor) Q5 transistor (fifth transistor) Q6 transistor (sixth transistor) Q7 transistor (seventh transistor) Q8 transistor (eighth transistor) Q9 transistor (ninth transistor) Q10 transistor (tenth transistor) R1 to R8 Resistors (First Resistor to Eighth Resistor) Rt1 to Rt6 Trimming Resistors (First Trimming Resistor to Sixth Trimming Resistor) Rt5G Trimming Resistor (Fifth Trimming Resistor) Rt6G Trimming Resistor (Sixth Trimming Resistor) T21 Negative Power Supply Terminal (First Power Supply Terminal) T22 Positive Power Supply Terminal (Second Power Supply Terminal) VEE Negative Power Supply Voltage (First Power Supply Voltage) VCC Positive Power Supply Voltage (Second Power Supply Voltage)

Claims

1. a first current circuit; a first differential transistor and a second differential transistor, having their emitters or sources commonly connected, and shunting the current from the first current circuit; a first resistor and a second resistor connected in series between the collector or drain of the first differential transistor and a first power supply terminal supplied with a first power supply voltage; a first amplifier circuit having a third resistor and a fourth resistor connected in series between the collector or drain of the second differential transistor and the first power supply terminal; a second current circuit; a third differential transistor and a fourth differential transistor, having their emitters or sources commonly connected, shunting the current from the second current circuit, and having a reverse polarity to the first differential transistor and the second differential transistor; a fifth resistor and a sixth resistor connected in series between the collector or drain of the third differential transistor and a second power supply terminal supplied with a second power supply voltage; a second amplifier circuit having a seventh resistor and an eighth resistor connected in series between the collector or drain of the fourth differential transistor and the second power supply terminal; a third current circuit; a first adjustable resistor and a second adjustable resistor, connected in series between the connection point of the first resistor and the second resistor and the connection point of the third resistor and the fourth resistor, and shunting the current from the third current circuit; a fourth current circuit; a third adjustable resistor and a fourth adjustable resistor, connected in series between the connection point of the fifth resistor and the sixth resistor and the connection point of the seventh resistor and the eighth resistor, and shunting the current from the fourth current circuit; an operational amplifier provided such that the current supplied from at least one of the third current circuit and the fourth current circuit can be turned on and off; an operational amplifier.

2. In the operational amplifier according to Claim 1, a fifth current circuit; a fifth adjustable resistor and a sixth adjustable resistor, connected in series between the connection point of the first resistor and the second resistor and the connection point of the third resistor and the fourth resistor, or between the connection point of the fifth resistor and the sixth resistor and the connection point of the seventh resistor and the eighth resistor, and shunting the current from the fifth current circuit. The fifth adjustment resistor and the sixth adjustment resistor are connected in parallel with the first adjustment resistor and the second adjustment resistor, or the third adjustment resistor and the fourth adjustment resistor, operational amplifier. **Claim 3** In the operational amplifier according to claim 2, when the input common-mode voltage range in which only the first amplification circuit can operate is defined as a first voltage range, the input common-mode voltage range in which both the first amplification circuit and the second amplification circuit can operate is defined as a second voltage range, and the input common-mode voltage range in which only the second amplification circuit can operate is defined as a third voltage range, the third current circuit has a current turned on only when the input common-mode voltage is one of the first voltage range to the third voltage range, the fourth current circuit has a current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage range in which the third current circuit is turned on among the first voltage range to the third voltage range, the fifth current circuit has a current turned on when the input common-mode voltage is in the first voltage range to the third voltage range, or has a current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage ranges in which the third current circuit and the fourth current circuit are turned on among the first voltage range to the third voltage range, operational amplifier. **Claim 4** In the operational amplifier according to claim 1, the first resistor connected to the first differential transistor side and the third resistor connected to the second differential transistor side are composed of a fifth adjustment resistor and a sixth adjustment resistor whose resistance values are adjustable, operational amplifier. **Claim 5** In the operational amplifier according to claim 1 or 4, when the input common-mode voltage range in which only the first amplification circuit can operate is defined as a first voltage range, the input common-mode voltage range in which both the first amplification circuit and the second amplification circuit can operate is defined as a second voltage range, and the input common-mode voltage range in which only the second amplification circuit can operate is defined as a third voltage range, the third current circuit has a current turned on only when the input common-mode voltage is one of the first voltage range to the third voltage range, the fourth current circuit has a current turned on only when the input common-mode voltage is one of the remaining voltage ranges excluding the voltage range in which the third current circuit is turned on among the first voltage range to the third voltage range, operational amplifier. **Claim 6** In the operational amplifier according to claim 1, When the input non-inverting voltage is within a predetermined fourth voltage range, supply current from the first current circuit to the first differential transistor and the second differential transistor, and cut off the current supplied from the second current circuit to the third differential transistor and the fourth differential transistor. A switching unit that supplies current from the second current circuit to the third differential transistor and the fourth differential transistor and cuts off the current supplied from the first current circuit to the first differential transistor and the second differential transistor when the input non-inverting voltage is within a predetermined fifth voltage range. Operational amplifier.

7. In the operational amplifier according to claim 6, the third current circuit has current turned on only when the input non-inverting voltage is within the fourth voltage range, the fourth current circuit has current turned on only when the input non-inverting voltage is within the fifth voltage range. Operational amplifier.

8. In the operational amplifier according to claim 6, the second current circuit forms a current mirror circuit and has a fifth transistor connected in diode connection and a sixth transistor that folds back the current flowing through the fifth transistor, the fifth transistor is connected in series to the first current circuit, the sixth transistor is connected between the emitters or sources of the third differential transistor and the fourth differential transistor and the first power supply terminal, the switching unit is connected between the first current circuit and the fifth transistor, the fourth current circuit forms a current mirror circuit with the fifth transistor and has a seventh transistor that folds back the current flowing through the fifth transistor, the seventh transistor is connected between the connection point of the third adjustment resistor and the fourth adjustment resistor and the first power supply terminal, the first current circuit forms a current mirror circuit with an eighth transistor to which current is supplied from a current source and has a ninth transistor that folds back the current flowing through the eighth transistor, the third current circuit forms a current mirror circuit with the eighth transistor and has a tenth transistor that folds back the current flowing through the eighth transistor, the tenth transistor is connected between the connection point of the first adjustment resistor and the second adjustment resistor and the second power supply terminal. Operational amplifier.

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