Electro-optical device and electronic apparatus

Abstract

To provide an electro-optical device and an electronic apparatus that can prevent damage to a gate insulating film.SOLUTION: An electro-optical device comprises: a substrate; a transistor having a semiconductor layer, a gate insulating film, and a gate electrode, arranged side by side in a direction away from the substrate; a first insulating layer covering the transistor; a first contact provided on the first insulating layer and connected to the gate electrode; a first light shielding film provided on the first insulating layer; and a second light shielding film provided between the substrate and the semiconductor layer. The second light shielding film has, when seen in the normal direction of the substrate, a first portion overlapping the semiconductor layer, and a second portion overlapping the first light shielding film at a position different from the semiconductor layer.SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to an electro-optical device and an electronic device.

Background Art

[0002] In electronic devices such as projectors, electro-optical devices such as liquid crystal display devices whose optical characteristics can be changed for each pixel are used. As an example of the electro-optical device, the electro-optical device described in Patent Document 1 is known.

[0003] The electro-optical device described in Patent Document 1 includes a transistor having a semiconductor layer, a gate electrode, and a gate insulating film provided therebetween. The gate electrode of the transistor is electrically connected to a first contact hole provided in an interlayer insulating film in a layer above it. Further, a light-shielding layer is provided below the transistor. The light-shielding layer overlaps the gate electrode and the gate insulating film in a plan view.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, when the light-shielding layer overlaps the gate insulating film in a plan view, when forming a hole for forming the first contact hole in the interlayer insulating layer by etching, the gate insulating film may be damaged by the etching.

Means for Solving the Problems

[0006] One aspect of the electro-optical device of the present invention includes a substrate, a transistor having a semiconductor layer, a gate insulating film, and a gate electrode arranged in a direction away from the substrate, a first insulating layer covering the transistor, a first contact provided on the first insulating layer and connected to the gate electrode, a first light-shielding film provided on the first insulating layer, and a second light-shielding film provided in a layer between the substrate and the semiconductor layer. The second light-shielding film has a first portion overlapping the semiconductor layer and a second portion overlapping the first light-shielding film at a position different from the semiconductor layer when viewed in the normal direction of the substrate.

[0007] One aspect of the electronic device of the present invention includes an electro-optical device and a control unit that controls the operation of the electro-optical device.

Brief Description of the Drawings

[0008]

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Best Mode for Carrying Out the Invention

[0009] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Note that the dimensions or scales of each part in the drawings are appropriately different from the actual ones, and there are also parts schematically shown for easy understanding. Also, the scope of the present invention is not limited to these embodiments unless there is a description specifically limiting the present invention in the following description.

[0010] A. Electro-optical device 1. Basic configuration FIG. 1 is a plan view of an electro-optical device 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line A-A of the electro-optical device 100 shown in FIG. 1. Hereinafter, for convenience of explanation, the X-axis, Y-axis, and Z-axis that are perpendicular to each other will be appropriately used for explanation. Also, one direction along the X-axis is denoted as the X1 direction, and the direction opposite to the X1 direction is denoted as the X2 direction. Similarly, one direction along the Y-axis is denoted as the Y1 direction, and the direction opposite to the Y1 direction is denoted as the Y2 direction. One direction along the Z-axis is denoted as the Z1 direction, and the direction opposite to the Z1 direction is denoted as the Z2 direction.

[0011] Also, in this specification, "element β on element α" means that element β is located above element α. Therefore, "element β on element α" includes not only the case where element β is in direct contact with element α, but also the case where element α and element β are separated. Also, "electrical connection" between element α and element β includes not only a configuration in which element α and element β are directly joined to conduct, but also a configuration in which element α and element β conduct indirectly via another conductor.

[0012] The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device of an active matrix driving method. The electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. As shown in FIG. 2, the element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in the Z1 direction in this order. Note that "plan view" means viewing from the Z1 direction or Z2 direction, which is the overlapping direction of these. Also, the shape of the electro-optical device 100 in plan view shown in FIG. 1 is a quadrilateral, but it may be a polygon other than a quadrilateral or a circle.

[0013] The element substrate 2 shown in FIG. 2 includes a first substrate 21 having translucency, a laminate 22 having translucency, a plurality of pixel electrodes 25 having translucency, and a first alignment film 29 having translucency. The first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 are laminated in the Z1 direction in this order. Note that "translucency" means transmittance with respect to visible light, and preferably the transmittance of visible light is 50% or more.

[0014] The first substrate 21 corresponds to the "substrate". The first substrate 21 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The normal direction of the first substrate 21 coincides with the direction along the Z-axis. The laminate 22 includes a plurality of insulating films having translucency. In addition, various wirings and the like are provided on the laminate 22. The pixel electrode 25 is used to apply an electric field to the liquid crystal layer 5. The pixel electrode 25 includes a transparent conductive material such as, for example, ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). Although not shown, the element substrate 2 has a plurality of dummy pixel electrodes that surround the plurality of pixel electrodes 25 in a plan view. The first alignment film 29 has translucency and insulation. The first alignment film 29 aligns the liquid crystal molecules of the liquid crystal layer 5. The first alignment film 29 is disposed so as to cover the plurality of pixel electrodes 25. The material of the first alignment film 29 is, for example, polyimide and silicon oxide.

[0015] The counter substrate 3 is disposed to face the element substrate 2. The counter substrate 3 includes a second substrate 31 having translucency, an inorganic insulating layer 32 having translucency, a common electrode 33 having translucency, and a second alignment film 34 having translucency. Although not shown, the counter substrate 3 has a light-shielding cut-off that surrounds the plurality of pixel electrodes 25 in a plan view. Note that the "light-shielding property" means light-shielding property against visible light, preferably a transmittance of visible light of less than 50%, more preferably 10% or less.

[0016] The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are laminated in this order in the Z2 direction. The second substrate 31 is a flat plate having translucency and insulation, and is composed of, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 has translucency and insulation, and is formed of an inorganic material containing silicon such as silicon oxide. The common electrode 33 is a counter electrode disposed with respect to the plurality of pixel electrodes 25 via the liquid crystal layer 5. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 has translucency and conductivity. The common electrode 33 contains, for example, a transparent conductive material such as ITO, IZO, and FTO. The second alignment film 34 has translucency and insulation. The second alignment film 34 aligns the liquid crystal molecules included in the liquid crystal layer 5. The material of the second alignment film 34 is, for example, polyimide and silicon oxide.

[0017] The seal member 4 is disposed between the element substrate 2 and the counter substrate 3. The seal member 4 is formed using an adhesive or the like containing various curable resins such as epoxy resin. The seal member 4 may include a gap material composed of an inorganic material such as glass.

[0018] The liquid crystal layer 5 is disposed in a region surrounded by the element substrate 2, the counter substrate 3, and the seal member 4. The liquid crystal layer 5 is an electro-optic layer whose optical characteristics change in response to an electric field. The liquid crystal layer 5 contains liquid crystal molecules having positive or negative dielectric anisotropy. The alignment of the liquid crystal molecules changes according to the voltage applied to the liquid crystal layer 5.

[0019] Such an electro-optical device 100 has a display region A10 for displaying an image and a peripheral region A20 located outside the display region A10 in a plan view. In the display region A10, a plurality of pixels P arranged in a matrix are provided. A plurality of pixel electrodes 25 are arranged one-to-one with respect to the plurality of pixels P. The aforementioned common electrode 33 is provided in common for the plurality of pixels P. Further, the peripheral region A20 surrounds the display region A10 in a plan view.

[0020] In this embodiment, the electro-optical device 100 is a transmissive type. Specifically, as shown in FIG. 2, after the light LL is incident on the counter substrate 3, an image is displayed by modulating the light while it is being emitted from the element substrate 2. Note that an image may also be displayed by modulating the light while it is being incident on the element substrate 2 and being emitted from the counter substrate 3.

[0021] Further, the electro-optical device 100 is applied to a display device that performs color display, such as a personal computer and a smartphone, which will be described later. When applied to the display device, a color filter is appropriately used for the electro-optical device 100. Further, the electro-optical device 100 is applied to a projection type projector, which will be described later, for example. In this case, the electro-optical device 100 functions as a light valve. Note that in this case, the color filter is omitted for the electro-optical device 100.

[0022] 2. Peripheral Circuit FIG. 3 is a diagram schematically showing the peripheral circuit 10 in the electro-optical device 100 of FIG. 1. As shown in FIG. 3, in the peripheral region A20 of the electro-optical device 100, the peripheral circuit 10 and a plurality of external terminals 13 are provided. The plurality of external terminals 13 are connected to wirings (not shown) routed from the peripheral circuit 10.

[0023] In addition, n scanning lines 241 and m data lines 242 are arranged in the display region A10. n and m are each an integer of 2 or more. The n scanning lines 241 extend in a direction along the X axis and are arranged at equal intervals in a direction along the Y axis. The m data lines 242 extend in a direction along the Y axis and are arranged at equal intervals in a direction along the X axis. The n scanning lines 241 and the m data lines 242 are electrically insulated from each other and are arranged in a grid pattern in a plan view. A region surrounded by two adjacent scanning lines 241 and two adjacent data lines 242 corresponds to a pixel P.

[0024] Examples of the peripheral circuit 10 include two scanning line driving circuits 11, a data line driving circuit 12, an inspection circuit 14, and a sampling circuit 15.

[0025] In the illustrated example, the two scanning line driving circuits 11 are arranged with the display area A10 therebetween. The scanning line driving circuit 11 includes a plurality of transistors. For example, the scanning line driving circuit 11 disposed on the left side of the display area A10 drives the odd-numbered scanning lines 241, and the scanning line driving circuit 11 disposed on the right side of the display area A10 drives the even-numbered scanning lines 241. Note that the same scanning line 241 may be driven by the scanning line driving circuits 11 disposed on both the left and right sides thereof.

[0026] The inspection circuit 14 is disposed, for example, on the side opposite to the plurality of external terminals 13 of the display area A10. A data line 242 is connected to the inspection circuit 14. The inspection circuit 14 is used to inspect operation defects or the like of the electro-optical device 100 by detecting an image signal during the manufacture or shipment of the electro-optical device 100. The inspection circuit 14 has, for example, transistors provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to an inspection line (not shown). In addition, the gate of each transistor is electrically connected to a control signal line (not shown).

[0027] The data line driving circuit 12 and the sampling circuit 15 are disposed, for example, on the side opposite to the inspection circuit 14 of the display area A10. The data line driving circuit 12 is electrically connected to the m data lines 242 via the sampling circuit 15. Based on the sampling signal output from the data line driving circuit 12, the sampling circuit 15 samples the image signal and supplies it to the data line 242.

[0028] The sampling circuit 15 has transistors provided for each data line 242. One source / drain region of the transistor is electrically connected to the data line 242, and the other source / drain region is connected to a constant potential line (not shown). In addition, the gate of each transistor is electrically connected to a signal line to which a sampling signal (not shown) is supplied.

[0029] 3. Electrical Configuration of Element Substrate 2 FIG. 4 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 in FIG. 1. As shown in FIG. 4, in the display area A10 of the element substrate 2, a second transistor 23, a pixel electrode 25, and a capacitor element 24 are provided for each pixel P. The second transistor 23 is, for example, a TFT (Thin Film Transistor) that functions as a switching element. Each second transistor 23 includes a gate, a source, and a drain. The pixel electrode 25 is electrically connected to the drain of the corresponding second transistor 23. In addition, as described above, n scanning lines 241 and m data lines 242 are arranged in the display area A10, and n constant potential lines 243 are also arranged.

[0030] Each of the n scanning lines 241 is electrically connected to the gates of a corresponding plurality of second transistors 23. Scanning signals G1, G2,..., and Gn are sequentially supplied from the scanning line driving circuit 11 described above to the 1st to nth scanning lines 241.

[0031] Each of the m data lines 242 is electrically connected to the sources of a corresponding plurality of second transistors 23. Image signals S1, S2,..., and Sm are supplied in parallel from the data line driving circuit 12 described above to the 1st to mth data lines 242 via the sampling circuit 15.

[0032] The n constant potential lines 243 extend in the X1 direction and are arranged at equal intervals in the Y2 direction. Also, the n constant potential lines 243 are electrically insulated from the n scanning lines 241 and the m data lines 242 and are arranged at intervals with respect to these. A constant potential Vcom is applied to each constant potential line 243. Each of the n constant potential lines 243 is electrically connected to one of the two electrodes of the corresponding capacitor element 24. Also, the other of the two electrodes of each capacitor element 24 is electrically connected to the corresponding pixel electrode 25. Each capacitor element 24 is a holding capacitor for holding the potential of the pixel electrode 25. A constant potential Vcom is applied to one electrode of the capacitor element 24, and the other electrode is electrically connected to the drain of the second transistor 23.

[0033] When the scanning signals G1, G2, …, and Gn are sequentially activated and the n scanning lines 241 are sequentially selected, the second transistor 23 connected to the selected scanning line 241 is turned on. Then, image signals S1, S2, …, and Sm having magnitudes corresponding to the gradations to be displayed are taken into the pixel P corresponding to the selected scanning line 241 via the m data lines 242 and applied to the pixel electrode 25. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitance formed between the pixel electrode 25 and the common electrode 33 in FIG. 2, and the alignment of the liquid crystal molecules changes according to the applied voltage. Further, the applied voltage is held by the capacitive element 24. Such a change in the alignment of the liquid crystal molecules modulates light and enables gradation display.

[0034] 4. Display area A10 FIG. 5 shows a part of the element substrate 2 in the display area A10 of FIG. 2. As shown in FIG. 5, the display area A10 has a plurality of opening areas A11 and a light-shielding area A12. The plurality of opening areas A11 are arranged in a matrix in a plan view. The shape of the light-shielding area A12 in a plan view is a frame shape located between the plurality of opening areas A11. Each opening area A11 is an area where the pixel electrode 25 is arranged and is an area where light passes through. On the other hand, the second transistor 23 is arranged in the light-shielding area A12, which is an area having light-shielding properties. Although not shown in FIG. 5, various wirings such as the scanning line 241, the data line 242, and the constant potential line 243 shown in FIG. 4 and the capacitive element 24 are arranged in the light-shielding area A12.

[0035] 5. Configuration of the light-shielding area A12 of the element substrate 2 FIG. 6 is a cross-sectional view taken along the line A1 - A1 of FIG. 2. FIG. 7 is a cross-sectional view taken along the line A2 - A2 in FIG. 5.

[0036] As shown in FIGS. 6 and 7, the element substrate 2 includes a first substrate 21 which is a "substrate" and a laminate 22. The laminate 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229. The insulating layers 221, 222, 223, 224, 225, 226, 227, 228, and 229 are laminated in this order from the first substrate 21. Also, the insulating layers 223 and 224 constitute a first insulating layer 220. The insulating layers 221 to 229 have translucency and insulation properties. Each material of the insulating layers 221 to 229 is, for example, an inorganic material containing silicon such as silicon oxide and silicon oxynitride.

[0037] In the light-shielding region A12 of the laminate 22, the aforementioned second transistor 23, capacitor element 24, scanning line 241, and data line 242 are arranged. Further, third light-shielding films 244 and 240 are provided on the laminate 22. Also, relay electrodes 245, 246, 247, 248, and 249 are arranged on the laminate 22. Further, a fourth light-shielding film 210 is arranged on the first substrate 21.

[0038] As described above, the first substrate 21 is composed of, for example, a glass substrate or a quartz substrate. The first substrate 21 has a recess H1. The recess H1 is a depression formed in the first substrate 21 and is formed for each second transistor 23. The recess H1 is formed along the Y1 direction which is the extending direction of a second semiconductor layer 231 described later.

[0039] The fourth light-shielding film 210 is arranged in the recess H1. The fourth light-shielding film 210 is formed using, for example, a damascene method. The fourth light-shielding film 210 is provided to prevent light from entering the second semiconductor layer 231 of the second transistor 23. Note that the first substrate 21 may not have the recess H1. In this case, the fourth light-shielding film 210 is arranged on a flat surface facing the Z1 direction of the first substrate 21.

[0040] On the insulating layer 221, a second transistor 23 is disposed. The second transistor 23 includes a second semiconductor layer 231, a second gate insulating film 233, and a second gate electrode 232, which are arranged in a direction away from the first substrate 21. The second semiconductor layer 231 is disposed on the insulating layer 221. The second gate electrode 232 is disposed on the insulating layer 222. The second gate insulating film 233 is interposed between the second gate electrode 232 and the second semiconductor layer 231. The region of the insulating layer 222 corresponding to the second gate electrode 232 in plan view corresponds to the second gate insulating film 233.

[0041] The second transistor 23 has, for example, an LDD (Lightly Doped Drain) structure. The second semiconductor layer 231 extends in a direction along the Y-axis. The second semiconductor layer 231 includes a drain region 231a, a source region 231b, a channel region 231c, a lightly doped drain region 231d, and a lightly doped source region 231e. The channel region 231c is located between the drain region 231a and the source region 231b. The lightly doped drain region 231d is located between the channel region 231c and the drain region 231a. The lightly doped source region 231e is located between the channel region 231c and the source region 231b. The second semiconductor layer 231 is formed of, for example, polysilicon. Regions excluding the channel region 231c are doped with impurities to increase conductivity. The impurity concentration in the lightly doped drain region 231d is lower than the impurity concentration in the drain region 231a. The impurity concentration in the lightly doped source region 231e is lower than the impurity concentration in the source region 231b. Note that, for example, the second transistor 23 may not have an LDD structure, and for example, the lightly doped source region 231e may be omitted.

[0042] The second gate electrode 232 is formed, for example, by doping polysilicon with impurities that enhance conductivity. Note that the second gate electrode 232 may be formed using a material having conductivity such as a metal, a metal oxide, and a metal compound. The second gate electrode 232 overlaps with the channel region 231c of the second semiconductor layer 231 in plan view. Further, the second gate insulating film 233 is composed of, for example, a silicon oxide film formed by thermal oxidation or a CVD (chemical vapor deposition) method or the like. Such a second transistor 23 overlaps with the fourth light-shielding film 210 in plan view.

[0043] As shown in FIG. 6, a third light-shielding film 244 and 240 are disposed on the insulating layer 223. The third light-shielding film 240 covers the low-concentration drain region 231d of the second semiconductor layer 231 in plan view. The third light-shielding film 240 is connected to the drain region 231a of the second semiconductor layer 231 via a contact 270. Therefore, the third light-shielding film 240 is the pixel potential. For example, the contact 270 is a contact plug that fills a hole penetrating the insulating layers 222 and 223. Further, the contact 270 has a portion that covers the low-concentration drain region 231d in plan view. Note that the third light-shielding film 240 and the contact 270 are, for example, integrated and formed by a damascene method.

[0044] The third light-shielding film 244 is electrically connected to the source region 231b of the second semiconductor layer 231 via a contact 271. For example, the contact 271 is a contact plug that fills a hole penetrating the insulating layers 222 and 223. Note that the third light-shielding film 244 and the contact 271 are, for example, integrated and formed by a damascene method.

[0045] A second contact 7 is disposed in the insulating layers 221 to 224. The second contact 7 is formed using, for example, a damascene method. As shown in FIG. 6, the second contact 7 fills a contact hole H3 that is a hole penetrating the insulating layers 223 and 224.

[0046] As shown in FIG. 7, the second contact 7 is electrically connected to the second gate electrode 232. The second contact 7 is arranged so as to surround the second gate electrode 232 from the directions along the Z axis and the Y axis. Also, a part of the second contact 7 fills a hole penetrating the insulating layers 221 and 222 and is electrically connected to the fourth light-shielding film 210. The fourth light-shielding film 210 functions as a back gate.

[0047] Although not shown in detail, the low-concentration drain region 231d is surrounded by the second contact 7, the third light-shielding film 240, and the contact 270. Therefore, the incidence of light on the low-concentration drain region 231d can be suppressed. Thus, it is possible to suppress the operation of the second transistor 23 from becoming unstable due to the incidence of such light. As a result, it is possible to suppress the occurrence of display defects such as luminance unevenness. Therefore, it is possible to suppress a decrease in display quality.

[0048] As shown in FIG. 6, a scanning line 241, a relay electrode 245, and a relay electrode 246 are arranged on the insulating layer 224. The scanning line 241 is electrically connected to the second gate electrode 232 via the second contact 7 penetrating the insulating layers 223 and 224. The relay electrode 245 is electrically connected to the third light-shielding film 240 via a contact 272 penetrating the insulating layer 224. The relay electrode 246 is electrically connected to the third light-shielding film 244 via a contact 273 penetrating the insulating layer 224.

[0049] A relay electrode 247 and a relay electrode 248 are arranged on the insulating layer 225. The relay electrode 247 is electrically connected to the relay electrode 246 via a contact 275 penetrating the insulating layer 225. Also, the relay electrode 248 is electrically connected to the relay electrode 245 via a contact 274 penetrating the insulating layer 225.

[0050] On the insulating layer 226, a data line 242 is disposed. The data line 242 is electrically connected to the relay electrode 247 via a contact 276 penetrating the insulating layer 226. Therefore, the data line 242 is electrically connected to the source region 231b via the contact 276, the relay electrode 247, the contact 275, the relay electrode 246, the contact 273, the third light-shielding film 244, and the contact 271.

[0051] As shown in FIG. 7, on the insulating layer 226, a relay electrode 249 is disposed. The relay electrode 249 is electrically connected to the relay electrode 248 via a contact 277 penetrating the insulating layer.

[0052] On the insulating layer 227, a capacitor element 24 is disposed. The capacitor element 24 has a pair of electrodes 2401 and 2402 and a dielectric layer 2403. The electrode 2401 is disposed on the insulating layer 227. The electrode 2402 is disposed on the insulating layer 228. The dielectric layer 2403 is disposed between the electrode 2401 and the electrode 2402. The electrode 2401 also serves as the constant potential line 243 in FIG. 4. Further, as shown in FIG. 7, the electrode 2402 is electrically connected to the relay electrode 249 via a contact 278 penetrating the insulating layers 227 and 228. Therefore, as shown in FIG. 6 or FIG. 7, the electrode 2402 is electrically connected to the drain region 231a via the contact 278, the relay electrode 249, the contact 277, the relay electrode 248, the contact 274, the relay electrode 245, the contact 272, the third light-shielding film 240, and the contact 270.

[0053] As shown in FIG. 6, on the insulating layer 229, a pixel electrode 25 is disposed. The pixel electrode 25 is electrically connected to the electrode 2402 via a contact 279 penetrating the insulating layer 229.

[0054] Each of the foregoing scanning line 241, data line 242, electrodes 2401, 2402, third light-shielding films 244 and 240, relay electrodes 245, 246, 247, 248, and 249 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron, and aluminum (Al), metal nitrides, and metal silicides. These may be single-layer or laminated. For example, these are composed of a laminate of an aluminum film and a titanium nitride film.

[0055] Each of the foregoing contacts 270, 271 to 279 includes, for example, metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), metal nitrides, and metal silicides. Each of contacts 270, 271 to 279 may be single-layer or laminated. Also, each of contacts 270, 271 to 279 may be integrally formed with the electrode or wiring to which it is connected, or may be formed separately.

[0056] Note that the arrangement of wirings, electrodes, etc. in the light-shielding region A12 shown in FIGS. 6 and 7 is an example. For example, other capacitive elements than the capacitive element 24 may be provided in the light-shielding region A12. The scanning line 241, data line 242, and capacitive element 24 are arranged in this order in the Z1 direction, but they do not have to be arranged in this order.

[0057] 6. Configuration of Peripheral Region A20 of Element Substrate 2 In FIG. 8, a part of the scanning line driving circuit 11 in the peripheral region A20 of FIG. 3 is shown. As shown in FIG. 8, unit circuits 22a are provided in the laminate 22. The unit circuits 22a are provided, for example, for each scanning line 241. The unit circuit 22a includes a transistor 26. Also, first light-shielding films 281 and 282 are provided in the laminate 22. Also, relay electrodes 283, 284, 285, and 286 are provided in the laminate 22. Also, a peripheral electrode 250 is disposed on the laminate 22. The peripheral electrode 250 is, for example, an electrode for an ion trap. Also, a plurality of second light-shielding films 211 are disposed on the first substrate 21.

[0058] The first substrate 21 has a plurality of recesses H0. Each recess H0 is a depression formed in the first substrate 21. A second light-shielding film 211 is disposed in each recess H1. The second light-shielding film 211 is formed, for example, using a damascene process. The second light-shielding film 211 is provided to prevent light from entering the semiconductor layer 261 of the transistor 26. Note that the first substrate 21 may not have the recess H0. In this case, the second light-shielding film 211 is disposed on the flat surface facing the Z1 direction of the first substrate 21.

[0059] A transistor 26 is disposed on the insulating layer 221. The transistor 26 has a semiconductor layer 261, a gate insulating film 263, and a gate electrode 262, which are arranged in a direction away from the first substrate 21. The semiconductor layer 261 is disposed on the insulating layer 221. The semiconductor layer 261 is disposed in the same layer as the second semiconductor layer 231 provided in the light-shielding region A12. The gate electrode 262 is disposed on the insulating layer 222. The gate electrode 262 is disposed in the same layer as the second gate electrode 232 provided in the light-shielding region A12. The gate insulating film 263 is interposed between the second gate electrode 232 and the second semiconductor layer 231. The gate insulating film 263 is disposed in the same layer as the second gate insulating film 233 provided in the light-shielding region A12. The region of the insulating layer 222 corresponding to the gate electrode 262 in plan view corresponds to the gate insulating film 263. Also, the insulating layers 223 and 224 are the first insulating layer 220 that covers the transistor 26.

[0060] The transistor 26 has, for example, an LDD structure. The semiconductor layer 261 has a drain region 261a, a source region 261b, a channel region 261c, a lightly doped drain region 261d, and a lightly doped source region 261e. The channel region 261c is located between the drain region 261a and the source region 261b. The lightly doped drain region 261d is located between the channel region 261c and the drain region 261a. The lightly doped source region 261e is located between the channel region 261c and the source region 261b. The semiconductor layer 261 is formed of, for example, polysilicon. Regions excluding the channel region 261c are doped with impurities to enhance conductivity. The impurity concentration in the lightly doped drain region 261d is lower than the impurity concentration in the drain region 261a. The impurity concentration in the lightly doped source region 261e is lower than the impurity concentration in the source region 261b. Note that, for example, the transistor 26 may not have an LDD structure, and for example, the lightly doped source region 261e may be omitted.

[0061] The gate electrode 262 is formed, for example, by doping polysilicon with impurities to enhance conductivity. Note that the gate electrode 262 may be formed using a material having conductivity such as a metal, a metal oxide, and a metal compound. The gate electrode 262 overlaps the channel region 261c of the semiconductor layer 261 in plan view. Also, the gate insulating film 263 is composed of, for example, a silicon oxide film formed by thermal oxidation or a CVD method or the like.

[0062] Also, a first light-shielding film 281 and 282 are disposed on the insulating layer 223. The first light-shielding film 281 is electrically connected to the drain region 261a of the semiconductor layer 261 via a contact 291. Also, the first light-shielding film 282 is electrically connected to the source region 261b of the semiconductor layer 261 via a contact 292.

[0063] On the insulating layer 224, relay electrodes 280, 283, and relay electrode 284 are arranged. The relay electrode 280 is electrically connected to the gate electrode 262 through a first contact 290 that fills a contact hole H2 which is a hole penetrating the insulating layers 223 and 224. The relay electrode 283 is electrically connected to the first light-shielding film 281 through a contact 293 penetrating the insulating layer 224. The relay electrode 284 is electrically connected to the first light-shielding film 282 through a contact 294 penetrating the insulating layer 224.

[0064] On the insulating layer 225, relay electrodes 285 and relay electrode 286 are arranged. The relay electrode 285 is electrically connected to the relay electrode 283 through a contact 295 penetrating the insulating layer 225. The relay electrode 286 is electrically connected to the relay electrode 284 through a contact 296 penetrating the insulating layer 225. Each of the relay electrode 285 and the relay electrode 286 is electrically connected to an element such as another transistor adjacent to the transistor 26.

[0065] Note that various wirings, electrodes, or light-shielding layers (not shown) may be arranged in the insulating layer 226. Also, on the insulating layer 229, a peripheral electrode 250 is arranged. The peripheral electrode 250 is arranged in the same layer as the pixel electrode 25.

[0066] In addition, from the viewpoint of manufacturing ease, the various wirings or electrodes arranged in the light-shielding region A12 and the various wirings or electrodes arranged in the peripheral region A20 are preferably formed of the same material for each layer.

[0067] 7. Unit circuit 22a FIG. 9 is a diagram showing a planar arrangement of the transistors 26 and 27 included in the unit circuit 22a of FIG. 8. A cross-section taken along line B3 - B3 in FIG. 9 corresponds to the diagram of FIG. 8. Also, FIG. 10 is a diagram showing a planar arrangement of the second light-shielding film 211 and the semiconductor layer 261 of FIG. 8. FIG. 11 is a diagram showing a planar arrangement of the first light-shielding films 281 and 282 and the second light-shielding film 211 of FIG. 8.

[0068] As shown in FIG. 9, the unit circuit 22a has two transistors 26. The unit circuit 22a includes, for example, a NOT circuit. One of the two transistors 26 is an n-channel MOS transistor, and the other is a p-channel MOS transistor. In the present embodiment, for the two transistors 26, the gate electrodes 262 are common.

[0069] In the present embodiment, four second light-shielding films 211 are provided as the plurality of second light-shielding films 211. In the example of FIG. 9, in addition to the plurality of second light-shielding films 211, a plurality of light-shielding films 212 are provided. The plurality of light-shielding films 212 are arranged at intervals from each other. In FIG. 9, the plurality of light-shielding films 212 are located on the left side with respect to the plurality of second light-shielding films 211.

[0070] A slit is provided between the plurality of second light-shielding films 211. Specifically, a gap S10 is provided between two second light-shielding films 211 provided on both sides along the Y-axis of the semiconductor layer 261. The gap S10 overlaps the gate electrode 262 in plan view.

[0071] As shown in FIG. 10, the semiconductor layer 261 overlaps two second light-shielding films 211 spaced apart from each other along the Y-axis. However, a part of the semiconductor layer 261 does not overlap the second light-shielding film 211 in plan view. Specifically, the channel region 261c of the semiconductor layer 261 does not overlap the second light-shielding film 211 in plan view. The plurality of light-shielding films 212 do not overlap the semiconductor layer 261.

[0072] Also, as shown in FIG. 9, the gate electrode 262 extends in the direction along the X-axis. The gate electrode 262 is arranged at a position different from that of the second light-shielding film 211 in plan view. That is, the gate electrode 262 does not overlap the second light-shielding film 211 in plan view. Therefore, the gate insulating film 263 does not overlap the second light-shielding film 211 in plan view. Also, the first contact 290 does not overlap the second light-shielding film 211 in plan view.

[0073] Also, as shown in FIGS. 11 and 8, the second light-shielding film 211 has a first portion 2111 and a second portion 2112. The first portion 2111 is a portion that overlaps with the semiconductor layer 261 in plan view. The second portion 2112 is a portion that overlaps with the first light-shielding film 281 or 282 at a position different from the semiconductor layer 261 in plan view. That is, the second portion 2112 is a portion that does not overlap with the semiconductor layer 261 in plan view and overlaps with the first light-shielding film 281 or 282 in plan view. Further, the second portion 2112 is located outside the semiconductor layer 261 in plan view. The second portion 2112 is located outside the first portion 2111 in plan view. The second portion 2112 is located on the side opposite to the semiconductor layer 261 of the first portion 2111 in plan view. In the present embodiment, the second portion 2112 is provided so as to surround the first portion 2111 in plan view.

[0074] 8. The first light-shielding film and the second light-shielding film As described above, the first light-shielding films 281 and 282 shown in FIG. 8 are provided on the first insulating layer 220. The second light-shielding film 211 is provided between the first substrate 21 and the semiconductor layer 261. Then, as shown in FIGS. 8 and 11, the second light-shielding film 211 has a first portion 2111 that overlaps with the semiconductor layer 261 when viewed in the normal direction of the first substrate 21, and a second portion 2112 that overlaps with the first light-shielding film 281 or 282 at a position different from the semiconductor layer 261. Therefore, the first light-shielding film 281 and the second light-shielding film 211 can be capacitively coupled. That is, the space between the first light-shielding film 281 and the second light-shielding film 211 can function as a capacitive coupling. Similarly, the first light-shielding film 282 and the second light-shielding film 211 can be capacitively coupled. That is, the space between the first light-shielding film 282 and the second light-shielding film 211 can function as a capacitive coupling. Therefore, when forming the contact hole H2, which is a through hole for arranging the first contact 290, the destruction of the gate insulating film 263 due to etching can be prevented. For this reason, it is possible to suppress the possibility that a malfunction occurs in the transistor 26 due to the destruction of the gate insulating film 263. Thus, a decrease in display quality can be suppressed.

[0075] FIG. 12 is a diagram for explaining the etching of the contact hole H2 in the comparative example. In the comparative example of FIG. 12, the second light-shielding film 211x does not have a portion that overlaps with the first light-shielding film 281 or 282 at a position different from the semiconductor layer 261 in plan view. In this case, when forming the contact hole H2, there is a risk that damage D2 occurs in the gate electrode 262, damage D3 occurs in the gate insulating film 263, and damage D1 occurs in the semiconductor layer 261 due to etching. This is considered to be because the electric field generated by the charge of the etching concentrates on the second light-shielding film 211x. In particular, it is considered that the electric field concentrates at the end of the second light-shielding film 211x. For this reason, there is a risk that the gate insulating film 263 that overlaps with the end of the second light-shielding film 211x in plan view will be destroyed. When damage D3 occurs in the gate insulating film 263, a leakage current may flow and the transistor 26 may malfunction.

[0076] FIG. 13 is a diagram for explaining the etching of the contact hole H2 in the present embodiment. In the transistor 26 of the present embodiment in FIG. 13, the second light-shielding film 211 has a second portion 2112 that overlaps with the first light-shielding film 281 or 282 at a position different from the semiconductor layer 261 in plan view. In this case, the first light-shielding film 281 or 282 and the second light-shielding film 211 can be capacitively coupled. That is, the space between the first light-shielding film 281 or 282 and the second light-shielding film 211 can be made to function as a capacitive coupling. Therefore, the capacitive coupling can absorb the electric field generated by the charge of the etching of the contact hole H2 described above. For this reason, the electric field concentration in the portion of the second light-shielding film 211 that overlaps with the gate insulating film 263 can be alleviated. Therefore, the risk of the gate insulating film 263 being destroyed due to the concentration of the electric field can be reduced. Therefore, the occurrence of malfunction of the transistor 26 due to the destruction can be avoided.

[0077] Furthermore, the second light-shielding film 211 is provided at a position different from that of the gate electrode 262 in plan view. That is, the second light-shielding film 211 does not overlap the gate electrode 262 in plan view. For this reason, the second light-shielding film 211 does not overlap the gate insulating film 263 in plan view. Therefore, even if the electric field generated by the charge of etching concentrates on the end portion of the second light-shielding film 211x, it is possible to avoid the possibility of damaging the gate insulating film 263. Even if the electric field concentrates on the end portion, the semiconductor layer 261 is damaged to such an extent that the damage D10 is extremely small compared to the above-described damage D1.

[0078] In addition, in the present embodiment, the first light-shielding films 281 and 282 also do not overlap the gate electrode 262 in plan view, similarly to the second light-shielding film 211. For this reason, the first light-shielding films 281 and 282 do not overlap the gate insulating film 263 in plan view. In other words, the first light-shielding films 281 and 283 are provided at positions different from that of the gate insulating film 263 in plan view.

[0079] Also, the first contact 290 is provided at a position different from that of the second light-shielding film 211 when viewed in the normal direction of the first substrate 21. That is, the first contact 290 does not overlap the second light-shielding film 211 in plan view. For this reason, the contact hole H2 does not overlap the second light-shielding film 211 in plan view. Therefore, it is possible to avoid the concentration of the electric field generated by the charge of etching on the second light-shielding film 211 as compared with the case where the contact hole H2 overlaps the second light-shielding film 211 in plan view.

[0080] In addition, in the present embodiment, the first contact 290 is a contact plug filled in a contact hole H2 which is a hole formed in the first insulating layer 220. The contact plug is easier to increase the aspect ratio compared to the trench electrode. For this reason, the aspect ratio of the contact hole H2 tends to be high. Therefore, the etching time for forming the contact hole H2 tends to be long. Then, the electric field generated by the charge of the etching is likely to concentrate on the second light shielding film 211. For this reason, when the first contact 290 is a contact plug, it is particularly preferable that the second light shielding film 211 has the second portion 2112.

[0081] Here, in order to avoid damage to the gate insulating film 263 due to the electric field generated by the charge of the etching concentrating on the second light shielding film 211, it is preferable not to provide the second light shielding film 211. However, when the second light shielding film 211 is not provided, there is a risk that the return light of the light LL enters the semiconductor layer 261. In particular, when light enters the low-concentration drain region 261d, the operation of the transistor 26 may become unstable.

[0082] In the present embodiment, the second light shielding film 211 overlaps the low-concentration drain region 261d in plan view. For this reason, compared with the case where the second light shielding film 211 does not overlap the low-concentration drain region 261d in plan view, the risk of the return light of the light LL entering the low-concentration drain region 261d can be suppressed. Therefore, the operation of the transistor 26 becoming unstable due to the incidence of the light is suppressed. In particular, in an electronic device such as a projector, it is preferable to suppress the incidence of the return light.

[0083] Further, the transistor 26 is provided in the scanning line driving circuit 11 as the peripheral circuit 10. In the transistor 26 provided in the scanning line driving circuit 11, a first light-shielding film 281 or 282 and a second light-shielding film 211 having a first portion 2111 and a second portion 2112 are provided. By the transistor 26 provided in the scanning line driving circuit 11 having such a first light-shielding film 281 or 282 and the second light-shielding film 211, display defects of the electro-optical device 100 can be particularly effectively suppressed.

[0084] Note that the "first light-shielding film" and the "second light-shielding film" may be provided for components other than the transistor 26. For example, the "first light-shielding film" and the "second light-shielding film" may be provided for one or more of the transistors other than the transistor 26 included in the scanning line driving circuit 11, the transistors included in the sampling circuit 15, and the transistors included in the inspection circuit 14. By providing the "first light-shielding film" and the "second light-shielding film" in the peripheral circuit 10, display defects of the electro-optical device 100 can be effectively suppressed.

[0085] 8. Fourth light-shielding film 210 FIG. 14 is a diagram showing a planar arrangement of the fourth light-shielding film 210 and the second transistor 23 shown in FIG. 6. As shown in FIG. 14, the fourth light-shielding film 210 is provided so as to overlap with the second semiconductor layer 231 of the second transistor 23 in a plan view and cover the second semiconductor layer 231 in the plan view.

[0086] It is particularly desired to avoid display defects caused by the incidence of light LL and return light on the second semiconductor layer 231 disposed in the display area A10. For this reason, the fourth light-shielding film 210 disposed in the display area A10 is not provided with slits or the like and is preferably provided so as to cover the second semiconductor layer 231 in a plan view.

[0087] Further, the fourth light-shielding film 210 has a third portion 2101 and a fourth portion 2102. The third portion 2101 is a portion that overlaps with the second semiconductor layer 231 in a plan view. The fourth portion 2102 is a portion that overlaps with the third light-shielding film 240 or 244 at a position different from the second semiconductor layer 231 in a plan view. That is, the fourth portion 2102 is a portion that does not overlap with the second semiconductor layer 231 in a plan view and overlaps with the third light-shielding film 240 or 244 in a plan view.

[0088] Since the fourth light-shielding film 210 has the fourth portion 2102, the third light-shielding film 244 and the fourth light-shielding film 210 can be capacitively coupled. That is, the space between the third light-shielding film 244 and the fourth light-shielding film 210 can be made to function as a capacitive coupling. Similarly, the third light-shielding film 240 and the fourth light-shielding film 210 can be capacitively coupled. That is, the space between the third light-shielding film 240 and the fourth light-shielding film 210 can be made to function as a capacitive coupling. Therefore, with this capacitive coupling, the electric field generated by the charge of the etching of the contact hole H3 described above can be absorbed. For this reason, it is possible to reduce the risk of the second gate insulating film 233 being broken due to the concentration of the electric field. Thus, even if the fourth light-shielding film 210 overlaps with the second gate insulating film 233 in a plan view, the risk of the second gate insulating film 233 being broken can be reduced. Therefore, it is possible to avoid the occurrence of malfunction of the second transistor 23 due to such breakage.

[0089] Note that each of the third light-shielding films 240 and 244 may be regarded as corresponding to the "first light-shielding film", and the fourth light-shielding film 210 may be regarded as corresponding to the "second light-shielding film".

[0090] 2. Second Embodiment For elements whose functions are the same as those in the first embodiment in the following second embodiment, the reference numerals used in the description of the first embodiment are reused, and the detailed description of each is omitted as appropriate.

[0091] FIG. 15 is a cross-sectional view showing the first light-shielding films 281A and 282A and the second light-shielding film 211 of the second embodiment. FIG. 16 is a plan view showing the first light-shielding films 281A and 282A and the second light-shielding film 211 of the second embodiment.

[0092] The first light-shielding film 281A shown in FIGS. 15 and 16 further has a portion that overlaps with the gate electrode 262 in a plan view. Therefore, the first light-shielding film 281A and the gate electrode 262 can be capacitively coupled. That is, the space between the first light-shielding film 281A and the gate electrode 262 can function as a capacitive coupling. Therefore, the electric field generated by the charge of the etching of the contact hole H2 described above can be absorbed by the capacitive coupling. For this reason, the electric field concentration at the end of the second light-shielding film 211A can be alleviated. Thus, the possibility that the gate insulating film 263 is broken due to the concentration of the electric field can be further reduced as compared with the first embodiment. Therefore, the occurrence of malfunction of the transistor 26 due to the breakage can be more effectively avoided than in the first embodiment.

[0093] Similarly, the first light-shielding film 282A has a portion that overlaps with the gate electrode 262 in a plan view. Therefore, the first light-shielding film 282A and the gate electrode 262 can be capacitively coupled. That is, the space between the first light-shielding film 282A and the gate electrode 262 can function as a capacitive coupling. Therefore, the electric field generated by the charge of the etching can be absorbed by the capacitive coupling. Thus, the possibility that the gate insulating film 263 is broken due to the concentration of the electric field can be reduced, and the occurrence of malfunction of the transistor 26 can be more effectively avoided than in the first embodiment.

[0094] In addition, the first light-shielding film 281A is provided so as to cover the low-concentration drain region 261d in a plan view. The first light-shielding film 282A is provided so as to cover the low-concentration source region 261e in a plan view. By providing the first light-shielding film 282A so as to cover the low-concentration drain region 261d in a plan view, the incidence of light to the low-concentration drain region 261d can be suppressed. Thus, the instability of the operation of the transistor 26 due to the incidence of the light LL is suppressed.

[0095] 3. Third Embodiment For elements whose functions are the same as those in the second embodiment in the following third embodiment, the reference numerals used in the description of the second embodiment are reused, and the detailed description of each is omitted as appropriate.

[0096] FIG. 17 is a cross-sectional view showing the first light-shielding film 281 or 282 and the second light-shielding film 211B of the third embodiment. FIG. 18 is a plan view showing the first light-shielding film 281 or 282 and the second light-shielding film 211B of the third embodiment.

[0097] The second light-shielding film 211B shown in FIGS. 17 and 18 overlaps the entire semiconductor layer 261 in plan view and is provided so as to cover the semiconductor layer 261 in plan view. Therefore, it is possible to particularly effectively suppress display defects caused by the return light incident on the semiconductor layer 261.

[0098] Also, in this embodiment, since the first light-shielding film 281 or 282 and the second light-shielding film 211B are capacitively coupled, it is possible to suppress the possibility that the gate insulating film 263 is damaged by the electric field generated by the charge of the etching described above. Therefore, according to this embodiment, since the gate insulating film 263 is less likely to be damaged and light is less likely to be incident on the semiconductor layer 261, the malfunction of the transistor 26 is particularly less likely to occur.

[0099] B. Modification The embodiments exemplified above can be variously modified. Specific modification modes applicable to the above-described embodiments are exemplified below. Two or more modes arbitrarily selected from the following examples can be appropriately combined within a range that does not conflict with each other.

[0100] B1. First Modification FIG. 19 is a cross-sectional view showing the first light-shielding films 281C and 282C of the first modification. As shown in FIG. 19, the first light-shielding film 281C overlaps the low-concentration drain region 261d in plan view. Similarly, the first light-shielding film 282C overlaps the low-concentration source region 261e in plan view. Since the first light-shielding film 281C overlaps the low-concentration drain region 261d in plan view, it is possible to suppress the operation of the transistor 26 from becoming unstable due to the incidence of light LL on the low-concentration drain region 261d.

[0101] Further, the second light-shielding film 211C overlaps with the low-concentration drain region 261d in plan view. Similarly, the second light-shielding film 211C overlaps with the low-concentration source region 261e in plan view. Since the second light-shielding film 211C overlaps with the low-concentration drain region 261d in plan view, it is possible to suppress the operation of the transistor 26 from becoming unstable due to the incidence of light LL on the low-concentration drain region 261d.

[0102] B2. Second Modification FIG. 20 is a diagram showing a part of the display region A10 of the element substrate 2D of the second modification. FIG. 21 is a diagram showing a part of the peripheral region A20 of the element substrate 2D of the second modification. The laminate 22D included in the element substrate 2D shown in FIGS. 20 and 21 further includes a lens layer 213, and insulating layers 214 and 215. The lens layer 213, the insulating layers 214 and 215 are laminated in this order from the insulating layer 229. Each material of the lens layer 213, the insulating layers 214 and 215 is an inorganic material containing silicon such as silicon oxide and silicon oxynitride, for example.

[0103] As shown in FIG. 20, in the light-shielding region A12 of the display region A10, a relay electrode 234 is disposed on the insulating layer 229. The relay electrode 234 is connected to the contact 291. A relay electrode 236 is disposed on the insulating layer 214. The relay electrode 236 is connected to the relay electrode 234 via a contact 235 that penetrates the lens layer 213 and the insulating layer 214. In the light-shielding region A12, a pixel electrode 25 is disposed on the insulating layer 215. The pixel electrode 25 is connected to the relay electrode 236 via a contact 237 that penetrates the insulating layer 215. Further, as shown in FIG. 21, in the peripheral region A20, a peripheral electrode 250 is disposed on the insulating layer 215.

[0104] Each of the relay electrodes 234 and 236 includes, for example, a metal such as aluminum, a metal nitride, and a metal silicide. Further, each of the contacts 235 and 237 described above includes, for example, a metal such as tungsten and aluminum, a metal nitride, and a metal silicide.

[0105] Also, the lens layer 213 has a plurality of lens surfaces 2130. In the display area A10, one lens surface 2130 is provided for one pixel electrode 25. Therefore, in the display area A10, one lens surface 2130 is provided for one second transistor 23. On the other hand, as shown in FIG. 21, in the peripheral area A20, the number of lens surfaces 2130 provided for one transistor 26 may be any number. In the illustrated example, two lens surfaces 2130 are provided for one transistor 26.

[0106] Also according to the second modification example, as described above, since the second light shielding film 211 has the second portion 2112, destruction of the gate insulating film 263 can be suppressed.

[0107] In each of the above-described embodiments, the active matrix type electro-optical device 100 is illustrated, but the present invention is not limited thereto. The driving method of the electro-optical device 100 may be, for example, a passive matrix method or the like.

[0108] The driving method of the "electro-optical device" is not limited to the vertical electric field method, and a horizontal electric field method may also be used. Examples of the horizontal electric field method include, for example, an IPS (In Plane Switching) mode. Examples of the vertical electric field method include a TN (Twisted Nematic) mode, a VA (Virtical Alignment), a PVA mode, and an OCB (Optically Compensated Bend) mode.

[0109] 2. Electronic device The electro-optical device 100 can be used in various electronic devices.

[0110] FIG. 22 is a perspective view showing a personal computer 2000 which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 for displaying various images, a main body 2010 where a power switch 2001 and a keyboard 2002 are installed, and a control unit 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0111] FIG. 23 is a plan view showing a smartphone 3000 which is an example of an electronic device. The smartphone 3000 includes an operation button 3001, an electro-optical device 100 for displaying various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 is changed according to the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0112] FIG. 24 is a schematic view showing a projector which is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. The electro-optical device 1r is the electro-optical device 100 corresponding to the red display color, the electro-optical device 1g is the electro-optical device 100 corresponding to the green display color, and the electro-optical device 1b is the electro-optical device 100 corresponding to the blue display color. That is, the projection display device 4000 has three electro-optical devices 1r, 1g, and 1b corresponding to the red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

[0113] The illumination optical system 4001 supplies the red component r of the emitted light from the illumination device 4002 which is a light source to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. Each of the electro-optical devices 1r, 1g, and 1b functions as a light modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to the display image. The projection optical system 4003 synthesizes the emitted light from each of the electro-optical devices 1r, 1g, and 1b and projects it onto the projection surface 4004.

[0114] The above electronic device includes the aforementioned electro-optical device 100 and a control unit 2003, 3002, or 4005. In the aforementioned electro-optical device 100, damage to the gate insulating film 263 is suppressed, and malfunction of the transistor 26 is less likely to occur. Therefore, the possibility of display defects is suppressed. Thus, by including the electro-optical device 100, the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000 can be improved.

[0115] Note that the electronic devices to which the electro-optical device of the present invention is applied are not limited to the exemplified devices. For example, they include PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation devices, in-vehicle displays, electronic notebooks, electronic paper, calculators, word processors, workstations, video phones, and POS (Point of Sale) terminals, etc. Furthermore, the electronic devices to which the present invention is applied include printers, scanners, copiers, video players, or devices equipped with touch panels, etc.

[0116] As described above, the present invention has been described based on preferred embodiments, but the present invention is not limited to the aforementioned embodiments. Also, the configuration of each part of the present invention can be replaced with any configuration that exhibits the same function as that of the aforementioned embodiments, and any configuration can be added.

[0117] Also, in the above description, a liquid crystal display device has been described as an example of the electro-optical device of the present invention, but the electro-optical device of the present invention is not limited thereto. For example, the electro-optical device of the present invention can also be applied to image sensors, etc.

Explanation of Reference Numerals

[0118] 2... Element substrate, 3... Opposing substrate, 4... Seal member, 5... Liquid crystal layer, 7... Second contact, 10... Peripheral circuit, 11... Scanning line drive circuit, 21... First substrate, 23... Second transistor, 25... Pixel electrode, 26... Transistor, 100... Electro-optical device, 210... Fourth light-shielding film, 211... Second light-shielding film, 213... Lens layer, 220... First insulating layer, 231... Second semiconductor layer, 232... Second gate electrode, 233... Second gate insulating film, 244... Third light-shielding film, 240... Third light-shielding film, 261... Semiconductor layer, 261a... Drain region, 261b... Source region, 261c... Channel region, 261d... Low-concentration drain region, 261e... Low-concentration source region, 262... Gate electrode, 263... Gate insulating film, 281... First light-shielding film, 282... First light-shielding film, 290... First contact, 2111... First portion, 2112... Second portion, A10... Display region, A11... Opening region, A12... Light-shielded region, A20... Peripheral region, H2... Contact hole, H3... Contact hole, P... Pixel.

Claims

1. A substrate, a transistor having a semiconductor layer, a gate insulating film, and a gate electrode arranged in a direction away from the substrate, a first insulating layer covering the transistor, a first contact provided on the first insulating layer and connected to the gate electrode, a first light-shielding film provided on the first insulating layer, and a second light-shielding film provided between the substrate and the semiconductor layer, wherein the second light-shielding film has a first portion overlapping with the semiconductor layer and a second portion overlapping with the first light-shielding film at a position different from the semiconductor layer when viewed in the normal direction of the substrate, characterized in that it is an electro-optical device.

2. The second light-shielding film and the first light-shielding film are capacitively coupled. The electro-optical device according to Claim 1.

3. The second portion is located on the side opposite to the semiconductor layer of the first portion when viewed in the normal direction. The electro-optical device according to Claim 1.

4. The first light-shielding film has a portion overlapping with the gate electrode when viewed in the normal direction. The electro-optical device according to Claim 1.

5. The first light-shielding film and the gate electrode are capacitively coupled. The electro-optical device according to Claim 4.

6. The semiconductor layer has a channel region, a drain region, and a low-concentration drain region having a lower impurity concentration than the drain region, and the second light-shielding film overlaps with the low-concentration drain region when viewed in the normal direction. The electro-optical device according to Claim 4.

7. The first light-shielding film overlaps with the low-concentration drain region when viewed in the normal direction. The electro-optical device according to Claim 6.

8. The second light-shielding film is provided so as to cover the semiconductor layer when viewed in the normal direction. The electro-optical device according to Claim 1.

9. An electro-optical device comprising a display region for displaying an image and a peripheral region provided outside the display region, wherein the peripheral region has a peripheral circuit electrically connected to wiring arranged in the display region, and the peripheral circuit has the transistor, the first contact, the first light-shielding film, and the second light-shielding film. The electro-optical device according to Claim 1.

10. There further exist a display region for displaying an image and a peripheral region provided outside the display region, wherein a scanning line driving circuit connected to a scanning line is provided in the peripheral region, and the scanning line driving circuit has the transistor, the first contact, the first light-shielding film, and the second light-shielding film. The electro-optical device according to Claim 1.

11. The first contact is a contact plug filled in a hole formed in the first insulating layer. The electro-optical device according to claim 1.

12. The second light-shielding film is provided at a position different from the gate electrode when viewed in the normal direction. The electro-optical device according to claim 1.

13. An electro-optical device according to any one of claims 1 to 12, and a control unit that controls the operation of the electro-optical device, wherein the electronic device is characterized by having the above.

Images