Silicon carbide semiconductor device and manufacturing method for the same

Abstract

To provide a silicon carbide semiconductor device in which the entry of hydrogen ions into a gate electrode and a gate insulating film is prevented and the reliability is improved.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide substrate 2 formed of silicon carbide of a first conductivity type, a drift layer 3 formed of silicon carbide of the first conductivity type on a first surface 30 of the silicon carbide substrate, a body layer 4 formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers 5 formed of silicon carbide of the first conductivity type, a gate insulating film 7 formed in contact with a body layer and a source layer, a gate electrode 8, an interlayer insulating film 9 formed so as to cover the gate electrode with the gate insulating film, and a source wire electrode 15 formed so as to cover the source electrode and the interlayer insulating film. The source electrode wire includes a first layer 16 including polycrystal metal with an average particle diameter of 1 μm or more and a second layer 17 including polycrystal metal with an average particle diameter of 0.1 μm or less.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device using silicon carbide (SiC) for a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed than a semiconductor device using silicon (Si) for the substrate, and is thus used, for example, as a power semiconductor device.

[0003] For example, a SiC-MOSFET as a silicon carbide semiconductor device described in Patent Document 1 is disclosed. Non-Patent Document 1 shows that in a trench-type power SiC-MOSFET, when hydrogen ions (H + ) enter the device, they have an effect of impairing the reliability of the HTRB (High-Temperature Reverse Bias) test, and that by adopting a material with a high phosphorus concentration for the interlayer insulating film as a countermeasure, hydrogen ions can be adsorbed to prevent hydrogen ions from entering the inside of the semiconductor device and improve the reliability of the semiconductor device. Non-Patent Document 2 describes that when the average particle size (grain size) of aluminum is small, the diffusion rate of hydrogen (hydrogen permeability) tends to decrease. FIG. 10 is a cross-sectional view showing a state in which two silicon carbide semiconductor devices 100 as unit cells that are the minimum unit structure of a conventional planar SiC-MOSFET are arranged side by side. This silicon carbide semiconductor device 100 includes a silicon carbide substrate 102, a drift layer 103, a source wiring electrode 111, a source electrode 110, a gate insulating film 107, a gate electrode 108, an interlayer insulating film 109, a body layer 104, a source layer 105, a body contact layer 106, and a drain electrode 112. Further, the silicon carbide semiconductor device 100 is sealed with a resin 114 together with a wiring 113 provided by wire bonding on the source wiring electrode 111.

Prior Art Documents

Patent Documents

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2021-93496 [Non-Patent Document]

[0005] [Non-Patent Document 1] Ai Loon Ooi, David Goh, V. C. Ngwan, STMicroelectronics Pte Ltd “High Temperature Reverse Bias (HTRB) & Temperature Humidity Bias (THB) Reliability Failure Mechanisms and Improvements in Trench Power MOSFET and IGBT” DOI 10.1109 / JEDS.2021.3109347, IEEE Journal of the Electron Devices Society [Non-Patent Document 2] Minoru Ichimura*, Yasushi Sasajima* and mamoru Imabayashi* “Grain Boundary Effect on Diffusion of Hydrogen in Pure Aluminium” Materials Transactions, JIM, Vol. 32, No. 12(1991), pp. 1109 to 1114 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] The silicon carbide semiconductor device 100 such as an SiC-MOSFET shown in FIG. 10 has hydrogen ions precipitated from the resin 114 used for encapsulation reaching the channel area of the body layer 104 through the source wiring electrode 111, the gate electrode 108, and the gate insulating film 107, which impairs the reliability in the HTRB (High Temperature Reverse Bias) test and is considered to cause fluctuations in the gate threshold voltage (Vth) of the silicon carbide semiconductor device 100 and an increase in leakage current. Therefore, it is preferable that hydrogen ions do not reach the channel area. For this reason, in order to improve the reliability of the semiconductor device, as described in Non-Patent Document 2, it is also conceivable to reduce the particle size of aluminum in the source wiring electrode to suppress the permeation of hydrogen ions. However, when the source wiring electrode 111 is formed at a low temperature, voids tend to be easily formed during the formation of the source wiring electrode 111, and particularly in the vicinity of the region 120 between the adjacent interlayer insulating films 109 in FIG. 10, due to the step between the interlayer insulating film 109 and the source electrode 110, cavities that are not formed during the film formation process tend to occur, so it is difficult to form the source wiring electrode 111 at a low temperature. In view of these problems, an object of the present invention is to provide a silicon carbide semiconductor device that prevents the generation of voids in the source wiring electrode, prevents hydrogen ions from reaching the channel area through the source wiring electrode, and improves reliability.

Means for Solving the Problems

[0007] One aspect of the silicon carbide semiconductor device of the present invention is a silicon carbide substrate formed of silicon carbide of a first conductivity type, a drift layer formed of silicon carbide of a first conductivity type on the first surface of the silicon carbide substrate, a plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers respectively formed of silicon carbide of a first conductivity type having a higher impurity concentration than the drift layer on each of the plurality of body layers, a gate insulating film formed so as to be in contact with the body layer and the source layer, a gate electrode formed on the gate insulating film An interlayer insulating film formed to cover the gate electrode together with the gate insulating film, A source electrode formed on the source layer, And a source wiring electrode formed to cover the source electrode and the interlayer insulating film. The source electrode wiring includes a first layer made of polycrystalline metal having an average particle size of 1 μm or more, And has a second layer formed on the first layer and made of polycrystalline metal having an average particle size of 0.1 μm or less. It is such a thing.

[0008] Thus, in the silicon carbide semiconductor device of the present invention, since the source wiring electrode has a second layer made of polycrystalline metal having an average particle size of 0.1 μm or less, the second layer can reduce the hydrogen permeability. The second layer can prevent hydrogen ions precipitated from the resin from reaching the channel area, prevent a decrease in reliability caused by hydrogen ions, and ensure the reliability of the silicon carbide semiconductor over a long period. Moreover, since the first layer on the silicon carbide substrate side of the second layer is made of polycrystalline metal having an average particle size of 1 μm or more, it can be formed at the same temperature as before, and there is no generation of voids due to steps in the manufacturing process. Therefore, it is possible to prevent a decrease in reliability caused by hydrogen ions and improve the reliability of the silicon carbide semiconductor, and at the same time, it is possible to prevent the generation of voids in the manufacturing process.

[0009] As a specific aspect of the above-described aspect, the silicon carbide semiconductor device of the present invention includes a conductive barrier layer formed between the first layer and the second layer and having a lower hydrogen permeability than the polycrystalline metal of the first layer.

[0010] Thus, since the conductive barrier layer formed between the first layer and the second layer has a lower hydrogen permeability than the polycrystalline metal of the first layer, it is possible to prevent the passage of hydrogen ions as a conductive barrier layer without increasing the electrical resistance value. Thereby, it becomes possible to enhance the reliability of the silicon carbide semiconductor device.

[0011] As a specific embodiment of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the conductive barrier layer is made of tantalum, tantalum nitride, or titanium nitride.

[0012] Thus, since the conductive barrier layer is made of tantalum, tantalum nitride, or titanium nitride, these materials have conductivity and are difficult to permeate hydrogen. Therefore, it is possible to prevent the passage of hydrogen ions as a conductive barrier layer without increasing the electrical resistance value. Thereby, it becomes possible to improve the reliability of the silicon carbide semiconductor device.

[0013] One aspect of the method for manufacturing a silicon carbide semiconductor device of the present invention includes a step of forming a drift layer on a silicon carbide substrate, a step of forming a body layer and a source layer by ion implantation on the drift layer, a step of forming a gate insulating film so as to be in contact with the body layer and the source layer, a step of forming a gate electrode on the gate insulating film, a step of forming an interlayer insulating film so as to cover the gate electrode, a step of forming a source electrode so as to cover the source layer, a step of forming a source wiring electrode so as to cover the interlayer insulating film and the source electrode, and the step of forming the source wiring electrode includes a step of forming a first layer made of aluminum or an alloy mainly composed of aluminum at 350°C or higher and 550°C or lower by a deposition method, a step of forming a second layer made of aluminum or an alloy mainly composed of aluminum at 0°C or higher and 250°C or lower.

[0014] ​Thus, in the method for manufacturing a silicon carbide semiconductor device, in the step of forming the source wiring electrode, by forming the second layer made of aluminum at a temperature of 0°C or higher and 250°C or lower, the average particle size of the second layer can be reduced, and the hydrogen ion permeability of the second layer can be decreased. Therefore, the intrusion of hydrogen ions from the resin into the channel area can be prevented, and the reliability of the silicon carbide semiconductor device can be improved. Further, since the first layer made of polycrystalline metal at 350°C or higher and 550°C or lower is formed on the silicon carbide substrate side of the second layer, no voids are formed in the vicinity of the step due to film formation at a low temperature in the first layer. Therefore, a method for manufacturing a silicon carbide semiconductor device can be realized in which both the generation of voids in the first layer and the improvement in reliability against the generation of hydrogen ions are achieved.

Effect of the Invention

[0015] According to the present invention, in the source wiring electrode of the silicon carbide semiconductor device, since the second layer made of polycrystalline metal having an average particle size of 0.1 μm or less is provided, the hydrogen permeability of the second layer is low, so that hydrogen ions precipitated from the resin can be blocked or suppressed from passing through by the second layer and prevented from reaching the channel area, thereby preventing a decrease in reliability caused by hydrogen ions and ensuring the reliability of the silicon carbide semiconductor over a long period. Therefore, it is possible to prevent a decrease in reliability, a change in the gate threshold voltage (Vth), and an increase in leakage current in the HTRB (high temperature reverse bias) test due to hydrogen ions reaching the channel area, and improve the reliability of the silicon carbide semiconductor device. Moreover, since the first layer on the silicon carbide substrate side of the second layer is made of polycrystalline metal having an average particle size of 1 μm or more, the source wiring electrode can be formed at the conventional temperature, and no voids are formed even when the film is formed at a low temperature in the manufacturing process. In this way, a silicon carbide semiconductor device can be realized in which both the long-term improvement in reliability against the generation of hydrogen ions and the prevention of void generation in the manufacturing process are achieved.

Brief Description of the Drawings

[0016]

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Embodiments for Carrying Out the Invention

[0017] <Regarding Definitions in the Description> In the embodiments described hereinafter, it will be described that the first conductivity type in the silicon carbide semiconductor device is n-type and the second conductivity type is p-type. However, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0018] Also, regarding words indicating directions such as up and down, left and right, side, inside, and outside, for the sake of convenience, since they are based on FIG. 1, they may be different from the actual product orientation. Also, the drawings are schematic, and include parts where the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. are different from the actual ones. Also, there are parts where the dimensional relationships and ratios are different between the drawings.

[0019] <Configuration of the First Embodiment> A first embodiment will be described as an example of a silicon carbide semiconductor device according to the present invention. FIG. 1 is a plan view of a semiconductor chip 50 including a silicon carbide semiconductor device 1 according to the present embodiment. The shape of the semiconductor chip 50 is, for example, rectangular in plan view. On the plane of the semiconductor chip, a source pad 51 and a gate pad 52 are provided, and an element region (not shown) is arranged thereunder in plan view. A plurality of silicon carbide semiconductor devices 1 as unit cells each serving as a minimum unit structure of a MOS-FET are arranged in these element regions. The source pad 51 is electrically connected to the source electrode of each silicon carbide semiconductor device 1. The gate pad 52 is electrically connected to the gate electrode of each silicon carbide semiconductor device 1. Further, wirings (not shown) are provided on the source pad 51 and the gate pad 52 by wire bonding, respectively. Note that the source pad 51 and the gate pad 52 are examples, and their shapes may actually be different from those of the present embodiment. A drain pad is provided on the bottom surface (back surface) of the semiconductor chip not shown, and the drain pad is electrically connected to the drain electrode of each silicon carbide semiconductor device 1.

[0020] FIG. 2 is a cross-sectional view showing a state in which two silicon carbide semiconductor devices 1 as unit cells each serving as a minimum unit structure of a planar SiC-MOSFET are arranged side by side. A plurality of silicon carbide semiconductor devices similar to the silicon carbide semiconductor device 1 in FIG. 2 are provided inside the semiconductor chip in FIG. 1.

[0021] The silicon carbide semiconductor device 1 in FIG. 2 includes a silicon carbide substrate 2, a drift layer 3, a body layer 4, a source layer 5, a body contact layer 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, a source electrode 10, a source wiring electrode 15, and a drain electrode 12.

[0022] As shown in FIG. 2, a planar MOSFET is formed on an n-type silicon carbide substrate 2 of the first conductivity type. The silicon carbide substrate 2 has a first surface 30 on the upper main surface side and a second surface 31 on the lower main surface side in the drawing of FIG. 2. The n- + type+ The silicon carbide substrate 2 of this type is configured to have a higher impurity concentration than the n-type drift layer 3 described later. The thickness of the silicon carbide substrate 2 is about 350 μm if the wafer is 6 inches, and about 500 μm if the wafer is 8 inches. However, before the step of forming the drain electrode 12 described later, it may be thinned to about 100 to 200 μm for improving heat dissipation.

[0023] An n-type drift layer 3 made of silicon carbide epitaxially grown on the first surface 30 (the upper surface in FIG. 2) of the silicon carbide substrate 2 is formed. The impurity concentration of the n-type drift layer 3 is lower than that of the silicon carbide substrate 2, and the thickness is 5 to 20 μm. For example, nitrogen is used as the n-type impurity in the n-type drift layer 3.

[0024] On the upper surface of the n-type drift layer 3 (the side opposite to the silicon carbide substrate 2), two p-type body layers 4 of the second conductivity type are formed so as to be arranged at intervals from each other. The thickness of the body layer 4 is about 1 μm. The p-type body layer 4 is formed, for example, by ion implantation of aluminum. The body layer 4 is formed by connecting between two adjacent silicon carbide semiconductor devices 1.

[0025] On each p-type body layer 4, an n + -type source layer 5 is provided. The impurity concentration of the n + -type source layer 5 is configured to be higher than that of the n-type drift layer 3. The thickness of the n + -type source layer 5 is, for example, about 0.3 to 0.4 μm. Above the p-type body layer 4 and outside the n + -type source layer 5, a p + -type body contact layer 6 is provided. One body contact layer 6 is provided between two adjacent silicon carbide semiconductor devices 1. Also, the body contact layer 6 is configured to have a higher impurity concentration than the p-type body layer 4.

[0026] Also, the body layer 4 is n +It is formed between the source layer 5 of the type and the drift layer 3 so as to be in contact with the gate insulating film 7. The gate insulating film 7 is disposed on the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided on the upper surface of the gate insulating film 7. This gate electrode 8 is made of, for example, polysilicon into which an n-type impurity [for example, phosphorus (P)] is ion-implanted in order to enhance conductivity. Further, the gate electrode 8 is provided with a contact hole (not shown because it is a different cross-section from FIG. 2) provided in the interlayer insulating film 9 and is electrically connected to the gate pad 52 of the semiconductor chip via an external wiring.

[0027] The interlayer insulating film 9 is formed so as to cover a part of the gate insulating film 7 and the gate electrode 8. One of the roles of the interlayer insulating film 9 is to insulate the gate electrode 8 from other energizing members such as the source wiring electrode 15. This interlayer insulating film 9 is composed of one or a plurality of different layers. In the present embodiment, specifically, for example, the interlayer insulating film 9 is configured with a two-layer structure of a BPSG film formed so as to cover the gate electrode 8 and a TEOS oxide film formed so as to cover this BPSG film. The interlayer insulating film 9 also has a role of preventing hydrogen ions from reaching the channel area from the source wiring electrode 15 via the gate insulating film 7 because the hydrogen ion transmittance of the interlayer insulating film 9 is lower than that of aluminum or an alloy mainly composed of aluminum.

[0028] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 15 is in contact with and electrically connected to the source electrode 10 and is provided on the source electrode 10 and the interlayer insulating film 9. The source wiring electrode 15 includes a first layer 16 and a second layer 17. The first layer 16 is provided on the side of the interlayer insulating film 9. The first layer 16 is formed of aluminum or an aluminum alloy as a polycrystalline metal at a temperature of 350°C or higher and 550°C or lower by a sputtering method as a deposition method, so that the average grain size is formed to be 1 μm or more. The second layer is formed of aluminum or an aluminum alloy as a polycrystalline metal at a temperature of 0°C or higher and 250°C or lower by a sputtering method as a deposition method, so that the average grain size is formed to be 0.005 μm or more and 0.1 μm or less. The temperature during film formation is more preferably 150°C or higher and 250°C or lower. Regarding the average grain size, it is based on the standard of symbol I: "average line segment length per crystal of the test line crossing within the crystal grain" in "JIS G 0551: 2020" according to Japanese Industrial Standards. Specifically, a test line, which is a straight line of length l, is drawn across the grain image observed by a microscope so as to cross the crystal grain, and the intersection point P with the boundary of the crystal grain crossed by the test line is found. Then, the number of crystal grains N is counted by the found intersection point P, and it is the average value obtained by dividing the length l of the test line by the number of crystal grains N.

[0029] The material of the source wiring electrode 15 (the first layer 16 and the second layer 17) is, for example, aluminum as a polycrystalline metal, but it may also be an alloy mainly composed of aluminum. The alloy mainly composed of aluminum means, for example, an alloy in which the components other than aluminum are 3% by weight or less in total, and more preferably an aluminum alloy in which the components other than aluminum are about 1.5% by weight in total. The alloys mainly composed of aluminum include, for example, alloys of aluminum, copper, silicon, and magnesium (Al-Cu-Si-Mg), alloys of aluminum, copper, and silicon (Al-Cu-Si), alloys of aluminum, silicon, and magnesium (Al-Si-Mg), alloys of aluminum and copper (Al-Cu), and alloys of aluminum and silicon (Al-Si). Also, the materials of the first layer 16 and the second layer 17 of the source wiring electrode 15 may be the same polycrystalline metal, or may be composed of different polycrystalline metals.

[0030] On the source wiring electrode 15, a wiring 13 is provided via a ball bond 13a. As the material of the wiring 13, for example, aluminum or an alloy of aluminum and copper (Al-Cu) is used.

[0031] In the planar SiC-MOSFET as the silicon carbide semiconductor device 1 configured as described above, in the body layer 4 mentioned above, the region near the gate insulating film 7 is the channel area. Using this channel region as a current path, an electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. Also, by controlling the applied voltage of the gate electrode 8 to control the width of the depletion layer formed in the channel area, the current flowing through the channel area is controlled, so that the current flowing between the source electrode 10 and the drain electrode 12 can be controlled.

[0032] Thus, the source wiring electrode 15 of the silicon carbide semiconductor device 1 includes a first layer 16 and a second layer. The second layer is formed of aluminum or an aluminum alloy as a polycrystalline metal at a temperature of 0°C or higher and 250°C or lower by a sputtering method as a deposition method, so that the average particle size is formed to be 0.1 μm or less. Since the hydrogen permeability decreases when the average particle size of aluminum or an aluminum alloy is small, the second layer can prevent hydrogen ions precipitated from the resin from reaching the channel area, prevent a decrease in reliability caused by hydrogen ions, and improve the reliability of the silicon carbide semiconductor. Further, the first layer is formed by sputtering aluminum or an aluminum alloy at a temperature of 350°C or higher and 550°C or lower, so that the average particle size is formed to be 1 μm or more, and no voids are generated due to film formation at a low temperature. It is possible to both prevent a decrease in reliability caused by hydrogen ions and improve the reliability of the silicon carbide semiconductor, and prevent the generation of voids due to film formation at a low temperature.

[0033] <Manufacturing Process of the First Embodiment> The manufacturing process of the silicon carbide semiconductor device 1 according to the first embodiment will be described with reference to FIGS. 3 to 8. FIGS. 3 to 5 show a part of the manufacturing process for one silicon carbide semiconductor device 1, and FIGS. 6 to 8 show a part of the manufacturing process in which two silicon carbide semiconductor devices 1 are formed side by side. As shown in FIG. 3(A), an n-type silicon carbide substrate 2 is prepared. Then, an n-type drift layer 3 is epitaxially grown on the first surface 30 (the upper surface in FIG. 1) of the silicon carbide substrate 2. + Next, a mask such as SiO2 is formed on the surface of the n-type drift layer 3, and a mask 20 is formed through a photolithography process so that the upper part of the formation planned area of the p-type body layer 4 as the second conductivity type is exposed. Then, ion implantation of p-type impurity aluminum (Al) is performed from above the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In this embodiment, p-type impurities such as Al are used, but B (boron) or BF2 (boron difluoride) may also be used.

[0034] ​

[0035] Next, as shown in FIG. 3(B), a layer of the same material as the mask 20 (e.g., SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then, by a self-alignment method formed by anisotropic etching, a mask 21 that is widely formed from the mask 20 is formed. The upper part of the planned formation region of the n-type source layer 5 is exposed in the formed mask 21. Then, for example, nitrogen (N) is ion-implanted as an n-type impurity from above the mask 21. In this embodiment, for example, nitrogen (N) is used as the n-type impurity, but phosphorus (P) may also be used.

[0036] Next, as shown in FIG. 3(C), after removing the mask 21, a mask 23 such as SiO2 is formed, and then, through a photolithography process, a mask 23 is formed so that the upper part of the planned formation region of the P + type body contact layer 6 is exposed. Then, for example, aluminum (Al) is ion-implanted as a p-type impurity into the planned formation region of the body contact layer 6 to form the body contact layer 6.

[0037] Next, after removing the mask 23, for example, annealing at 1600 °C is performed. By this annealing, the p-type body layer 4, n + type source layer 5 and body contact layer 6 are activated.

[0038] Next, as shown in FIG. 4(A), a gate insulating film 7 such as SiO2 is formed. Specifically, SiO2 is formed by heating the region including the upper parts of the body layer 4, n + type source layer 5 and body contact layer 6 at 900 to 1350 °C for thermal oxidation, and the gate insulating film 7 is patterned using the resist formed by photolithography and etching as a mask to form the gate insulating film 7.

[0039] Next, as shown in FIG. 4(B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, in order to enhance conductivity, for example, after forming a polysilicon film doped with an n-type impurity, patterning is performed using the resist formed by photolithography and etching as a mask to form the gate electrode 8.

[0040] Next, as shown in FIG. 4(C), an interlayer insulating film 9 is formed so as to cover the gate electrode 8. The interlayer insulating film 9 may have, for example, a single-layer structure made of BPSG, TEOS, or PSG, or may have a multilayer structure. For example, in the case of a two-layer structure of a BPSG insulating film and a TEOS film, a BPSG insulating film may be formed on the gate electrode 8, and a TEOS insulating film may be formed thereon. In that case, a BPSG film is formed over the entire main surface of the wafer including the gate electrode 8, and the BPSG film is patterned using the resist formed by photolithography and etching as a mask to form a first interlayer insulating film made of BPSG. Thereafter, a TEOS film is formed over the entire main surface of the wafer including the first interlayer insulating film made of BPSG, and the TEOS film is patterned using the resist formed by photolithography and etching as a mask to form a TEOS insulating film as a second interlayer insulating film. The BPSG film is subjected to reflow to perform planarization of the upper portion and to make the corners of the interlayer insulating film 9 rounded as shown in FIG. 4(C) and the like. By making the corners rounded, it is possible to prevent the concentration of electrolysis due to the corners in the interlayer insulating film 9.

[0041] Next, as shown in FIG. 5, a source electrode 10 made of, for example, nickel silicide (NiSi) is formed. Specifically, first, nickel (Ni) is deposited on the main surface side of the substrate 2 including the upper portions of the source layer 5 and the body contact layer 6 by sputtering. Thereafter, an annealing process for alloying is performed. Specifically, for the silicon carbide substrate 2 on which nickel (Ni) is deposited, heat treatment at 900° C. or higher and 1100° C. or lower is performed for about 5 minutes, for example, by laser. As a result, at least a part of the source electrode 10 (the portion where the films of the source layer 5 and the body contact layer 6 are in contact with the Ni film) is silicided to become nickel silicide. Thereafter, the non-silicided nickel (Ni) portion is removed. Thereby, the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6 is formed.

[0042] Next, as shown in FIG. 6, the first layer 16 of the source wiring electrode 15 is formed. Specifically, the first layer 16 is formed by sputtering in a temperature range of 350°C or higher and 550°C or lower so as to cover the source electrode 10 and the interlayer insulating film 9. As an example of the conditions other than the temperature in this sputtering, sputtering is performed by an RF sputtering apparatus, the vacuum pressure is 1 to 10 [Pa], the flow rate of argon (Ar) gas as an inert gas is 5 to 10 [sccm], the RF Power is 100 to 250 [W], and the film formation rate is 1 to 2 [nm / s]. Also, the film thickness is adjusted by the sputtering time. As described above, the material of the source wiring electrode 15 is, for example, aluminum (Al), but an alloy mainly composed of aluminum may also be used. Also, the thickness of the source wiring electrode 15 is about 5 μm. As shown in FIG. 6, a recess 16a is formed on the step between the source electrode 10 and the interlayer insulating film 90 in the first layer 16. The height difference between the highest part and the lowest part of the recess 16a becomes smaller than the step between the source electrode 10 and the interlayer insulating film 90, and its inclination is also gently formed. Since the height difference of this recess 16a is gentle, even if the second layer 17 described next is formed at a relatively low temperature, voids due to film formation at a low temperature and steps do not occur. That is, by forming this recess 16a, the problem of voids occurring in the source wiring electrode 15 can be solved.

[0043] In this embodiment, the thickness of the source wiring electrode 15 is, for example, about 5 μm, the first layer 16 is about 2.5 μm, and the second layer is 2.5 μm. However, as long as the first layer is formed without voids at 350°C or higher and 550°C or lower, and at the stage where the formation of the first layer is completed, the recess 16a that relaxes the height difference of the step between the source electrode 10 and the interlayer insulating film 90 is relaxed to such an extent that no voids are formed even when the second layer is formed at 0°C or higher and 250°C or lower, it is not limited to the above. For example, the thickness of the first layer may be such that the height of the first layer is equal to or higher than the height of the interlayer insulating film 9, and the part above that is the second layer, and the second layer may be made thicker than 2.5 μm. If the second layer is made thicker, the time for hydrogen to permeate through the second layer can be lengthened proportionally.

[0044] Next, as shown in FIG. 7, the second layer 17 of the source wiring electrode 15 is formed. The second layer 17 of the source wiring electrode 15 is formed. Specifically, the first layer 16 is formed by sputtering in a temperature range of 0°C or higher and 250°C or lower (more preferably 150°C or higher and 250°C or lower) so as to cover the first layer 16. As an example of the conditions other than the temperature in this sputtering, sputtering is performed by an RF sputtering apparatus, the pressure of the vacuum is 1 to 10 [Pa], the flow rate of argon (Ar) gas as an inert gas is 5 to 10 [sccm], the RF Power is 100 to 250 [W], and the film formation rate is 1 to 2 [nm / s]. Also, the film thickness is adjusted by the sputtering time. As described above, the material of the source wiring electrode 15 is, for example, aluminum (Al), but an alloy mainly composed of aluminum may also be used. Although not shown, the first layer 16 and the second layer 17 of the source wiring electrode 15 are etched before the wiring 13 is attached by wire bonding for the formation of the source pad 51.

[0045] Next, as shown in FIG. 8, a drain electrode 12 made of, for example, NiSi is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed, for example, by sputtering Ni, and then the deposited Ni is heated, for example, by laser annealing. As a result, at least a part of the Ni is silicided. Then, the Ni that has not been silicided is removed. Thereby, the drain electrode 12 is formed.

[0046] Next, as shown in FIG. 8, the wiring 13 is attached to the source wiring electrode 15 (second layer 17) by wire bonding via a ball bond 13a. This wiring 13 is composed of, for example, an alloy of aluminum (Al) and copper (Cu).

[0047] Next is the step of being sealed with the resin 14, as shown in FIG. 2. The silicon carbide semiconductor device 1 and the wiring 13 are sealed (molded) with the resin 14. Specifically, the resin 14 is provided so as to cover the source wiring electrode 15 side. In this way, the silicon carbide semiconductor device 1 of the first embodiment is manufactured. <Second Embodiment> As an example of the silicon carbide semiconductor device according to the present invention, a second embodiment is shown in FIG. 9. FIG. 9 is a cross-sectional view showing a state in which two silicon carbide semiconductor devices 1A of the second embodiment are arranged side by side. Parts that perform the same role as those in the first embodiment are denoted by the same reference numerals and the description thereof is omitted. The silicon carbide semiconductor device 1A in FIG. 9 is configured as a planar SiC-MOSFET. In the silicon carbide semiconductor device 1 (FIG. 2) showing the first embodiment, the second layer 17 is formed on the first layer 16 of the source wiring electrode 15. However, in this second embodiment, as shown in FIG. 9, a conductive barrier layer 19 is provided between the first layer 16 and the second layer 17 of the source wiring electrode 15.

[0048] The material of the conductive barrier layer 19 is preferably tantalum (Ta), tantalum nitride (TaN), or titanium nitride (TiN). However, the material of the conductive barrier layer 19 has conductivity and a hydrogen permeability lower than that of aluminum (hydrogen permeability: 1×10 -12 [m -1 ·s -1 ·Pa -0.5 ) which is the material of the first layer 16 of the source wiring electrode 15. Therefore, if the material of the conductive barrier layer 19 has an electrical resistivity of "1.6 [μΩ·cm] or more and 200 [μΩ·cm] or less and a hydrogen permeability of 1×10 -20 [m -1 ·s -1 ·Pa -0.5 or more and less than 1×10 -12 [m -1 ·s -1 ·Pa -0.5 , materials other than the above materials may be used.

[0049] In the second embodiment, similar to the first embodiment, by reducing the particle size of the second layer 17 of the source wiring electrode 15, it is made difficult for hydrogen ions to pass through, and the reliability of the silicon carbide semiconductor device 1 can be improved. Further, since the conductive barrier layer 19 with a low hydrogen permeability is provided, it becomes more difficult for hydrogen ions to reach the channel area than in the first embodiment, and thus the reliability of the silicon carbide semiconductor device can be improved. <Regarding the manufacturing method of the second embodiment> Regarding the steps similar to those of the first embodiment, the description will be omitted. The conductive barrier layer 19 in FIG. 8 is formed by sputtering the conductive barrier layer 19 so as to cover the first layer 16 after forming the first layer 16 of the source wiring electrode 15. As an example of specific sputtering conditions, when forming titanium nitride (TiN), an RF sputtering apparatus is used, the substrate temperature is 150 to 250 ° C, argon (Ar) and nitrogen (N2) are used as inert gases, the flow rate of argon is 5 [sccm], the flow rate of nitrogen is 10 [sccm], the vacuum pressure is 1 to 10 [Pa], the RF Power is 100 to 250 [W], and the film formation rate is 0.2 to 2 nm / s. When forming tantalum nitride (TaN), replace the target with Ta from the above. When forming tantalum (Ta), using tantalum as the target from the above example, use only argon as the inert gas, and its flow rate is, for example, 5 to 10 sccm.

[0050] Next to the conductive barrier layer 19, the second layer 17 is formed in the same manner as in the first embodiment.

[0051] In these embodiments, as an example of the silicon carbide semiconductor device of the present invention, an example of applying it to a planar SiC-MOSFET has been described, but it is also applicable to an IGBT.

[0052] As described above, the present invention has been described. However, when implementing the present invention, various modifications and additions are possible without departing from the gist of the present invention, not limited to the above-described examples.

Explanation of reference numerals

[0053] 1 Semiconductor device 2 Silicon carbide substrate 3 Drift layer 4 Body layer 5 Source layer 6 Body contact layer 7 Gate insulating film 8 Gate electrode 9 Interlayer insulating film 10 Source electrode 12 Drain electrode 13 Wiring 13a Ball bond 14 Resin 15 Source wiring electrode 16 First layer 17 Second layer 19 Conductive barrier layer 30 First surface

Claims

1. A silicon carbide substrate formed of silicon carbide of a first conductivity type, A drift layer formed of silicon carbide of a first conductivity type on a first surface of the silicon carbide substrate, A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers respectively formed of silicon carbide of a first conductivity type having an impurity concentration higher than that of the drift layer on each of the plurality of body layers, A gate insulating film formed so as to be in contact with the body layer and the source layer, A gate electrode formed on the gate insulating film, An interlayer insulating film formed so as to cover the gate electrode together with the gate insulating film, A source electrode formed on the source layer, A source wiring electrode formed so as to cover the source electrode and the interlayer insulating film, and comprising: The source electrode wiring includes a first layer made of polycrystalline metal having an average particle diameter of 1 μm or more, A second layer formed on the first layer and made of polycrystalline metal having an average particle diameter of 0.1 μm or less, A silicon carbide semiconductor device.

2. Comprising a conductive barrier layer formed between the first layer and the second layer, The silicon carbide semiconductor device according to claim 1.

3. The conductive barrier layer is made of tantalum, tantalum nitride, or titanium nitride, The silicon carbide semiconductor device according to claim 2.

4. A step of forming a drift layer on a silicon carbide substrate, A step of forming a body layer and a source layer by ion implantation on the drift layer, A step of forming a gate insulating film so as to be in contact with the body layer and the source layer, A step of forming a gate electrode on the gate insulating film, A step of forming an interlayer insulating film so as to cover the gate electrode, A step of forming a source electrode so as to cover the source layer, A step of forming a source wiring electrode so as to cover the interlayer insulating film and the source electrode, and including: The step of forming the source wiring electrode A step of forming a first layer made of aluminum at 350°C or higher and 550°C or lower by a deposition method, A step of forming a second layer made of aluminum at 0°C or higher and 250°C or lower, A method for manufacturing a silicon carbide semiconductor device.

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