Silicon carbide semiconductor device and manufacturing method for the same

Abstract

To provide a silicon carbide semiconductor device in which the reliability is improved.SOLUTION: A silicon carbide semiconductor device includes a silicon carbide substrate 2 formed of silicon carbide of a first conductivity type, a drift layer 3 formed of silicon carbide of the first conductivity type, a plurality of body layers 4 formed of silicon carbide of a second conductivity type on the drift layer, a plurality of source layers 5 formed of silicon carbide of the first conductivity type with higher impurity concentration than the drift layer on each of the body layers, a gate insulating film 7 formed in contact with a body layer and a source layer, a gate electrode 8 formed on the gate insulating film, an interlayer insulating film 9 formed covering the gate electrode, a source electrode formed on the source layer, a source wire electrode formed so as to cover the source electrode and the interlayer insulating film, a sealing part provided so as to cover the source wire electrode, and a barrier layer for suppressing transmission of hydrogen formed between the source wire electrode and the sealing part.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing the same.

Background Art

[0002] A semiconductor device using silicon carbide (SiC) for a substrate and a drift layer (epitaxial layer) can achieve higher breakdown voltage, lower loss, and higher speed than a semiconductor device using silicon (Si) for the substrate, and thus is used, for example, as a power semiconductor device.

[0003] For example, Patent Document 1 discloses an SiC-MOSFET as a silicon carbide semiconductor device. Non-Patent Document 1 shows that in a trench-type power SiC-MOSFET, when hydrogen ions (H + ) enter the device, it has an effect of impairing the reliability of the HTRB (High-Temperature Reverse Bias) test, and as a countermeasure, by adopting a material with a high phosphorus concentration for the interlayer insulating film, hydrogen ions can be adsorbed to prevent hydrogen ions from entering the inside of the semiconductor device and improve the reliability of the semiconductor device.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Non-Patent Documents

[0005]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] Silicon carbide semiconductor devices such as SiC-MOSFETs are often encapsulated with resin. Hydrogen ions precipitated from the resin pass through the source wiring electrode, and then through the gate electrode, gate insulating film or source electrode, etc., and reach the channel area of the body layer, which impairs the reliability in the HTRB (High Temperature Reverse Bias) test and causes fluctuations in the gate (Vth) threshold voltage and an increase in leakage current of the semiconductor device. Therefore, it is required to prevent hydrogen ions from reaching the channel area. In view of these problems, an object of the present invention is to provide a highly reliable silicon carbide semiconductor device by preventing hydrogen ions precipitated from the resin from permeating into the source wiring electrode.

Means for Solving the Problems

[0007] One aspect of the silicon carbide semiconductor device of the present invention includes a silicon carbide substrate formed of silicon carbide of a first conductivity type, a drift layer formed of silicon carbide of the first conductivity type on the first surface of the silicon carbide substrate, a plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers, each formed of silicon carbide of a first conductivity type having a higher impurity concentration than the drift layer, on each of the plurality of body layers; A gate insulating film formed so as to be in contact with the body layer and the source layer; A gate electrode formed on the gate insulating film; An interlayer insulating film formed so as to cover the gate electrode together with the gate insulating film; A source electrode formed on the source layer; A source wiring electrode formed so as to cover the source electrode and the interlayer insulating film; A sealing portion provided so as to cover the source wiring electrode; And a barrier layer for suppressing hydrogen permeation formed between the source wiring electrode and the sealing portion.

[0008] Thus, since it includes a barrier layer for suppressing hydrogen permeation formed between the source wiring electrode and the sealing portion, and the barrier layer has a low hydrogen ion permeation rate, the barrier layer can prevent hydrogen ions precipitated from the resin of the sealing portion from moving to the source wiring electrode. As a result, it is possible to prevent hydrogen ions from reaching the channel area of the silicon carbide semiconductor device, so that the reliability of the silicon carbide semiconductor device can be improved.

[0009] As a specific aspect of the above-described aspect, in the silicon carbide semiconductor device of the present invention, the barrier layer is made of aluminum oxide.

[0010] Thus, since the barrier layer is made of aluminum oxide, the hydrogen permeation rate of the barrier layer is significantly lower than that of the source wiring electrode, so that it is possible to prevent hydrogen ions precipitated from the resin of the sealing portion from moving to the source wiring electrode. As a result, it is possible to prevent hydrogen ions from reaching the channel area of the silicon carbide semiconductor device, so that a highly reliable silicon carbide semiconductor device can be manufactured.

[0011] As a specific aspect of the above-described aspect, the thickness of the barrier layer of the silicon carbide semiconductor device of the present invention is 20 nm or more and 100 nm or less.

[0012] In this way, since the thickness of the barrier layer through which hydrogen ions hardly permeate is set to 20 nm or more and 100 nm or less, a barrier layer through which hydrogen ions hardly pass can be formed in proportion to the hydrogen permeation rate and the thickness, and the passage of hydrogen ions can be better prevented by the barrier layer.

[0013] As a specific aspect of the above-described aspect, the silicon carbide semiconductor device of the present invention includes a bonding wire bonded to the source wiring electrode. The source wiring electrode has a joint portion that joins with the bonding wire. The barrier layer is not formed at the joint portion of the source wiring electrode. That is the case.

[0014] In this way, while preventing the passage of hydrogen ions by the barrier layer to improve reliability, a configuration is adopted in which the source wiring electrode, wire bonding, and joint portion are not interposed with the barrier layer. Therefore, a silicon carbide semiconductor device in which the electrical resistance value is not increased by the barrier layer can be realized in the connection between the source wiring electrode and the bonding wire. That is, both improvement in reliability by the barrier layer and non-increase in the electrical resistance value can be achieved.

[0015] One aspect of the method for manufacturing a silicon carbide semiconductor device of the present invention includes a step of forming a drift layer on a silicon carbide substrate, a step of forming a body layer and a source layer by ion implantation on the drift layer, a step of forming a gate insulating film so as to contact the body layer and the source layer, a step of forming a gate electrode on the gate insulating film, a step of forming an interlayer insulating film so as to cover the gate electrode, a step of forming a source electrode so as to cover the source layer, a step of forming a source wiring electrode so as to cover the interlayer insulating film and the source electrode. A step of bonding a bonding wire to the source wiring electrode; A step of forming a barrier layer for suppressing hydrogen permeation on the source wiring electrode by plasma oxidation or sputtering; A step of filling and sealing with resin so as to cover the barrier layer; It includes the above.

[0016] In this way, since the step of forming a barrier layer on the source wiring electrode by plasma oxidation or sputtering is included, a barrier layer is formed between the source wiring electrode and the sealing portion, and the hydrogen ions precipitated from the resin of the sealing portion are prevented from moving to the source wiring electrode by the barrier layer. As a result, since hydrogen ions can be prevented from reaching the channel area of the silicon carbide semiconductor device, a silicon carbide semiconductor device with improved reliability can be manufactured.

[0017] Further, since the step of forming a barrier layer on the source wiring electrode by plasma oxidation or sputtering is performed after the step of bonding the bonding wire to the source wiring electrode, the bonding wire is bonded to the source wiring electrode without passing through the barrier layer, and it is possible to avoid an increase in the resistance value between the source electrode and the bonding wire due to the barrier layer.

[0018] As a specific aspect of the above aspect, in the manufacturing method of the silicon carbide semiconductor device of the present invention, the barrier layer is made of aluminum oxide.

[0019] In this way, since the barrier layer is made of aluminum oxide, the hydrogen permeation rate of the barrier layer is significantly lower than that of the source wiring electrode, so it is possible to prevent hydrogen ions precipitated from the resin of the sealing portion from moving to the source wiring electrode. As a result, since hydrogen ions can be prevented from reaching the channel area of the silicon carbide semiconductor device, a highly reliable silicon carbide semiconductor device can be manufactured.

Effect of the Invention

[0020] According to the present invention, since a barrier layer for suppressing hydrogen permeation formed between the source wiring electrode and the sealing portion is provided, and the barrier layer has a low hydrogen ion permeability (diffusion rate), the barrier layer can prevent hydrogen ions precipitated from the resin of the sealing portion from moving to the source wiring electrode. As a result, it is possible to prevent hydrogen ions from reaching the channel area of the silicon carbide semiconductor device, and thus the reliability of the silicon carbide semiconductor device can be improved.

Brief Description of the Drawings

[0021]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0022] <Regarding Definitions in the Description> In the embodiments described hereinafter, the first conductivity type will be described as n-type and the second conductivity type as p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type.

[0023] Also, for words indicating directions such as up and down, left and right, side, inside, outside, etc., for the sake of convenience and with reference to FIG. 2, they may be different from the actual orientation of the product. Also, the drawings are schematic, and may include parts that are different from the actual ones in terms of the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc. Also, there are parts where the dimensional relationships and ratios are different between the drawings.

[0024] <Configuration of the First Embodiment> A first embodiment will be described as an example of a silicon carbide semiconductor device according to the present invention. FIG. 1 is a plan view of a semiconductor chip 50 including a silicon carbide semiconductor device 1 according to this embodiment. The semiconductor chip 50 in FIG. 1 shows a state before the bonding wires 13 and 15 are bonded and before being encapsulated with a resin 14 to be described later. The shape of the semiconductor chip 50 is, for example, rectangular in plan view. On the plane of the semiconductor chip, a source pad 51 and a gate pad 52 are provided, and a plurality of element regions (not shown) are arranged below them in plan view. A plurality of silicon carbide semiconductor devices 1 are arranged in these element regions as unit cells that are the minimum unit structures of MOS-FETs.

[0025] The gate pad 52 is electrically connected to the gate electrode of each silicon carbide semiconductor device 1. The source pad 51 also serves as a source wiring electrode 11 (to be described later) of each silicon carbide semiconductor device 1. A bonding wire 13 is bonded to the source pad 51 by wire bonding. The bonding wire 13 is bonded to a wiring member for a package such as a lead frame (not shown), for example.

[0026] The bonding wire 15 is bonded to the gate pad 52. Also, a drain pad is provided on the bottom surface (back surface) of the semiconductor chip (not shown), and the drain pad is electrically connected to the drain electrode of each silicon carbide semiconductor device 1. Note that the shapes of the source pad 51 and the gate pad 52 of the semiconductor chip 50 can take various shapes. Also, the bonding wires 13 and 15 can have various shapes, arrangements, and numbers, and thus are not limited to the aspect shown in FIG. 1.

[0027] Figure 2 is a cross-sectional view of a planar SiC-MOSFET as a silicon carbide semiconductor device according to this embodiment. In FIG. 2, the silicon carbide semiconductor device 1 includes a silicon carbide substrate 2, a drift layer 3, two body layers 4, two source layers 5, two body contact layers 6, a gate insulating film 7, a gate electrode 8, an interlayer insulating film 9, two source electrodes 10, a source wiring electrode 11, and a drain electrode 12.

[0028] As shown in FIG. 2, a planar MOSFET is formed on an n-type silicon carbide substrate 2 of the first conductivity type. The silicon carbide substrate 2 has a first surface 30 on the upper main surface side and a second surface 31 on the lower main surface side in the drawing of FIG. 2. The thickness of the silicon carbide substrate 2 is about 350 μm if the wafer is 6 inches, and about 500 μm if the wafer is 8 inches. However, before the step of forming the drain electrode 12 described later, it may be thinned to about 100 to 200 μm in order to improve heat dissipation. + An n-type drift layer 3 made of silicon carbide epitaxially grown on the first surface 30 (upper surface in FIG. 2) of the silicon carbide substrate 2 is formed. The impurity concentration of the n-type drift layer 3 is lower than that of the silicon carbide substrate 2, and the thickness is 5 to 20 μm. For example, nitrogen is used as the n-type impurity in the n-type drift layer 3.

[0029] On the upper surface of the n-type drift layer 3 (opposite side to the silicon carbide substrate 2), two p-type body layers 4 of the second conductivity type are formed so as to be spaced apart from each other. The thickness of the body layer 4 is about 1 μm. The p-type body layer 4 is formed by, for example, ion implantation of aluminum.

[0030] On each p-type body layer 4, an n-type source layer 5 with a high impurity concentration is provided. The impurity concentration of the n-type source layer 5 is configured to be higher than that of the n-type drift layer 3.

[0031] On each p-type body layer 4, an n + -type source layer 5 is provided. The n + -type source layer 5 is configured to have a higher impurity concentration than the n-type drift layer 3. The n +The thickness of the p-type source layer 5 is, for example, about 0.3 to 0.4 μm. Above the p-type body layer 4 and outside the n + -type source layer 5, a p + -type body contact layer 6 is provided. The p + -type body contact layer 6 is configured with an impurity concentration higher than that of the p-type body layer 4.

[0032] Also, the body layer 4 is between the n + -type source layer 5 and the drift layer 3 and is formed to be in contact with the gate insulating film 7. The gate insulating film 7 is disposed above the drift layer 3, the body layer 4, and the source layer 5, and a gate electrode 8 is provided on the upper surface of the gate insulating film 7. This gate electrode 8 is made of, for example, polysilicon doped with an n-type impurity (e.g., phosphorus [P]) in order to enhance conductivity. Further, the gate electrode 8 is provided with a contact hole (not shown because it is a different cross-section from FIG. 2) provided in the interlayer insulating film 9 and is electrically connected to the gate pad 52 via an external wiring.

[0033] The interlayer insulating film 9 is formed so as to cover a part of the gate insulating film 7 and the gate electrode 8. One role of the interlayer insulating film 9 is to insulate the gate electrode 8 from other energizing members such as the source wiring electrode 11. This interlayer insulating film 9 is composed of one or a plurality of different layers. In the present embodiment, specifically, for example, the interlayer insulating film 9 is configured with a two-layer structure of a BPSG film formed to cover the gate electrode 8 and a TEOS oxide film formed to cover this BPSG film. Since the interlayer insulating film 9 has a lower hydrogen ion transmittance than aluminum or an alloy mainly composed of aluminum, it also serves to prevent hydrogen ions from reaching the channel area from the source wiring electrode 11 via the interlayer insulating film 9 and the gate insulating film 7.

[0034] The source electrode 10 is formed on the source layer 5 and the body contact layer 6. The source electrode 10 is made of, for example, nickel silicide (NiSi). The source wiring electrode 11 is in contact with and electrically connected to the source electrode 10 and is provided on the source electrode 10 and the interlayer insulating film 9. The material of the source wiring electrode 11 is, for example, aluminum, or an alloy mainly composed of aluminum may also be used. The alloy mainly composed of aluminum means, for example, an alloy in which the components other than aluminum total 3% by weight or less, and more preferably an aluminum alloy in which the components other than aluminum total about 1.5% by weight. The alloys mainly composed of aluminum include, for example, an alloy of aluminum, silicon, and magnesium (Al-Si-Mg) and an alloy of aluminum and silicon (Al-Si).

[0035] As shown in FIG. 2, a bonding wire 13 is joined at the joint 11a on the source wiring electrode 11. The bonding wire 13 has a ball 13a at its tip. As the material of the bonding wire 13, for example, aluminum or an alloy of aluminum and copper (Al-Cu) is used.

[0036] As shown in FIG. 2, a barrier layer 16 for suppressing hydrogen permeation is provided between the source wiring electrode 11 and the resin 14 as a sealing portion. The barrier layer 16 is made of aluminum oxide (Al2O3). Since the hydrogen permeation rate of aluminum oxide is significantly lower than that of aluminum, it is possible to prevent (or significantly suppress) the hydrogen ions deposited from the resin 14 from moving to the source wiring electrode 11. Therefore, when aluminum oxide is used for the barrier layer 16, it is possible to prevent hydrogen ions from reaching the channel area, so that the reliability of the silicon carbide semiconductor device 1 can be improved. The hydrogen permeation rate of aluminum is 1×10 -12 [m -1 ·s -1 ·Pa -0.5 , and the hydrogen permeation rate of aluminum oxide is 9×10 -17 [m -1 ·s -1 ·Pa -0.5That is. Since there is a difference of five digits when comparing the digits of these numerical values, it is a significant difference. Note that the unit of hydrogen permeability may also be expressed as [ / (m·s·Pa^0.5)].

[0037] Also, as shown in FIG. 2, since aluminum oxide has insulating properties, a barrier layer 16 is not formed at the joint 11a between the bonding wire 13 and the source wiring electrode 11. Thereby, it is possible to prevent an increase in the resistance value due to the insulating property of the barrier layer 16. Further, even if oxygen plasma oxidation or sputtering is performed to form aluminum oxide after bonding (bonding) the bonding wire 13, the bonding wire 13 does not deteriorate to a problematic extent, which is also an advantageous point of aluminum oxide.

[0038] The thickness of the barrier layer 16 is preferably 20 nm or more and 100 nm or less. This is because a thickness of 20 nm or more has a sufficient effect of preventing hydrogen permeation, and a thickness of 100 nm or more is considered to have a weak merit even if the film is formed thicker to block hydrogen.

[0039] Table 1 below is a table showing the calculated hydrogen diffusion block effect of aluminum (Al) and aluminum oxide (Al2O3).

[0040]

Table 1

[0041] Table 1 has combinations of films from A to G. The film combination A is a single aluminum, while for the film combinations B to G, the hydrogen permeation time was calculated assuming that the aluminum of the source wiring electrode 11 (thickness according to "Al thickness" in Table 1) and the aluminum oxide of the barrier layer 16 (thickness according to "Al2O3 thickness" in Table 1) are laminated. The hydrogen diffusion time (H Diffusion time) is (Hydrogen Diffusion Time: H Diffusion time) = (Thickness) / (H Permeability) was calculated as follows. Regarding the hydrogen permeability (H Permeability), the hydrogen permeability of aluminum is 1×10 -12 [m -1 ·s -1 ·Pa -0.5 , and the hydrogen permeability of aluminum oxide was calculated to be 9×10 -17 [m -1 ·s -1 ·Pa -0.5 . Regarding the numerical value, for example, 5.00E+06 means 5.00×10 +6 .

[0042] To explain the membrane combination C shown in Table 1, the membrane combination C is a combination of a 4.98-μm-thick aluminum layer and a 0.02-μm (20-nm)-thick aluminum oxide layer overlapping each other. The time for hydrogen to permeate through this membrane combination C (the "Total Hydrogen Diffusion Time" in Table 1) is such that the time for hydrogen to permeate through aluminum is 5×10 +6 seconds, and the time for hydrogen to permeate through aluminum oxide is 2.3×10 +8 seconds. When these two times are added together and rounded, the total hydrogen diffusion time of the membrane combination C is 2.3×10 +8 seconds. In terms of years, this is nearly 7 years. Also, since the total hydrogen diffusion time of this membrane combination C is about twice the total diffusion time of the membrane combination B, it can be said that there is a sufficient hydrogen blocking effect. Note that the membrane combination B was calculated for comparison considering that the natural oxide film on the aluminum surface is about 0.01 μm (10 nm) thick, and its total hydrogen diffusion time is 1.2×10 +8 seconds.

[0043] As shown in Table 1, for the membrane combination E, although the aluminum oxide is 0.1 μm (100 nm) thick, the total hydrogen diffusion time is 1.10×10 +09It becomes seconds, and when this time is converted to years, it is about 34 years. These 34 years are long enough as an electronic device, and it is considered that there are few merits even if aluminum oxide is thickened to 100 nm or more. Accordingly, it can be said that the film thickness of aluminum oxide is preferably 20 nm or more and 100 nm or less. In addition, since there may be a case where it is more preferable that the total hydrogen diffusion time exceeds 10 years, the film thickness of aluminum oxide is more preferably 30 nm or more and 50 nm or less.

[0044] In the planar type SiC-MOSFET as the silicon carbide semiconductor device 1 configured as described above, in the body layer 4 described above, the region near the gate insulating film 7 is the channel area. Using this channel area as a current path, an electron current flows from the source electrode 10 through the source layer 5 and the drift layer 3 to the drain electrode 12. Further, by controlling the applied voltage of the gate electrode 8 and controlling the width of the depletion layer formed in the channel area, the current flowing through the channel area is controlled, so that the current flowing between the source electrode 10 and the drain electrode 12 can be controlled.

[0045] In the present embodiment, by providing a barrier layer 16 made of aluminum oxide between the source wiring electrode 11 and the resin 14 as a sealing portion, it is possible to prevent hydrogen ions precipitated from the resin 14 of the sealing portion from moving to the source wiring electrode 11. For this reason, it is possible to prevent hydrogen ions from reaching the channel area of the body layer 4 and causing fluctuations in characteristics, and to improve the reliability of the silicon carbide semiconductor device 1.

[0046] <Manufacturing Process of the First Embodiment> The manufacturing process of the silicon carbide semiconductor device 1 of the present embodiment will be described with reference to FIGS. 3 to 6. As shown in FIG. 3(A), an n-type silicon carbide substrate 2 of the first conductivity type is prepared. Thereafter, an n-type drift layer 3 is epitaxially grown on the first surface 30 (the upper surface in FIG. 1) of the silicon carbide substrate 2. + An n-type drift layer 3 is epitaxially grown on the first surface 30 (the upper surface in FIG. 1) of the silicon carbide substrate 2.

[0047] Next, a mask such as SiO2 is formed on the surface of the n-type drift layer 3, and through a photolithography process, a mask 20 is formed so that the upper part of the planned formation region of the p-type body layer 4 as the second conductivity type is exposed. Then, ion implantation of p-type impurity aluminum (Al) is performed from above the mask 20. The thickness of the body layer 4 is, for example, 1 μm. In this embodiment, although p-type impurity uses, for example, Al, B (boron) or BF2 (boron difluoride) may also be used.

[0048] Next, as shown in FIG. 3(B), a layer of the same material as the mask 20 (for example, SiO2) is laminated on the main surface of the silicon carbide substrate 2, and then, by a self-alignment method formed by anisotropic etching, a mask 21 formed widely from the mask 20 is formed. The formed mask 21 exposes the upper part of the planned formation region of the n-type source layer 5. Then, ion implantation of, for example, nitrogen (N) as an n-type impurity is performed from above the mask 21. In this embodiment, although nitrogen (N) is used for the n-type impurity, phosphorus (P) may also be used.

[0049] Next, as shown in FIG. 3(C), after removing the mask 21, a mask 23 such as SiO2 is formed, and then, through a photolithography process, the mask 23 is formed so that the upper part of the planned formation region of the P + type body contact layer 6 is exposed. Then, ion implantation of, for example, aluminum (Al) as a p-type impurity is performed into the planned formation region of the body contact layer 6 to form the body contact layer 6.

[0050] Next, after removing the mask 23, annealing at, for example, 1600 °C is performed. By this annealing, the p-type body layer 4, n + type source layer 5, and body contact layer 6 are activated.

[0051] Next, as shown in FIG. 4(A), a gate insulating film 7 such as SiO2 is formed. Specifically, the body layer 4 and n +By heating the region including the upper portions of the source layer 5 and the body contact layer 6 of the [[TYPE]] at 900 to 1350 °C for thermal oxidation to form SiO2, and patterning the gate insulating film 7 using the resist formed by photolithography and etching as a mask to form the gate insulating film 7.

[0052] Next, as shown in FIG. 4(B), a gate electrode 8 is formed on the surface of the gate insulating film 7. Specifically, in order to enhance conductivity, for example, after forming a polysilicon layer doped with an n-type impurity, it is patterned using the resist formed by photolithography and etching as a mask.

[0053] Next, as shown in FIG. 4(C), an interlayer insulating film 9 is formed so as to cover the gate electrode 8. The interlayer insulating film 9 may be, for example, a single-layer structure made of BPSG, TEOS, or PSG, or a multilayer structure. For example, in the case of a two-layer structure of a BPSG insulating film and a TEOS film, a BPSG insulating film may be formed on the gate electrode 8, and a TEOS insulating film may be formed thereon. In that case, a BPSG film is formed over the entire main surface of the wafer including the area above the gate electrode 8, and the BPSG film is patterned using the resist formed by photolithography and etching as a mask to form a first interlayer insulating film made of BPSG. Thereafter, a TEOS film is formed over the entire main surface of the wafer including the area above the first interlayer insulating film made of BPSG, and the TEOS film is patterned using the resist formed by photolithography and etching as a mask to form a TEOS insulating film as a second interlayer insulating film.

[0054] Next, as shown in FIG. 5(A), for example, a source electrode 10 made of nickel silicide (NiSi) is formed. Specifically, first, nickel (Ni) is deposited on the main surface side of the substrate 2 including the upper portions of the source layer 5 and the body contact layer 6 by sputtering. Thereafter, an annealing process for alloying is performed. Specifically, for the silicon carbide substrate 2 on which nickel (Ni) is deposited, heat treatment at 900°C or higher and 1100°C or lower is performed for about 5 minutes, for example, by laser. As a result, at least a part of the source electrode 10 (the part where the Ni film contacts the source layer 5 and the body contact layer 6) is silicided to become nickel silicide. Thereafter, the non-silicided nickel (Ni) portion is removed. Thereby, the source electrode 10 that makes an ohmic contact with the source layer 5 and the body contact layer 6 is formed.

[0055] Next, as shown in FIG. 5(B), a source wiring electrode 11 is formed. Specifically, the source wiring electrode 11 is formed by, for example, sputtering so as to cover the source electrode 10, the interlayer insulating film 9, and the barrier layer 15.

[0056] Next, as shown in FIG. 6(A), a drain electrode 12 made of, for example, NiSi is formed on the second surface 31 of the silicon carbide substrate 2. The drain electrode 12 is formed, for example, by depositing Ni by sputtering, and then the deposited Ni is heated, for example, by laser annealing. As a result, at least a part of the Ni is silicided. Thereafter, the non-silicided Ni is removed. Thereby, the drain electrode 12 is formed.

[0057] Next, as shown in FIG. 6(A), a bonding wire 13 is bonded (wire bonding) to the source wiring electrode 11.

[0058] Next, as shown in FIG. 6(B), the surface on top of the source wiring electrode 11 is oxidized by plasma oxidation to form a film of aluminum oxide. As an example of the specific conditions for plasma oxidation, the vacuum pressure is 100 Pa, the oxygen (O2) gas flow rate is 20 [sccm], the substrate temperature is 150 to 250 °C, and the RF Power (power of the high-frequency power supply) is 200 [W]. The control of the film thickness is adjusted by the time of plasma oxidation. For example, the surface of the source wiring electrode 11 made of aluminum or an alloy mainly composed of aluminum is plasma oxidized for about 1 hour to form a 50-nm-thick aluminum oxide film.

[0059] As shown in FIG. 6(B), since the cross-sectional shape of the barrier layer 16 is formed by film formation by plasma oxidation, it has a shape that spreads vertically from the surface of the original source wiring electrode 11 shown in FIG. 6(A). Also, among the upper surfaces of the source wiring electrode 11, the joint portion 11a with the bonding wire 13 is not formed with aluminum oxide as the barrier layer 16. This is because during plasma oxidation, the surface of the source wiring electrode 11 is covered by the ball 13a at the joint portion 11a and is not oxidized. Although aluminum oxide is also formed as a surface oxide film by plasma oxidation on the surfaces of the bonding wire 13 and the ball 13a, the thickness of the surface oxide film is extremely small compared to the diameter of the bonding wire 13, so it is not shown in FIGS. 6(B) and 2.

[0060] Next, as shown in FIG. 2, the space between the barrier layer 16 and the bonding wire 13 is filled with resin 14 and sealed. The portion sealed by the resin 14 constitutes the sealed portion. Specifically, the resin 14 is filled on the main surface so as to cover the upper part of the source wiring electrode 11, and the sealed portion is provided. In this way, the silicon carbide semiconductor device 1 is manufactured.

[0061] <Second Embodiment> A second embodiment according to the present invention is shown in FIG. 7. Parts that perform the same roles as those in the first embodiment are denoted by the same reference numerals, and their description is omitted. The silicon carbide semiconductor device 1A in FIG. 7 is configured as a planar SiC-MOSFET. In the silicon carbide semiconductor device 1A of FIG. 7, a barrier layer 16A is formed by sputtering. The barrier layer 16A is made of aluminum oxide.

[0062] The barrier layer 16A is not formed on the joint portion 11B of the source wiring electrode 11 with the bonding wire 13. This is because, in the manufacture of the silicon carbide semiconductor device 1A of the second embodiment, after the bonding with the bonding wire 13 in the source wiring electrode 11, the barrier layer 16A is formed by sputtering. Thus, since the barrier layer 16A is not present at the joint portion 11B of the bonding wire 13 (ball 13a) in the source wiring electrode 11, the resistance value is not increased by the barrier layer 16A.

[0063] The silicon carbide semiconductor device 1A in the present embodiment shown in FIG. 7 is different from the silicon carbide semiconductor device 1 shown in the first embodiment in FIG. 2 in the boundary between the barrier layers 16, 16A and the source wiring electrode 11. This is caused by the difference in the film formation method of the barrier layers 16, 16A. In the silicon carbide semiconductor device 1A of FIG. 7, since the barrier layer 16A is formed by sputtering, the boundary between the barrier layer 16A and the source wiring electrode 11 is not changed during film formation.

[0064] In addition, the plasma oxidation used for forming the barrier layer 16 in the first embodiment has a limit in the film thickness because it oxidizes the surface of the source wiring electrode 11. On the other hand, sputtering used in the manufacturing method of the second embodiment can form a film without such a limitation.

[0065] Thus, similar to the first embodiment, the silicon carbide semiconductor device 1A of the second embodiment makes it difficult for the hydrogen ions deposited by the resin 14 to pass through the barrier layer 16A to the source wiring electrode 14, so that it is possible to prevent the hydrogen ions from reaching the channel area of the body layer 4. Therefore, the reliability of the silicon carbide semiconductor device 1A can be improved.

[0066] In addition, in the first manufacturing method of the first embodiment, aluminum oxide may be further formed by sputtering on the aluminum oxide formed by plasma oxidation. In that case, it becomes possible to form the conductive barrier layer 16 made of aluminum oxide beyond the thickness limit of the film formation by plasma oxidation.

[0067] In the above embodiment, as an example of the silicon carbide semiconductor device of the present invention, an example of applying it to a planar SiC-MOSFET has been described, but it is also applicable to IGBT and trench-type power SiC-MOSFET.

[0068] Although the present invention has been described above, when implementing the present invention, various modifications and additions are possible without departing from the gist of the present invention, not limited to the above-described examples.

Explanation of reference numerals

[0069] 1, 1A Semiconductor device 2 Silicon carbide substrate 3 Drift layer 4 Body layer 5 Source layer 6 Body contact layer 7 Gate insulating film 8 Gate electrode 9 Interlayer insulating film 10 Source electrode 11 Source wiring electrode 11a, 11B Junction 12 Drain electrode 13 Bonding wire (wiring) 13a Ball 14 Resin (sealing part) 15 Bonding wire (wiring) 16, 16A Barrier layer

Claims

1. A silicon carbide substrate formed of silicon carbide of a first conductivity type, A drift layer formed of silicon carbide of a first conductivity type on a first surface of the silicon carbide substrate, A plurality of body layers formed of silicon carbide of a second conductivity type on the drift layer, A plurality of source layers each formed of silicon carbide of a first conductivity type having a higher impurity concentration than the drift layer on each of the plurality of body layers, A gate insulating film formed so as to be in contact with the body layer and the source layer, A gate electrode formed on the gate insulating film, An interlayer insulating film formed so as to cover the gate electrode together with the gate insulating film, A source electrode formed on the source layer, A source wiring electrode formed so as to cover the source electrode and the interlayer insulating film, A sealing portion provided so as to cover the source wiring electrode, And a barrier layer for suppressing the permeation of hydrogen formed between the source wiring electrode and the sealing portion A silicon carbide semiconductor device comprising.

2. The barrier layer is made of aluminum oxide The semiconductor device according to claim 1.

3. The thickness of the barrier layer is 20 nm or more and 100 nm or less The semiconductor device according to claim 2.

4. Comprising a bonding wire joined to the source wiring electrode, The source wiring electrode has a joint portion for joining with the bonding wire, The barrier layer is not formed at the joint portion of the source wiring electrode, The semiconductor device according to claim 1.

5. A step of forming a drift layer on a silicon carbide substrate, A step of forming a body layer and a source layer by ion implantation on the drift layer, A step of forming a gate insulating film so as to be in contact with the body layer and the source layer, A step of forming a gate electrode on the gate insulating film, A step of forming an interlayer insulating film so as to cover the gate electrode, A step of forming a source electrode so as to cover the source layer, A step of forming a source wiring electrode so as to cover the interlayer insulating film and the source electrode, A step of joining a bonding wire to the source wiring electrode, A step of forming a barrier layer for suppressing the permeation of hydrogen on the source wiring electrode by plasma oxidation or sputtering, A step of filling and sealing with resin so as to cover the barrier layer, A method for manufacturing a silicon carbide semiconductor device including.

6. The barrier layer is made of aluminum oxide The manufacturing method of the silicon carbide semiconductor device according to claim 5.

Images