Test circuit

Abstract

To provide a BIST circuit with which it is possible to test a RAM at high speed even for the case where a memory size has increased.SOLUTION: A test circuit comprises: a selection circuit for selecting the output data of a target RAM to be tested from the output data of a plurality of RAMs on the basis of a selection signal; a pipeline flip-flop for holding the selection data selected by the selection circuit; a comparison circuit for comparing the output of the pipeline flip-flop with an expected value; and a control circuit for controlling the selection signal and the expected value.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The disclosed technology relates to a test circuit.

Background Art

[0002] Patent Document 1 describes "an internal circuit for accessing a memory circuit and a test circuit for performing a test operation of the memory circuit, which compares a read signal from the memory circuit with an expected value corresponding thereto, and when a mismatch occurs, outputs the mismatch information serially from first and second external terminals together with a shift clock signal, and also outputs a latch clock signal corresponding to such mismatch information from a third external terminal."

[0003] Patent Document 2 describes "writing an address of ROM1 and its data from the outside as RAM data to RAM2, connecting the ROM address output among the RAM data from RAM2 to the address of ROM1, reading the data of that address from ROM1, comparing the ROM data output with the ROM data output among the RAM data from RAM2 by a coincidence circuit 7, outputting the comparison result to the outside at an arbitrary timing, and reading the comparison result to the outside at a low speed."

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In recent years, in order to facilitate the test of the RAM (Random Access Memory) mounted on an LSI (Large Scale Integration), a BIST (Built-In Self Test) circuit has been incorporated, enabling testing at speed. The BIST circuit can test one or a plurality of RAMs with a single control circuit and can output the address, data, and test state that resulted in an error during the test. However, when testing a plurality of RAMs or a RAM with a large number of bits, etc., as the memory capacity to be tested increases, there has been a problem that the BIST circuit cannot satisfy the timing specifications.

[0006] Here, Patent Document 1 proposes a RAM BIST circuit that can output test results, and Patent Document 2 proposes a RAM BIST circuit that can test at speed. However, in neither document can a countermeasure be taken when the memory capacity increases, and the above problems have not been solved.

[0007] Therefore, an object of the present disclosure is to provide a BIST circuit capable of testing a RAM at high speed even when the memory capacity increases.

Means for Solving the Problems

[0008] The test circuit according to the first aspect of the present disclosure includes a selection circuit that selects output data of a target RAM to be tested from output data of a plurality of RAMs based on a selection signal, a pipeline flip-flop that holds the selection data selected by the selection circuit, a comparison circuit that compares the output of the pipeline flip-flop with an expected value based on the selection signal, and a control circuit that controls the selection signal and the expected value.

[0009] The test circuit according to the second aspect of the present disclosure includes a split comparison circuit that selects a target bit to be compared from a plurality of bits obtained by splitting the output data of the target RAM to be tested based on a selection signal, and compares the target bit with an expected value, and a control circuit that controls the selection signal and the expected value.

Brief Description of Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Embodiments for Carrying Out the Invention

[0011] Hereinafter, an example of an embodiment of the technology of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings may be exaggerated for convenience of explanation and may be different from the actual ratios.

[0012] In addition, when the term "connection" is used hereinafter, the term shall be construed in a broad sense to mean an electrical connection, including not only a direct connection but also an indirect connection (for example, a connection via passive components).

[0013] Also, when the term "provided between ~" is used hereinafter, the term may be interpreted to mean the electrical connection position, rather than the physical position where circuits, elements, etc. are arranged.

[0014] FIG. 1 is a diagram showing an example of the schematic configuration of an LSI 1 in which a BIST circuit 100 according to a conventional example is incorporated. In the LSI 1, RAM peripheral circuits 10_1 to 10_n and a BIST circuit 100 are provided.

[0015] The RAM peripheral circuits 10_1 to 10_n (collectively referred to as "RAM peripheral circuit 10") each include RAMs 20_1 to 20_n (collectively referred to as "RAM 20"). The BIST circuit 100 is a test circuit incorporated in the LSI 1 to test the RAM 20.

[0016] In general in RAMBIST, the BIST circuit 100 controls the RAM peripheral circuit 10 to write data into the RAM 20 and reads the data written into the RAM 20. Then, the BIST circuit 100 collates the output data read from the RAM 20 with the expected value to perform an operation test of the RAM 20.

[0017] The BIST circuit 100 includes a control circuit 110, an output pipeline flip-flop (also referred to as "output PLFF (PipeLine Flip-Flop)") 120, input pipeline flip-flops 130_1 to 130_n (collectively referred to as "input PLFF 130"), a selection comparison circuit 140, a data holding flip-flop (also referred to as "data holding FF") 150, an address / status holding flip-flop (also referred to as "address / status holding FF") 160, and an output circuit 170.

[0018] The control circuit 110 controls the entire BIST circuit 100. The control circuit 110 supplies a control signal for controlling the RAM peripheral circuit 10 and RAM data for writing to the RAM 20 to the output PLFF 120. Also, the control circuit 110 supplies a selection signal for selecting a test target and an expected value for collating the selected data selected by the selection signal to the selection comparison circuit 140.

[0019] The output PLFF 120 is provided between the control circuit 110 and the RAM peripheral circuit 10, and pipelines the control signal and the RAM data from the control circuit 110.

[0020] The input PLFF 130 is provided between the RAM peripheral circuit 10 and the selection comparison circuit 140, and pipelines the output data dout read from the RAM 20. For example, the input PLFF 130_1 pipelines the output data dout_1 read from the RAM 20_1. Similarly, the input PLFF 130_n pipelines the output data dout_n read from the RAM 20_n.

[0021] The selection comparison circuit 140 selects the output data dout_t of the target RAM 20_t to be tested from the output data dout_1 to dout_n of the plurality of RAMs 20_1 to 20_n based on the selection signal supplied from the control circuit 110. Next, the selection comparison circuit 140 compares the selected data selected by the selection signal with the expected value supplied from the control circuit 110. Then, the selection comparison circuit 140 supplies the selected data and the comparison result to the control circuit 110. In response to this, the control circuit 110 supplies the address of the RAM 20 and the comparison result, that is, the test state, to the address / status holding FF 160. Also, when the comparison result is an error, the control circuit 110 supplies the selected data to the data holding FF 150.

[0022] The data holding FF 150 holds the selected data supplied from the control circuit 110.

[0023] The address / status holding flip-flop 160 holds the address and test state supplied from the control circuit 110.

[0024] The output circuit 170 outputs the selected data held by the data holding flip-flop 150 and the address and test state held by the address / status holding flip-flop 160 as diagnostic outputs. Thereby, the BIST circuit 100 can output the address, data, and test state that have become errors in the test.

[0025] In such a BIST circuit 100, by the control circuit 110 controlling the selection signal and the expected value, a plurality of RAMs 20_1 to 20_n can be tested. Here, inside the selection comparison circuit 140, a plurality of selectors are configured in a circuit configuration stacked in multiple stages like a tournament table. The number of such selector stages increases in proportion to the number of output data dout_1 to dout_n and the number of bits of each of the output data dout_1 to dout_n. Therefore, when the number of RAMs 20 mounted on the LSI1 or the number of bits of the RAM 20 increases, the number of logic gate stages between the input PLFF 130 and the data holding flip-flop 150 and the address / status holding flip-flop 160 increases.

[0026] However, in recent years, the high resolution and high performance of liquid crystal televisions and liquid crystal monitors have advanced, and the number of RAMs 20 mounted on LSI and the number of bits of the RAM 20 tend to increase. That is, the number of logic gate stages between the input PLFF 130 and the data holding flip-flop 150 and the address / status holding flip-flop 160 tends to increase. On the other hand, the operating frequency of the memory has become as high as several hundred MHz, and the processing time per cycle has become as short as several ns. Therefore, in RAMBIST, it has become impossible to satisfy the timing specifications.

[0027] Therefore, in the present embodiment, a RAMBIST circuit that operates at high speed is realized by reducing the number of logic gate stages between the flip-flops. This will be described in detail.

[0028] FIG. 2 is a diagram showing an example of the functional configuration of the BIST circuit 100_1 according to the first embodiment. Instead of the BIST circuit 100 according to the conventional example, the BIST circuit 100_1 according to the first embodiment may be incorporated in the LSI 1. In this figure, the same or equivalent components and parts as those in FIG. 1 are given the same reference numerals.

[0029] The BIST circuit 100_1 according to the first embodiment includes a control circuit 110_1, an output PLFF 120, an input PLFF 130, a selection circuit 142, a pipeline flip-flop (also referred to as "PLFF") 144, a comparison circuit 146, a data holding flip-flop (also referred to as "data holding FF") 150_1, an address / status holding FF 160, and an output circuit 170.

[0030] The output PLFF 120, the input PLFF 130, the address / status holding FF 160, and the output circuit 170 may be the same as those of the BIST circuit 100 according to the conventional example, and thus the description thereof is omitted here. The greatest difference from the BIST circuit 100 according to the conventional example is that the selection comparison circuit 140 is divided into a selection circuit 142 and a comparison circuit 146, and one stage of PLFF 144 is added between the selection circuit 142 and the comparison circuit 146.

[0031] The control circuit 110_1 supplies a selection signal to the selection circuit 142 and supplies a selection signal and an expected value to the comparison circuit 146. At this time, the control circuit 110_1 may delay the selection signal supplied to the comparison circuit 146 by the amount of PLFF 144 compared to the selection signal supplied to the selection circuit 142.

[0032] The selection circuit 142 selects the output data dout_t of the target RAM 20_t to be tested from the output data dout_1~dout_n of the plurality of RAMs 20_1~20_n based on the selection signal supplied from the control circuit 110_1.

[0033] The PLFF 144 holds the selected data selected by the selection circuit 142, that is, the output data dout_t.

[0034] The comparison circuit 146 compares the output of the PLFF 144 with the expected value based on the selection signal.

[0035] The data holding flip-flop 150_1 holds the output of the PLFF 144. At this time, the data holding flip-flop 150 of the BIST circuit 100 according to the conventional example holds the selection data supplied from the control circuit 110 only when the comparison result is an error, whereas the data holding flip-flop 150_1 of the BIST circuit 100_1 according to the first embodiment holds the output of the PLFF 144 regardless of the comparison result by the comparison circuit 146.

[0036] Then, by the control circuit 110_1 controlling the selection signal and the expected value, the BIST circuit 100_1 according to the first embodiment can test the plurality of RAMs 20_1 to 20_n.

[0037] Thus, the BIST circuit 100_1 according to the first embodiment divides the selection comparison circuit 140 into a selection circuit 142 and a comparison circuit 146, and adds one stage of the PLFF 144 therebetween, thereby reducing the number of stages of the logic gates between the flip-flops. According to this, according to the BIST circuit 100_1 according to the first embodiment, even when the number of RAMs 20 mounted on the LSI 1 increases, it is possible to realize a RAMBIST circuit capable of testing the RAM 20 at high speed, preferably at at-speed.

[0038] In the first embodiment, the case where the selection comparison circuit 140 is divided into a selection circuit 142 and a comparison circuit 146, and one stage of the PLFF 144 is added therebetween to reduce the number of stages of the logic gates between the flip-flops has been described as an example. However, when the number of bits of the output data dout_t of the target RAM 20_t is large, if all the bits are to be compared with the expected value at one comparison timing, the number of stages of the logic gates required for the comparison increases. Therefore, in the second embodiment, the output data dout_t of the target RAM 20_t is compared with the expected value in multiple times to reduce the number of stages of the logic gates between the flip-flops.

[0039] FIG. 3 is a diagram showing an example of the functional configuration of the BIST circuit 100_2 according to the second embodiment. Instead of the BIST circuit 100 according to the conventional example, the BIST circuit 100_2 according to the second embodiment may be incorporated in the LSI 1. In this figure, the same or equivalent components and parts as those in FIG. 1 are given the same reference numerals.

[0040] The BIST circuit 100_2 according to the second embodiment includes a control circuit 110_2, an output PLFF 120, an input PLFF 130, a split comparison circuit 148, a data holding FF 150, an address / status holding FF 160, and an output circuit 170.

[0041] The output PLFF 120, the input PLFF 130, the data holding FF 150, the address / status holding FF 160, and the output circuit 170 may be the same as those of the BIST circuit 100 according to the conventional example, and thus the description thereof is omitted here. The most significant difference from the BIST circuit 100 according to the conventional example is that the selection comparison circuit 140 is changed to a split comparison circuit 148.

[0042] The control circuit 110_2 supplies a selection signal for selecting a comparison target and an expected value for collating the selected data selected by the selection signal to the split comparison circuit 148.

[0043] Based on the selection signal supplied from the control circuit 110_2, the split comparison circuit 148 selects a target bit to be compared from a plurality of bits obtained by splitting the output data dout_t of the target RAM_t to be tested. Next, the split comparison circuit 148 compares the selected data selected by the selection signal with the expected value supplied from the control circuit 110_2. Then, the split comparison circuit 148 supplies the selected data and the comparison result to the control circuit 110_2. In response thereto, the control circuit 110_2 supplies the address of the RAM 20 and the comparison result, that is, the test state, to the address / status holding FF 160. Further, when the comparison result is an error, the control circuit 110_2 supplies the selected data to the data holding FF 150.

[0044] Then, by the control circuit 110_2 controlling the selection signal and the expected value, the BIST circuit 100_2 according to the second embodiment can test the target RAM 20_t in multiple times.

[0045] As an example, when the number of bits of the target RAM 20_t is 120 bits, the division comparison circuit 148 divides 120 bits into a first bit group from the 1st bit to the 30th bit, a second bit group from the 31st bit to the 60th bit, a third bit group from the 61st bit to the 90th bit, and a fourth bit group from the 91st bit to the 120th bit based on the selection signal. Then, the division comparison circuit 148 compares the first bit group with the expected value as the selected data at the first comparison timing based on the control signal. Similarly, the division comparison circuit 148 compares the second bit group with the expected value as the selected data at the second comparison timing based on the control signal. Similarly, the division comparison circuit 148 compares the third bit group with the expected value as the selected data at the third comparison timing based on the control signal. Similarly, the division comparison circuit 148 compares the fourth bit group with the expected value as the selected data at the fourth comparison timing based on the control signal.

[0046] For example, in this way, when the number of bits of the output data dout_t of the target RAM 20_t is 120 bits, the BIST circuit 100_2 according to the second embodiment compares with the expected value in four portions of 30 bits each.

[0047] In this way, the BIST circuit 100_2 according to the second embodiment sequentially executes the process of the division comparison circuit 148 selecting the target bits to be compared from a plurality of bits based on the selection signal and comparing them with the expected value. Thereby, the BIST circuit 100_2 according to the second embodiment can reduce the number of stages of the logic gates required for comparison, and thus can reduce the number of stages of the logic gates between FFs.

[0048] FIG. 4 is a diagram showing an example of a time chart of the BIST circuit 100 according to the conventional example. In this figure, from top to bottom, it shows the clock, address, chip enable, write enable, input data and output data of the RAM 20, as well as the input PLFF data, comparison result and diagnostic output. Also, in this figure, the upward arrow indicates the timing for holding the comparison result.

[0049] In the BIST circuit 100 according to the conventional example, all bits of the output data dout_t of the target RAM 20_t are compared with the expected value at one comparison timing. That is, for example, when the number of bits of the target RAM 20_t is 120 bits, the selection comparison circuit 140 executes an expected value comparison of 120 bits at one comparison timing.

[0050] In this figure, as an example, as a result of comparing 120 bits of A2D0 in the output data dout_t of the target RAM 20_t with the expected value, it does not match the expected value and the comparison result becomes High, and error information, that is, the address, data and test state where the error occurred are output as the diagnostic output. This is shown as an example.

[0051] FIG. 5 is a diagram showing an example of a time chart of the BIST circuit 100_2 according to the second embodiment. Also in this figure, similar to FIG. 4, from top to bottom, it shows the clock, address, chip enable, write enable, input data and output data of the RAM 20, as well as the input PLFF data, comparison result and diagnostic output. Also, in this figure, similar to FIG. 4, the upward arrow indicates the timing for holding the comparison result.

[0052] In the BIST circuit 100_2 according to the second embodiment, the output data dout_t of the target RAM 20_t is divided into bit groups and compared with the expected value at one comparison timing. That is, for example, when the number of bits of the target RAM 20_t is 120 bits, the division comparison circuit 148 executes an expected value comparison of 30 bits obtained by dividing 120 bits into 4 parts at one comparison timing.

[0053] In this figure, as an example, as a result of comparing the 4th bit group from the 91st bit to the 120th bit out of 120 bits of A0D1 in the output data dout_t of the target RAM20_t, it does not match the expected value and the comparison result is High, and an example where error information is output as a diagnostic output is shown.

[0054] Thus, according to the BIST circuit 100_2 according to the second embodiment, by controlling the read, write, and expected value comparison of the RAM20 as shown in this figure and reducing the number of bits for which the expected value comparison is executed at one comparison timing, the number of bits input to the comparator in the divided comparison circuit 148 can be reduced, and thus the number of stages of the logic gates between the FFs can be reduced.

[0055] In the above description, the first embodiment and the second embodiment are shown as separate embodiments. However, by combining the first embodiment and the second embodiment, the number of stages of the logic gates between the FFs can be further reduced.

[0056] In this case, the comparison circuit 146 in the first embodiment may function in the same manner as the divided comparison circuit 148 in the second embodiment. In this case, the comparison circuit 146 may select a target bit to be compared from a plurality of bits obtained by dividing the output of the PLFF144 based on a selection signal, and compare the target bit with the expected value. Thereby, since the number of stages of the logic gates between the FFs can be further reduced, a RAMBIST circuit that operates at a higher speed can be realized.

[0057] The present disclosure also includes the following content.

[0058] (Appendix 1) A selection circuit that selects output data of a target RAM to be tested from output data of a plurality of RAMs based on a selection signal; A pipeline flip-flop that holds the selection data selected by the selection circuit; A comparison circuit that compares the output of the pipeline flip-flop with an expected value based on the selection signal; A control circuit that controls the selection signal and the expected value; Comprising: A test circuit. (Appendix 2) Further comprising a data holding flip-flop that holds the output of the pipeline flip-flop, The test circuit according to Appendix 1. (Appendix 3) The data holding flip-flop holds the output of the pipeline flip-flop regardless of the comparison result by the comparison circuit, The test circuit according to Appendix 2. (Appendix 4) The control circuit delays the selection signal supplied to the comparison circuit by the number of pipeline flip-flops more than the selection signal supplied to the selection circuit, The test circuit according to any one of Appendices 1 to 3. (Appendix 5) The comparison circuit selects a target bit to be compared from a plurality of bits obtained by dividing the output of the pipeline flip-flop based on the selection signal, and compares the target bit with the expected value, The test circuit according to any one of Appendices 1 to 4. (Appendix 6) A split comparison circuit that selects a target bit to be compared from a plurality of bits obtained by dividing the output data of a target RAM to be tested based on a selection signal, and compares the target bit with an expected value; A control circuit that controls the selection signal and the expected value; Comprising: A test circuit.

Explanation of Signs

[0059] 1 LSI 10 RAM peripheral circuit 20 RAM 100 BIST circuit 110 Control circuit 120 Output PLFF 130 Input PLFF 140 Selection and Comparison Circuit 142 Selection Circuit 144 PLFF 146 Comparison Circuit 148 Split Comparison Circuit 150 Data Retention FF 160 Address and Status Retention FF 170 Output Circuit

Claims

1. A selection circuit that selects output data of a target RAM to be tested from output data of a plurality of RAMs based on a selection signal; A pipeline flip-flop that holds the selection data selected by the selection circuit; A comparison circuit that compares the output of the pipeline flip-flop with an expected value based on the selection signal; A control circuit that controls the selection signal and the expected value; A test circuit comprising: A test circuit.

2. The test circuit according to claim 1, further comprising a data holding flip-flop that holds the output of the pipeline flip-flop. The test circuit according to claim 1.

3. The test circuit according to claim 2, wherein the data holding flip-flop holds the output of the pipeline flip-flop regardless of the comparison result by the comparison circuit. The test circuit according to claim 2.

4. The test circuit according to any one of claims 1 to 3, wherein the control circuit delays the selection signal supplied to the comparison circuit by the amount of the pipeline flip-flop compared to the selection signal supplied to the selection circuit. The test circuit according to any one of claims 1 to 3.

5. The test circuit according to any one of claims 1 to 3, wherein the comparison circuit selects a target bit to be compared from a plurality of bits obtained by dividing the output of the pipeline flip-flop based on the selection signal, and compares the target bit with the expected value. The test circuit according to any one of claims 1 to 3.

6. A split comparison circuit that selects a target bit to be compared from a plurality of bits obtained by dividing the output data of a target RAM to be tested based on a selection signal, and compares the target bit with an expected value; A control circuit that controls the selection signal and the expected value; A test circuit comprising: A test circuit.

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