Memory circuit, resistance type nonvolatile memory, and operating method for the same

Abstract

To provide a resistance type nonvolatile memory.SOLUTION: A resistance type nonvolatile memory includes at least one resistance change type field effect transistor electrically connected to at least one bit line, and a monopolar source / channel / drain diode formed of a field effect transistor without a gate electrode and having both ends electrically connected to a source wire and at least one resistance change type field effect transistor.SELECTED DRAWING: Figure 7A

Description

Technical Field

[0001] The present invention relates to a memory circuit and an operation method thereof, and more particularly, to a memory circuit, a resistive non-volatile memory, and an operation method thereof.

Background Art

[0002] With the development speed of Moore's law, various embedded memories have come to be mass-produced at foundries. In many application fields, semiconductor memories are widely applied to various electronic products.

Summary of the Invention

Problems to be Solved by the Invention

[0003] However, since conventional embedded memories are formed by the front-end process and the back-end process of complementary metal-oxide-semiconductor (CMOS) technology, the number of photomasks and manufacturing processes increases, resulting in high costs. Also, in the technology of conventional embedded memories, all of them adopt a three-terminal active element as a control transistor and require a word line and related circuits separately, so the power consumption increases and the area becomes too large.

Means for Solving the Problems

[0004] The present invention proposes a memory circuit, a resistive non-volatile memory, and an operation method thereof that improve the problems of the background art.

[0005] In some embodiments of the present invention, the present invention proposes a resistive non-volatile memory including at least one resistive change type field effect transistor electrically connected to at least one bit line, and a field effect transistor without a gate electrode, and a unipolar source / channel / drain diode having both ends electrically connected to a source line and at least one resistive change type field effect transistor, respectively.

[0006] In some embodiments of the present invention, at least one resistive change type field effect transistor has a gate electrically connected to at least one bit line, a first end that is floating, and a unipolar source / channel / drain diode has both ends electrically connected to a source line and a second end of at least one resistive change type field effect transistor respectively, and the unipolar source / channel / drain diode is an npn type diode or a nin type diode.

[0007] In some embodiments of the present invention, the unipolar source / channel / drain diode includes a floating dummy gate, a first source / drain diffusion region and a second source / drain diffusion region respectively located on opposite sides of the floating dummy gate, and the first source / drain diffusion region contacts one end of a contact plug, and the other end of the contact plug contacts the source line.

[0008] In some embodiments of the present invention, the unipolar source / channel / drain diode and at least one resistive change type field effect transistor share the second source / drain diffusion region, and the at least one resistive change type field effect transistor includes a shallow trench isolation that directly contacts the gate of the at least one resistive change type field effect transistor, and the shallow trench isolation and the second source / drain diffusion region are respectively located on opposite sides of the gate of the at least one resistive change type field effect transistor, the shallow trench isolation functions as the first end of the at least one resistive change type field effect transistor, and the second source / drain diffusion region functions as the second end of the at least one resistive change type field effect transistor.

[0009] In some embodiments of the present invention, a unipolar source / channel / drain diode has both ends electrically connected to a source line and a gate of at least one resistive change type field effect transistor respectively, and at least one resistive change type field effect transistor has a first end that is floating and a second end that is electrically connected to at least one bit line. The unipolar source / channel / drain diode is a pnp type diode or a pip type diode.

[0010] In some embodiments of the present invention, a unipolar source / channel / drain diode includes a floating dummy gate, a first source / drain diffusion region and a second source / drain diffusion region located on opposite sides of the floating dummy gate respectively.

[0011] In some embodiments of the present invention, a resistive non-volatile memory further includes a first conductive layer and a second conductive layer that are electrically insulated from each other, a first contact plug having both ends contacting the first source / drain diffusion region and the first conductive layer respectively, a second contact plug having both ends contacting the first conductive layer and the source line respectively, a third contact plug having both ends contacting the second source / drain diffusion region and the second conductive layer respectively, and a fourth contact plug having both ends contacting a gate of at least one resistive change type field effect transistor and the second conductive layer respectively.

[0012] In some embodiments of the present invention, at least one resistive change type field effect transistor includes a shallow trench isolation that directly contacts a gate of at least one resistive change type field effect transistor and functions as a first end of at least one resistive change type field effect transistor, and a third source / drain diffusion region that is located on opposite sides of the shallow trench isolation with respect to the gate of at least one resistive change type field effect transistor and functions as a second end of at least one resistive change type field effect transistor.

[0013] In some embodiments of the present invention, the resistive non-volatile memory further includes a fifth contact plug whose both ends are in contact with a third source / drain diffusion region and at least one bit line, respectively.

[0014] In some embodiments of the present invention, the present invention proposes a memory circuit including a plurality of memory cells arranged in an array and each including a resistive non-volatile memory, where the resistive non-volatile memory includes at least one resistive change type field effect transistor electrically connected to at least one bit line, and a field effect transistor without a gate electrode, and a unipolar source / channel / drain diode whose both ends are electrically connected to a source line and at least one resistive change type field effect transistor, respectively.

[0015] In some embodiments of the present invention, each memory cell includes another resistive non-volatile memory whose one end is electrically connected to the resistive non-volatile memory and at least one bit line, and the other end is electrically connected to another source line.

[0016] In some embodiments of the present invention, each memory cell includes another resistive non-volatile memory whose one end is electrically connected to the resistive non-volatile memory and the source line, and the other end is electrically connected to at least one bit line.

[0017] In some embodiments of the present invention, at least one resistive change type field effect transistor has a gate electrically connected to at least one bit line, a first end that is floating, and a unipolar source / channel / drain diode having both ends electrically connected to a source line and a second end of at least one resistive change type field effect transistor respectively. Each memory cell includes another resistive non-volatile memory, and the other resistive non-volatile memory is composed of another at least one resistive change type field effect transistor having a gate electrically connected to another at least one bit line and a first end that is floating, and another field effect transistor without a gate electrode, and another unipolar source / channel / drain diode having both ends electrically connected to a source line and a second end of another at least one resistive change type field effect transistor respectively.

[0018] In some embodiments of the present invention, a unipolar source / channel / drain diode has both ends electrically connected to a source line and a gate of at least one resistive change type field effect transistor respectively. The at least one resistive change type field effect transistor has a first end that is floating and a second end electrically connected to at least one bit line. Each memory cell includes another resistive non-volatile memory, and the other resistive non-volatile memory is composed of another at least one resistive change type field effect transistor having a first end that is floating and a second end electrically connected to at least one bit line, and another field effect transistor without a gate electrode, and another unipolar source / channel / drain diode having both ends electrically connected to another source line and a gate of another at least one resistive change type field effect transistor respectively.

[0019] In some embodiments of the present invention, the present invention is a method of operating a resistive non-volatile memory including a resistive change type field effect transistor and a unipolar source / channel / drain diode connected to each other, the method including the step of operating the resistive non-volatile memory by applying a zero voltage to one of a bit line and a source line and applying a non-zero voltage to the other of the bit line and the source line, the resistive change type field effect transistor being electrically connected to the bit line, the unipolar source / channel / drain diode being composed of a field effect transistor without a gate electrode, and both ends being electrically connected to the source line and the resistive change type field effect transistor respectively, and a method of operating a resistive non-volatile memory is proposed.

[0020] In some embodiments of the present invention, for the resistive change type field effect transistor, the gate is electrically connected to the bit line, the first end is floating, for the unipolar source / channel / drain diode, both ends are electrically connected to the source line and the second end of the resistive change type field effect transistor respectively, the unipolar source / channel / drain diode is an npn type diode or a nin type diode, and the operation method further includes, in the startup stage, when the resistive non-volatile memory is selected, applying a startup voltage to the bit line and applying a zero voltage to the source line; in the setting stage, when the resistive non-volatile memory is selected, applying a setting voltage whose absolute value is less than or equal to the absolute value of the startup voltage to the bit line and applying a zero voltage to the source line; in the reset stage, when the resistive non-volatile memory is selected, applying a reset voltage whose absolute value is smaller than the absolute value of the setting voltage to the bit line and applying a zero voltage to the source line; and in the reading stage, when the resistive non-volatile memory is selected, applying a reading voltage whose absolute value is smaller than the absolute value of the reset voltage to the bit line and applying a zero voltage to the source line.

[0021] In some embodiments of the present invention, the operation method includes, in the startup stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the startup voltage to the source line and applying a zero voltage to the bit line; in the setting stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the setting voltage to the source line and applying a zero voltage to the bit line; in the reset stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the reset voltage to the source line and applying a zero voltage to the bit line; and in the readout stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the readout voltage to the source line and applying a zero voltage to the bit line.

[0022] In some embodiments of the present invention, the unipolar source / channel / drain diode has both ends electrically connected to the source line and the gate of the resistive change type field effect transistor respectively. However, for the resistive change type field effect transistor, the first end is floating and the second end is electrically connected to the bit line. The unipolar source / channel / drain diode is a pnp type diode or a pip type diode. The operation method includes, in the startup stage, when the resistive non-volatile memory is selected, applying the startup voltage to the source line and applying a zero voltage to the bit line; in the setting stage, when the resistive non-volatile memory is selected, applying a setting voltage whose absolute value is less than or equal to the absolute value of the startup voltage to the source line and applying a zero voltage to the bit line; in the reset stage, when the resistive non-volatile memory is selected, applying a reset voltage whose absolute value is smaller than the absolute value of the setting voltage to the source line and applying a zero voltage to the bit line; and in the readout stage, when the resistive non-volatile memory is selected, applying a readout voltage whose absolute value is smaller than the absolute value of the reset voltage to the source line and applying a zero voltage to the bit line.

[0023] In some embodiments of the present invention, the operation method includes, in the startup stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the startup voltage to the bit line and applying a zero voltage to the source line; in the setting stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the setting voltage to the bit line and applying a zero voltage to the source line; in the reset stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the reset voltage to the bit line and applying a zero voltage to the source line; and in the read stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the read voltage to the bit line and applying a zero voltage to the source line.

Advantages of the Invention

[0024] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The resistive non-volatile memory of the present invention does not require a separate word line and its related circuits, realizes a super-small chip size, contributes to the continuous scaling of CMOS, a simpler chip configuration layout, and higher cost efficiency.

[0025] Hereinafter, the above description will be described in detail by embodiments to further interpret the technical solution of the present invention.

Brief Description of the Drawings

[0026] The following description of the accompanying drawings is for the purpose of making the above and other objects, features, advantages and embodiments of the present invention more obvious and understandable.

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DETAILED DESCRIPTION OF THE INVENTION

[0027] To make the description of the present invention more detailed and complete, reference can be made to the accompanying drawings and various embodiments shown below, and the same reference numerals in the drawings represent the same or similar elements. On the other hand, well-known elements and processes are not described in the embodiments in order to avoid unnecessary limitations on the present invention.

[0028] FIG. 1A is a circuit diagram of a unipolar source / channel / drain diode 110 according to some embodiments of the present invention. As shown in FIG. 1A, the unipolar source / channel / drain diode 110 is an npn-type diode and is composed of a field-effect transistor without a gate electrode so as to be compatible with a semiconductor manufacturing process. As an example, for the unipolar source / channel / drain diode 110, both ends 111 and 112 are a source and a drain, respectively.

[0029] FIG. 1B is a circuit diagram of a unipolar source / channel / drain diode 120 according to some embodiments of the present invention. As shown in FIG. 1B, the unipolar source / channel / drain diode 120 is a nin-type diode and is composed of a field-effect transistor without a gate electrode so as to be compatible with a semiconductor manufacturing process. As an example, for the unipolar source / channel / drain diode 120, both ends 121 and 122 are a source and a drain, respectively.

[0030] FIG. 1C is a circuit diagram of a unipolar source / channel / drain diode 130 according to some embodiments of the present invention. As shown in FIG. 1C, the unipolar source / channel / drain diode 130 is a pip-type diode and is composed of a field-effect transistor without a gate electrode so as to be compatible with a semiconductor manufacturing process. As an example, both ends 131 and 132 of the unipolar source / channel / drain diode 130 are a source and a drain, respectively.

[0031] FIG. 1D is a circuit diagram of a unipolar source / channel / drain diode 140 according to some embodiments of the present invention. As shown in FIG. 1D, the unipolar source / channel / drain diode 140 is a pnp-type diode and is composed of a field-effect transistor without a gate electrode so as to be compatible with a semiconductor manufacturing process. As an example, both ends 141 and 142 of the unipolar source / channel / drain diode 140 are a source and a drain, respectively.

[0032] FIG. 2 shows the electrical characteristics 200 of the unipolar source / channel / drain diode 140 of FIG. 1D. As shown in FIG. 2, the unipolar source / channel / drain diode 140 has unipolar rectification characteristics. The drain current flows in the forward direction when the drain-source voltage of the unipolar source / channel / drain diode 140 is greater than zero voltage, but saturates in the reverse direction when the drain-source voltage of the unipolar source / channel / drain diode 140 is less than zero voltage.

[0033] Referring to FIGS. 3A-3D and 4A-4D, the technical aspects of the present invention are resistive non-volatile memories 301-304, 401-404, which can be applied to embedded resistive non-volatile memories or widely used in related technical stages. The resistive non-volatile memories 301-304, 401-404 of this technical aspect can achieve considerable technological progress and have broad industrial application value. Hereinafter, specific embodiments of the resistive non-volatile memories 301-304, 401-404 will be described in accordance with FIGS. 3A-3D and 4A-4D, respectively.

[0034] It should be understood that various embodiments of the resistive non-volatile memories 301 to 304, 401 to 404 will be described with reference to FIGS. 3A to 3D, 4A to 4D. In the following description, in order to make it easier to understand, many specific details are further set to provide a comprehensive description of one or more embodiments. However, the present technology can be implemented without these specific details. In other examples, in order to effectively describe these embodiments, known structures and devices are shown in block diagrams. The term "for example" used herein means "by way of example, instance or illustration". Any example described herein as "for example" should not be construed as being preferred or superior to other examples.

[0035] FIG. 3A is a circuit diagram of a resistive non-volatile memory 301 according to some embodiments of the present invention. As shown in FIG. 3A, the resistive non-volatile memory 301 includes a resistive change type field effect transistor 310 and a unipolar source / channel / drain diode 110. Structurally, the resistive change type field effect transistor 310 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 110 has both ends 111 and 112 electrically connected to the source line SL and the resistive change type field effect transistor 310, respectively.

[0036] In FIG. 3A, for the resistive change type field effect transistor 310, the gate 313 is electrically connected to the bit line BL, its first end 311 is floating, and for the unipolar source / channel / drain diode 110, both ends 111 and 112 are electrically connected to the source line SL and the second end 312 of the resistive change type field effect transistor 310, respectively. The unipolar source / channel / drain diode 110 is an npn type diode, and the resistive change type field effect transistor 310 is an npn type resistive change type field effect transistor.

[0037] It should be noted that although various elements may be described herein using terms such as "first", "second", etc., these elements are not limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the embodiments, the first element may be referred to as the second element, and similarly, the second element may be referred to as the first element.

[0038] FIG. 3B is a circuit diagram of a resistive nonvolatile memory 302 according to some embodiments of the present invention. As shown in FIG. 3B, the resistive nonvolatile memory 302 includes a resistive change type field effect transistor 320 and a unipolar source / channel / drain diode 110. Structurally, the resistive change type field effect transistor 320 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 110 has both ends 111 and 112 electrically connected to the source line SL and the resistive change type field effect transistor 320, respectively.

[0039] In FIG. 3B, for the resistive change type field effect transistor 320, the gate 323 is electrically connected to the bit line BL, its first end 321 is floating, and for the unipolar source / channel / drain diode 110, both ends 111 and 112 are electrically connected to the source line SL and the second end 322 of the resistive change type field effect transistor 320, respectively. The unipolar source / channel / drain diode 110 is an npn type diode, and the resistive change type field effect transistor 320 is a pnp type resistive change type field effect transistor.

[0040] FIG. 3C is a circuit diagram of a resistive nonvolatile memory 303 according to some embodiments of the present invention. As shown in FIG. 3C, the resistive nonvolatile memory 303 includes a resistive change type field effect transistor 330 and a unipolar source / channel / drain diode 120. Structurally, the resistive change type field effect transistor 330 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 120 has both ends 121 and 122 electrically connected to the source line SL and the resistive change type field effect transistor 330, respectively.

[0041] In FIG. 3C, for the resistive change type field effect transistor 330, the gate 333 is electrically connected to the bit line BL, its first end 331 is floating, and for the unipolar source / channel / drain diode 120, both ends 121 and 122 are electrically connected to the source line SL and the second end 332 of the resistive change type field effect transistor 330, respectively. The unipolar source / channel / drain diode 120 is a nin-type diode, and the resistive change type field effect transistor 330 is a nin-type resistive change type field effect transistor.

[0042] FIG. 3D is a circuit diagram of a resistive nonvolatile memory 304 according to some embodiments of the present invention. As shown in FIG. 3D, the resistive nonvolatile memory 304 includes a resistive change type field effect transistor 340 and an unipolar source / channel / drain diode 120. Structurally, the resistive change type field effect transistor 340 is electrically connected to the bit line BL, and for the unipolar source / channel / drain diode 120, both ends 121 and 122 are electrically connected to the source line SL and the resistive change type field effect transistor 340, respectively.

[0043] In FIG. 3D, for the resistive change type field effect transistor 340, the gate 343 is electrically connected to the bit line BL, its first end 341 is floating, and for the unipolar source / channel / drain diode 120, both ends 121 and 122 are electrically connected to the source line SL and the second end 342 of the resistive change type field effect transistor 340, respectively. The unipolar source / channel / drain diode 120 is a nin-type diode, and the resistive change type field effect transistor 330 is a pip-type resistive change type field effect transistor.

[0044] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 301 to 304 are all the same. To simplify the description, hereinafter, taking the operation of the resistive non-volatile memory 301 as an example, a zero voltage is applied to one of the bit line BL and the source line SL, and a non-zero voltage is applied to the other of them to operate the resistive non-volatile memory 301.

[0045] Specifically, in the forming stage, when the resistive non-volatile memory 301 is selected, a forming voltage is applied to the bit line BL and a zero voltage is applied to the source line SL to form a conductive filament in the gate dielectric layer of the gate of the resistive change type field effect transistor 310. In the setting stage, when the resistive non-volatile memory 301 is selected, a setting voltage whose absolute value is less than or equal to the absolute value of the forming voltage is applied to the bit line BL and a zero voltage is applied to the source line SL to set the gate dielectric layer of the gate of the resistive change type field effect transistor 310 to the first resistance state. In the reset stage, when the resistive non-volatile memory 301 is selected, a reset voltage whose absolute value is smaller than the absolute value of the setting voltage is applied to the bit line BL and a zero voltage is applied to the source line SL to set the gate dielectric layer of the gate of the resistive change type field effect transistor 310 to the second resistance state. In the reading stage, when the resistive non-volatile memory 301 is selected, a reading voltage whose absolute value is smaller than the absolute value of the reset voltage is applied to the bit line BL and a zero voltage is applied to the source line SL. Based on the magnitude of the reading current by the reading circuit, it is determined whether the resistive non-volatile memory 301 is set or reset.

[0046] On the one hand, in the startup stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL. In the setting stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL. In the reset stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL. In the readout stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the readout voltage is applied to the source line SL, and a zero voltage is applied to the bit line BL.

[0047] FIG. 4A is a circuit diagram of a resistive non-volatile memory 401 according to some embodiments of the present invention. As shown in FIG. 4A, the resistive non-volatile memory 401 includes a resistive change type field effect transistor 410 and a unipolar source / channel / drain diode 140. Structurally, the resistive change type field effect transistor 410 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 140 has both ends 141 and 142 electrically connected to the source line SL and the resistive change type field effect transistor 410, respectively.

[0048] In FIG. 4A, for the unipolar source / channel / drain diode 140, both ends 141 and 142 are electrically connected to the source line SL and the gate 413 of the resistive change type field effect transistor 410, respectively. For the resistive change type field effect transistor 410, the first end 411 is floating, and the second end 412 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 140 is a pnp type diode, and the resistive change type field effect transistor 410 is a pnp type resistive change type field effect transistor.

[0049] FIG. 4B is a circuit diagram of a resistive non-volatile memory 402 according to some embodiments of the present invention. As shown in FIG. 4B, the resistive non-volatile memory 402 includes a resistive change type field effect transistor 420 and a unipolar source / channel / drain diode 130. Structurally, the resistive change type field effect transistor 420 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 130 has both ends 131 and 132 electrically connected to the source line SL and the resistive change type field effect transistor 420, respectively.

[0050] In FIG. 4B, for the unipolar source / channel / drain diode 130, both ends 131 and 132 are electrically connected to the source line SL and the gate 423 of the resistive change type field effect transistor 420, respectively. For the resistive change type field effect transistor 420, the first end 421 is floating, and the second end 422 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 130 is a pip type diode, and the resistive change type field effect transistor 420 is a pip type resistive change type field effect transistor.

[0051] FIG. 4C is a circuit diagram of a resistive non-volatile memory 403 according to some embodiments of the present invention. As shown in FIG. 4C, the resistive non-volatile memory 403 includes a resistive change type field effect transistor 430 and a unipolar source / channel / drain diode 140. Structurally, the resistive change type field effect transistor 430 is electrically connected to the bit line BL, and the unipolar source / channel / drain diode 140 has both ends 141 and 142 electrically connected to the source line SL and the resistive change type field effect transistor 430, respectively.

[0052] In FIG. 4C, the unipolar source / channel / drain diode 140 has both ends 141 and 142 electrically connected to the source line SL and the gate 433 of the resistive change type field effect transistor 430, respectively. However, for the resistive change type field effect transistor 430, the first end 431 is floating and the second end 432 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 140 is a pnp type diode, and the resistive change type field effect transistor 430 is an npn type resistive change type field effect transistor.

[0053] FIG. 4D is a circuit diagram of the resistive non-volatile memory 404 according to some embodiments of the present invention. As shown in FIG. 4D, the resistive non-volatile memory 404 includes a resistive change type field effect transistor 440 and a unipolar source / channel / drain diode 140. Structurally, the resistive change type field effect transistor 440 is electrically connected to the bit line BL, and for the unipolar source / channel / drain diode 140, both ends 141 and 142 are electrically connected to the source line SL and the resistive change type field effect transistor 440, respectively.

[0054] In FIG. 4D, the unipolar source / channel / drain diode 140 has both ends 141 and 142 electrically connected to the source line SL and the gate 443 of the resistive change type field effect transistor 440, respectively. However, for the resistive change type field effect transistor 440, the first end 441 is floating and the second end 442 is electrically connected to the bit line BL. The unipolar source / channel / drain diode 140 is a pnp type diode, and the resistive change type field effect transistor 440 is an nin type resistive change type field effect transistor.

[0055] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 401 to 404 are all the same. To simplify the description, hereinafter, taking the operation of the resistive non-volatile memory 403 as an example, the resistive non-volatile memory 403 is operated by applying a zero voltage to one of the bit line BL and the source line SL and applying a non-zero voltage to the other.

[0056] Specifically, in the startup phase, when the resistive non-volatile memory 403 is selected, an activation voltage is applied to the source line SL and a zero voltage is applied to the bit line BL, thereby forming a conductive filament in the gate dielectric layer of the gate of the resistive change type field effect transistor 430. In the setting phase, when the resistive non-volatile memory 403 is selected, a setting voltage whose absolute value is equal to or less than the absolute value of the activation voltage is applied to the source line SL and a zero voltage is applied to the bit line BL, thereby setting the gate dielectric layer of the gate of the resistive change type field effect transistor 430 to a first resistance state. In the reset phase, when the resistive non-volatile memory 403 is selected, a reset voltage whose absolute value is smaller than the absolute value of the setting voltage is applied to the source line SL and a zero voltage is applied to the bit line BL, thereby setting the gate dielectric layer of the gate of the resistive change type field effect transistor 430 to a second resistance state. In the readout phase, when the resistive non-volatile memory 403 is selected, a readout voltage whose absolute value is smaller than the absolute value of the reset voltage is applied to the source line SL and a zero voltage is applied to the bit line BL. Based on the magnitude of the readout current by the readout circuit, it is determined whether the resistive non-volatile memory 403 is set or reset.

[0057] On the other hand, in the startup phase, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the activation voltage is applied to the bit line BL and a zero voltage is applied to the source line SL. In the setting phase, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the bit line BL and a zero voltage is applied to the source line SL. In the reset phase, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the bit line BL and a zero voltage is applied to the source line SL. In the readout phase, when the resistive non-volatile memory 403 is not selected, a voltage between one-half and one-fifth of the readout voltage is applied to the bit line BL and a zero voltage is applied to the source line SL.

[0058] FIG. 5A is a circuit diagram of a memory circuit according to some embodiments of the present invention. As shown in FIG. 5A, the memory circuit includes a plurality of memory cells 505 arranged in an array. Each memory cell 505 includes a resistive non-volatile memory 501. In practice, by way of example, the architecture of the resistive non-volatile memory 501 may be any one of the resistive non-volatile memories 301 to 304 and 401 to 404 described above.

[0059] In FIG. 5A, a circuit 511 is electrically connected to one end of a unipolar source / channel / drain diode in a corresponding resistive non-volatile memory 501 via source lines SL0 to SLn, and a circuit 512 is electrically connected to a resistive change type field effect transistor in a corresponding resistive non-volatile memory 501 via bit lines BL1 to BLn. In practice, by way of example, the circuit 511 includes a source line peripheral circuit and a control circuit, the circuit 512 includes a bit line peripheral circuit and a control circuit, and the read circuit may be selectively provided in the circuit 511 or the circuit 512.

[0060] FIG. 5B is a circuit diagram of a memory circuit according to some embodiments of the present invention. As shown in FIG. 5B, the memory circuit includes a plurality of memory cells 506 arranged in an array. Each memory cell 506 includes resistive non-volatile memories 502a and 502b. In practice, by way of example, the architecture of the resistive non-volatile memory 502a may be any one of the resistive non-volatile memories 301 to 304 and 401 to 404 described above. Similarly, the architecture of the resistive non-volatile memory 502b may be any one of the resistive non-volatile memories 301 to 304 and 401 to 404 described above.

[0061] Taking the corner memory cell 506 as an example, the resistive non-volatile memories 502a and 502b share the same bit line BL1. One end of the resistive non-volatile memory 502b is electrically connected to one end of the resistive non-volatile memory 502a and the bit line BL1. The other end of the resistive non-volatile memory 502b is electrically connected to the source line SL1, and the other end of the resistive non-volatile memory 502a is electrically connected to the source line SL0.

[0062] In FIG. 5B, circuit 521 is electrically connected to one end of each of the unipolar source / channel / drain diodes of the corresponding resistive nonvolatile memories 502a and 502b via source lines SL0 to SLn, and circuit 522 is electrically connected to the resistive change type field effect transistors of the corresponding resistive nonvolatile memories 502a and 502b via bit lines BL1 to BLn. Actually, as an example, circuit 521 includes a source line peripheral circuit and a control circuit, circuit 522 includes a bit line peripheral circuit and a control circuit, and the read circuit may be selectively provided in circuit 521 or circuit 522.

[0063] FIG. 5C is a circuit diagram of a memory circuit according to some embodiments of the present invention. As shown in FIG. 5C, the memory circuit includes a plurality of memory cells 507 arranged in an array. Each memory cell 507 includes resistive nonvolatile memories 503a and 503b. Actually, as an example, the architecture of resistive nonvolatile memory 503a may be any one of the resistive nonvolatile memories 301 to 304 and 401 to 404 described above. Similarly, the architecture of resistive nonvolatile memory 503b may be any one of the resistive nonvolatile memories 301 to 304 and 401 to 404 described above.

[0064] Taking the corner memory cell 507 as an example, the resistive nonvolatile memories 503a and 503b share the same bit line BL1 and the same source line SL0. One end of the resistive nonvolatile memory 503b is electrically connected to one end of the resistive nonvolatile memory 503a and the source line SL0. The other end of the resistive nonvolatile memory 503b is electrically connected to the bit line BL1, and the other end of the resistive nonvolatile memory 503a is electrically connected to the bit line BL1.

[0065] In FIG. 5C, circuit 531 is electrically connected to one end of each of the unipolar source / channel / drain diodes of the corresponding resistive nonvolatile memories 503a and 503b via source lines SL0 to SLn, and circuit 532 is electrically connected to the resistive change type field effect transistors of the corresponding resistive nonvolatile memories 503a and 503b via bit lines BL1 to BLn. Actually, for example, circuit 531 includes a source line peripheral circuit and a control circuit, circuit 532 includes a bit line peripheral circuit and a control circuit, and the read circuit may be selectively provided in circuit 531 or circuit 532.

[0066] FIG. 6A is a circuit diagram of a memory cell 600 according to some embodiments of the present invention. As shown in FIG. 6A, the memory cell 600 includes resistive nonvolatile memories 301a and 301b, both of which have substantially the same structure and are arranged symmetrically with respect to each other. Each of the resistive nonvolatile memories 301a and 301b in FIG. 6A is substantially the same as the resistive nonvolatile memory 301 in FIG. 3A.

[0067] In FIG. 6A, for the resistive change type field effect transistor 310b, the gate 313 is electrically connected to the bit line BL1, but the first end 311 is floating, and for the unipolar source / channel / drain diode 110b, both ends 111 and 112 are electrically connected to the source line SL1 and the second end 312 of the resistive change type field effect transistor 310b, respectively. For the resistive change type field effect transistor 310a, the gate 313 is electrically connected to the bit line BL0, but the first end 311 is floating, and for the unipolar source / channel / drain diode 110a, both ends 111 and 112 are electrically connected to the source line SL1 and the second end 312 of the resistive change type field effect transistor 310a, respectively.

[0068] FIG. 6B is a layout schematic diagram of the memory cell 600 according to some embodiments of the present invention. As shown in FIG. 6B, the source line SL0 is located above the diffusion region 612, and the source line SL1 is located above the diffusion region 611.

[0069] FIG. 6C is a cross-sectional view of a memory cell 600 according to some embodiments of the present invention. As shown in FIG. 6C, the unipolar source / channel / drain diode 110b includes a floating dummy gate 621, a first source / drain diffusion region 661, and a second source / drain diffusion region 662. The first source / drain diffusion region 661 and the second source / drain diffusion region 662 are located on opposite sides of the floating dummy gate 621, respectively. The first source / drain diffusion region 661 contacts one end of the contact plug 670, and the other end of the contact plug 670 contacts the source line SL1. In practice, by way of example, the floating dummy gate 621 has no gate electrode and is not connected to any conducting wire. The first source / drain diffusion region 661 and the second source / drain diffusion region 662 in FIG. 6C function as both ends 111 and 112 of the unipolar source / channel / drain diode 110b in FIG. 6A, respectively.

[0070] The unipolar source / channel / drain diodes 110a and 110b share the first source / drain diffusion region 661. The unipolar source / channel / drain diode 110a includes a floating dummy gate 622, a first source / drain diffusion region 661, and a third source / drain diffusion region 663. In practice, by way of example, the floating dummy gate 622 has no gate electrode and is not connected to any conducting wire. The second source / drain diffusion region 661 and the third source / drain diffusion region 663 in FIG. 6C function as both ends 111 and 112 of the unipolar source / channel / drain diode 110a in FIG. 6A, respectively.

[0071] In FIG. 6C, the unipolar source / channel / drain diode 110b and the resistive change type field effect transistor 310b share the second source / drain diffusion region 662. The resistive change type field effect transistor 310b includes a shallow trench isolation 651. The shallow trench isolation 651 is in direct contact with the gate 313 of the resistive change type field effect transistor 310b, and the shallow trench isolation 651 and the second source / drain diffusion region 662 are respectively located on opposite sides of the gate 313 of the resistive change type field effect transistor 310b, and the channel region 630 is between the shallow trench isolation 651 and the second source / drain diffusion region 662. The shallow trench isolation 651 in FIG. 6C functions as the first end 311 of the resistive change type field effect transistor 310b in FIG. 6A, and the second source / drain diffusion region 662 in FIG. 6C functions as the second end 312 of the resistive change type field effect transistor 310b in FIG. 6A.

[0072] Actually, by way of example, the gate 313 of the resistive change type field effect transistor 310b includes a gate dielectric layer 601 and a gate electrode layer 602. The outside of the gate dielectric layer 601 is connected to the gate spacer 640, the inside of the gate dielectric layer 601 is connected to the outside of the gate electrode layer 602, and the inside of the gate electrode layer 602 is connected to the bit line BL1.

[0073] The unipolar source / channel / drain diode 110a and the resistive change type field effect transistor 310a share the third source / drain diffusion region 663. The resistive change type field effect transistor 310a includes a shallow trench isolation 652. The shallow trench isolation 652 is in direct contact with the gate 313 of the resistive change type field effect transistor 310a. The shallow trench isolation 652 and the third source / drain diffusion region 663 are located on opposite sides of the gate 313 of the resistive change type field effect transistor 310a respectively, and the channel region is between the shallow trench isolation 652 and the third source / drain diffusion region 663. The shallow trench isolation 652 in FIG. 6C functions as the first end 311 of the resistive change type field effect transistor 310a in FIG. 6A, and the third source / drain diffusion region 663 in FIG. 6C functions as the second end 312 of the resistive change type field effect transistor 310a in FIG. 6A.

[0074] In other embodiments, the circuits of the resistive non-volatile memories 301 - 304 in FIGS. 3A - 3D are all applicable to the cross-sectional structure in FIG. 6C, and the description thereof is omitted here.

[0075] FIG. 7A is a circuit diagram of a resistive non-volatile memory 700 according to some embodiments of the present invention. The internal structure of the resistive non-volatile memory 700 in FIG. 7A is substantially the same as the internal structure of the resistive non-volatile memory 403 in FIG. 4C.

[0076] FIG. 7B is a layout schematic diagram of a resistive non-volatile memory 700 according to some embodiments of the present invention. An N-type well region 711 and a P-type well region 712 are shown in FIG. 7B.

[0077] FIG. 7C is a cross-sectional view of a resistive non-volatile memory 700 according to some embodiments of the present invention. As shown in FIG. 7C, the unipolar source / channel / drain diode 140 includes a floating dummy gate 721, a first source / drain diffusion region 761, and a second source / drain diffusion region 762. The first source / drain diffusion region 761 and the second source / drain diffusion region 762 are located on opposite sides of the floating dummy gate 721, respectively.

[0078] In FIG. 7C, the resistive non-volatile memory 700 further includes a first conductive layer 781, a second conductive layer 782, a first contact plug 771, a second contact plug 772, a third contact plug 773, and a fourth contact plug 774. The first conductive layer 781 and the second conductive layer 782 are electrically insulated from each other. The first contact plug 771 has both ends in contact with the first source / drain diffusion region 761 and the first conductive layer 781, respectively. The second contact plug 772 has both ends in contact with the first conductive layer 781 and the source line SL0, respectively. The third contact plug 773 has both ends in contact with the second source / drain diffusion region 762 and the second conductive layer 782, respectively. The fourth contact plug 774 has both ends in contact with the gate 433 of the resistive change type field effect transistor 430 and the second conductive layer 782, respectively.

[0079] In FIG. 7C, the resistive change type field effect transistor 430 includes a shallow trench isolation 751 and a third source / drain diffusion region 763. The shallow trench isolation 751 is in direct contact with the gate 433 of the resistive change type field effect transistor 430, and the shallow trench isolation 751 in FIG. 7C functions as the first end 431 of the resistive change type field effect transistor 430 in FIG. 7A. The third source / drain diffusion region 763 and the shallow trench isolation 751 are respectively located on opposite sides of the gate 433 of the resistive change type field effect transistor 430, and the third source / drain diffusion region 763 in FIG. 7C functions as the second end 432 of the resistive change type field effect transistor 430. A shallow trench isolation 752 is provided in the vicinity of the third source / drain diffusion region 763.

[0080] In FIG. 7C, the resistive nonvolatile memory 700 further includes a fifth contact plug 775. Both ends of the fifth contact plug 775 are in contact with the third source / drain diffusion region 763 and the bit line BL0 respectively.

[0081] In other embodiments, the circuits of the resistive nonvolatile memories 401 to 404 in FIGS. 4A to 4D are all applicable to the cross-sectional structure in FIG. 7C, and the description thereof is omitted here.

[0082] FIG. 8A is a circuit diagram of a memory cell 800 according to some embodiments of the present invention. The memory cell 800 includes resistive nonvolatile memories 403a and 403b, both of which have substantially the same structure and are arranged symmetrically with respect to each other. Each of the resistive nonvolatile memories 403a and 403b in FIG. 8A is substantially the same as the resistive nonvolatile memory 403 in FIG. 4C.

[0083] FIG. 8B is a layout schematic diagram of a memory cell 800 according to some embodiments of the present invention. As shown in FIG. 8B, the bit line BL0 is located above the diffusion region 812, and the bit line BL1 is located above the diffusion region 811.

[0084] FIG. 8C is a cross-sectional view of a memory cell 800 according to some embodiments of the present invention. As shown in FIG. 8C, the unipolar source / channel / drain diode 140a includes a floating dummy gate 822, a source / drain diffusion region 865, and a source / drain diffusion region 864. The source / drain diffusion region 865 and the source / drain diffusion region 864 are located on opposite sides of the floating dummy gate 822, respectively. The contact plug 877 has both ends contacting the source / drain diffusion region 865 and the source line SL1, respectively.

[0085] The resistive change type field effect transistor 430a includes a gate 433, a shallow trench isolation 852, and a source / drain diffusion region 863. The shallow trench isolation 852 and the source / drain diffusion region 863 are located on opposite sides of the gate 433 of the resistive change type field effect transistor 430a, respectively. The shallow trench isolation 852 is in direct contact with the gate 433 of the resistive change type field effect transistor 430a. The shallow trench isolation 852 is located in the vicinity of the source / drain diffusion region 864. The contact plug 875 has both ends contacting the source / drain diffusion region 864 and the conductive layer 882, respectively, and the contact plug 876 has both ends contacting the gate 433 of the resistive change type field effect transistor 430a and the conductive layer 882, respectively.

[0086] The contact plug 870 has both ends contacting the source / drain diffusion region 863 and the conductive layer 880, respectively. The contact plug 871 has both ends contacting the conductive layer 880 and the bit line BL0, respectively.

[0087] The unipolar source / channel / drain diode 140b includes a floating dummy gate 821, a source / drain diffusion region 861, and a source / drain diffusion region 862. The source / drain diffusion region 861 and the source / drain diffusion region 862 are located on opposite sides of the floating dummy gate 821, respectively. The contact plug 874 has both ends in contact with the source / drain diffusion region 861 and the source line SL2, respectively. The contact plug 872 has both ends in contact with the source / drain diffusion region 862 and the conductive layer 881, respectively.

[0088] The resistive change type field effect transistor 430b includes a gate 433, a shallow trench isolation 851, and a source / drain diffusion region 863. The shallow trench isolation 851 and the source / drain diffusion region 863 are located on opposite sides of the gate 433 of the resistive change type field effect transistor 430b, respectively. The shallow trench isolation 851 is in direct contact with the gate 433 of the resistive change type field effect transistor 430b. The shallow trench isolation 851 is located in the vicinity of the source / drain diffusion region 862. The contact plug 873 has both ends in contact with the gate 433 of the resistive change type field effect transistor 430b and the conductive layer 881, respectively.

[0089] FIG. 9A is a circuit diagram of a resistive nonvolatile memory 901 according to some embodiments of the present invention. The resistive nonvolatile memory 901 in FIG. 9A is an extended architecture of the resistive nonvolatile memory 301 in FIG. 3A. As shown in FIG. 9A, a plurality of resistive change type field effect transistors 310 are electrically connected to bit lines BL0, BL1 to BLn, respectively. The unipolar source / channel / drain diode 110 has both ends electrically connected to the source line SL and the plurality of resistive change type field effect transistors 310, respectively.

[0090] FIG. 9B is a circuit diagram of a resistive nonvolatile memory 902 according to some embodiments of the present invention. The resistive nonvolatile memory 902 in FIG. 9B is an extended architecture of the resistive nonvolatile memory 302 in FIG. 3B. As shown in FIG. 9B, a plurality of resistive change type field effect transistors 320 are electrically connected to bit lines BL0, BL1 to BLn, respectively. The unipolar source / channel / drain diode 110 has both ends electrically connected to the source line SL and the plurality of resistive change type field effect transistors 320, respectively.

[0091] In some embodiments of the present invention, the operation methods of the resistive nonvolatile memories 901 to 902 are all the same. To simplify the description, hereinafter, taking the operation of the resistive nonvolatile memory 901 as an example, a zero voltage is applied to one of the bit lines BL0, BL1 to BLn and the source line SL, and a non-zero voltage is applied to the other of the bit lines BL0, BL1 to BLn and the source line SL, thereby operating the resistive nonvolatile memory 901.

[0092] Specifically, in the startup phase, when the resistive change type field effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, an activation voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the activation voltage is applied to the bit lines BL1 to BLn, and a zero voltage is applied to the source line SL, thereby forming a conductive filament in the gate dielectric layer of the gate of the resistive change type field effect transistor 310 connected to the bit line BL0. In the setting phase, when the resistive change type field effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a setting voltage whose absolute value is equal to or less than the absolute value of the activation voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the setting voltage is applied to the bit lines BL1 to BLn, and a zero voltage is applied to the source line SL, thereby setting the gate dielectric layer of the gate of the resistive change type field effect transistor 310 connected to the bit line BL0 to a first resistance state. In the reset phase, when the resistive change type field effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a reset voltage whose absolute value is smaller than the absolute value of the setting voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the reset voltage is applied to the bit lines BL1 to BLn, and a zero voltage is applied to the source line SL, thereby setting the gate dielectric layer of the gate of the resistive change type field effect transistor 310 connected to the bit line BL0 to a second resistance state. In the readout phase, when the resistive change type field effect transistor 310 connected to the bit line BL0 in the resistive non-volatile memory 901 is selected, a readout voltage whose absolute value is smaller than the absolute value of the reset voltage is applied to the bit line BL0, a voltage between one-half and one-fifth of the readout voltage is applied to the bit lines BL1 to BLn, and a zero voltage is applied to the source line SL. Based on the magnitude of the readout current by the readout circuit, it is determined whether the resistive non-volatile memory 301 connected to the bit line BL0 is set or reset.

[0093] On the one hand, in the startup stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the startup voltage is applied to the source line SL, and a zero voltage is applied to the bit lines BL0, BL1 to BLn. In the setting stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the source line SL, and a zero voltage is applied to the bit lines BL0, BL1 to BLn. In the reset stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the source line SL, and a zero voltage is applied to the bit lines BL0, BL1 to BLn. In the readout stage, when the resistive non-volatile memory 301 is not selected, a voltage between one-half and one-fifth of the readout voltage is applied to the source line SL, and a zero voltage is applied to the bit lines BL0, BL1 to BLn.

[0094] FIG. 10A is a circuit diagram of a resistive non-volatile memory 1001 according to some embodiments of the present invention. The resistive non-volatile memory 1001 in FIG. 10A is an extended architecture of the resistive non-volatile memory 401 in FIG. 4A. As shown in FIG. 10A, a plurality of resistive change type field effect transistors 410 are electrically connected to the bit lines BL0, BL1 to BLn, respectively. The unipolar source / channel / drain diode 140 has both ends electrically connected to the source line SL and the plurality of resistive change type field effect transistors 410, respectively.

[0095] FIG. 10B is a circuit diagram of a resistive non-volatile memory according to some embodiments of the present invention. The resistive non-volatile memory 1002 in FIG. 10B is an extended architecture of the resistive non-volatile memory 403 in FIG. 4C. As shown in FIG. 10B, a plurality of resistive change type field effect transistors 430 are electrically connected to the bit lines BL0, BL1 to BLn, respectively. The unipolar source / channel / drain diode 140 has both ends electrically connected to the source line SL and the plurality of resistive change type field effect transistors 430, respectively.

[0096] Figure 10C is a circuit diagram of a resistive non-volatile memory 1003 according to some embodiments of the present invention. As shown in Figure 10C, a plurality of resistive change type field effect transistors 440 are electrically connected to bit lines BL0, BL1 to BLn, respectively. A unipolar source / channel / drain diode 130 has both ends electrically connected to a source line SL and a plurality of resistive change type field effect transistors 440, respectively.

[0097] Figure 10D is a circuit diagram of a resistive non-volatile memory 1004 according to some embodiments of the present invention. The resistive non-volatile memory 1004 in Figure 10D is an extended architecture of the resistive non-volatile memory 402 in Figure 4B. As shown in Figure 10D, a plurality of resistive change type field effect transistors 420 are electrically connected to bit lines BL0, BL1 to BLn, respectively. A unipolar source / channel / drain diode 130 has both ends electrically connected to a source line SL and a plurality of resistive change type field effect transistors 420, respectively.

[0098] In some embodiments of the present invention, the operation methods of the resistive non-volatile memories 1001 to 1004 are all the same, and since they are opposite to the voltage application forms of the operation methods 901 to 902, the description thereof is omitted.

[0099] Figure 11 is a circuit diagram of a memory circuit according to some embodiments of the present invention. As shown in Figure 11, the memory circuit includes a plurality of memory cells 1105 arranged in an array. Each memory cell 1105 includes a resistive non-volatile memory 1101. Actually, as an example, the architecture of the resistive non-volatile memory 1101 may be any one of the above resistive non-volatile memories 901 to 902, 1001 to 1004.

[0100] In FIG. 11, circuit 1111 is electrically connected to one end of the unipolar source / channel / drain diode in the corresponding resistive non-volatile memory 1101 via source lines SL0 to SLn. On the other hand, circuit 1112 is electrically connected to the resistive change type field effect transistor in the corresponding resistive non-volatile memory 1101 via bit lines BL0 to BLn, BLn+1 to BLh, BLh+1 to BLp, and BLm-k-2 to BLm. Actually, as an example, circuit 1111 includes a source line peripheral circuit and a control circuit, circuit 1112 includes a bit line peripheral circuit and a control circuit, and the read circuit may be selectively provided in circuit 1111 or circuit 1112.

[0101] FIG. 12A is a circuit diagram of a resistive non-volatile memory 1200 according to some embodiments of the present invention. The internal structure of the resistive non-volatile memory 1200 in FIG. 12A is substantially the same as the internal structure of the resistive non-volatile memory 1001 in FIG. 10A. The structure of each of the resistive change type field effect transistors 410_0 to 410_n is substantially the same as the structure of the resistive change type field effect transistor 410.

[0102] FIG. 12B is a layout schematic diagram of a resistive non-volatile memory 1200 according to some embodiments of the present invention. As shown in FIG. 12B, the source line SL0 is located above the active region 1212, and the source line SL1 is located above the active region 1211.

[0103] FIG. 12C is a cross-sectional view of a resistive nonvolatile memory 1200 according to some embodiments of the present invention. As shown in FIG. 12C, the unipolar source / channel / drain diode 140 includes a floating dummy gate 1221, a source / drain diffusion region 1261, and a source / drain diffusion region 1262. The source / drain diffusion region 1261 and the source / drain diffusion region 1262 are located on opposite sides of the floating dummy gate 1221, respectively. The contact plug 1270 has both ends in contact with the source / drain diffusion region 1261 and the conductive layer 1280, respectively. The contact plug 1271 has both ends in contact with the conductive layer 1280 and the conductive layer 1282, respectively. The contact plug 1272 has both ends in contact with the conductive layer 1282 and the source line SL0, respectively. The contact plug 1273 has both ends in contact with the source / drain diffusion region 1262 and the conductive layer 1281, respectively. The contact plug 1274 has both ends in contact with the conductive layer 1281 and the conductive layer 1283, respectively.

[0104] The resistive change type field effect transistor 410_0 includes a gate 413, a shallow trench isolation 1251, and a source / drain diffusion region 1263. The shallow trench isolation 1251 and the source / drain diffusion region 1263 are located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_0, respectively. The shallow trench isolation 1251 is in direct contact with the gate 413 of the resistive change type field effect transistor 410_0. The shallow trench isolation 1251 is located in the vicinity of the source / drain diffusion region 1262. The contact plug 1275 has both ends in contact with the gate 413 of the resistive change type field effect transistor 410_0 and the conductive layer 1283, respectively. The contact plug 1290 has both ends in contact with the source / drain diffusion region 1263 and the bit line BL0, respectively.

[0105] The resistive change type field effect transistor 410_1 includes a gate 413, a source / drain diffusion region 1263, and a source / drain diffusion region 1264. The source / drain diffusion region 1263 and the source / drain diffusion region 1264 are located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_1, respectively. The contact plug 1276 contacts the gate 413 of the resistive change type field effect transistor 410_1 and the conductive layer 1283 at both ends, and the contact plug 1291 contacts the source / drain diffusion region 1264 and the bit line BL1 at both ends, respectively.

[0106] The resistive change type field effect transistor 410_2 includes a gate 413, a source / drain diffusion region 1264, and a source / drain diffusion region 1265. The source / drain diffusion region 1264 and the source / drain diffusion region 1265 are located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_2, respectively. The contact plug 1277 contacts the gate 413 of the resistive change type field effect transistor 410_2 and the conductive layer 1283 at both ends, and the contact plug 1292 contacts the source / drain diffusion region 1265 and the bit line BL2 at both ends, respectively.

[0107] The resistive change type field effect transistor 410_3 includes a gate 413, a source / drain diffusion region 1265, and a source / drain diffusion region 1266. The source / drain diffusion region 1265 and the source / drain diffusion region 1266 are located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_3, respectively. The contact plug 1278 contacts the gate 413 of the resistive change type field effect transistor 410_3 and the conductive layer 1283 at both ends, and the contact plug 1293 contacts the source / drain diffusion region 1266 and the bit line BL3 at both ends, respectively. The shallow trench isolation 1252 is located in the vicinity of the source / drain diffusion region 1266.

[0108] FIG. 13A is a circuit diagram of a resistive nonvolatile memory 1300 according to some embodiments of the present invention. The internal structure of the resistive nonvolatile memory 1300 in FIG. 13A is substantially the same as the internal structure of the resistive nonvolatile memory 1001 in FIG. 10A.

[0109] FIG. 13B is a layout schematic diagram of a resistive nonvolatile memory 1300 according to some embodiments of the present invention. As shown in FIG. 13B, the source line SL0 is located above the active region 1312, and the source line SL1 is located above the active region 1311.

[0110] FIG. 13C is a cross-sectional view of a resistive nonvolatile memory 1300 according to some embodiments of the present invention. As shown in FIG. 13C, the unipolar source / channel / drain diode 140 includes a floating dummy gate 1321, a source / drain diffusion region 1361, and a source / drain diffusion region 1360. The source / drain diffusion region 1361 and the source / drain diffusion region 1360 are located on opposite sides of the floating dummy gate 1321, respectively. The contact plug 1370 has both ends in contact with the source / drain diffusion region 1361 and the conductive layer 1380, respectively. The contact plug 1371 has both ends in contact with the conductive layer 1380 and the conductive layer 1382, respectively. The contact plug 1372 has both ends in contact with the conductive layer 1382 and the source line SL0, respectively. The contact plug 1373 has both ends in contact with the source / drain diffusion region 1360 and the conductive layer 1381, respectively. The contact plug 1374 has both ends in contact with the conductive layer 1381 and the conductive layer 1383, respectively.

[0111] The resistive change type field effect transistor 410_0 includes a gate 413, a shallow trench isolation 1351, and a source / drain diffusion region 1362. The shallow trench isolation 1351 and the source / drain diffusion region 1362 are respectively located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_0, and the channel region 1330 is between the shallow trench isolation 1351 and the source / drain diffusion region 1362. The shallow trench isolation 1351 is in direct contact with the gate 413 of the resistive change type field effect transistor 410_0. The shallow trench isolation 1351 is located in the vicinity of the source / drain diffusion region 1360. The contact plug 1375 has both ends in contact with the gate 413 of the resistive change type field effect transistor 410_0 and the conductive layer 1383 respectively, and the contact plug 1390 has both ends in contact with the source / drain diffusion region 1362 and the bit line BL0 respectively.

[0112] The resistive change type field effect transistor 410_1 includes a gate 413, a shallow trench isolation 1352, and a source / drain diffusion region 1363. The shallow trench isolation 1352 and the source / drain diffusion region 1363 are respectively located on opposite sides of the gate 413 of the resistive change type field effect transistor 410_1. The shallow trench isolation 1352 is in direct contact with the gate 413 of the resistive change type field effect transistor 410_1. The shallow trench isolation 1352 is located in the vicinity of the source / drain diffusion region 1362. The contact plug 1376 has both ends in contact with the gate 413 of the resistive change type field effect transistor 410_1 and the conductive layer 1383 respectively, and the contact plug 1391 has both ends in contact with the source / drain diffusion region 1363 and the bit line BL1 respectively.

[0113] The resistive change type field effect transistor 410_2 includes a gate 413, a shallow trench isolation 1353, and a source / drain diffusion region 1364. The shallow trench isolation 1353 and the source / drain diffusion region 1364 are respectively located on both opposite sides of the gate 413 of the resistive change type field effect transistor 410_2. The shallow trench isolation 1353 is in direct contact with the gate 413 of the resistive change type field effect transistor 410_2. The shallow trench isolation 1353 is located in the vicinity of the source / drain diffusion region 1363. The contact plug 1377 has both ends in contact with the gate 413 of the resistive change type field effect transistor 410_2 and the conductive layer 1383 respectively, and the contact plug 1392 has both ends in contact with the source / drain diffusion region 1364 and the bit line BL2 respectively.

[0114] The resistive change type field effect transistor 410_3 includes a gate 413, a shallow trench isolation 1354, and a source / drain diffusion region 1365. The shallow trench isolation 1354 and the source / drain diffusion region 1365 are respectively located on both opposite sides of the gate 413 of the resistive change type field effect transistor 410_3. The shallow trench isolation 1354 is in direct contact with the gate 413 of the resistive change type field effect transistor 410_3. The shallow trench isolation 1354 is located in the vicinity of the source / drain diffusion region 1364. The contact plug 1378 has both ends in contact with the gate 413 of the resistive change type field effect transistor 410_3 and the conductive layer 1383 respectively, and the contact plug 1393 has both ends in contact with the source / drain diffusion region 1365 and the bit line BL3 respectively.

[0115] In summary, the technical solution of the present invention has obvious advantages and beneficial effects compared with the prior art. The resistive type non-volatile memory of the present invention does not require a separate word line and its related circuits, realizes an ultra-small chip size, contributes to the continuous reduction of CMOS, a simpler chip configuration layout, and higher cost efficiency.

[0116] Although the present invention has been disclosed as described above according to the embodiments, it is not limited to the above-described embodiments, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention is based on the content specified in the following claims.

Explanation of Reference Numerals

[0117] 110, 120, 130, 140 Unipolar Source / Channel / Drain Diode 110a, 110b Unipolar Source / Channel / Drain Diode 140a, 140b Unipolar Source / Channel / Drain Diode 111, 112, 121, 122, 131, 132, 141, 142 Terminals 200 Electrical Characteristics 301~304 Resistive Non-Volatile Memory 301a, 301b Resistive Non-Volatile Memory 310, 320, 330, 340 Resistive Change-Type Field-Effect Transistor 310a, 310b Resistive Change-Type Field-Effect Transistor 311, 321, 331, 341 First Terminal 312, 322, 332, 342 Second Terminal 313, 323, 333, 343 Gate 401~404 Resistive Non-Volatile Memory 403a, 403b Resistive Non-Volatile Memory 410, 420, 430, 440 Resistive Change-Type Field-Effect Transistor 410_0~410_n Resistive Change-Type Field-Effect Transistor 430a, 430b Resistive Change-Type Field-Effect Transistor 411, 421, 431, 441 First Terminal 412, 422, 432, 442 Second Terminal 413, 423, 433, 443 Gate 505, 506, 507 Memory Cells 501, 502a, 502b, 503a, 503b Resistive Non-Volatile Memory 511, 512, 521, 522, 531, 532 circuits 600 memory cells 601 gate dielectric layer 602 gate electrode layer 611, 612 diffusion regions 621, 622 floating dummy gates 630 channel region 640 gate spacer 651, 652 shallow trench isolation 661 First source / drain diffusion region 662 Second source / drain diffusion region 663 Third source / drain diffusion region 670 contact plug 700 resistive non-volatile memory 711 N-type well region 712 P-type well region 721 floating dummy gate 751, 752 shallow trench isolation 761 First source / drain diffusion region 762 Second source / drain diffusion region 763 Third source / drain diffusion region 771 First contact plug 772 Second contact plug 773 Third contact plug 774 Fourth contact plug 775 Fifth contact plug 781 First conductive layer 782 Second conductive layer 800 memory cells 811, 812 diffusion regions 821, 822 floating dummy gates 851, 852 shallow trench isolation 861 - 865 source / drain diffusion regions 870 - 877 contact plugs 880 - 882 conductive layers 901 and 902 resistive non-volatile memories 1001 to 1004 resistive non-volatile memories 1101 resistive non-volatile memory 1105 memory cell 1111 and 1112 circuits 1200 resistive non-volatile memory 1211 and 1212 active regions 1221 floating dummy gate 1251 and 1252 shallow trench isolations 1261 to 1266 source / drain diffusion regions 1270 to 1278 contact plugs 1280 to 1283 conductive layers 1290 to 1293 contact plugs 1300 resistive non-volatile memory 1311 and 1312 active regions 1321 floating dummy gate 1330 channel region 1351 to 1355 shallow trench isolations 1360 to 1365 source / drain diffusion regions 1370 to 1378 contact plugs 1380 to 1383 conductive layers 1390 to 1393 contact plugs BL, BL0 to BLn, BLn+1 to BLh, BLh+1 to BLp, BLm-k-2 to BLm bit lines SL, SL0 to SLn source lines

Claims

1. At least one resistive change type field effect transistor electrically connected to at least one bit line, A unipolar source / channel / drain diode composed of a field effect transistor without a gate electrode, and both ends thereof are electrically connected to a source line and the at least one resistive change type field effect transistor respectively, A resistive non-volatile memory including the above.

2. For the at least one resistive change type field effect transistor, the gate is electrically connected to the at least one bit line, the first end is floating, for the unipolar source / channel / drain diode, both ends are electrically connected to the source line and the second end of the at least one resistive change type field effect transistor respectively, and the unipolar source / channel / drain diode is an npn type diode or a nin type diode. The resistive non-volatile memory according to Claim 1.

3. The unipolar source / channel / drain diode includes A floating dummy gate, A first source / drain diffusion region and a second source / drain diffusion region respectively located on both opposite sides of the floating dummy gate, And includes One end of the first source / drain diffusion region contacts one end of a contact plug, and the other end of the contact plug contacts the source line. The resistive non-volatile memory according to Claim 2.

4. The unipolar source / channel / drain diode and the at least one resistive change type field effect transistor share the second source / drain diffusion region. The at least one resistive change type field effect transistor includes A shallow trench isolation that directly contacts the gate of the at least one resistive change type field effect transistor, The shallow trench isolation and the second source / drain diffusion region are respectively located on both opposite sides of the gate of the at least one resistive change type field effect transistor. The shallow trench isolation functions as the first end of the at least one resistive change type field effect transistor, and the second source / drain diffusion region functions as the second end of the at least one resistive change type field effect transistor. The resistive non-volatile memory according to Claim 3.

5. The unipolar source / channel / drain diode has both ends electrically connected to the source line and the gate of the at least one resistive change type field effect transistor respectively, and the at least one resistive change type field effect transistor has a first end that is floating and a second end that is electrically connected to the at least one bit line, and the unipolar source / channel / drain diode is a pnp type diode or a pip type diode. The resistive non-volatile memory according to claim 1.

6. The unipolar source / channel / drain diode is a floating dummy gate, a first source / drain diffusion region and a second source / drain diffusion region respectively located on opposite sides of the floating dummy gate, The resistive non-volatile memory according to claim 5, comprising

7. a first conductive layer and a second conductive layer that are electrically insulated from each other, a first contact plug having both ends in contact with the first source / drain diffusion region and the first conductive layer respectively, a second contact plug having both ends in contact with the first conductive layer and the source line respectively, a third contact plug having both ends in contact with the second source / drain diffusion region and the second conductive layer respectively, a fourth contact plug having both ends in contact with the gate of the at least one resistive change type field effect transistor and the second conductive layer respectively, The resistive non-volatile memory according to claim 6, further comprising

8. The at least one resistive change type field effect transistor is a shallow trench isolation that directly contacts the gate of the at least one resistive change type field effect transistor and functions as the first end of the at least one resistive change type field effect transistor, a third source / drain diffusion region that is located on opposite sides of the shallow trench isolation and the gate of the at least one resistive change type field effect transistor respectively and functions as the second end of the at least one resistive change type field effect transistor, The resistive non-volatile memory according to claim 7, comprising

9. The resistive non-volatile memory according to claim 8, further comprising a fifth contact plug having both ends in contact with the third source / drain diffusion region and the at least one bit line respectively.

10. A memory circuit comprising a plurality of memory cells arranged in an array, each including a resistive non-volatile memory, wherein the resistive non-volatile memory at least one resistive change type field effect transistor electrically connected to at least one bit line, a unipolar source / channel / drain diode composed of a field effect transistor without a gate electrode, both ends of which are electrically connected to a source line and the at least one resistive change type field effect transistor, respectively.

11. The memory circuit according to claim 10, wherein each of the memory cells includes another resistive non-volatile memory, one end of which is electrically connected to the resistive non-volatile memory and the at least one bit line, and the other end of which is electrically connected to another source line.

12. The memory circuit according to claim 10, wherein each of the memory cells includes another resistive non-volatile memory, one end of which is electrically connected to the resistive non-volatile memory and the source line, and the other end of which is electrically connected to the at least one bit line.

13. The at least one resistive change type field effect transistor has a gate electrically connected to the at least one bit line, a first end that is floating, and the unipolar source / channel / drain diode has both ends electrically connected to the source line and a second end of the at least one resistive change type field effect transistor, respectively. Each of the memory cells includes another resistive non-volatile memory, and the other resistive non-volatile memory at least one another resistive change type field effect transistor having a gate electrically connected to at least one another bit line and a first end that is floating, a unipolar source / channel / drain diode composed of another field effect transistor without a gate electrode, both ends of which are electrically connected to the source line and a second end of the at least one another resistive change type field effect transistor, respectively.

14. The unipolar source / channel / drain diode has both ends electrically connected to the source line and the gate of the at least one resistive change type field effect transistor respectively. The at least one resistive change type field effect transistor has a first end that is floating and a second end that is electrically connected to the at least one bit line. Each of the memory cells includes another resistive non-volatile memory, and the another resistive non-volatile memory includes another at least one resistive change type field effect transistor having a first end that is floating and a second end that is electrically connected to the at least one bit line, and is composed of another field effect transistor without a gate electrode, and another unipolar source / channel / drain diode having both ends electrically connected to another source line and the gate of the another at least one resistive change type field effect transistor respectively. The memory circuit according to claim 10.

15. A method for operating a resistive non-volatile memory including a resistive change type field effect transistor and a unipolar source / channel / drain diode connected to each other, comprising the step of operating the resistive non-volatile memory by applying a zero voltage to one of the bit line and the source line and applying a non-zero voltage to the other of the bit line and the source line. The resistive change type field effect transistor is electrically connected to the bit line, and the unipolar source / channel / drain diode is composed of a field effect transistor without a gate electrode, and both ends are electrically connected to the source line and the resistive change type field effect transistor respectively. A method for operating a resistive non-volatile memory.

16. The resistive change type field effect transistor has a gate electrically connected to the bit line and a first end that is floating. The unipolar source / channel / drain diode has both ends electrically connected to the source line and the second end of the resistive change type field effect transistor respectively. The unipolar source / channel / drain diode is an npn type diode or a nin type diode. In a startup stage, when the resistive non-volatile memory is selected, the step of applying a startup voltage to the bit line and applying the zero voltage to the source line. In a setting stage, when the resistive nonvolatile memory is selected, a setting voltage whose absolute value is equal to or less than the absolute value of the activation voltage is applied to the bit line, and a zero voltage is applied to the source line; In a reset stage, when the resistive nonvolatile memory is selected, a reset voltage whose absolute value is smaller than the absolute value of the setting voltage is applied to the bit line, and a zero voltage is applied to the source line; In a read stage, when the resistive nonvolatile memory is selected, a read voltage whose absolute value is smaller than the absolute value of the reset voltage is applied to the bit line, and a zero voltage is applied to the source line; The operation method according to claim 15, further comprising:

17. In the activation stage, when the resistive nonvolatile memory is not selected, a voltage between one-half and one-fifth of the activation voltage is applied to the source line, and a zero voltage is applied to the bit line; In the setting stage, when the resistive nonvolatile memory is not selected, a voltage between one-half and one-fifth of the setting voltage is applied to the source line, and a zero voltage is applied to the bit line; In the reset stage, when the resistive nonvolatile memory is not selected, a voltage between one-half and one-fifth of the reset voltage is applied to the source line, and a zero voltage is applied to the bit line; In the read stage, when the resistive nonvolatile memory is not selected, a voltage between one-half and one-fifth of the read voltage is applied to the source line, and a zero voltage is applied to the bit line; The operation method according to claim 16, further comprising:

18. Both ends of the unipolar source / channel / drain diode are electrically connected to the source line and the gate of the resistive change type field effect transistor respectively. The resistive change type field effect transistor has a floating first end and a second end electrically connected to the bit line. The unipolar source / channel / drain diode is a pnp type diode or a pip type diode. In the activation stage, when the resistive nonvolatile memory is selected, an activation voltage is applied to the source line, and a zero voltage is applied to the bit line; In a setting stage, when the resistive non-volatile memory is selected, applying a setting voltage whose absolute value is less than or equal to the absolute value of the startup voltage to the source line and applying the zero voltage to the bit line; In a reset stage, when the resistive non-volatile memory is selected, applying a reset voltage whose absolute value is less than the absolute value of the setting voltage to the source line and applying the zero voltage to the bit line; In a readout stage, when the resistive non-volatile memory is selected, applying a readout voltage whose absolute value is less than the absolute value of the reset voltage to the source line and applying the zero voltage to the bit line; The operation method according to claim 15, further comprising the above.

19. In the startup stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the startup voltage to the bit line and applying the zero voltage to the source line; In the setting stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the setting voltage to the bit line and applying the zero voltage to the source line; In the reset stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the reset voltage to the bit line and applying the zero voltage to the source line; In the readout stage, when the resistive non-volatile memory is not selected, applying a voltage between one-half and one-fifth of the readout voltage to the bit line and applying the zero voltage to the source line; The operation method according to claim 18, further comprising the above.

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