Method of manufacturing substrate including packaging substrate

Abstract

To provide a method of manufacturing a substrate in which consistency of alignment marks in a packaging substrate and accuracy between layers are improved.SOLUTION: A method of manufacturing a substrate that is divided into a product area where a plurality of products is disposed and a dummy area other than the product area includes: a preparation step of preparing a glass core 21a having a plurality of core vias; a step of forming an electrically conductive layer 21d on the glass core; a step of laminating a first insulative material layer 23pa on the electrically conductive layer; and a step of curing the first insulative material layer 23pa to prepare a first insulating layer 23a, the step including a pre-curing process of pre-curing the first insulative material layer 23pa at a pre-curing temperature of 80°C or higher and lower than 175°C, and a post-curing process of post-curing the first insulative material layer 23pa at a post-curing temperature of 175°C or higher and 230°C or lower. The method also includes the steps of forming, above the first insulative material layer 23pa, an electrically conductive layer 23c electrically connected to the electrically conductive layer 21d, and laminating a second insulative material layer 23pe on the electrically conductive layer 23c.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiment examples relate to a method for manufacturing a substrate on which a semiconductor packaging substrate is disposed, a method for manufacturing a substrate on which a packaging substrate including a glass core and an insulating layer is disposed, a method for manufacturing a packaging substrate, and the like.

Background Art

[0002] In manufacturing electronic components, forming a circuit on a semiconductor wafer is called the front-end (FE) process, and assembling the wafer into a state where it can be used as an actual product is called the back-end (BE) process, and this back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the rapid development of recent electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has developed into various forms such as line widths in nano units below micro, more than 10 million cells, high-speed operation, and a large amount of heat dissipation. However, relatively, there is no technology to perfectly package this. Therefore, the electrical performance of the semiconductor may sometimes be determined by the packaging technology and the electrical connection thereby, rather than the performance of the semiconductor technology itself.

[0004] As materials for packaging substrates, ceramics or resins are applied. Recently, research on applying silicon or glass to high-end packaging substrates has been underway. In particular, a packaging substrate having a cavity structure has been developed by applying a glass core.

[0005] In addition, for the most widely used packaging substrate, for example, FC-BGA (Flip Chip-Ball Grid Array), ABF (Ajinomoto Build-up Film) that serves as an insulating agent and an adhesive is used.

[0006] On the one hand, in the packaging process, the redistribution layer (RDL) generally refers to the technology of changing the position of the already formed electrical terminals to any position. Such an RDL is used as a method to eliminate the design limitations in the semiconductor manufacturing factory through the package, that is, it is utilized in the stack of semiconductor chips.

[0007] As related prior arts, there are Korean Patent Publication No. 10-2022-0135442, Korean Patent Publication No. 10-2013-0090115, Chinese Patent Application Publication No. CN115334784, etc.

Summary of the Invention

Problems to be Solved by the Invention

[0008] The purpose of the embodiment is to provide a manufacturing method of a packaging substrate with improved alignment and position stability of alignment marks when formed on the build-up layer.

[0009] Another purpose of the embodiment is to provide a manufacturing method of a packaging substrate that can minimize or prevent the influence of shrinkage of the insulating material.

Means for Solving the Problems

[0010] To achieve the above object, a manufacturing method of a substrate according to an embodiment relates to a manufacturing method of a substrate on which a packaging substrate is disposed, and includes a preparation step of preparing a glass core which is a glass plate having a plurality of core vias; a first-1 step of forming a first metal layer on the glass core; a first-2 step of laminating a first insulating material layer on the first metal layer; a first-3 step of curing the first insulating material layer to provide a first insulating layer; a second-1 step of forming a second metal layer electrically connected to the first metal layer on the upper part of the first insulating material layer; and a second-2 step of laminating a second insulating material layer on the second metal layer.

[0011] The first to third steps include a pre-curing process of pre-curing the first insulating material layer at a pre-curing temperature of 80°C or higher and lower than 175°C, and a post-curing process of post-curing the first insulating material layer at a post-curing temperature of 175°C or higher and 230°C or lower.

[0012] Through this, a substrate is manufactured, which is divided into a product area where a large number of products that are the packaging substrates are arranged, and a dummy area other than the product area.

[0013] The pre-curing process can proceed to the second step after the first step.

[0014] The first step is a heat treatment performed at a temperature of 110°C or higher and lower than 150°C for 10 minutes or more.

[0015] The second step is a heat treatment performed at a temperature of 150°C or higher and lower than 175°C for 10 minutes or more.

[0016] The method for manufacturing the substrate can further include a second - 3 step after the second - 2 step.

[0017] The second - 3 step can be a step of curing the second insulating material layer to provide a second insulating layer.

[0018] The first redistribution layer includes the first metal layer and the first insulating layer, and the second redistribution layer includes the second metal layer and the second insulating layer.

[0019] A first alignment mark can be arranged on the first redistribution layer in the dummy area, and a second alignment mark can be arranged on the second redistribution layer in the dummy area.

[0020] For the substrate, the distance between the position of the first alignment mark and the position of the second alignment mark can have a difference of 5μm or less from a predetermined distance.

[0021] The first alignment mark may be a part of the first metal layer.

[0022] The second alignment mark may be a part of the second metal layer.

[0023] When the distance between the first alignment mark and the second alignment mark in the second - 1 step is D1, and the distance between the first alignment mark and the second alignment mark in the second - 3 step is D2, the difference between D1 and D2 may be 5 μm or less.

[0024] The second - 3 step may include a pre - cure process of pre - curing the second insulating material layer at a temperature of 80°C or higher and lower than 175°C; and a post - cure process of post - curing the second insulating material layer at a temperature of 175°C or higher and 230°C or lower.

[0025] The method for manufacturing the substrate may further include a third - 1 step, a third - 2 step, and a third - 3 step after the second - 2 step.

[0026] The third - 1 step is a step of forming a third metal layer electrically connected to the second metal layer on the upper part of the second insulating material layer.

[0027] The third - 2 step is a step of laminating a third insulating material layer on the third metal layer.

[0028] The third - 3 step is a step of curing the third insulating material layer to provide a third insulating layer.

[0029] The degree of thermal shrinkage of the first insulating layer may be smaller than the degree of thermal shrinkage of the first insulating material layer.

[0030] The method for manufacturing a packaging substrate according to another embodiment includes a step of preparing a substrate manufactured by the above - described manufacturing method, and a singulation step of separating a product disposed in the product region from the substrate.

Advantages of the Invention

[0031] In the manufacturing method of the packaging substrate of the embodiment, by repeatedly exposing insulating materials and the like to heat during the build-up of layers, the resistance to shrinkage and curing of the insulating layer can be enhanced.

[0032] In the manufacturing method of the packaging substrate of the embodiment, the occurrence of shrinkage of insulating materials and the like can be minimized or prevented during heat treatment processes and the like. Through this, the steps generated due to shrinkage of the insulating material and the like and the bending of the surface of the insulating layer when pre-cured (pre-hardened) can be reduced.

[0033] In the manufacturing method of the packaging substrate of the embodiment, the alignment and position stability of wirings represented by alignment marks formed in the build-up layer can be improved.

[0034] The embodiment can enhance the accuracy of alignment of patterns and vias between layers and the position stability of patterns and vias by minimizing the deformation of the pre-cured insulating material.

Brief Description of the Drawings

[0035]

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Best Mode for Carrying Out the Invention

[0036] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings so that those having ordinary knowledge in the technical field to which the embodiments belong can easily implement them. However, the embodiments can be realized in various different forms and are not limited to the embodiments described herein. The same reference numerals are given to similar parts throughout the specification.

[0037] Throughout this specification, the term "these combinations" included in the Markush-form expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-form expression, and means including one or more selected from the group consisting of the said components.

[0038] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. Also, the singular expression includes the plural expression unless the context clearly indicates otherwise.

[0039] In this specification, the "~" system may mean including a compound corresponding to "~" or a derivative of "~" in the compound.

[0040] In this specification, the meaning that B is located on A means that B is located directly in contact with A or B is located on A while another layer is located between them, and it is not construed as being limited to B being located in contact with the surface of A.

[0041] In this specification, the meaning that B is connected to A means that A and B are directly connected or A and B are connected via other components therebetween, and unless otherwise specified, it is not construed as being limited to A and B being directly connected.

[0042] In this specification, a singular expression is construed to include the singular or plural as construed in the context unless otherwise explained.

[0043] In the process of developing a semiconductor device that is more integrated and can exhibit high performance with a thin thickness, the inventors recognized that not only the element itself but also the part related to packaging is an important factor in improving performance, and continued research on this. Different from applying two or more layers of cores such as a conventional interposer and an organic substrate as a packaging substrate on a motherboard, the inventors confirmed that by applying a glass core in a single layer and applying a cavity structure, etc., the packaging substrate can be made thinner and can contribute to improving the electrical characteristics of the semiconductor device.

[0044] The RDL formation process involves a process of forming an insulating layer such as ABF (Ajinomoto Build-up Film). The insulating layer can be formed through a fluidization process of moving an insulating material to the surface of the glass core and the inside of holes such as core vias, a pre-cure process of preliminarily curing the fluidized insulating material etc. without completely curing it, and a post-cure process of later completely curing the insulating material. However, it was found that the positional alignment of the metal pattern and the via decreases in this process, and the need for improvement was recognized.

[0045] As a result of repeated research, it was confirmed that by subdividing the curing step and repeatedly exposing the insulating layer to heat during the curing of the insulating material for layer buildup, the resistance of the insulating layer to shrinkage curing can be increased, and an embodiment will be presented.

[0046] FIG. 1 is a conceptual diagram for explaining a cross-sectional structure of a packaging substrate according to an embodiment, FIG. 2 shows a conceptual diagram for explaining in cross-section the structure of a packaging substrate according to another embodiment, and FIGS. 3(a) and 3(b) are conceptual diagrams for explaining in cross-section a part of a packaging substrate according to an embodiment.

[0047] To achieve the above object, a semiconductor device 100 according to an embodiment includes a semiconductor element part 30 where one or more semiconductor elements 32, 34, 36 are located, a packaging substrate 20 electrically connected to the semiconductor elements, and a motherboard 10 electrically connected to the packaging substrate 20, transmitting electrical signals between the semiconductor elements 32, 34, 36 and the outside, and connecting to each other.

[0048] A packaging substrate 20 according to an embodiment includes a core layer 22, an upper layer 26 located on one surface of the core layer 22, and a cavity part 28 where an electrical element 40 can be located.

[0049] The semiconductor element part 30 means an element mounted on a semiconductor device and is mounted on the packaging substrate 20 by connection electrodes or the like. Specifically, as the semiconductor element part 30, for example, arithmetic elements such as a CPU and a GPU (first element: 32, second element: 34), memory elements such as a memory chip (third element: 36), etc. may be applied, but any semiconductor element mounted on a semiconductor device can be applied without limitation.

[0050] As the motherboard 10, a motherboard such as a printed circuit board or a printed wiring board may be applied.

[0051] The packaging substrate 20 may further include a lower layer (not shown) selectively located under the core layer.

[0052] The core layer 22 includes a glass core 21 having a first region 221 with a first thickness 211 and a second region 222 adjacent to the first region 221 and having a second thickness 212 thinner than the first thickness, a plurality of core vias 23 penetrating the glass core 21 in the thickness direction, and a core distribution layer 24 located on the surface of the glass core 21 or the core vias 23 and electrically connecting a first surface 213 of the glass core 21 and a second surface 214 facing the first surface through the core vias 23. That is, the core layer 22 can refer to a glass structure including the core vias 23, the cavity portion 28, or all of these in the glass core 21 including the first surface 213 and the second surface 214 facing each other.

[0053] The second region 222 of the core layer 22 can serve as a cavity structure.

[0054] Within the same region, the glass core 21 has a first surface 213 and a second surface 214 facing each other, and these two surfaces are generally parallel to each other, so the glass core 21 has a constant thickness throughout.

[0055] The internal space 281 formed by the difference in thickness between the first region 221 and the second region 222 serves to accommodate part or all of the electrical element 40.

[0056] The glass core 21 can include core vias 23 penetrating the first surface 213 and the second surface 214. The core vias 23 can be formed in both the first region 221 and the second region 222 and can be formed with an intended pitch and pattern.

[0057] As a packaging substrate for semiconductor devices, conventionally, a form in which a silicon substrate and an organic substrate are laminated has been applied. In the case of a silicon substrate, due to the characteristics of a semiconductor, there is a risk of parasitic elements occurring when applied to a high-speed circuit, and there is a drawback that power loss is relatively large. In the case of an organic substrate, in order to form a more complex distribution pattern, it is necessary to increase the area, but this does not match the manufacturing process of miniaturized electronic devices. In order to form a complex distribution pattern within a defined size, it is substantially necessary to miniaturize the pattern, but due to the characteristics of materials such as polymers applied to organic substrates, there is a substantial limit to the miniaturization of the pattern.

[0058] In the embodiment, as a method for solving such problems, the glass core 21 is applied as a support of the core layer 22. Further, together with the glass core 21, by applying the core via 23 formed through the glass core 21, the length of the electrical flow is further shortened, and a packaging substrate 20 having a further miniaturized, faster reaction, and less loss characteristic is provided.

[0059] It is preferable to apply plate glass applied to a semiconductor to the glass core 21. For example, borosilicate plate glass, non-alkali plate glass, etc. may be applied, but it is not limited thereto.

[0060] The core via 23 penetrates the glass core 21. The core via 23 can be formed by a method of removing a predetermined region of the glass core 21, and specifically, it can be formed by etching plate-shaped glass by physical and / or chemical methods.

[0061] Specifically, for the formation of the core via 23, after forming a defect (scratch) on the surface of the glass core by a method such as a laser, a method of chemically etching, laser etching, etc. may be applied, but it is not limited thereto.

[0062] The core vias 23 may be located in a number ranging from 100 to 3,000, from 100 to 2,500, or from 225 to 1,024, based on the unit area (1 cm × 1 cm) of the glass core 21. When such pitch conditions are satisfied, the formation of an electrically conductive layer or the like and the performance of the packaging substrate can be improved.

[0063] The core distribution layer 24 includes a core distribution pattern 241, which is an electrically conductive layer that electrically connects the first surface and the second surface of the glass core through a through-via, and a core insulating layer 223 that covers the core distribution pattern. The core layer 22 forms an electrically conductive layer through the core vias inside thereof, thereby serving as an electrical path across the glass core 21. By connecting the upper and lower portions of the glass core at a relatively short distance, it can have faster electrical signal transmission and low-loss characteristics. The electrically conductive layer may be, for example, a copper plating layer, but is not limited thereto.

[0064] The cavity portion 28 is not limited in shape, and may be substantially circular, triangular, square, hexagonal, octagonal, cross-shaped, or the like.

[0065] The shape of the electrical element 40 may generally be cylindrical, cuboid, or polygonal.

[0066] The cavity portion 28 may include a cavity distribution pattern, which is an electrically conductive layer that electrically connects the electrical element 40 and the core distribution layer 24, and an insulating layer that covers the cavity distribution pattern.

[0067] On the other hand, the cavity portion according to another embodiment may be embodied in a form that penetrates the first surface 213 and the second surface 214 of the glass core 21. In this case, the cavity portion may be formed by the same process as the formation process of the core vias 23, and the area and shape penetrating the glass core 21 may be different from those of the core vias 23.

[0068] In such an embodiment, after the electrical elements 40 are arranged in the cavity portion, an insulating layer may be formed. That is, through the process of forming the above-described core insulating layer 223, an insulating layer may also be formed in the cavity portion.

[0069] The core distribution pattern 241 may be formed in a pattern so as to be electrically connectable to the electrical element 40.

[0070] The electrical element 40 may include an active element such as a transistor, or a power transmission element such as a multilayer ceramic capacitor (MLCC), that is, a passive element.

[0071] When an element such as a transistor that serves to convert an electrical signal between the motherboard and the semiconductor element portion to an appropriate level is applied as the electrical element 40, a transistor or the like is applied to the passage of the packaging substrate 20, so that a semiconductor device 100 that is more efficient and has a high speed can be provided.

[0072] Also, a power transmission element such as a multilayer ceramic capacitor (MLCC) plays an important role in the performance of the semiconductor element. The power transmission element, which is a passive element, is generally applied to at least 200 or more semiconductor elements. In transmitting power, its performance is also affected by the characteristics of the electrically conductive layer around the element. In one embodiment, a non-circular core via that is not circular can be applied to a place where a low-resistance electrically conductive layer is required, such as for such a power transmission element.

[0073] On the other hand, as the electrical element 40, passive elements such as capacitors may be individually inserted and applied, or an element group including a large number of passive elements in a form embedded between insulator layers (cavity insulating layers) may be formed such that the electrodes are exposed and then inserted into the electrical element. In the latter case, the workability of manufacturing the packaging substrate can be made smoother, and it is more advantageous for the insulating layer to be positioned in the complex space between the elements sufficiently and with high reliability.

[0074] The glass core 21 serves an intermediate role in connecting the semiconductor element portion 30 and the motherboard 10 to the upper and lower parts respectively, and the core via 23 serves as a passage for transmitting these electrical signals, so as to enable smooth signal transmission. For the purpose of distinguishing from the core vias in the second region 222 described later, the core vias arranged in the first region 221 are referred to as first region core vias.

[0075] An upper layer 26 is located on the first surface 213.

[0076] The upper layer 26 includes an upper distribution layer 25 and an upper surface connection layer 27 located on the upper distribution layer 25. The uppermost surface of the upper layer 26 can be protected by a cover layer 60 in which an opening is formed where the connection electrode of the semiconductor element portion can directly abut.

[0077] The upper distribution layer 25 includes an upper insulating layer 253 located on the first surface, and an electrically conductive layer having a predetermined pattern and being electrically connected to at least a part of the core distribution layer 24, and an upper distribution pattern 251 built in the upper insulating layer 253. The upper distribution layers 25 arranged one above the other can be connected to each other via blind vias.

[0078] The upper insulating layer 253 can be applied as an insulator layer to semiconductor elements or packaging substrates. For example, an epoxy resin containing a filler or the like may be applied, but it is not limited thereto.

[0079] The insulator layer may be formed by a method of forming a coating layer and curing it, or may be formed by a method of laminating an insulator film formed in an uncured or semi-cured state on the core layer 22 and curing it. At this time, if a vacuum lamination method or the like is applied, the insulator can be embedded into the internal space of the core via 23, enabling efficient progress of the process.

[0080] According to an embodiment, even when a multilayer insulator layer is laminated and applied, it may be difficult to substantially distinguish between the insulator layers, and the plurality of insulator layers are collectively referred to as an upper insulator layer. Also, the same insulating material may be applied to the core insulating layer 223 and the upper insulating layer 253, and in such a case, the boundary therebetween may be substantially difficult to distinguish. Alternatively, according to another embodiment, the boundary of the insulator layer can also be generated by setting different pressures and temperatures for curing the multilayer insulator layer.

[0081] The upper distribution pattern 251 means an electrically conductive layer located in the upper insulating layer 253 in a preset form, and may be formed, for example, by a build-up layer method. Specifically, after forming an insulator layer and removing unnecessary portions of the insulator layer, an electrically conductive layer is formed by a method such as copper plating, and after selectively removing unnecessary portions of the electrically conductive layer, an insulator layer is formed again on this electrically conductive layer, and after removing unnecessary portions again, the method of forming an electrically conductive layer by a method such as plating is repeated to form the upper distribution pattern 251 in which the electrically conductive layer is formed in a vertical or horizontal direction in a desired pattern.

[0082] Since the upper distribution pattern 251 is located between the core layer 22 and the semiconductor element portion 30, electrical signals are smoothly transmitted between the semiconductor element portion 30, and at least a part thereof is formed to include a fine pattern so that a desired complex pattern can be sufficiently accommodated. At this time, the fine pattern may have a width and a pitch each less than 4 μm, may be 3.5 μm or less, may be 3 μm or less, may be 2.5 μm or less, or may be 2.3 μm or less. Also, the pitch may be 1 μm or more (hereinafter, the description of the fine pattern is the same).

[0083] The upper surface connection layer 27 includes a top surface connection pattern 272 located on the upper insulating layer 253, which is electrically connected to at least a part of the upper distribution pattern 251, and an upper surface connection electrode 271 that electrically connects the semiconductor element portion 30 and the top surface connection pattern 272. The top surface connection pattern 272 may be located on one surface of the upper insulating layer 253, or at least a part of it may be embedded while being exposed on the upper insulating layer. For example, when the top surface connection pattern is located on one surface of the upper insulating layer, the upper insulating layer can be formed by a method such as plating. When the top surface connection pattern is embedded while a part of it is exposed on the upper insulating layer, it may be obtained by removing a part of the insulating layer or the electrically conductive layer by methods such as surface polishing and surface etching after forming a copper plating layer or the like.

[0084] The top surface connection pattern 272 can include a fine pattern in at least a part of it, like the upper distribution pattern 251 described above. The top surface connection pattern 272 including such a fine pattern enables electrical connection of more elements in a narrow area, making the connection of electrical signals between elements or to the outside smoother and enabling more integrated packaging.

[0085] The upper surface connection electrode 271 may be directly connected to the semiconductor element portion 30 with a terminal or the like, or may be connected through an element connection portion 51 such as a solder ball.

[0086] The cavity portion 28 is located above and / or below the second region 222 and includes a cavity distribution layer 282 electrically connected to the core distribution pattern 241 and an internal space 281 where the electrical element 40 is located. The cavity distribution layer 282 can be formed through the second region core via.

[0087] Specifically, in the second region 222, the thickness of the glass core 21 is further thinner than that in the first region 221, and the electrical element 40 can be located in the internal space 281 formed by the difference in thickness. Further, the core vias 23 and the core distribution layer 24 formed in the glass core 21 serve as an electrical connection structure for connecting the electrical element 40 and external elements.

[0088] Also, as described above, instead of the second region 222, a cavity portion penetrating the first surface 213 and the second surface 214 of the glass core 21, i.e., the first region 221, can be generated, and the electrical elements 40 can be arranged in the cavity portion.

[0089] The packaging substrate 20 is also connected to the motherboard 10. The motherboard 10 may be directly connected to the core distribution pattern 241 located on at least a part of the second surface 214 of the core layer 22, or may be electrically connected through a board connection portion 52 such as a solder ball. Further, the core distribution pattern 241 in contact with the motherboard 10 may be connected to the motherboard 10 through a lower layer (not shown) located below the core layer 22. The element connection portion 51 and the board connection portion 52 are collectively referred to as a connection portion 50.

[0090] By way of example, in the packaging substrate 20 located between the semiconductor element portion 30 and the motherboard 10, substantially no additional other substrate can be applied other than the glass core 21.

[0091] Conventionally, when connecting an element to a motherboard, an interposer and an organic substrate were laminated together and applied between them. This is understood to be applied in such a multi-layered form for at least two reasons. One is that there are scale problems in directly bonding the fine pattern of the element to the motherboard, and the other is that problems of wiring damage due to differences in the coefficient of thermal expansion may occur during the bonding process or the driving process of the semiconductor device. In an embodiment, a glass core with a coefficient of thermal expansion similar to that of the semiconductor element is applied, and a fine pattern having a fine scale sufficient for mounting the element is formed on the first surface of the glass core and its upper layer, thereby solving such problems.

[0092] Hereinafter, a method for manufacturing a substrate on which a packaging substrate according to an embodiment of the present invention is disposed will be described.

[0093] A method for manufacturing a substrate according to an embodiment includes a preparation step of preparing a glass core which is a glass plate having a plurality of core vias; a first-1 step of forming a first metal layer on the glass core; a first-2 step of laminating a first insulating material layer on the first metal layer; a first-3 step of curing the first insulating material layer to provide a first insulating layer; a second-1 step of forming a second metal layer electrically connected to the first metal layer on the upper part of the first insulating material layer; a second-2 step of laminating a second insulating material layer on the second metal layer; and a second-3 step of curing the second insulating material layer to provide a second insulating layer.

[0094] The first-3 step may include a pre-curing process of pre-curing the first insulating material layer at a temperature of 80°C or higher and lower than 175°C, and a post-curing process of post-curing the first insulating material layer at a temperature of 175°C or higher and 230°C or lower.

[0095] By including such steps, a substrate can be manufactured which is divided into a product area where a large number of products which are the packaging substrates are arranged and a dummy area other than the product area.

[0096] Hereinafter, the manufacturing process of the substrate will be described in more detail.

[0097] FIGS. 4 to 6 are flowcharts for explaining, in cross-section, the manufacturing process of a substrate on which a packaging substrate according to an embodiment is disposed.

[0098] FIG. 4 is a flowchart for explaining, in cross-section, the process of generating a core layer in the manufacturing process of a substrate according to an embodiment.

[0099] As shown in FIG. 4(a), a glass core 21a having a core via 23 is prepared (preparation step). The core via 23 may be physically or chemically etched on the glass core 21a. This etching process is referred to as an etching step.

[0100] Before chemical etching, defects (grooves) (not shown) may be formed on the glass surface at a predetermined position for forming a core via on a glass core 21a having flat first and second surfaces. The glass core may be a glass core applicable to a substrate of an electronic device or the like. For example, a non-alkali glass core or the like may be applied, but is not limited thereto. As a commercially available product, products manufactured by manufacturing companies such as Corning, Schott, and AGC may be applied. For forming the defects (grooves), methods such as mechanical etching and laser irradiation may be applied.

[0101] In the etching process, the glass core may form a via in the defective portion and at the same time the surface of the glass core 21a may also be etched. In order to prevent such etching of the glass surface, a masking film or the like may be applied. However, considering the annoyance of the process of applying and removing the masking film, the defective glass core itself can be etched. In such a case, the thickness of the glass core having a core via may be slightly thinner than the thickness of the original glass core.

[0102] Thereafter, an electrically conductive layer covering the core via 23, the first surface and the second surface of the glass core 21a may be formed. The electrically conductive layer may typically be a metal layer containing copper metal, but is not limited thereto.

[0103] Thereafter, a step of forming a metal layer (metal layer forming step) may be performed. This step can be exemplified as the first - 1 step when performed on the glass core, the second - 1 step when performed on the first redistribution layer, and the third - 1 step when performed on the second redistribution layer.

[0104] The metal layer forming step includes a process of forming an electrically conductive layer (metal layer) after the formation of the seed layer / primer layer, and in order to form the electrically conductive layer (metal layer) in a predetermined form and shape, it may further include a process of partially removing the seed layer / primer layer or the electrically conductive layer.

[0105] Specifically, as shown in FIG. 4(b), a seed layer 21c can be generated on the surface of the glass core 21a and the inner diameter of the core via 23.

[0106] Since the surface of the glass (including the surface of the glass core and the surface of the core via) and the surface of the copper metal have different properties, the adhesion is poor. In embodiments, the adhesion between the glass surface and the metal can be improved by two methods: the dry method and the wet method.

[0107] The dry method is a method applying sputtering, that is, a method of forming a seed layer 21c on the glass surface and the inner diameter of the core via by metal sputtering. For the formation of the seed layer, dissimilar metals such as titanium, chromium, and nickel may be sputtered together with copper or the like. In such a case, the adhesion between the glass and the metal can be improved by an anchor effect in which the surface morphology of the glass and the metal particles interact.

[0108] The wet method is a method of performing primer treatment, which is a method of pre-treating with a compound having a functional group such as an amine to form a primer layer (not shown). After pre-treatment with a silane coupling agent according to the intended degree of adhesion, primer treatment can be performed with a compound or particles having an amine functional group. As mentioned above, the support substrate of the embodiment needs to be highly performant enough to form a fine pattern, which must be maintained even after primer treatment. Therefore, when such a primer contains nanoparticles, it is preferable to apply nanoparticles having an average diameter of 150 nm or less. For example, particles having an amine group preferably have nanoparticles applied thereto. The primer layer may be formed by applying a bonding strength improver manufactured by, for example, the CZ series of MEC.

[0109] The seed layer / primer layer can selectively form a metal layer of the electrically conductive layer in a state where a portion where formation of the electrically conductive layer is unnecessary has been removed or in a state where it has not been removed. Further, the seed layer / primer layer can process a portion where formation of the electrically conductive layer is necessary or unnecessary in a selectively activated state or inactivated state for metal plating, and subsequent steps can be performed. For example, for the activation or inactivation treatment, light irradiation treatment such as laser light of a certain wavelength, chemical treatment, or the like may be applied. For the formation of the metal layer, a copper plating method or the like applied in the manufacture of semiconductor elements may be applied, but is not limited thereto.

[0110] The seed layer 21c is a layer for improving the adhesion between the glass core 21a and the electrically conductive layer 21d, and can contain a metal having good adhesion to copper that can be normally used in the art. For example, as the seed layer 21c, dissimilar metals such as chromium (Cr), titanium (Ti), silver (Ag), copper (Cu), nickel (Ni), nichrome, and palladium (Pd) can be sputtered together with copper or the like. In such a case, the adhesion between the glass and the metal can be improved by an anchor effect or the like in which the surface morphology of the glass core 21a and the metal particles interact.

[0111] Such a seed layer 21c functions as a seed so that copper can be effectively plated when forming a copper metal layer in the plating process. By way of example, the metal functioning as the seed is preferably any one metal selected from the group comprising at least copper (Cu), silver (Ag), and nickel (Ni). Preferably it is copper (Cu). In this case, there is an advantage that forming a metal electrode through processes (wet processes) such as plating and etching is more advantageous than using other metals such as silver (Ag). In particular, when copper plating is performed on the copper formed on the seed layer 21c, the thickness of the copper conductive line can be increased more easily compared to other metal materials, and thereby, the resistance of the copper conductive line can be easily reduced.

[0112] By way of example, as the seed layer 21c, titanium and copper can be sequentially sputtered, and titanium and copper can be laminated in a thickness range of about 200 μm to 400 μm.

[0113] Forming the seed layer 21c to improve the adhesion between the glass core 21a and the electrically conductive layer 21d is a dry method, and by way of another example, a wet method which is a primer treatment method of performing pretreatment with a compound substance is also applicable.

[0114] Referring to Fig. 4(c), based on such a seed layer 21c, an electrically conductive layer 21d can be formed on the glass core 21a. The seed layer 21c can be formed as a metal layer which is an electrically conductive layer in a state where parts unnecessary for forming the electrically conductive layer 21d are removed or not removed. This metal layer can be the first metal layer.

[0115] Also, the electrically conductive layer 21d can be formed in a state where unnecessary parts are removed from the seed layer 21c. Or, after the electrically conductive layer 21d is formed, a part thereof may be removed along a defined pattern (21e).

[0116] For removal, a photoresist layer may be formed over the seed layer 21c or the electrically conductive layer 21d.

[0117] The photoresist layer may be formed by applying a photoresist solution, or may be formed by laminating a dry film photoresist (DFR) on the seed layer 21c. In addition, various conventional techniques can be widely applied as long as it is a photoresist capable of forming a circuit pattern through photosensitivity. Depending on the design, a positive type or a negative type photoresist may be applied. Thereafter, the dry film photoresist can be exposed to ultraviolet (UV) light and developed.

[0118] Exemplarily, the dry film photoresist under the UV-blocking portion of the dry film photoresist remains unexposed. In the region irradiated with UV, the dry film photoresist is exposed to ultraviolet (UV) light, and development is performed on the exposed dry film photoresist and removal is performed on the unexposed portion of the photoresist layer.

[0119] After development, the dry film photoresist under the UV-blocking portion that was not exposed to UV is washed away by, for example, water washing, and only the region of the dry film photoresist exposed to UV remains.

[0120] A metal layer can be formed by plating a metal such as copper on the portion where the dry film photoresist has been removed.

[0121] The seed layer 21c can be exposed in the portion where the unexposed dry film photoresist has been removed. Due to the characteristics of metal plating, when plating the same metal as the seed layer 21c on the exposed seed layer 21c, a thicker metal wiring can be formed more easily than growing a metal layer by sputtering. Also, since the metal of the seed layer 21c and the metal of the electrically conductive layer 21d are the same, the seed layer 21c and the electrically conductive layer 21d after plating can form an integrated wiring.

[0122] Thereafter, stripping (strip) can be performed on the remaining portion of the dry film photoresist.

[0123] By stripping the dry film photoresist, the seed layer 21c made of a metal material is exposed to the etching solution, and the region where the metal layer is not formed in the seed layer 21c is removed by etching. Any stripping solution that can strip the photoresist can be widely used as the etching solution.

[0124] After going through the above steps, finally, when the seed layer 21c in the region where the metal layer is not formed is removed, an electrically conductive layer 21d through which current can flow may be formed on the glass core 21a.

[0125] As shown in FIG. 4(c), when a part of the core distribution layer is unnecessary, it may be removed, or after a part of the seed layer is removed or inactivated, electroplating is performed to form an electrically conductive layer in a predetermined pattern, so that an etching layer 21e of the core distribution layer may be formed.

[0126] The step of forming the insulating material layer is a step of disposing a layer of insulating material on the electrically conductive layer (metal layer) (insulating material layer forming step). Exemplarily, the step of laminating the first insulating material layer on the first metal layer can be referred to as the first - 2 step; the step of laminating the second insulating material layer on the second metal layer can be referred to as the second - 2 step; the step of laminating the third insulating material layer on the third metal layer can be referred to as the third - 2 step.

[0127] The step of forming the insulating layer is a step of curing the insulating material layer to provide an insulating layer (curing step). Exemplarily, the step of curing the first insulating material layer to provide the first insulating layer can be referred to as the first - 3 step; the step of curing the second insulating material layer to provide the second insulating layer can be referred to as the second - 3 step; the step of curing the third insulating material layer to provide the third insulating layer can be referred to as the third - 3 step.

[0128] Specifically, an insulating material layer 23pa can be formed.

[0129] After the formation of the core via, which is the core distribution layer of the electrically conductive layer 21d, a step of filling the empty space with an insulating material to form an insulating material layer can be performed. At this time, the insulating material layer formed as the core insulating layer or the insulating layer 23a in FIG. 4 can be performed by coating a resin composition or laminating an insulating film. Simply, it is preferable to apply the method of laminating an insulating film. The lamination of the insulating film can be performed by a process of laminating the insulating film. At this time, if a vacuum lamination method is applied, the insulating material can be sufficiently embedded even in a portion where the electrically conductive layer is not formed inside the core via. By performing vacuum lamination in this way, since the insulating material is sufficiently embedded in the empty space inside the core via, a core insulating layer substantially free of voids can be obtained. It is preferable that the glass core and the insulating layer (fully cured) have a characteristic that the adhesion test value according to ASTM D3359 satisfies 4B or more.

[0130] The step of curing the insulating material can include a pre-cure process of preliminarily curing the insulating material that has been fluidized and arranged in a predetermined place without completely solidifying it, and a post-cure process of completely solidifying the insulating material.

[0131] Specifically, after laminating an insulating material in the form of a film or the like on the first surface and / or the second surface of the glass core 21a, the bonding force with the glass core 21a is increased by a vacuum lamination method so that the insulating material can be arranged so that substantially no voids are formed inside the core or the like. Then, pre-cure can be performed by a thermal curing method. At this time, pre-cure means that the insulating film is not in a completely cured state but is cured to an intermediate stage, and can be controlled by adjusting the curing temperature and the like.

[0132] Exemplarily, the curing step can include a pre-cure process of pre-curing the insulating material layer at a pre-curing temperature of 80°C or higher and lower than 175°C, and a post-cure process of post-curing the insulating material layer at a post-curing temperature of 175°C or higher and 230°C or lower.

[0133] Exemplarily, the pre-curing temperature may be 80°C or higher, 90°C or higher, 100°C or higher, 110°C or higher, or 120°C or higher. The pre-curing temperature may be lower than 175°C, or 170°C or lower.

[0134] Exemplarily, the heat treatment time in the pre-cure process may be 20 minutes or longer, 30 minutes or longer, 40 minutes or longer, or 50 minutes or longer. The heat treatment time may be 150 minutes or shorter, 130 minutes or shorter, 110 minutes or shorter, 90 minutes or shorter, 80 minutes or shorter, or 70 minutes or shorter.

[0135] Exemplarily, the post-curing temperature may be 175°C or higher, 180°C or higher, 185°C or higher, or 190°C or higher. The post-curing temperature may be 230°C or lower, 220°C or lower, 210°C or lower, or 205°C or lower.

[0136] Exemplarily, the heat treatment time in the post-cure process may be 30 minutes or longer, 40 minutes or longer, 50 minutes or longer, or 60 minutes or longer. The heat treatment time may be 130 minutes or shorter, 120 minutes or shorter, 100 minutes or shorter, or 90 minutes or shorter.

[0137] Referring to FIGS. 4(d) and 4(e), the insulating layer 23a can be formed through a pre-cure process of pre-curing after forming the insulating material layer 23pa on the first surface, and a post-cure process of completely curing the insulating material layer to obtain the insulating layer.

[0138] The insulating layer formed of a plurality of layers can be post-cured all at once in the final step so that the entire insulating material layer is completely cured after pre-curing is performed after the insulating material for forming each layer is arranged to form an insulating material layer, and this process is repeated several times. In such a case, since each insulating layer that has only been pre-cured is in an incomplete state of curing shrinkage, its resistance to heat can be reduced. As a result, the insulating material layer filling the core via may shrink during the curing process, and the alignment (e.g., alignment of the metal layer) in each layer may decrease.

[0139] In an embodiment, in order to improve such instability of the insulating layer, post-curing for forming each insulating layer can be performed multiple times. Through such a process, the resistance to shrinkage curing can be increased by repeatedly exposing the insulating layer to heat during the build-up of the layer.

[0140] At this time, the temperature applied during the post-curing step can be higher than the temperature applied during the pre-curing step, and the curing time applied during the post-curing step can be longer than the curing time applied during the pre-curing step. The temperature and time of pre-curing and the temperature and time of post-curing are as described above. However, depending on the insulating material applied, the temperature and time can be changed.

[0141] The difference between the pre-curing temperature and the post-curing temperature may be 30°C or higher, 35°C or higher, or 40°C or higher. In such a case, it can be further helpful for improving the alignment of each layer.

[0142] The pre-curing process can proceed to a second step after the first step.

[0143] The first step is a heat treatment performed at a temperature of 110°C or higher and less than 150°C for 10 minutes or more, and the second step can be a heat treatment performed at a temperature of 150°C or higher and less than 175°C for 10 minutes or more.

[0144] Specifically, the temperature in the first step may be 110°C or higher, 115°C or higher, 120°C or higher, or 125°C or higher. The temperature in the first step may be less than 150°C, 145°C or lower, 140°C or lower, or 135°C or lower. The heat treatment time in the first step may be 10 minutes or longer, 15 minutes or longer, or 20 minutes or longer. Also, the heat treatment time may be 50 minutes or shorter, 45 minutes or shorter, 40 minutes or shorter, or 35 minutes or shorter.

[0145] Specifically, the temperature in the second step may be 150°C or higher, 155°C or higher, or 160°C or higher. The temperature in the second step may be less than 175°C, 170°C or lower, or 165°C or lower. The heat treatment time in the second step may be 10 minutes or longer, 15 minutes or longer, or 20 minutes or longer. Also, the heat treatment time may be 50 minutes or shorter, 45 minutes or shorter, 40 minutes or shorter, or 35 minutes or shorter.

[0146] Summarizing the manufacturing method of the packaging substrate described through FIG. 4, a first metal layer such as an electrically conductive layer covering the first and second surfaces of the core via 23 and the glass core 21a can be formed, and an insulating layer can be formed on top of the first metal layer. Such an insulating layer can be formed through a pre-cure step of laminating an insulating film on the first surface and then pre-curing, and a post-cure step of completely curing the insulating film.

[0147] According to the above-described embodiment, when the insulating layer 23a is formed on the upper or lower surface of the glass core 21a, a metal distribution pattern and an insulator layer having a multilayer structure can be formed on top of the insulating layer 23a. That is, an upper layer 26 shown in FIGS. 2 and 3 can be formed on top of the insulating layer 23a, and a lower layer (not shown) can also be formed on a lower insulating layer (not shown).

[0148] A second metal layer electrically connected to the first metal layer can be formed on top of the insulating layer.

[0149] FIG. 5 is a flowchart for explaining, in cross-section, the process of forming a second redistribution layer on a first redistribution layer during the manufacturing process of a packaging substrate according to an embodiment.

[0150] The first redistribution layer includes the first metal layer and the first insulating layer, and the second redistribution layer includes the second metal layer and the second insulating layer.

[0151] In this embodiment, the second redistribution layer can refer to the first layer included in the upper layer formed on the core layer. The second redistribution layer can include a second metal layer that is an upper redistribution pattern and a second insulating layer 23e formed on the second metal layer.

[0152] First, as shown in FIG. 5(a), blind vias 23b for forming the second metal layer can be formed in the first insulating layer 23a. To form the blind vias 23b, dry etching methods such as laser etching and plasma etching, or wet etching methods using a masking layer and an etching solution may be applied.

[0153] After forming the blind vias 23b, the second metal layer can be formed by a plating process (FIGS. 5(b) and (c)).

[0154] The second metal layer can be formed by repeating the process of forming an electrically conductive layer 23c in a predetermined pattern on the first insulating layer 23a and etching away unnecessary portions to form an etched layer 23d of the electrically conductive layer.

[0155] Thereafter, a step of forming a second insulating material layer 23pe on the upper portion of the second metal layer can be performed. The second insulating material layer 23pe is formed through a pre-curing process (FIG. 5(d)) of laminating an insulating material layer on the second metal layer and a post-curing process of completely curing the insulating material layer (FIG. 5(e)).

[0156] According to this embodiment, after the first insulating layer formed in FIG. 4, that is, the core insulating layer covering the first surface or the second surface while filling the core via, is formed through pre-curing and post-curing, the second insulating layer 23e of the second redistribution layer formed on the upper layer can also be formed through pre-curing and post-curing. In other words, by performing pre-curing and post-curing for each step in which the insulating layer is formed, the resistance to shrinkage can be increased.

[0157] FIG. 6 is a flowchart for explaining, in cross-section, the process of generating the second redistribution layer in the manufacturing process of a packaging substrate according to another embodiment.

[0158] According to this embodiment, the first insulating layer 23a is cured through pre-curing and post-curing as shown in FIGS. 6(a) and 6(b), and the second insulating layer 23e can be formed in the state of the second insulating material layer 23pe only through the pre-curing step (FIG. 6(c)).

[0159] Thereafter, a third metal layer included in the third redistribution layer can be formed on the upper portion of the second insulating material layer 23pe. Similar to the second metal layer, the third metal layer can include an electrically conductive layer 23f and an etched portion. A third insulating material layer 23pg can be formed on the upper portion of the third metal layer.

[0160] In the case of this embodiment, the third insulating material layer 23pg is formed through a pre-curing process (FIG. 6(d)) in which an insulating material such as an insulating film is laminated on the third metal layer, and a post-curing process (FIG. 6(e)) for completely curing the laminated insulating material layer.

[0161] In summary, the packaging substrate according to this embodiment can include a second insulating material layer 23pe formed on the upper portion of the second metal layer, a third metal layer formed on the upper portion of the second insulating material layer 23pe and electrically connected to the second metal layer, and a third insulating material layer 23pg formed on the upper portion of the third metal layer. The second insulating material layer 23pe is formed through a step of pre-curing after laminating an insulating material on the second metal layer. The third insulating material layer 23pg can be formed through a step of pre-curing after laminating an insulating material on the third metal layer and a post-curing step of completely curing the insulating film.

[0162] According to another embodiment, the second insulating layer 23e may also be formed by performing pre-curing and post-curing steps.

[0163] In other words, in a packaging substrate in which a plurality of layers are formed and each layer includes an insulating layer, each insulating layer may be formed through pre-curing and post-curing each time a layer is formed, or may be formed through pre-curing and post-curing with an interval of two to three layer formations. For example, if the insulating layer included in the first redistribution layer is formed through pre-curing and post-curing, then thereafter, only pre-curing is performed on the insulating layers included in the second redistribution layer and the third layer, and then the insulating layer included in the fourth layer may be formed again through pre-curing and post-curing.

[0164] Thereafter, although not shown, an upper surface connection layer and a cover layer may be formed.

[0165] The upper surface connection pattern and the upper surface connection electrode can also be formed by a process similar to the formation of the upper redistribution layer. Specifically, it may be formed by a method such as forming an etching layer of the insulating layer on the upper insulating layer, forming an electrically conductive layer on this again, and then forming an etching layer of the electrically conductive layer, but a method of selectively forming only the electrically conductive layer without applying an etching method may also be applied. The cover layer can be formed with an opening (not shown) formed at a position corresponding to the upper surface connection electrode so that the upper surface connection electrode is exposed and can be directly connected to an element connection portion or a terminal of an element, etc.

[0166] When the upper layer is generated, a step of forming a lower surface connection layer and a cover layer to generate a lower layer can be performed. The lower distribution layer and / or the lower surface connection layer, and optionally a cover layer (not shown), can be formed in a manner similar to the upper surface connection layer and cover layer formation steps described above.

[0167] When the upper layer or the lower layer is finally formed, a full curing step of completely curing the insulating films of the core insulating layer and the multilayered insulator layer can be additionally performed.

[0168] Between the pre-curing process and the post-curing process described above, a process of planarizing the surface of the substrate can be performed. That is, it can be induced so that the upper surface of the insulating layer is planarized. Exemplarily, a method of positioning a planarizing film (e.g., a PET film) on the insulating layer in a vacuum lamination process may be applied. However, the method of planarizing is not limited thereto.

[0169] FIG. 7 is a diagram for explaining an align mark of a packaging substrate according to an embodiment.

[0170] In the manufacturing process of the packaging substrate, when each layer is generated, align marks are formed for each layer on the packaging substrate for the alignment of the metal layers formed on each layer.

[0171] The substrate can include a predetermined dummy region.

[0172] The substrate is divided into a product region where a large number of products that are the packaging substrate are arranged and a dummy region other than the product region, and the align mark can be formed outside the product region or inside the packaging substrate (e.g., at the edge).

[0173] By way of an example, the align mark can be generated when forming the first metal layer and the second metal layer in the embodiment described above, that is, when forming the metal layer of each layer.

[0174] FIG. 7 shows a first redistribution layer 26a and a second redistribution layer 26b formed on the glass core 21a, and shows alignment marks 90 formed in each layer.

[0175] The alignment marks serve as indicators for measuring and examining the degree of alignment of the wirings in each layer, the degree of shift between the layers, and the accuracy. The smaller the positional deviation d of the alignment marks in each layer, the less the shift between the layers and the higher the wiring accuracy.

[0176] Exemplarily, FIG. 7 illustrates that the alignment marks are arranged vertically, but the alignment marks of the first redistribution layer 26a and the second redistribution layer 26b are not necessarily arranged vertically. It is sufficient if they are arranged at predetermined positions. However, shrinkage of materials may occur during processes such as the formation of the insulating layer, which may cause the positions of the alignment marks to deviate from the predetermined positions. The embodiments minimize this.

[0177] Specifically, the first redistribution layer 26a includes the first metal layer and the first insulating layer, the second redistribution layer 26b includes the second metal layer and the second insulating layer, a first alignment mark is arranged in the first redistribution layer of the dummy region, and a second alignment mark is arranged in the second redistribution layer of the dummy region.

[0178] The first alignment mark may be a part of the first metal layer.

[0179] The second alignment mark may be a part of the second metal layer.

[0180] The distance between the position of the first alignment mark and the position of the second alignment mark on the substrate can have a difference of 5 μm or less from a predetermined distance. The difference may be 5 μm or less, 4 μm or less, 3.5 μm or less, or 3 μm or less. The difference may also be 0.1 μm or more, 1 μm or more, or 2 μm or more.

[0181] Exemplarily, the first redistribution layer 26a includes the first metal layer and the first insulating layer, the second redistribution layer 26b includes the second metal layer and the second insulating layer, a first alignment mark is disposed on the first redistribution layer in the dummy region, and a second alignment mark is disposed on the second redistribution layer in the dummy region.

[0182] When the distance between the first alignment mark and the second alignment mark in the second - 1 step is D1 and the distance between the first alignment mark and the second alignment mark in the second - 3 step is D2, the difference between D1 and D2 can be 5 μm or less. The difference may be 5 μm or less, 4 μm or less, 3.5 μm or less, or 3 μm or less. The difference may also be 0.1 μm or more, 1 μm or more, or 2 μm or more. According to an embodiment, during heat treatment, the degree of thermal shrinkage of the first insulating layer can be smaller than the degree of thermal shrinkage of the first insulating material layer.

[0183] The manufacturing method of a packaging substrate according to another embodiment includes the process of singulating the product portion from the substrate manufactured by the above - described substrate manufacturing method. The packaging substrate manufactured in this way has excellent alignment accuracy in fine alignment, so that it is possible to realize a thin line - space and a more integrated packaging substrate can be realized.

[0184] The manufacturing method of a substrate including the packaging substrate according to the embodiments described above and the packaging substrate using the same can increase the resistance to shrinkage hardening of the insulating layer by repeatedly exposing the insulating layer to heat during the build - up of the layer, and can minimize or prevent the movement of the silica filler and the filler. Through this, it is possible to minimize the steps generated due to the mobility of the filler and the bending of the surface of the insulating layer when semi - cured (pre - cured). That is, according to the manufacturing method of the packaging substrate according to the above - mentioned embodiment, the fluidity of the RDL can be minimized, and the alignment and position stability of the alignment marks formed in the build - up layer can be improved.

[0185] The present invention described above has been described with reference to the embodiments shown in the drawings, but this is merely exemplary, and those having ordinary knowledge in the art will understand that various modifications and variations of the embodiments are possible hereinafter. That is, the scope of the rights of the present invention is not limited to the above-described embodiments, and various modifications and improvements by those skilled in the art using the basic concepts of the embodiments defined in the appended claims also belong to the scope of the rights of the embodiments. Therefore, the true technical protection scope of the present invention must be determined by the technical idea of the appended claims.

Explanation of Signs

[0186] 100 Semiconductor device 10 Motherboard 30 Semiconductor element part 32 First semiconductor element 34 Second semiconductor element 36 Third semiconductor element 20 Packaging substrate 21, 21a Glass core 22 Core layer 223 Core insulating layer 213 First surface 214 Second surface 23 Core via 24 Core distribution layer 241 Core distribution pattern 26 Upper layer 26a First redistribution layer 26b Second redistribution layer 25 Upper redistribution layer 251 Upper redistribution pattern 253 Upper insulating layer 27 Upper surface connection layer 271 Upper surface connection electrode 272 Upper surface connection pattern 28 Cavity part 281 Internal space 282 Cavity distribution layer 40 Electrical element 50 Connection part 51 Element connection part 52 Board connection part 60 Cover layer 90 Alignment mark

Claims

1. A method for manufacturing a substrate on which a packaging substrate is disposed, comprising: a preparation step of preparing a glass core which is a glass plate having a plurality of core vias; a first-1 step of forming a first metal layer on the glass core; a first-2 step of laminating a first insulating material layer on the first metal layer; a first-3 step of curing the first insulating material layer to provide a first insulating layer; a second-1 step of forming a second metal layer electrically connected to the first metal layer on the upper portion of the first insulating material layer; a second-2 step of laminating a second insulating material layer on the second metal layer; The first-3 step includes: a pre-curing process of pre-curing the first insulating material layer at a pre-curing temperature of 80 °C or higher and less than 175 °C; a post-curing process of post-curing the first insulating material layer at a post-curing temperature of 175 °C or higher and 230 °C or lower, A method for manufacturing a substrate, wherein the substrate is divided into a product area where a plurality of products which are the packaging substrates are disposed and a dummy area other than the product area.

2. The pre-curing process proceeds to the second step after the first step, The first step is a heat treatment performed at a temperature of 110 °C or higher and less than 150 °C for 10 minutes or more, The second step is a heat treatment performed at a temperature of 150 °C or higher and less than 175 °C for 10 minutes or more. The method for manufacturing a substrate according to claim 1.

3. The method for manufacturing the substrate further includes: a second-3 step after the second-2 step, The second-3 step is a step of curing the second insulating material layer to provide a second insulating layer. The method for manufacturing a substrate according to claim 1.

4. The first redistribution layer includes the first metal layer and the first insulating layer, The second redistribution layer includes the second metal layer and the second insulating layer, A first alignment mark is disposed on the first redistribution layer located in the dummy area, A second alignment mark is disposed on the second redistribution layer located in the dummy area, The distance between the position of the first alignment mark and the position of the second alignment mark on the substrate has a difference of 5 μm or less from a predetermined distance. The method for manufacturing a substrate according to claim 3.

5. The first alignment mark is a part of the first metal layer, The second alignment mark is a part of the second metal layer. The method for manufacturing a substrate according to claim 4.

6. The first redistribution layer includes the first metal layer and the first insulating layer, The second redistribution layer includes the second metal layer and the second insulating layer, A first alignment mark is disposed on the first redistribution layer located in the dummy region, A second alignment mark is disposed on the second redistribution layer located in the dummy region, In the second - 1 step, the distance between the first alignment mark and the second alignment mark is D1, In the second - 3 step, the distance between the first alignment mark and the second alignment mark is D2, The difference between the D1 and the D2 is 5 μm or less. The method for manufacturing a substrate according to claim 3.

7. The second - 3 step is A pre - cure process of pre - curing the second insulating material layer at a temperature of 80°C or higher and less than 175°C, A post - cure process of post - curing the second insulating material layer at a temperature of 175°C or higher and 230°C or lower. The method for manufacturing a substrate according to claim 3.

8. The method for manufacturing the substrate is Further includes a third - 1 step, a third - 2 step, and a third - 3 step after the second - 2 step, The third - 1 step is a step of forming a third metal layer electrically connected to the second metal layer on the upper part of the second insulating material layer, The third - 2 step is a step of laminating a third insulating material layer on the third metal layer, The third - 3 step is a step of curing the third insulating material layer to provide a third insulating layer. The method for manufacturing a substrate according to claim 1.

9. The degree of thermal shrinkage of the first insulating layer is smaller than the degree of thermal shrinkage of the first insulating material layer. The method for manufacturing a substrate according to claim 1.

10. A step of preparing a substrate manufactured by the manufacturing method according to claim 1, A singulation step of separating a product disposed in the product region from the substrate. The method for manufacturing a packaging substrate.

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