Method for manufacturing packaging substrate

Abstract

To provide a method for manufacturing a packaging substrate that suppresses misalignment of rewiring layers and provides the packaging substrate, etc. with excellent electrical reliability.SOLUTION: A method includes a preparation step for preparing a base substrate including a core layer 10 that includes a top surface and in which a through hole in the thickness direction is formed, a via insulating part formation step for providing a via-plugged substrate by forming the via insulating part 30 in the through hole, and a fabrication step of fabricating a packaging substrate 300 from the via-plugged substrate.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The embodiment relates to a method for manufacturing a packaging substrate.

Background Art

[0002] In fabricating electronic components, forming a circuit on a semiconductor wafer is called the front-end process (FE), and assembling the wafer into a state where it can be used as an actual product is called the back-end process (BE). The back-end process includes a packaging process.

[0003] The four core technologies of the semiconductor industry that have enabled the recent rapid development of electronic products are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology has evolved into various forms such as sub-micron nanometer line widths, over ten million cells, high-speed operation, and a large amount of heat dissipation. However, relatively speaking, there is no technology that perfectly packages this. Therefore, the electrical performance of a semiconductor may sometimes be determined by the packaging technology and the electrical connections it provides, rather than the performance of the semiconductor technology itself.

[0004] Recently, research has been carried out on applying ceramic materials to high-end packaging substrates. By forming through-holes in a ceramic material substrate and applying a conductive substance to these through-holes, the wiring length between the element and the motherboard can be shortened, and excellent electrical characteristics can be achieved.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] The object of the embodiment is to provide a packaging substrate or the like in which misalignment of the rewiring layer is suppressed and which has excellent electrical reliability.

Means for Solving the Problem

[0007] A method for manufacturing a packaging substrate according to an embodiment of the present specification includes a preparation step of preparing a base substrate including a core layer having an upper surface and through holes formed in the thickness direction, a via insulation part forming step of forming a via insulation part in the through holes to provide a via-plugged substrate, and a manufacturing step of manufacturing a packaging substrate from the via-plugged substrate.

[0008] The ratio of the thickness of the core layer to the diameter of the through hole observed from the upper surface of the core layer can be 4 to 12.

[0009] The core layer can be a glass core.

[0010] The core layer can include two or more of the through holes.

[0011] The diameter of the through hole can be 40 μm to 200 μm.

[0012] The pitch of the through holes can be 50 μm to 1500 μm.

[0013] The via insulation part forming step can include a filling process of filling the through holes with a composition for manufacturing a via insulation part by screen printing, and a curing process of curing the injected composition for manufacturing a via insulation part to form the via insulation part.

[0014] The viscosity of the composition for manufacturing a via insulation part can be 100 dPa·s to 500 dPa·s.

[0015] The via insulation part forming step can further include a descum process of plasma descumming the via-plugged substrate.

[0016] The via insulating portion may include one end located on the upper surface side of the core layer.

[0017] The via-plugged substrate may have a trench structure in which one end of the via insulating portion is located lower than the upper surface of the core layer.

[0018] In the via-plugged substrate, the depth of the trench structure may be 1 μm to 15 μm.

[0019] The packaging substrate may include the core layer in which the through hole is formed in the thickness direction, and the via insulating portion formed in the through hole.

[0020] The via insulating portion may include a filler.

[0021] The average particle size of the filler may be 0.1 μm or more and less than 15 μm.

[0022] The elongation rate of the via insulating portion may be 0.1% to 5%.

[0023] The composition for manufacturing the via insulating portion may include an epoxy resin, a curing agent, and a filler.

[0024] The packaging substrate may include the core layer in which the through hole is formed in the thickness direction, the via insulating portion formed in the through hole, and a first insulating layer formed in contact with at least a part of the upper surface of the core layer.

[0025] The depth of the dimple of the first insulating layer may be 15 μm or less.

Advantages of the Invention

[0026] The method for manufacturing the packaging substrate according to the embodiment can provide a packaging substrate with suppressed misalignment of the rewiring layer and excellent electrical reliability.

Brief Description of the Drawings

[0027]

Figure 1A

Figure 1B

Figure 2A

Figure 2B

Figure 3A

Figure 3B

Figure 4

Figure 5A

Figure 5B

Figure 5C

Figure 6A

Figure 6B

Figure 6C

Figure 7

Best Mode for Carrying Out the Invention

[0028] Hereinafter, for the convenience of those having ordinary knowledge in the technical field to which the present invention pertains to easily implement, embodiments will be described in detail with reference to the accompanying drawings. However, the present invention can be realized in various different forms and is not limited to the embodiments described herein. The same reference numerals are assigned to similar parts throughout the specification.

[0029] Throughout this specification, the term "these combinations" included in the Markush-form expression means one or more mixtures or combinations selected from the group consisting of the components described in the Markush-form expression, and means including one or more selected from the group consisting of the said components.

[0030] Throughout this specification, terms such as "first", "second" or "A", "B" are used to distinguish the same terms from each other. Also, a singular expression includes a plural expression unless the context clearly indicates a different meaning.

[0031] In this specification, the "~" system may mean including a compound corresponding to "~" or a derivative of "~" in the compound.

[0032] In this specification, the meaning that B is located on A means that B is located directly in contact with A or B is located on A while another layer is located between them, and is not construed as being limited to B being located in contact with the surface of A.

[0033] In this specification, the meaning that B is connected to A means that A and B are directly connected or A and B are connected via other components therebetween, and is not construed as being limited to A and B being directly connected unless otherwise specified.

[0034] In this specification, a singular expression is construed to include a singular or plural meaning as interpreted in the context unless otherwise explained.

[0035] In this specification, the form, relative size, angle, etc. of each component in the drawings are exemplary and may be exaggerated for the purpose of explanation, and the rights shall not be construed as limited to the drawings.

[0036] In this specification, when it is said that A and B are adjacent, it means that A and B are in contact with each other or, although A and B are not in contact, they are located close to each other. In this specification, the expression that A and B are adjacent shall not be construed as limited to the case where A and B are in contact with each other unless otherwise specified.

[0037] In this specification, unless otherwise explained, a fine line means a line having a width of 5 μm or less, and exemplarily means a line having a width of 1 to 4 μm or less.

[0038] For the optimization of the signal transmission path, a core layer with through-holes formed in the thickness direction can be introduced into the packaging substrate. However, when forming a redistribution layer on the core layer, during the process of embedding an insulating resin into the internal space of the through-holes, a defect may occur in that a part of the insulating layer disposed on the core layer may be depressed or wrinkled in a wavy manner, inducing misalignment of the redistribution layer.

[0039] The inventors of the embodiment experimentally confirmed that by applying technical features such as forming via insulation parts in the through-holes, misalignment of the redistribution layer can be suppressed, and a packaging substrate with excellent electrical reliability can be manufactured, and thus completed the embodiment.

[0040] Hereinafter, the embodiment will be described.

[0041] Preparation step FIG. 1A is a cross-sectional view for explaining a core layer applied to an embodiment of this specification. The embodiment will be described with reference to FIG. 1A.

[0042] The manufacturing method of the packaging substrate of the embodiment includes a preparation step of preparing a base substrate 100 including a core layer 10 having an upper surface 12 and through holes 11 formed in the thickness direction.

[0043] The core layer 10 can have the shape of a substrate. The core layer 10 is not limited as long as it is a substrate applicable as an electronic component.

[0044] The core layer 10 may be any one of a glass core, a ceramic core, a glass fiber reinforced core, and an organic core. In particular, the core layer 10 can be a glass core. The glass core is advantageous in that it can embody a fine pattern and reduce the possibility of parasitic elements.

[0045] Exemplarily, the glass core may be applied with alkali borosilicate plate glass, alkali-free borosilicate plate glass, alkali-free alkaline earth borosilicate plate glass, etc. The glass core can be applied with a glass substrate for electronic devices. Exemplarily, those manufactured by Shot, AGC, Corning, etc. may be applied, but it is not limited thereto.

[0046] The surface of the core layer 10 can include the upper surface 12 and side surfaces formed in the thickness direction of the core layer 10 and connected to the upper surface 12. The surface of the core layer 10 can include a lower surface facing the upper surface 12.

[0047] The fact that the side surfaces are formed in the thickness direction of the core layer 10 is interpreted to mean that not only do the side surfaces form a perpendicular with the upper surface 12 of the core layer 10, but also at least a part of the side surfaces forms an angle (tilt angle) other than 90° with the upper surface 12.

[0048] The side surfaces may be flat or curved.

[0049] The core layer 10 may have through holes 11 formed in the thickness direction.

[0050] The through hole 11 can have a substantially uniform inner diameter in the thickness direction of the core layer 10. The through hole 11 can have an inner diameter that varies in the thickness direction of the core layer 10.

[0051] The cross section of the through hole 11 can be rectangular. In addition to the rectangular shape, the cross section of the through hole 11 may have a shape such as an hourglass shape, a triangular shape, or a trapezoidal shape. The cross section of the through hole 11 means the cross section in the thickness direction of the core layer 10.

[0052] In the preparation step, the core layer 10 in which the through hole 11 is formed can be obtained and prepared, or the through hole 11 can be formed in a substrate in which the through hole is not formed to prepare the core layer 10.

[0053] In particular, the method of forming the through hole 11 in a substrate made of a glass material to prepare the core layer 10 is as follows.

[0054] Defects can be formed at positions in the surface of the substrate made of a glass material where the through holes are to be arranged. As a method of forming the defects, methods such as mechanical etching and laser irradiation may be applied.

[0055] After the formation of the defects, the through hole 11 can be formed through physical or chemical etching. When applying chemical etching, wet etching through an etching solution can be performed. The etching solution is not limited as long as it can be generally applied to etch the glass substrate. Exemplarily, the etching solution may be a sulfuric acid solution, a nitric acid solution, a hydrofluoric acid solution, etc.

[0056] In the process of etching, the surface of the remaining glass substrate excluding the region where the defects are formed may be masked, or etching may be performed without masking.

[0057] Defects can be formed at one point in the upper surface of the glass substrate, and defects can be formed at another point in the lower surface of the glass substrate facing the one point, and etching can be performed in a direction facing each other to provide the core layer 10 in which the through hole 11 is formed.

[0058] The ratio of the thickness of the core layer 10 to the diameter of the through hole 11 observed from the upper surface 12 of the core layer can be 4 to 12.

[0059] In the via insulation part formation step, the composition for manufacturing the via insulation part can be filled into the through hole 11 from the upper surface 12 side of the core layer. At this time, the composition may not be uniformly filled in the entire region to be filled in the through hole 11, and defects such as voids may be formed in the manufactured via insulation part.

[0060] In the embodiment, by controlling the ratio of the thickness of the core layer 10 to the diameter of the through hole 11 within a preset range, the composition for manufacturing the via insulation part can be injected into the filling target region in the through hole 11 with substantially no empty space.

[0061] The ratio of the thickness of the core layer 10 to the diameter of the through hole 11 observed from the upper surface 12 of the core layer can be 4 to 12. The ratio may be 5 or more. The ratio may be 7 or more. The ratio may be 11 or less. In such a case, the formation of voids in the via insulation part can be substantially suppressed, which can be helpful for realizing a packaging substrate with improved integration density.

[0062] The core layer 10 can include two or more through holes 11. In the case of the core layer 10 of a glass material in which a plurality of through holes are formed, the more the through holes 11 having a fine diameter are densely arranged in the core layer 10, the more likely it is to have a characteristic of being vulnerable to external impact. When manufacturing a packaging substrate from the core layer 10 having such a structure, physical damage may occur to the core layer 10 due to the external force acting on the core layer 10 during the manufacturing process of the packaging substrate, particularly during the process of injecting the composition for manufacturing the via insulation part into the through hole 11 through screen printing.

[0063] Embodiments can apply a regulated diameter and pitch to the through holes 11. Through this, wiring penetrating the core layer 10 can be formed at high density on the packaging substrate, and the occurrence of cracks in the core layer 10 that may occur during the manufacturing process can be suppressed.

[0064] When the through hole 11 has a diameter that varies in the thickness direction of the core layer 10, the average value of the diameter is taken as the diameter of the through hole 11.

[0065] The diameter of the through hole 11 can be 40 μm to 200 μm. The diameter may be 50 μm or more. The diameter may be 70 μm or more. The diameter may be 170 μm or less. The diameter may be 150 μm or less. The diameter may be 130 μm or less.

[0066] The pitch of the through hole 11 can be 50 μm to 1500 μm. The pitch may be 100 μm or more. The pitch may be 200 μm or more. The pitch may be 300 μm or more. The pitch may be 500 μm or more. The pitch may be 1200 μm or less. The pitch may be 1000 μm or less.

[0067] In such a case, even if a material with high hardness and a complex structure are applied to the core layer 10, the core layer 10 may not be easily damaged during the manufacturing process.

[0068] FIG. 1B is a cross-sectional view illustrating a core layer applied to another embodiment of this specification. The embodiment will be described with reference to FIG. 1B.

[0069] The core layer 10 includes an upper surface 12 and has through holes 11 formed in the thickness direction. The specific configuration of the core layer 10 is directly applicable as described in FIG. 1A above. Below, the description will focus on the different parts.

[0070] The core layer 10 can include a via inner diameter surface 13 surrounding the through hole 11. An electrical conduction layer 41 can be formed on the via inner diameter surface 13.

[0071] The via inner diameter surface 13 is the surface of the core layer 10 formed inside the core layer 10. The electrical conduction layer 41 may be formed in contact with at least a part of the via inner diameter surface 13, or may be disposed on the via inner diameter surface 13 with other components disposed between the electrical conduction layer 41 and the via inner diameter surface 13.

[0072] The electrical conduction layer 41 can include a seed layer (or primer layer) (not shown) disposed on the via inner diameter surface 13, and a conductive layer (not shown) disposed on the seed layer. The seed layer (or primer layer) can help the electrical conduction layer 41 to be stably fixed to the via inner diameter surface 13 and can serve as a seed in the process of forming the conductive layer through plating.

[0073] The electrical conduction layer 41 may be formed by a dry method or a wet method.

[0074] The dry method is a method of forming a seed layer by performing sputtering on the region where the electrical conduction layer 41 is disposed, and forming the electrical conduction layer 41 by performing plating on the region where the seed layer is formed. When forming the seed layer, a metal such as titanium, chromium, or nickel may be sputtered, or the metal and copper may be applied together for sputtering. Through sputtering, an anchor effect appears in which the surface of the glass core or the insulating layer and the metal particles interact, and the adhesion of the electrical conduction layer 41 can be improved.

[0075] The wet method is a method of applying metal plating after treating a primer on the portion where formation of the electrical conduction layer 41 is required. The primer can include a compound having a functional group such as an amine. Depending on the intended degree of adhesion, the primer can include both a compound having a functional group such as an amine and a silane coupling agent. When applying the silane coupling agent, after pretreating the surface to be primer-treated with the silane coupling agent, a compound having an amine group can be applied to the pretreated region to form a primer layer.

[0076] After forming the seed layer or the primer layer, a conductive layer can be formed through metal plating to provide the electrical conduction layer 41. Copper plating may be applied when forming the conductive layer, but it is not limited thereto. Before metal plating, parts that do not require the formation of the electrical conduction layer 41 in the seed layer or the primer layer can be inactivated, or parts that require the formation of the electrical conduction layer 41 can be activated, and then plating can be performed. As the activation or inactivation treatment method, light irradiation treatment such as irradiating a laser with a specific wavelength, chemical treatment, etc. may be applied. However, after performing metal plating without applying the activation or inactivation treatment, the electrical conduction layer 41 can be etched and patterned according to a pre-designed shape.

[0077] As the material of the seed layer, materials different from the material applied to the conductive layer can be applied together. Exemplarily, when copper is applied to the conductive layer, metals such as titanium, chromium, and nickel can be applied to the lower part of the seed layer, and copper can be applied to the upper part of the seed layer.

[0078] The material of the conductive layer is not limited as long as it has conductivity. The material of the conductive layer may be any one selected from the group consisting of copper, nickel, aluminum, gold, silver, and combinations thereof. The material of the conductive layer may be copper.

[0079] The thickness of the electrical conduction layer 41 disposed in the through hole 11 can be 0.01 μm to 1 μm. The thickness may be 0.05 μm. The thickness may be 0.1 μm or more. The thickness may be 0.3 μm or more. The thickness may be 0.8 μm or less. In such a case, efficient and stable signal transmission can be achieved through the through hole 11.

[0080] The core layer 10 can further include a cavity (not shown) which is a space formed with a concave interior.

[0081] The cavity may be formed by partially recessing a part of the upper / lower surface side of the core layer 10 in the thickness direction of the core layer 10, or may penetrate the core layer 10 in the thickness direction.

[0082] An element may be mounted in the cavity, and the packaging substrate and the element may be electrically connected. The element may be not only a semiconductor element such as a CPU, a GPU, or a memory chip, but also a capacitor element, a transistor element, an impedance element, or other modules. That is, any semiconductor element mounted on a semiconductor device can be applied as the element without limitation.

[0083] Via insulation part formation step The manufacturing method of the packaging substrate of the embodiment further includes a via insulation part forming step of forming a via insulation part in a through hole to provide a via plugged substrate.

[0084] The via insulation part may be formed by being filled in at least a part of the through hole with substantially no voids inside. The via insulation part can suppress the resin constituting the insulation layer from being excessively embedded in the through hole in the process of forming the insulation layer on the upper side of the core layer. Through this, it can help to stably maintain the flatness of the upper surface of the insulation layer. Also, when an electric conduction layer is formed on the inner diameter surface of the via, it can help to stably protect and fix the electric conduction layer and maintain the electrical reliability of the manufactured packaging substrate at a certain level or higher.

[0085] The via insulation part forming step may include a filling process of filling the through hole with a composition for manufacturing a via insulation part by screen printing, and a curing process of curing the injected composition for manufacturing a via insulation part to form the via insulation part.

[0086] 1) Filling process FIG. 2A and FIG. 2B are cross-sectional views for explaining the filling process applied to an embodiment of the present specification. The embodiment will be described with reference to FIGS. 2A and 2B.

[0087] The core layer 10 includes an upper surface 12 and has a through hole 11 formed in the thickness direction. The specific configuration of the core layer 10 is directly applicable as described in FIG. 1A above. Hereinafter, the description will focus on the different parts.

[0088] In the filling process, the via insulation part manufacturing composition 22 can be filled into the through hole 11 by screen printing. Specifically, a screen 20 with a pattern corresponding to the position of the through hole 11 is placed on the core layer 10, and the composition 22 is squeegeed in the in-plane direction Dp of the base substrate 100 with a squeegee 21 and filled into the through hole 11.

[0089] Exemplarily, the material of the screen may be, but is not limited to, nylon resin, polyester resin, or stainless steel.

[0090] The embodiment can adjust the viscosity of the via insulation part manufacturing composition 22 applied in the filling process. Through this, the composition 22 can be easily filled into the through hole 11 without stagnation, and the filled composition 22 can be prevented from easily detaching from the through hole 11.

[0091] The viscosity of the via insulation part manufacturing composition 22 can be measured with a cone-plate rotational viscometer in accordance with JIS-Z8803:2011. The viscosity is measured at room temperature.

[0092] The viscosity of the via insulation part manufacturing composition 22 can be 100 dPa·s to 500 dPa·s. The viscosity may be 150 dPa·s or more. The viscosity may be 200 dPa·s or more. The viscosity may be 450 dPa·s or less. The viscosity may be 400 dPa·s or less. In such cases, the via insulation part manufacturing composition 22 can be filled into the through hole 11 more smoothly through screen printing.

[0093] The via insulation part manufacturing composition 22 can include an epoxy resin, a curing agent, and a filler.

[0094] The epoxy resin is the main component of the composition 22 for manufacturing via insulating parts, and can provide excellent adhesiveness and insulation properties to the composition 22 for manufacturing via insulating parts, along with low viscosity characteristics.

[0095] The epoxy resin can further contain a separate functional group. The epoxy resin can, for example, contain any one selected from the group consisting of a bisphenol group, an aminophenol group, a naphthalene group, a novolak group, a glycidylamine group, and combinations thereof.

[0096] The curing agent can help to form via insulating parts from the composition 22 for manufacturing via insulating parts by inducing a crosslinking reaction at high temperatures.

[0097] Any one of a polyamine-based compound, an imidazole-based compound, and combinations thereof may be applied as the curing agent.

[0098] Examples of the polyamine-based compound include ethylene diamine, propylene diamine, butylene diamine, pentylene diamine, modified polyamines such as diethylene triamine, and triethylene tetramine.

[0099] Examples of the imidazole-based compound include methylimidazole, dimethylimidazole, benzylmethylimidazole, benzylphenylimidazole, and cyanoalkylimidazole.

[0100] The filler can adjust the viscosity of the composition 22 for manufacturing via insulating parts within the range targeted in the embodiments, and can impart adjusted roughness to the via insulating parts.

[0101] The filler can be an inorganic filler. Examples of the filler that may be applied include silica, calcium carbonate, aluminum nitride, boron nitride, alumina, magnesium oxide, and the like.

[0102] The average particle size of the filler can be 0.1 μm or more and less than 15 μm. The average particle size may be 0.5 μm or more. The average particle size may be 1 μm or more. The average particle size may be 3 μm or more. The average particle size may be 5 μm or more. The average particle size may be 12 μm or less. The average particle size may be 10 μm or less. In such cases, the filler has excellent dispersibility and can help the composition 22 for manufacturing the via insulating portion to be easily filled into the through hole 11 having a fine diameter. Further, the surface of the via insulating portion can be made to have adjusted roughness characteristics, and the peel strength of the electrically conductive layer with respect to the surface can be improved to a certain level or more.

[0103] The average particle size of the filler is measured in accordance with JIS K 5600-2-5.

[0104] The composition 22 for manufacturing the via insulating portion can contain 4% to 70% by weight of an epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 10% by weight or more of an epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 20% by weight or more of an epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 60% by weight or less of an epoxy resin.

[0105] The composition 22 for manufacturing the via insulating portion can contain 1 to 30 parts by weight of a curing agent with respect to 100 parts by weight of the epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 3 parts by weight or more of a curing agent with respect to 100 parts by weight of the epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 5 parts by weight or more of a curing agent with respect to 100 parts by weight of the epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 10 parts by weight or more of a curing agent with respect to 100 parts by weight of the epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 25 parts by weight or less of a curing agent with respect to 100 parts by weight of the epoxy resin. The composition 22 for manufacturing the via insulating portion may contain 20 parts by weight or less of a curing agent with respect to 100 parts by weight of the epoxy resin.

[0106] The composition 22 for manufacturing the via insulating portion can contain 20% to 95% by weight of a filler. The composition 22 for manufacturing the via insulating portion may contain 30% by weight or more of the filler. The composition 22 for manufacturing the via insulating portion may contain 40% by weight or more of the filler. The composition 22 for manufacturing the via insulating portion may contain 80% by weight or less of the filler.

[0107] In such a case, a via insulating portion having excellent filling properties with respect to the through-hole 11 having a fine diameter and excellent adhesion and insulating properties with respect to the electrically conductive layer disposed in the through-hole 11 can be formed.

[0108] The composition 22 for manufacturing the via insulating portion can further contain other components in addition to the above-described components. The other components are not limited as long as they are those usually applied in the field of curable resin compositions. Examples of the substances added to the composition 22 include a thickener, an antifoaming agent, an adhesion promoter, a leveling agent, and the like.

[0109] After the injection of the composition 22 for manufacturing the via insulating portion into the through-hole 11 is completed, the screen 20 can be removed from the upper surface of the base substrate 100.

[0110] 2) Curing process In the curing process, the composition for manufacturing the via insulating portion injected into the through-hole can be cured to form a via insulating portion, and a via-plugged substrate can be provided.

[0111] The curing process can be performed by putting the base substrate into which the composition for manufacturing the via insulating portion has been injected into the through-hole into a chamber and then leaving it in a high-temperature atmosphere for a preset time.

[0112] The atmosphere temperature in the curing process may be 90°C or higher. The atmosphere temperature may be 100°C or higher. The atmosphere temperature may be 110°C or higher. The atmosphere temperature may be 120°C or higher. The atmosphere temperature may be 200°C or lower. The atmosphere temperature may be 170°C or lower.

[0113] The hardening process may be performed for 15 minutes or more. The hardening process may be performed for 20 minutes or more. The hardening process may be performed for 60 minutes or less. The hardening process may be performed for 50 minutes or less.

[0114] In such a case, the composition 22 for manufacturing the via insulating portion embedded in the through hole can be sufficiently hardened to form the via insulating portion.

[0115] 3) Descumming process FIG. 3A is a conceptual diagram for explaining a via-plugged substrate after a descum process according to an embodiment of the present specification. Hereinafter, an embodiment will be described with reference to FIG. 3A.

[0116] The core layer 10 includes an upper surface 12 and has a through hole formed in the thickness direction. The specific configuration of the core layer 10 is the same as that described with reference to FIG. 1A above. Hereinafter, the description will focus on the different parts.

[0117] The via insulating portion forming step may further include a descum process of plasma descumming the via-plugged substrate 200.

[0118] The via insulating portion 30 formed immediately after the filling process and the hardening process may have a shape protruding from the upper surface 12 of the core layer. In the via insulating portion forming step of the embodiment, by additionally applying the descum process, the one end 32 of the via insulating portion located on the upper surface 12 side of the core layer can be positioned substantially at the same height as the upper surface 12 of the core layer. Through this, the rewiring layer formed on the via-plugged substrate 200 can have excellent flatness.

[0119] At the same time, organic foreign matters adsorbed on the surface of the substrate during the filling process and the hardening process and not easily removed through the cleaning solution can be effectively removed. In particular, when the core layer 10 is a glass core, efficient removal of organic residues is possible without excessive damage to the core layer 10 without applying a separate process.

[0120] In the descum process, the via-plugged substrate 200 can be exposed to an O2 plasma atmosphere. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere for 2 to 10 minutes each time. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere for 3 minutes or more each time. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere for 7 minutes or less each time.

[0121] In the descum process, the via-plugged substrate 200 can be exposed to the O2 plasma atmosphere one or more times. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere two or more times. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere five or more times. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere 20 times or less. The via-plugged substrate 200 can be exposed to the O2 plasma atmosphere 10 times or less.

[0122] In such a case, one end 32 of the via insulating portion can be processed to the target height in the embodiment, and organic particles remaining on the surface of the via-plugged substrate 200 can be effectively removed.

[0123] FIG. 3B is a conceptual diagram illustrating a via-plugged substrate after the descum process according to another embodiment of the present specification.

[0124] The core layer 10 includes an upper surface 12 and has a through hole formed in the thickness direction. The specific configurations of the core layer 10 and the via insulating portion 30 are directly applicable to those described in FIGS. 1A and 3A above. Hereinafter, the description will focus on the different parts.

[0125] The via-plugged substrate 200 that has undergone the descum process can have a trench structure 31 in which one end 32 of the via insulating portion is disposed lower than the upper surface 12 of the core layer 10. When an insulating layer (not shown) is formed on the via-plugged substrate 200 having the trench structure 31, a structure (interlocking structure) in which the formed insulating layer and the upper surface side of the via-plugged substrate 200 are stably bonded to each other can be formed, and the contact area between the insulating layer and the upper surface side of the via-plugged substrate 200 is further increased, so that the bonding force of the insulating layer to the upper surface 12 of the substrate can be improved. At the same time, since deterioration such as wrinkling of the insulating layer does not occur, misalignment of the rewiring layer can be stably suppressed.

[0126] The depth of the trench structure 31 can be measured by a surface roughness meter. When the surface on the one end 32 side of the via insulating portion is not flat, the difference value between the average height of the upper surface profile of the via-plugged substrate 200 and the height at the point having the deepest depth among the profiles of the trench structure 31 to be measured is defined as the depth of the trench structure 31.

[0127] The depth of the trench structure 31 can be calculated by measuring the upper surface profile of the via-plugged substrate in one direction in the in-plane direction of the via-plugged substrate 200 using a surface roughness meter.

[0128] The depth of the trench structure 31 can be calculated by measuring the upper surface profile of the via-plugged substrate 200 in the x-axis direction and the y-axis direction in the in-plane direction of the via-plugged substrate 200 using a surface roughness meter. In this case, the larger value among the calculated depth values of the trench structure 31 is defined as the depth value of the trench structure 31.

[0129] Exemplarily, as the surface roughness meter, a surface roughness meter manufactured by Veeco can be applied.

[0130] The depth of the trench structure 31 can be 1 μm to 15 μm. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 3 μm or more. In such a case, the insulating layer formed on the core layer 10 can have an excellent bonding force with respect to the upper surface 12 side of the core layer and can exhibit a flat upper surface.

[0131] Cleaning step The manufacturing method of the packaging substrate according to the embodiment can further include a cleaning step of cleaning the via-plugged substrate provided through the via insulation part forming step before the manufacturing step.

[0132] In the cleaning step, it is possible to remove the composition for manufacturing the via insulation part and the remains of the via insulation part, as well as other organic particles, which remain on the surface of the substrate without being removed during the descum process. Through this, it is possible to suppress the connection or connection failure of the electric conduction layer due to particles.

[0133] The cleaning step can include an ultrasonic cleaning process of ultrasonically cleaning the via-plugged substrate.

[0134] In the ultrasonic cleaning process, the via-plugged substrate on which organic particles remain can be immersed in a water tank, and ultrasonic vibration can be applied to the water tank to generate a cavitation phenomenon. Through this, it is possible to easily remove the adsorbed particles without excessively damaging the substrate.

[0135] In the cleaning step of the embodiment, the vibration frequency can be 30 kHz to 200 kHz. The vibration frequency may be 50 kHz or more. The vibration frequency may be 70 kHz or more. The vibration frequency may be 100 kHz or more. The vibration frequency may be 150 kHz or less. In such a case, even if the core layer 10 has a fine and complex pattern structure, it can be effectively cleaned without major damage.

[0136] Manufacturing step The manufacturing method of the packaging substrate of the embodiment can further include a manufacturing step of manufacturing the packaging substrate from the via-plugged substrate.

[0137] In the manufacturing step, a redistribution layer can be formed above or below the core layer. The redistribution layer can include an electrically conductive layer and an insulating layer surrounding at least a part of the electrically conductive layer. In the redistribution layer, the insulating layer and the electrically conductive layer can be arranged in a mixed manner. The redistribution layer can be formed in a form in which an electrically conductive layer having a predetermined position and shape is embedded in the insulating layer. At least a part of the redistribution layer can be formed of fine wires of the electrically conductive layer.

[0138] The electrically conductive layer corresponds to a conducting wire for transmitting an electrical signal. The electrically conductive layer can include an electrically conductive material. Exemplarily, the electrically conductive layer can include at least any one of copper, nickel, aluminum, gold, and silver. Copper or the like can be applied as the material of the electrically conductive layer.

[0139] The electrically conductive layer may be formed by a dry method or a wet method. The descriptions of the dry method and the wet method are omitted because they overlap with the above-mentioned content.

[0140] The insulating layer is not limited as long as it can be applied as an insulating layer to a semiconductor element or a packaging substrate. Exemplarily, the insulating layer may be composed of an epoxy resin containing a filler or the like. Exemplarily, the insulating layer may be formed through a build-up layer material such as ABF (Ajinomoto Build-up Film) of Ajinomoto Co., Inc., an undercoat material, etc., but is not limited thereto.

[0141] After forming the electrically conductive layer, an insulating layer surrounding the electrically conductive layer can be formed. The insulating layer may be formed by forming a coating layer and curing it, or by laminating an uncured or semi-cured insulator film on the electrically conductive layer and then curing it. When laminating the insulator film on the electrically conductive layer through vacuum lamination, the formed insulating layer can surround the electrically conductive layer without voids.

[0142] Through the process of repeatedly forming and removing the insulating layer and the electrically conductive layer, a rewiring layer with a multilayer structure can be formed. The rewiring layer with a multilayer structure can be formed by the build-up layer method. Specifically, after forming a rewiring layer having one layer, unnecessary portions of the insulating layer within the rewiring layer are removed, an electrically conductive layer is formed through methods such as plating, and the electrically conductive layer can be selectively etched and patterned. Thereafter, an insulating layer can be laminated on the patterned electrically conductive layer to form a rewiring layer with a two-layer structure. The above-described method can be repeated to form a rewiring layer with a multilayer structure.

[0143] The rewiring layer can include a first rewiring layer formed on the core layer.

[0144] The first rewiring layer can include two or more electrically conductive layers. The first rewiring layer can include one electrically conductive layer and another electrically conductive layer disposed on the one electrically conductive layer.

[0145] The width of the other electrically conductive layer may be narrower than or the same as the width of the one electrically conductive layer. The width of the other electrically conductive layer may be narrower than the width of the one electrically conductive layer.

[0146] The thickness of the other electrically conductive layer may be thinner than or the same as the thickness of the one electrically conductive layer. The thickness of the other electrically conductive layer may be thinner than the thickness of the one electrically conductive layer.

[0147] The pitch of the other electrical conduction layer may be smaller than or the same as the pitch of the one electrical conduction layer. The pitch of the other electrical conduction layer may be smaller than the pitch of the one electrical conduction layer.

[0148] In the first rewiring layer of the multilayer structure, electrical conduction layers with smaller widths can be arranged as going upward. In the first rewiring layer of the multilayer structure, electrical conduction layers with thinner thicknesses can be arranged as going upward. Through this, the packaging substrate can form a stable electrical connection with a semiconductor element having a fine pattern.

[0149] The rewiring layer can include a second rewiring layer disposed under the core layer.

[0150] The second rewiring layer can include an electrical conduction layer and an insulating layer surrounding the electrical conduction layer. The materials and formation method of the electrical conduction layer and the insulating layer of the second rewiring layer can be the same as those of the electrical conduction layer and the insulating layer of the first rewiring layer. The description of the electrical conduction layer and the insulating layer of the second rewiring layer is omitted because it overlaps with the foregoing content.

[0151] The second rewiring layer can include two or more electrical conduction layers. The second rewiring layer can include one electrical conduction layer and another electrical conduction layer disposed under the one electrical conduction layer.

[0152] The width of the other electrical conduction layer may be wider than or the same as the width of the one electrical conduction layer. The width of the other electrical conduction layer may be wider than the width of the one electrical conduction layer.

[0153] The thickness of the other electrical conduction layer may be thicker than or the same as the thickness of the one electrical conduction layer. The thickness of the other electrical conduction layer may be thicker than the thickness of the one electrical conduction layer.

[0154] The pitch of the other electrical conduction layer may be larger than or the same as the pitch of the one electrical conduction layer. The pitch of the other electrical conduction layer may be larger than the pitch of the one electrical conduction layer.

[0155] In the second rewiring layer of the multilayer structure, an electrical conduction layer with a wider width can be arranged as it goes downward. In the second rewiring layer of the multilayer structure, an electrical conduction layer with a greater thickness can be arranged as it goes downward. Through this, the packaging substrate can form a stable electrical connection with the main board on which a wide or thick electrical conduction layer is formed.

[0156] The packaging substrate can further include bumps arranged under the second rewiring layer.

[0157] The bumps can be arranged in a predetermined form under the rewiring layer. Exemplarily, the bumps may be arranged on a part of the lower surface of the packaging substrate so as to contact the main board or the like.

[0158] Manufactured packaging substrate FIG. 4 is a cross-sectional view illustrating a packaging substrate manufactured according to an embodiment of the present specification. An embodiment will be described with reference to FIG. 4.

[0159] The core layer 10 includes an upper surface and has through holes formed in the thickness direction. A via insulating portion 30 can be formed in the through holes. The specific configurations of the core layer 10 and the via insulating portion 30 are directly applicable as those described in FIGS. 1A and 3A above. Hereinafter, the description will focus on the different parts.

[0160] The packaging substrate 300 manufactured by the manufacturing method of the packaging substrate of the embodiment can include a core layer 10 having through holes formed in the thickness direction and a via insulating portion 30 arranged in the through holes. The packaging substrate 300 can include a rewiring layer 40 arranged above and / or below the core layer 10. The descriptions of the core layer 10, the via insulating portion 30, and the rewiring layer 40 are omitted because they overlap with the foregoing content.

[0161] The via insulating portion 30 may contain a filler. The average particle size of the filler may be 0.1 μm or more and less than 15 μm. Since the description of the filler overlaps with the above-described content, it is omitted.

[0162] In the process of forming the rewiring layer 40 above or below the core layer 10 or driving the element, the packaging substrate 300 may be repeatedly exposed to a high-temperature atmosphere. In particular, since the core layer 10 and the via insulating portion 30 to which different materials are applied in the packaging substrate 300 have different thermal expansion characteristics, the via insulating portion 30 may apply stress to the core layer 10 in a high-temperature atmosphere. Such stress may induce deterioration of the electrical connection formed in the through hole.

[0163] The embodiment can suppress the formation of defects in the packaging substrate 300 by adjusting the mechanical properties of the via insulating portion 30 when repeatedly exposed to a high-temperature atmosphere or when the element is driven for a long period of time. Specifically, it is possible to suppress the formation of mechanical defects in the region near the through hole in the core layer 10, and when an electrical conduction layer is disposed in the through hole, it is possible to prevent the electrical conduction layer from being disconnected due to the thermal expansion of the via insulating portion 30.

[0164] The Young's modulus of the via insulating portion 30 may be 3,000 MPa or more. The Young's modulus may be 3,500 MPa or more. The Young's modulus may be 4,000 MPa or more. The Young's modulus may be 4,500 MPa or more. The Young's modulus may be 8,000 MPa or less.

[0165] The tensile strength of the via insulating portion 30 may be 5 MPa or more. The tensile strength may be 10 MPa or more. The tensile strength may be 15 MPa or more. The tensile strength may be 50 MPa or less. The tensile strength may be 45 MPa or less.

[0166] The elongation rate of the via insulating portion 30 can be 0.1% to 5%. The elongation rate may be 4% or less. The elongation rate may be 3% or less. The elongation rate may be 2% or less. The elongation rate may be 1% or less.

[0167] In such a case, the packaging substrate 300 can have stable electrical reliability and long-term durability even when repeatedly exposed to a high-temperature atmosphere.

[0168] The Young's modulus of the via insulating portion 30 is measured by DMA (Dynamic Mechanical Analysis) at 30°C. The tensile strength and elongation rate of the via insulating portion 30 are measured by UTM (Universal Testing Machine) at 30°C.

[0169] The packaging substrate 300 can further include an electrical conduction layer disposed between the via insulating portion 30 and the via inner diameter surface. At least a part of the electrical conduction layer can be disposed in contact with the via insulating portion 30. The description of the electrical conduction layer is omitted because it overlaps with the foregoing content.

[0170] In the embodiment, by adjusting the peel strength of the electrical conduction layer with respect to the surface of the via insulating portion 30 within a preset range, the via insulating portion 30 can stably fix and protect the electrical conduction layer, and the electrical reliability of the packaging substrate 300 can be improved.

[0171] The peel strength of the electrical conduction layer with respect to the surface of the via insulating portion 30 is measured as follows. After forming a copper thin film with a thickness of 20 μm on the surface of the via insulating portion 30, the peel strength of the copper thin film with respect to the surface of the via insulating portion is measured by a 180° peel test.

[0172] The peel strength of the electrical conductive layer with respect to the surface of the via insulating portion 30 may be 4 N / cm or more. The peel strength may be 4.5 N / cm or more. The peel strength may be 5 N / cm or more. The peel strength may be 10 N / cm or less. In such a case, the via insulating portion 30 can contribute to suppressing disconnection of the electrical conductive layer formed in the through hole.

[0173] In the embodiment, by adjusting the difference value of the coefficient of thermal expansion between the via insulating portion 30 and the core layer 10, it is possible to suppress the occurrence of physical defects in the core layer due to repeated thermal expansion of the via insulating portion 30 or damage to the electrical conductive layer in the through hole.

[0174] The coefficients of thermal expansion of the via insulating portion 30 and the core layer 10 can be measured with a TMA (Thermal Mechanical Analyzer) using a thermomechanical analysis method. Exemplarily, the coefficient of thermal expansion can be measured using a TMA of the Q400 model of TA Instruments.

[0175] The coefficient of thermal expansion is measured in an atmosphere of 150 °C or lower.

[0176] The difference value between the coefficient of thermal expansion value of the via insulating portion and the coefficient of thermal expansion value of the core layer 10 is the absolute value of the value obtained by subtracting the coefficient of thermal expansion value of the core layer 10 from the coefficient of thermal expansion value of the via insulating portion.

[0177] The difference value between the coefficient of thermal expansion value of the via insulating portion and the coefficient of thermal expansion value of the core layer 10 may be 35 ppm / °C or less. The difference value may be 32 ppm / °C or less. The difference value may be 30 ppm / °C or less. The difference value may be 10 ppm / °C or more. In such a case, even if the core layer 10 has a complex structure and high hardness characteristics, damage to the core layer 10 due to thermal expansion of the via insulating portion can be less likely to occur. Also, when an electrical conductive layer is disposed in the through hole, disconnection of the electrical conductive layer in a high-temperature atmosphere can be suppressed.

[0178] The packaging substrate 300 may further include a first insulating layer 421 formed in contact with at least a part of the upper surface of the core layer 10. The depth of the dimple of the first insulating layer 421 may be 15 μm or less.

[0179] The first insulating layer 421 is one of the insulating layers 42 described above, which is formed in contact with at least a part of the upper surface of the core layer 10. That is, the first insulating layer 421 is a component included in the insulating layer 42.

[0180] Since the description of the material, formation method, etc. of the first insulating layer 421 overlaps with the above-described content, it is omitted.

[0181] In the packaging substrate 300 of the embodiment, the depth of the dimple of the first insulating layer 421 can be adjusted within a specific range. The first insulating layer 421 having the above characteristics has a flatness suitable for forming the first rewiring layer 40 of the multilayer structure, the rewiring layer has excellent electrical reliability, and it can help reduce the occurrence frequency of misalignment in the rewiring layer to a certain level or less.

[0182] The depth of the dimple of the first insulating layer 421 can be measured by TEM (Transmission Electron Microscope).

[0183] The depth of the dimple of the first insulating layer 421 may be 15 μm or less. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 7 μm or less. The depth may be 1 μm or more. In such a case, the first rewiring layer 40 with improved flatness can be formed.

[0184] The packaging substrate 300 may further include a second insulating layer (not shown) formed in contact with at least a part of the lower surface of the core layer 10. The depth of the dimple of the second insulating layer may be 15 μm or less.

[0185] The second insulating layer is formed such that at least a part of it is in contact with the upper surface of the core layer 10 among the above-described insulating layers. That is, the second insulating layer is a component included in the insulating layer.

[0186] Since the description of the material, formation method, etc. of the second insulating layer overlaps with the above-described content, it is omitted.

[0187] The depth of the dimple of the second insulating layer may be 15 μm or less. The depth may be 12 μm or less. The depth may be 10 μm or less. The depth may be 7 μm or less. The depth may be 1 μm or more. In such a case, even if a multilayered rewiring layer is formed, the electrical reliability of the rewiring layer is excellent.

[0188] Hereinafter, embodiments will be described in more detail through specific examples. The following examples are merely illustrative for helping the understanding of the embodiments, and the scope of the embodiments is not limited thereto.

[0189] Manufacturing Example: Manufacturing of a Packaging Substrate Example 1: After forming defects through laser irradiation on the surface of a Corning glass plate SG7.8, wet etching was performed to form a plurality of through holes, and a core layer was provided. The inner diameter of the through holes was adjusted to about 150 μm.

[0190] A screen targeting the plurality of through holes was installed on the core layer, and a via insulating part manufacturing composition, Sun Ink's THP-100 DX1-450Ps ink, was filled into the through holes by screen printing. The average particle diameter of the filler included in the via insulating part manufacturing composition was applied as less than 15 μm. The average particle diameter of the filler was measured in accordance with JIS K5600-2-5.

[0191] A via-plugged substrate was provided by curing the filled ink at 140 °C for 30 minutes to form a via insulating portion. The via-plugged substrate was put into a chamber, and plasma descum was performed by repeating multiple times the exposure to an O2 plasma atmosphere for 5 minutes. The substrate on which descum was performed was immersed in a water-filled water tank, and then ultrasonic cleaning was performed for 300 seconds by applying a vibration frequency of 100 kHz to complete the packaging substrate.

[0192] Evaluation Example: Measurement of the Depth of the Trench Structure of the Packaging Substrate Three of the through holes located on each of the upper and lower surfaces of the packaging substrate of the example were specified, and the surface profile of the through holes was measured with a surface roughness meter manufactured by Veeco. From the measured surface profile, the average height value of the upper surface of the core layer (referred to as the A value) and the height value of the point with the lowest height in the through hole (referred to as the B value) were calculated, and then the value obtained by subtracting the B value from the A value was calculated as the depth value of the trench structure.

[0193] The surface profile for each through hole was measured once in the x-axis direction and once in the y-axis direction in the in-plane direction of the upper surface of the core layer.

[0194] The profiles of the trench structures for each through hole located on the upper surface of the packaging substrate of the example are shown in FIGS. 5A to 5C below, and the depth values of the trench structures are shown in Table 1 below.

[0195] The profiles of the trench structures for each through hole located on the lower surface of the packaging substrate of the example are shown in FIGS. 6A to 6C below, and the depth values of the trench structures are shown in Table 2 below.

[0196] Evaluation Example: Evaluation of Dimples An insulating layer was formed on the packaging substrate of the example. Specifically, an ABF (Ajinomoto Build-up Film) was laminated on the upper surface of the core layer by a vacuum lamination method to form an insulating layer.

[0197] The cross-section of the packaging substrate with the insulating layer formed was photographed by TEM, and the depth of the dimple was calculated. The TEM image of the packaging substrate with the insulating layer formed is shown in FIG. 7 below.

[0198] Evaluation Example: Composition for Manufacturing Via Insulation Part and Physical Properties of Via Insulation Part The viscosity of the composition for manufacturing the via insulation part applied to the production of the packaging substrate of the example was measured with a cone-plate rotational viscometer in accordance with JIS-Z8803:2011.

[0199] After applying the composition for manufacturing the via insulation part to a flat plate, it was cured at 140 °C for 30 minutes to form a film-like via insulation part. The Young's modulus of the via insulation part was measured through DMA at 30 °C. Also, the tensile strength and elongation rate of the via insulation part were measured with a UTM.

[0200] After forming a copper thin film with a thickness of 20 μm on the via insulation part, the peel strength of the copper thin film with respect to the surface of the via insulation part was measured by a 180° peel test.

[0201] The measured values of the composition for manufacturing the via insulation part and the via insulation part are shown in Table 3 below.

[0202] [Table 1]

[0203] [Table 2]

[0204] [Table 3]

[0205] In the evaluation of the dimple, the depth of the dimple in the example was measured to be 10 μm or less. This indicates that the degree to which the insulating layer is embedded in the through hole can be adjusted, and the upper surface of the insulating layer can have excellent flatness.

[0206] Also, in the TEM image shown in FIG. 7, it was observed that no voids were formed in the through holes. This means that when an electrically conductive layer is formed on the via inner diameter surface, the via insulating portion can stably fix and protect the electrically conductive layer.

[0207] Although the preferred embodiments of the present invention have been described in detail above, the scope of the rights of the present invention is not limited thereto, and various modifications and improvements made by those skilled in the art using the basic concept of the present invention defined in the appended claims also belong to the scope of the rights of the present invention.

Description of Reference Numerals

[0208] 100 Base substrate 10 Core layer 11 Through hole 12 Upper surface of the core layer 13 Via inner diameter surface 20 Screen 21 Squeegee 22 Composition for manufacturing via insulating portion 30 Via insulating portion 31 Trench structure 32 One end of the via insulating portion 40 First rewiring layer 41 Electrically conductive layer 42 Insulating layer 421 First insulating layer 200 Via-plugged substrate 300 Packaging substrate Dp In-plane direction of the base substrate

Claims

1. A preparation step of preparing a base substrate including a core layer having an upper surface and through-holes formed in the thickness direction; A via insulation part forming step of forming a via insulation part in the through-holes to provide a via-plugged substrate; A manufacturing step of manufacturing a packaging substrate from the via-plugged substrate, the manufacturing method of the packaging substrate comprising the above steps.

2. The core layer is a glass core; The core layer includes two or more of the through-holes; The diameter of the through-holes is 40 μm to 200 μm; The pitch of the through-holes is 50 μm to 1500 μm, the manufacturing method of the packaging substrate according to Claim 1.

3. The via insulation part forming step includes a filling process of filling the through-holes with a composition for manufacturing a via insulation part by screen printing, and a curing process of curing the injected composition for manufacturing a via insulation part to form the via insulation part; The viscosity of the composition for manufacturing a via insulation part is 100 dPa*s to 500 dPa*s, the manufacturing method of the packaging substrate according to Claim 1.

4. The via insulation part forming step further includes a descum process of plasma descumming the via-plugged substrate, the manufacturing method of the packaging substrate according to Claim 3.

5. The via insulation part includes one end located on the upper surface side of the core layer; The via-plugged substrate has a trench structure in which one end of the via insulation part is located lower than the upper surface of the core layer, the manufacturing method of the packaging substrate according to Claim 1.

6. In the via-plugged substrate, the depth of the trench structure is 1 μm to 15 μm, the manufacturing method of the packaging substrate according to Claim 5.

7. The packaging substrate includes the core layer in which the through-holes are formed in the thickness direction, and the via insulation parts formed in the through-holes; The via insulation part includes a filler; The average particle diameter of the filler is 0.1 μm or more and less than 15 μm, the manufacturing method of the packaging substrate according to Claim 1.

8. The elongation rate of the via insulation part is 0.1% to 5%, the manufacturing method of the packaging substrate according to Claim 1.

9. The composition for manufacturing a via insulation part includes an epoxy resin, a curing agent and a filler, the manufacturing method of the packaging substrate according to Claim 1.

10. The packaging substrate includes: the core layer in which the through hole is formed in the thickness direction; a via insulating portion formed in the through hole; and a first insulating layer formed in contact with at least a part of the upper surface of the core layer. The manufacturing method of the packaging substrate according to claim 1, wherein the depth of the dimple of the first insulating layer is 15 μm or less.

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