Semiconductor element and manufacturing method for semiconductor element

Abstract

To provide a semiconductor element.SOLUTION: A semiconductor element 10 includes a semiconductor layer 11 containing silicon, a first silicide layer 12 included in the semiconductor layer 11, and a second silicide layer 13 included in the first silicide layer 12. The first silicide layer 12 includes hafnium silicide, zirconium silicide, nickel silicide, and cobalt silicide containing metal that is different from titanium. The second silicide layer 12 includes TiSi2 with a C54 crystal structure. Thus, the contact resistance of the semiconductor element 10 can be reduced.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device including a silicide layer that enhances crystallization of a second silicide layer, and a method for manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device includes a junction of a metal and a semiconductor at a specific portion of the semiconductor device in order to exchange electrical signals. This is because the metal has a relatively lower resistance than the semiconductor and is easy to wire to the outside. However, in this case, a contact resistance due to a heterojunction of a semiconductor / metal occurs.

[0003] In order to reduce such contact resistance, various methods for reducing the Schottky energy barrier between a semiconductor and a metal have been proposed. For example, for an n-type semiconductor, a metal having a work function of around 4 eV may be used, and for a p-type semiconductor, a metal having a work function of around 5 eV may be used. However, since the phenomenon of pinning of the work function of the metal occurs on the surface of the semiconductor, there is a limit to reducing the Schottky energy barrier regardless of the type of metal. As another proposal, it is also possible to reduce the depletion width by doping the surface of the semiconductor in contact with the metal at a high concentration. However, as the requirements for smaller-sized semiconductor devices increase, the doping concentration has to be further increased, but there are limits to the method of increasing the doping concentration, the method of stably maintaining the doping state, and reducing the depletion width due to the increase in the doping concentration.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by the present invention is to provide a semiconductor device including a first silicide layer that enhances crystallization of a second silicide layer.

[0005] Another object of the present invention is to provide a method for manufacturing a semiconductor device including a first silicide layer that enhances crystallization of a second silicide layer.

Means for Solving the Problems

[0006] A semiconductor device according to an exemplary embodiment includes a semiconductor layer containing silicon, a first silicide layer located on the semiconductor layer, and a second silicide layer located on the first silicide layer and containing titanium and having a crystal structure. The first silicide layer contains a metal different from titanium, and the second silicide layer contains TiSi2 having a C54 crystal structure.

[0007] The first silicide layer contains at least one of hafnium silicide, zirconium silicide, nickel silicide, and cobalt silicide.

[0008] The first silicide layer has a thickness in the range of 3 Å to 30 Å.

[0009] The first silicide layer has a crystal structure. The second silicide layer has a thickness in the range of 5 Å or more and 70 Å or less.

[0010] The first silicide layer contains at least one of ZrSi, ZrSi2, Zr5Si3, and Zr3Si2.

[0011] The second silicide layer has a Schottky barrier height of 0.7 eV or less.

[0012] The semiconductor device further includes a metal layer located on the second silicide layer.

[0013] The metal layer includes magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or any combination thereof.

[0014] The metal layer includes a source electrode located on one side of the channel layer and a drain electrode located opposite to the other side of the channel layer. The second silicide layer includes a 2-1 silicide layer located between the source electrode and the channel layer and a 2-2 silicide layer located between the drain electrode and the channel layer. The first silicide layer includes a 1-1 silicide layer located between the 2-1 silicide layer and the channel layer and a 1-2 silicide layer located between the 2-2 silicide layer and the channel layer.

[0015] The semiconductor layer includes a single crystal or polycrystalline structure.

[0016] The first silicide layer is an undoped layer.

[0017] The second silicide layer is an undoped layer.

[0018] The first silicide layer is located so as to be in direct contact with the semiconductor layer.

[0019] The first silicide layer is located so as to be in direct contact with the second silicide layer.

[0020] The semiconductor layer includes a well region doped with a first conductivity type, and a source region and a drain region doped with a second conductivity type that is electrically opposite to the first conductivity type.

[0021] The semiconductor device further includes a gate electrode and a gate insulating film located above the gate electrode, and the semiconductor layer includes a channel layer located above the gate insulating film.

[0022] The semiconductor layer includes a channel layer, and the semiconductor device further includes a gate insulating film located on the upper surface of the channel layer and a gate electrode located above the gate insulating film.

[0023] A method for manufacturing a semiconductor device according to an exemplary embodiment includes forming a semiconductor layer containing silicon, forming a first silicide layer on the semiconductor layer, forming a second silicide layer containing titanium on the first silicide layer, and crystallizing the second silicide layer. The first silicide layer contains a metal different from titanium, and the second silicide layer contains TiSi2 having a C54 crystal structure.

[0024] The second silicide layer has a C54 crystal structure in the range of 200 to 400 °C.

Advantages of the Invention

[0025] A semiconductor device according to an exemplary embodiment includes a first silicide layer between a silicon semiconductor layer and a second silicide layer, and can promote the crystallization of the second silicide layer at a thin thickness and a low temperature. Thereby, the contact resistance of the miniaturized semiconductor device is reduced, the electrical characteristics are improved, and it can be applied to various semiconductor devices.

Brief Description of the Drawings

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Embodiments for Carrying Out the Invention

[0027] Hereinafter, with reference to the accompanying drawings, semiconductor elements and manufacturing methods of semiconductor elements according to various embodiments will be described in detail. In the following drawings, the same reference numerals denote the same components, and the size of each component on the drawing may be exaggerated for clarity and convenience of explanation. Terms such as first or second may be used to describe various components, but the components are not limited by the terms. The terms are used only for the purpose of distinguishing one component from another.

[0028] The singular forms include plural forms unless the context clearly indicates otherwise. Also, when a part "includes" a certain component, this means that, unless otherwise stated to the contrary, it does not exclude other components and may further include other components. Also, in the drawings, the sizes and thicknesses of the components may be exaggerated for clarity of explanation. Also, when a given material layer is described as being present on a substrate or another layer, the material layer may be present in direct contact with the substrate or another layer, or another third layer may be present therebetween. And the materials forming the layers in the following embodiments are exemplary, and other materials may be used instead.

[0029] FIG. 1 is a drawing schematically showing a semiconductor device according to an exemplary embodiment.

[0030] The semiconductor device 10 includes a semiconductor layer 11, a first silicide layer 12 provided in the semiconductor layer 11, and a second silicide layer 13 provided in the first silicide layer 12.

[0031] The semiconductor layer 11 includes silicon (Si). The semiconductor layer 11 constitutes various regions of the semiconductor device 10. The semiconductor device 10 is applied to, for example, a transistor, a FET (Field effect transistor, field effect transistor), a semiconductor memory device, a logic device, an image sensor, etc., and the semiconductor layer 11 can be used as a source / drain region or a channel region of these devices. The semiconductor layer 11 is an undoped layer, an n-type doped layer, or a p-type doped layer. When the semiconductor layer 11 is an n-type doped layer, it contains at least one dopant of arsenic (As), phosphorus (P), and antimony (Sb). When the semiconductor layer 11 is a p-type doped layer, it contains a boron (B) dopant. The semiconductor layer 11 includes single-crystal silicon or polycrystalline silicon.

[0032] The first silicide layer 12 enhances and promotes the crystallization of the second silicide layer 13. The first silicide layer 12 contains a material having a crystallization temperature lower than the crystallization temperature of the second silicide layer 13. The first silicide layer 12 is, for example, hafnium silicide (HfSix ), zirconium silicide (ZiSi x ), nickel silicide (NiSi x ), and cobalt silicide (CoSi x ), or at least one of them. Alternatively, the first silicide layer 12 contains, for example, at least one of ZrSi, ZrSi2, Zr5Si3, and Zr3Si2.

[0033] The second silicide layer 13 contains a metal and silicon. For example, the second silicide layer 13 contains Ti and silicon. The second silicide layer 13 contains TiS2. On the other hand, the first silicide layer 12 contains a metal different from Ti.

[0034] The first silicide layer 12 induces the second silicide layer 13 to crystallize at a thin thickness and low temperature. The first silicide layer 12 contains, for example, zirconium silicide (Zi x Si y ), and can promote the crystallization of the second silicide layer 13 even at a relatively low temperature and thin thickness. When the first silicide layer 12 contains Zr x Si y ), it contains at least one of ZrSi, ZrSi2, Zr5Si3, and Zr3Si2. On the other hand, the first silicide layer 12 may be disposed between the semiconductor layer 11 and the second silicide layer 13. Alternatively, the upper surface of the first silicide layer 12 may be arranged to be in direct contact with the lower surface of the second silicide layer 13. Alternatively, the lower surface of the first silicide layer 12 may be in direct contact with the semiconductor layer 11, and the upper surface of the first silicide layer 12 may be in direct contact with the second silicide layer 13.

[0035] The second silicide layer 13 may have a thickness in the range of 70 Å or less. Alternatively, the second silicide layer 13 may have a thickness in the range of 5 to 70 Å. Alternatively, the second silicide layer 13 may have a thickness in the range of 5 to 50 Å. However, it is difficult to crystallize the second silicide layer 13 while making its thickness this thin. This is because when the thickness is thin, the second silicide layer 13 is likely to be damaged during the crystallization process. When crystallizing the second silicide layer 13 having a very thin thickness of 70 Å or less, the crystallization of the second silicide layer 13 is enhanced and promoted by the first silicide layer 12, and the second silicide layer 13 crystallizes at a relatively low temperature, thereby suppressing damage to the second silicide layer 13 and other layers that may occur at high temperatures. In other words, the crystallization temperature of the second silicide layer 13 can be reduced compared to the case where the first silicide layer 12 is absent, and by reducing the crystallization temperature, damage to the second silicide layer 13 during the crystallization of the very thin second silicide layer 13 can be suppressed. The crystallization temperature of the second silicide layer 13 may be 500 °C or less. Alternatively, the crystallization temperature of the second silicide layer 13 may be 450 °C or less. Alternatively, the crystallization temperature of the second silicide layer 13 may be 400 °C or less. Alternatively, the crystallization temperature of the second silicide layer 13 may have a range of 200 - 400 °C.

[0036] A metal layer 14 may be further provided on top of the second silicide layer 13. The metal layer 14 is located in a direction opposite to the first silicide layer 12 with the second silicide layer 13 as the center. The metal layer 14 may be provided so as to be in direct contact with the second silicide layer 13. However, the metal layer 14 is not limited thereto. The metal layer 14 may be used, for example, as an electrode layer. The metal layer 14 contains magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), palladium (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or any combination thereof.

[0037] As the semiconductor memory element or logic element that employs the semiconductor element 10 becomes gradually smaller in size and its area becomes smaller, it is necessary to maintain ohmic characteristics even in a narrow area in order to maintain element performance. In order to maintain ohmic characteristics, the metal layer 14 needs to have a low specific resistance and a low contact resistance. However, in the case of the bonding structure between the silicon semiconductor layer 11 and the metal layer 14, due to the pinning effect generated at the bonding surface, a Schottky barrier height is generated at the bonding surface between silicon (Si) and the metal layer 14, which leads to a high contact resistance. Here, by providing the second silicide layer 13 between the metal layer 14 and the silicon semiconductor layer 11 and reducing the Schottky barrier height at the bonding surface between the silicon semiconductor layer 11 and the metal layer 14, the contact resistance can be reduced. In addition, the second silicide layer 13 has excellent specific resistance characteristics and improves the resistance characteristics between the silicon (Si) semiconductor layer 11 and the metal layer 14. The second silicide layer 13 is titanium silicide (TiSi xIncluding ([0]) to improve the resistance characteristics. Titanium silicide has relatively excellent thermal stability and low specific resistance, so it can be usefully applied as a contact material for silicon-based semiconductor devices. The second silicide layer 13 has excellent characteristics such as a low work-function, low resistivity, and crystal compatibility with the silicon semiconductor layer 11, so it is usefully used as an intermediate resistance material between the silicon semiconductor layer 11 and the metal layer 14.

[0038] The first silicide layer 12 can reduce the crystallization temperature of the second silicide layer 13 and cause the second silicide layer 13 to have a crystalline phase. When the second silicide layer 13 contains titanium silicide (TiSi x )), the second silicide layer 13 has a C54 crystal structure. Since the crystallization temperature of the second silicide layer 13 is lowered, it is possible to suppress adverse effects on other layers due to high temperature during the manufacturing process of the semiconductor device 10 and to give the semiconductor device 10 high conductivity. In addition, even when the second silicide layer 13 has a thin thickness, the first silicide layer 12 can have a C54 crystal structure by promoting crystallization at a relatively low temperature. Therefore, the Schottky barrier of the second silicide layer 13 can be reduced. For example, the second silicide layer 13 includes a Schottky barrier of 0.7 eV or less. Or, the second silicide layer 13 may include a Schottky barrier in the range of 0.3 to 0.7 eV. Also, the first silicide layer 12 may have a crystal structure instead of being amorphous.

[0039] Hereinafter, an example in which the second silicide layer 13 contains titanium silicide TiSi2 will be described in more detail.

[0040] Titanium silicide has, for example, a C49 crystal structure or a C54 crystal structure during the crystallization process.

[0041] FIG. 2 is a drawing showing the change in specific resistance with temperature when the thickness of the titanium silicide layer is 25 nm, 40 nm, and 60 nm. FIG. 2 is a drawing showing the case where the titanium silicide layer is crystallized without the first silicide layer 12. Line A indicates the process limit temperature of the semiconductor element including the titanium titanium silicide layer. The specific resistance increases as the thickness of the titanium silicide layer decreases. When the thickness of the titanium silicide layer is 40 nm or 60 nm, the specific resistance is relatively low even in the amorphous state. On the other hand, when the thickness of the titanium silicide layer is 25 nm, a C49 crystal structure is formed at a temperature of about 500 °C or higher, and the specific resistance is as high as 20 (Ω / sq) or more. A C54 crystal structure is formed at a temperature of about 700 °C or higher, and in this case, the specific resistance becomes as low as 20 (Ω / sq) or less. In the case of titanium silicide, the C49 structure is formed at a relatively low temperature, for example, about 500 °C, while the C54 structure, which exhibits lower resistance than the C49 structure, is formed at a higher temperature of about 700 °C. Since the C49 structure has a lower activation energy than the C54 structure, during the crystallization of titanium silicide, nucleation tends to occur in the C49 structure rather than the C54 structure. As a result, the packing density of the C54 structure titanium silicide becomes lower than that of the C49 structure, and such a low packing density may cause a volume shrinking problem in a subsequent process such as annealing. Not only is the crystal formation temperature of the C54 structure very high and difficult to crystallize, but the crystal formation temperature of the C54 structure increases significantly as the thickness decreases. Therefore, even if the resistance is slightly higher than that of the C54 structure, the titanium silicide layer has been used in an amorphous shape. On the other hand, although a small amount of Mo, Ta, Nb, etc. has been inserted into titanium silicide (TiSi x ) to reduce the crystallization temperature and form C54 at a relatively low temperature, there are problems such as an increase in specific resistance and no crystal formation at a thin thickness.

[0042] As described above, titanium silicide has better resistance characteristics in the C54 crystal structure than in the C49 crystal structure. However, due to the high activation energy of the C54 crystal structure, crystallization cannot be successfully achieved when joining the silicon semiconductor layer 11 and the second silicide layer 13 containing titanium. At a relatively low temperature, for example, about 500 °C, the C49 crystal structure is formed, but the C49 crystal structure not only exhibits high specific resistance characteristics but also shows a high contact resistance when joined to the silicon semiconductor layer 11. In comparison, titanium silicide TiSi2 with the C54 crystal structure has better resistance characteristics than the C49 crystal structure. However, since the crystallization temperature of the C54 crystal structure is higher than that of the C49 crystal structure, it has an adverse effect on other layers during the crystallization process, reducing the overall performance of the semiconductor device. Thus, in this embodiment, by disposing a first silicide layer 12 containing a crystallization driving intermediate material between the silicon semiconductor layer 11 and the second silicide layer 13, the second silicide layer 13 can be successfully crystallized even with a thin thickness. The first silicide layer 12 has a high reactivity with the silicon of the semiconductor layer 11, and can not only greatly reduce the crystallization activation energy of the second silicide layer 13 but also enhance the crystal stability.

[0043] The first silicide layer 12 can be a silicide containing a metal and silicon. The first silicide layer 12 may contain a metal different from titanium. The metal layer 14 can be a nitrogen-based metal layer such as TiN, WN, or MoN. Alternatively, the metal layer 14 may contain at least one of Mo, Ru, Co, Ti, and W.

[0044] Figure 3 shows the crystal form of titanium silicide in a comparative example without the first silicide layer 12 at about 400 °C based on XRD (X-ray diffraction) and RHEED (Reflection high-energy electron diffraction) analyses. This graph shows the light intensity by the crystallization specific angle 2θ (two-theta). The crystal structure of the substance can be understood from the peak value at a specific angle. Referring to Figure 3, the titanium silicide in the comparative example shows amorphous characteristics. This indicates that titanium silicide (TiSi x ) does not crystallize at a relatively low temperature of about 400 °C due to its high crystal activation energy. Figure 4 shows the crystal form of titanium silicide (TiSi x ) at about 500 °C based on XRD and RHEED analyses. At a relatively high temperature of 500 °C, the crystallization of titanium silicide (TiSi x ) was confirmed during growth through RHEED, but according to XRD analysis, a C49 crystal structure with high resistance characteristics was confirmed.

[0045] Figure 5 is a diagram showing the crystallinity when the first silicide layer 12 is disposed between the semiconductor layer 11 and the second silicide layer 13 according to an exemplary embodiment. Here, the first silicide layer 12 contains ZrSi2. The cases where the thickness of the first silicide layer 12 is 5 Å, 10 Å, and 20 Å are shown respectively. In Figure 5, for the sake of convenience, the graphs are shown separated regardless of the intensity in order to show both the cases where the thickness of the first silicide layer 12 is 5 Å, 10 Å, and 20 Å. When the first silicide layer 12 has a thickness of 5 Å, 10 Å, and 20 Å, it was shown that titanium silicide has a C54 crystal structure respectively. Even when the first silicide layer 12 is very thin, titanium silicide TiSi2 can have a C54 crystal structure. The first silicide layer 12 may have a thickness in the range of, for example, 3 Å to 30 Å. For example, the first silicide layer 12 may have a thickness in the range of 3 Å to 20 Å. For example, the first silicide layer 12 may have a thickness in the range of 5 Å to 20 Å.

[0046] Referring to FIG. 5, when the second silicide layer 13 is grown at about 400° C., it was found that titanium silicide TiSi2 was crystallized through RHEED. According to XRD analysis, the crystal phase of titanium silicide TiSi2 has a C54 structure with low resistance. The thickness of the titanium silicide TiSi2 has a range of 70 Å or less. In the semiconductor element 10 according to an exemplary embodiment, the second silicide layer 13 has a crystal phase. For example, the second silicide layer 13 has a C54 crystal structure.

[0047] FIG. 6 is a diagram showing a TEM image of a semiconductor element when the first silicide layer 12 contains ZrSi with a thickness of 20 Å. x It shows that the Si semiconductor layer 11, the first silicide layer 12 of ZrSi2, and the second silicide layer 13 of TiSi2 are stacked, indicating that they have a crystal structure. The TiSiO x layer shows an oxide layer formed in the process of exposing to the atmosphere after the lamination of the semiconductor element. The TiSiO x layer is not a component of the semiconductor element according to an exemplary embodiment. Here, the total thickness of the first silicide layer 12 of ZrSi2, the second silicide layer 13 of TiSi2, and the TiSiO x layer is about 90 Å.

[0048] FIG. 7 is a drawing showing a TEM image of a semiconductor element when the first silicide layer 12 contains ZrSi with a thickness of 5 Å. x It shows that the Si semiconductor layer 11, the first silicide layer 12 of ZrSi, x and the second silicide layer 13 of TiSi x are stacked, indicating that they have a crystal structure. Here, the total thickness of the first silicide layer 12 of ZrSi, x the second silicide layer 13 of TiSi, x and the TiSiO x layer is about 30 Å. Thus, even when the first silicide layer 12 is very thin, the second silicide layer 13 of TiSi x can be crystallized.

[0049] FIG. 8 shows the appearance of the C49-TiSi2 crystal structure and the C54-TiSi2 crystal structure in a semiconductor element according to an exemplary embodiment. C54-TiSi2 shows a peak value at a crystallization angle of about 40° in 2θ.

[0050] Next, a comparative example in which zirconium silicide (ZrSi x ) is laminated on top of titanium silicide will be described. That is, it is an example in which the ZrSi x layer is disposed not between the silicon layer and the TiSi x layer, but on top of the TiSi x layer. FIG. 9 is a diagram showing the crystallinity when a structure in which a 2-nm-thick TiSi x layer, a 0.5-nm-thick ZrSi x layer, and a 5-nm-thick TiSi x layer are sequentially laminated at 200° C. or lower is annealed at 200° C. and 400° C. for 30 minutes. In FIG. 9, the crystal structure of titanium silicide does not appear and shows an amorphous state. In other words, when the position of the ZrSi x layer corresponding to the first silicide layer 12 is changed to the top of the second silicide layer 13, the TiSi x layer is not crystallized at a temperature of about 400° C.

[0051] FIG. 10 is a diagram showing a TEM image of a comparative example having a Si / TiSi x / ZrSi x laminated structure and the atomic percentage according to the distance of the laminated structure. ZrSi x has a thickness of 2 nm. TiSi x has a thickness of about 2 nm. Here, TiSiO x indicates an oxide film oxidized during crystallization of the laminated structure. Referring to the TEM image, the TiSi x layer is not crystallized.

[0052] FIG. 11 is a diagram showing a TEM image of a comparative example having a Si / TiSi x / ZrSi x / TiSi x laminated structure and the atomic percentage according to the distance of the laminated structure. ZrSi xhas a thickness of about 0.5 nm. TiSi x has a thickness of about 0.5 nm. Referring to the TEM image, TiSi x layer is not crystallized.

[0053] Referring to FIGS. 10 and 11, when the ZrSi x layer corresponding to the first silicide layer is positioned on the TiSi2 layer to reduce the thickness, or when the ZrSi x layer is positioned between two TiSi x layers, the TiSi x layer is not crystallized. When the ZrSi x layer is provided with a thin thickness between two TiSi x layers, it has an effect similar to doping the TiSi x layer with Zr. Even if the TiSi x layer is doped with a dopant such as Zr, the TiSi x layer is difficult to crystallize.

[0054] In the semiconductor device 10 according to an exemplary embodiment, the first silicide layer 12 is an undoped layer. Also, the second silicide layer 13 may be an undoped layer. When the second silicide layer 13 is an undoped layer, it can have a lower specific resistance and a lower Schottky barrier compared to the doped silicide. At the same time, the second silicide layer 13 can have a C54 crystal structure at a relatively low temperature. However, the first silicide layer 12 and the second silicide layer 13 are not limited to these and may contain a dopant as needed.

[0055] As described above, the semiconductor element 10 according to the exemplary embodiment includes a first silicide layer 12 between the silicon semiconductor layer 11 and the second silicide layer 13, and enables the second silicide layer 13 to crystallize at a relatively low temperature in a state where the thickness of the second silicide layer 13 is very thin. When the first silicide layer 12 is absent, the titanium silicide of the semiconductor element 10 according to the exemplary embodiment can have a C54 crystal structure with the same thickness in the temperature range where titanium silicide has a C49 crystal structure. Therefore, the contact resistance of the semiconductor element 10 on the miniaturized silicon substrate can be reduced, and the performance of the semiconductor element 10 can be improved by suppressing the adverse effects on other layers of the semiconductor element 10 during the crystallization process.

[0056] FIG. 12 is a diagram for explaining a method of manufacturing a semiconductor element according to an exemplary embodiment.

[0057] Referring to FIGS. 12 and 1, the method of manufacturing a semiconductor element includes a step of forming a semiconductor layer 11 containing silicon (S10). Then, a first silicide layer 12 is formed on the semiconductor layer 11 (S20). The first silicide layer 12 contains a metal different from titanium. A second silicide layer 13 containing titanium is formed on the first silicide layer 12 (S30). Then, the second silicide layer 13 is crystallized by heat treatment (S40). The first silicide layer 12 promotes the crystallization of the second silicide layer 13, and the second silicide layer 13 can have a C54 crystal structure at a relatively low temperature. The second silicide layer 13 contains TiSi2 having a C54 crystal structure in the range of 200 to 400°C. The second silicide layer 13 may have a thickness in the range of 5 Å or more and 70 Å or less.

[0058] The semiconductor element 10 manufactured by the manufacturing method according to the exemplary embodiment can reduce the contact resistance and may be applied to a next-generation semiconductor memory element or a logic element or the like.

[0059] Logic elements are responsible for operations and control, while memory elements are responsible for information storage. Logic elements are applied to microcomponents, analog ICs (Integrated Circuits), logic ICs, etc. Analog ICs include power semiconductors, image sensors, touch controllers, etc. Logic ICs include DDI, T-CON (Timming Controller), media ICs, APs (Application Processors), automotive semiconductors, etc. Memory elements include DRAMs (Dynamic Random Access Memories), SRAMs, NAND memories, etc.

[0060] The semiconductor element 10 described above is applied to various devices such as field-effect transistors. For example, FIG. 13 is a cross-sectional view schematically showing the structure of a field-effect transistor according to an embodiment. Referring to FIG. 13, the field-effect transistor 100 includes a well region 101 doped with a first conductivity type, a source region 102a doped with a second conductivity type that is electrically opposite to the first conductivity type, a drain region 102b doped with the second conductivity type, a first-1 silicide layer 103a disposed on the source region 102a, a first-2 silicide layer 103b disposed on the drain region 102b, a second-1 silicide layer 104a disposed on the first-1 silicide layer 103a, a second-2 silicide layer 104b disposed on the first-2 silicide layer 103b, a source electrode 105a disposed on the second-1 silicide layer 104a, a drain electrode 105b disposed on the second-2 silicide layer 104b, a gate insulating film 108 disposed on the well region 101, and a gate electrode 109 disposed on the gate insulating film 108.

[0061] When compared with FIG. 1, the source region 102a and the drain region 102b correspond to a semiconductor layer containing silicon. The second-1 silicide layer 104a and the second-2 silicide layer 104b contain metal and silicon. The second-1 silicide layer 104a and the second-2 silicide layer 104b contain titanium silicide TiSi2. The first-1 silicide layer 103a and the first-2 silicide layer 103b are HfSi x , ZrSi x , NiSi x , and CoSi x and contain at least one of them. The first-1 silicide layer 103a and the first-2 silicide layer 103b contain at least one of ZrSi, ZrSi2, Zr5Si3, and Zr3Si2.

[0062] FIG. 13 shows that the well region 101 is doped p-type and the source region 102a and the drain region 102b are doped n-type, but this is merely an example, and the well region 101 may be doped n-type and the source region 102a and the drain region 102b may be doped p-type. Or, the source region 102a and the drain region 102b may be undoped. The well region 101 is doped at a relatively low concentration of about 10 14 to 10 18 / cm 3 , and the source region 102a and the drain region 102b are doped at a relatively high concentration of about 10 19 / cm 3 or more to reduce the depletion width.

[0063] The source region 102a and the drain region 102b are disposed on both side surfaces of the upper part of the well region 101. For example, after forming the well region 101 by doping the semiconductor substrate into a p-type, both sides of the upper surface of the semiconductor substrate are doped into an n-type to form the source region 102a and the drain region 102b. The well region 101 includes a channel region 101a between the source region 102a and the drain region 102b. The channel region 101a is doped into the first conductivity type in the same manner as the well region 101. The source region 102a and the drain region 102b are disposed apart from each other with the channel region 101a in between. Here, the source region 102a and the drain region 102b correspond to the semiconductor layer 11 shown in FIG. 1. In other words, when the field effect transistor 100 shown in FIG. 13 is made to correspond to the semiconductor element 10 shown in FIG. 1, the semiconductor layer 11 can include the source region 102a and the drain region 102b.

[0064] The first-1 silicide layer 103a and the first-2 silicide layer 103b are disposed apart from each other with the gate insulating film 108 therebetween.

[0065] The second-1 silicide layer 104a and the second-2 silicide layer 104b can play a role in reducing the contact resistance. The second-1 silicide layer 104a and the second-2 silicide layer 104b are disposed apart from each other with the gate insulating film 108 therebetween. The second-1 silicide layer 104a and the second-2 silicide layer 104b correspond to the second silicide layer 13 shown in FIG. 1. In other words, when the field effect transistor 100 shown in FIG. 13 is made to correspond to the semiconductor element 10 shown in FIG. 1, the second silicide layer 13 can include the second-1 silicide layer 104a and the second-2 silicide layer 104b.

[0066] The first - 1 silicide layer 103a promotes the crystallization of the second - 1 silicide layer 104a, and the first - 2 silicide layer 103b promotes the crystallization of the second - 2 silicide layer 104b. The lower surface of the first - 1 silicide layer 103a is in direct contact with the source region 102a, and the upper surface of the first - 2 silicide layer 103a is in direct contact with the second - 1 silicide layer 104a. Also, the lower surface of the first - 2 silicide layer 103b is in direct contact with the drain region 102b, and the upper surface of the first - 2 silicide layer 103b is in direct contact with the second - 2 silicide layer 104b.

[0067] The source electrode 105a disposed on the second - 1 silicide layer 104a and the drain electrode 105b disposed on the second - 2 silicide layer 104b can correspond to the metal layer 14 shown in FIG. 1. In other words, when the field - effect transistor 100 shown in FIG. 13 is made to correspond to the semiconductor element 10 shown in FIG. 1, the metal layer 14 can include the source electrode 105a and the drain electrode 105b. The source electrode 105a and the drain electrode 105b are arranged apart from each other via the gate electrode 109.

[0068] The gate insulating film 108 is disposed on the upper surface of the well region 101, particularly on the upper surface of the channel region 101a. The gate insulating film 108 includes at least one dielectric material among SiO2, SiNx, HfO2, and Al2O3. The gate electrode 109 disposed on the gate insulating film 108 includes polysilicon or the same metal material as the metal materials of the source electrode 105a and the drain electrode 105b.

[0069] The field - effect transistor 100 further includes a spacer 110 surrounding the sidewalls of the gate insulating film 108 and the gate electrode 109. The spacer 110 prevents the gate insulating film 108 and the gate electrode 109 from directly contacting the source electrode 105a and the drain electrode 105b. The spacer 110 may include an insulating material such as SiO2 or SiNx.

[0070] FIG. 14 is a cross-sectional view schematically showing the structure of a field-effect transistor according to still another embodiment. In the field-effect transistor 100 shown in FIG. 13, the upper surfaces of the well region 101, the source region 102a, and the drain region 102b are located in the same plane, and the first sidewall layer 104a and the second sidewall layer 104b extend so as to be in contact with the side surfaces of the spacer 110. On the other hand, in the field-effect transistor 100a shown in FIG. 14, the first sidewall layer 104a and the second sidewall layer 104b extend so as to be in contact with the lower surface of the spacer 110. For this reason, the upper surface of the well region 101 is formed higher than the upper surfaces of the source region 102a and the drain region 102b. The first sidewall layer 104a and the second sidewall layer 104b extend along the lower surface of the spacer 110 to the boundary surface between the spacer 110 and the gate insulating film 108. In this case, the first-1 sidewall layer 103a and the first-2 sidewall layer 103b also extend to the boundary surface between the spacer 110 and the gate insulating film 108.

[0071] The field-effect transistors 100 and 100a are employed in an image sensor. FIG. 15 is a diagram schematically showing the image sensor. The image sensor 150 includes an optical sensor array 160 in which optical sensors 161 for sensing light are arranged, a color filter array 180 in which color filters 181 for filtering light by color are arranged, a microlens array 190 in which microlenses 191 for focusing light for each pixel are arranged, and a driving layer 170 including the transistors 100 and 100a. The image sensor 150 generates an electrical image signal based on the intensity of incident light. The image sensor 150 is applied to various multimedia devices having a video shooting function. The image sensor 150 is applied to cameras such as mobile phones, smartphones, tablets, smart tablets, and notebook personal computers.

[0072] FIG. 16 is a cross-sectional view schematically showing the structure of a field effect transistor according to still another embodiment. Referring to FIG. 16, the field effect transistor 200 includes a gate electrode 201, a gate insulating film 202 disposed on the gate electrode 201, a channel layer 203 disposed on the gate insulating film 202, a source electrode 206a disposed on one side surface of the channel layer 203 and electrically contacting the channel layer 203, a drain electrode 206b disposed on the other side surface of the channel layer 203 and electrically contacting the channel layer 203, a second-1 silicide layer 205a disposed between the channel layer 203 and the source electrode 206a, a second-2 silicide layer 205b disposed between the channel layer 203 and the drain electrode 206b, a first-1 silicide layer 204a disposed between the second-1 silicide layer 205a and the channel layer 203, and a first-2 silicide layer 204b disposed between the second-2 silicide layer 205b and the channel layer 203.

[0073] The channel layer 203 corresponds to the semiconductor layer 11 shown in FIG. 1. In other words, when the field effect transistor 200 shown in FIG. 16 is made to correspond to the semiconductor element 10 shown in FIG. 1, the semiconductor layer 11 includes the channel layer 203 disposed on the gate insulating film 202. The channel layer 203 includes undoped silicon.

[0074] The source electrode 206a and the drain electrode 206b correspond to the metal layer 14 shown in FIG. 1. In other words, when the field effect transistor 200 shown in FIG. 16 is made to correspond to the semiconductor element 10 shown in FIG. 1, the metal layer 14 can include the source electrode 206a and the drain electrode 206b.

[0075] The 2-1 silicide layer 205a and the 2-2 silicide layer 205b correspond to the second silicide layer 13 shown in FIG. 1. In other words, when the field effect transistor 200 shown in FIG. 16 is made to correspond to the semiconductor element 10 shown in FIG. 1, the second silicide layer 13 can include the 2-1 silicide layer 205a and the 2-2 silicide layer 205b. The 2-1 silicide layer 205a extends from one side surface of the channel layer 203 to a partial region of the upper surface. Further, the 2-2 silicide layer 205b extends from the other side surface of the channel layer 203 to the other partial region of the upper surface so as not to contact the 2-1 silicide layer 205a. Therefore, the 2-1 silicide layer 205a and the 2-2 silicide layer 205b can be bent at about 90° between the side surface and the upper surface of the channel layer 203.

[0076] The 1-2 silicide layer 204a and the 1-2 silicide layer 204b correspond to the first silicide layer 12 shown in FIG. 1. In other words, when the field effect transistor 200 shown in FIG. 16 is made to correspond to the semiconductor element 10 shown in FIG. 1, the first silicide layer 12 can include the 1-1 silicide layer 204a and the 1-2 silicide layer 204b. The 1-1 silicide layer 204a extends from one side surface of the channel layer 203 to a partial region of the upper surface. Further, the 1-2 silicide layer 204b extends from the other side surface of the channel layer 203 to the other partial region of the upper surface so as not to contact the 1-1 silicide layer 204a. Therefore, the 1-1 silicide layer 204a and the 1-2 silicide layer 204b can be bent at about 90° between the side surface and the upper surface of the channel layer 203.

[0077] FIG. 17 is a cross-sectional view schematically showing the structure of a field-effect transistor according to still another embodiment. The field-effect transistor 200 in FIG. 16 has a difference in that the gate electrode 201 is disposed below the channel layer 203, and the field-effect transistor 200a shown in FIG. 17 has an upper gate structure. Referring to FIG. 17, the field-effect transistor 200a includes a substrate 221, an insulating layer 222 disposed on the upper surface of the substrate 221, a channel layer 223 disposed on the upper surface of the insulating layer 222, a gate insulating film 227 disposed in a partial region of the upper surface of the channel layer 223, a gate electrode 228 disposed on the upper surface of the gate insulating film 227, a first-1 silicide layer 224a and a first-2 silicide layer 224b respectively disposed on different regions of the upper surface of the channel layer 223, a second-1 silicide layer 225a disposed on the upper surface of the first-1 silicide layer 224a, a second-2 silicide layer 225b disposed on the upper surface of the first-2 silicide layer 224b, a source electrode 226a disposed on the upper surface of the second-1 silicide layer 225a, and a drain electrode 226b disposed on the upper surface of the second-2 silicide layer 225b.

[0078] The channel layer 223 corresponds to the semiconductor layer 11 shown in FIG. 1. In other words, when the field-effect transistor 200a shown in FIG. 17 is made to correspond to the semiconductor element 10 shown in FIG. 1, the semiconductor layer 11 includes the channel layer 223 disposed on the insulating layer 222. The channel layer 223 includes undoped silicon.

[0079] When the field-effect transistor 200a shown in FIG. 17 is made to correspond to the semiconductor element 10 shown in FIG. 1, the first silicide layer 12 can include a first-1 silicide layer 224a and a first-2 silicide layer 224b. The first-2 silicide layer 224a and the first-2 silicide layer 224b are arranged apart from each other with a gate insulating film 227 therebetween. The lower surface of the first-2 silicide layer 224a is in direct contact with the channel layer 223, and the upper surface of the first-2 silicide layer 224a is in direct contact with the second-1 silicide layer 225a. Also, the lower surface of the first-2 silicide layer 224b is in direct contact with the channel layer 223, and the upper surface of the first-2 silicide layer 224b is in direct contact with the second-2 silicide layer 225b.

[0080] The second-1 silicide layer 225a and the second-2 silicide layer 225b correspond to the second silicide layer 13 shown in FIG. 1. In other words, when the field-effect transistor 200a shown in FIG. 17 is made to correspond to the semiconductor element 10 shown in FIG. 1, the second silicide layer 13 can include the second-1 silicide layer 225a disposed on the first-1 silicide layer 224a and the second-2 silicide layer 225b disposed on the first-2 silicide layer 224b. The second-1 silicide layer 225a and the second-2 silicide layer 225b are arranged apart from each other with a gate insulating film 227 therebetween.

[0081] The source electrode 226a and the drain electrode 226b correspond to the metal layer 14 shown in FIG. 1. In other words, when the field-effect transistor 200a shown in FIG. 17 is made to correspond to the semiconductor element 10 shown in FIG. 1, the metal layer 14 can include the source electrode 226a disposed on the second-1 silicide layer 225a and the drain electrode 226b disposed on the second-2 silicide layer 225b. The source electrode 226a and the drain electrode 226b are arranged apart from each other with a gate electrode 228 therebetween.

[0082] FIG. 18 is a perspective view schematically showing the structure of a field effect transistor according to still another embodiment. Referring to FIG. 18, a field effect transistor 300 includes a substrate 301, a source structure 310 protruding in the Z direction from the upper surface of the substrate 301, a drain structure 340 protruding in the Z direction from the upper surface of the substrate 301, a rod-shaped channel 320 protruding in the Z direction from the upper surface of the substrate 301 and extending along the Y direction, and a gate structure 330 covering and surrounding the channel 320. The field effect transistor 300 may further include an element isolation film 302 for electrically separating it from other adjacent field effect transistors (not shown). The element isolation film 302 includes an insulating dielectric material and is disposed to extend in the Y direction along both side surfaces of the source structure 310, the channel 320, the gate structure 330, and the drain structure 340 on the upper surface of the substrate 301. The field effect transistor 300 shown in FIG. 18 is, for example, a fin field effect transistor (FinFET).

[0083] The channel 320 extends along the Y direction and is connected between the source structure 310 and the drain structure 340. In other words, the first end of the channel 320 contacts the source structure 310, and the second end of the channel 320 contacts the drain structure 340. The channel 320 includes a P-type silicon semiconductor doped at a relatively low concentration or an N-type silicon semiconductor doped at a relatively low concentration.

[0084] The gate structure 330 includes a gate insulating film 331 covering the channel 320 between the source structure 310 and the drain structure 340, and a gate electrode 332 covering the gate insulating film 331. The gate insulating film 331 is disposed to protrude from the upper surface of the substrate 301 so as to cover three sides of the channel 320, in other words, both side surfaces and the upper surface of the channel 320. Also, the gate electrode 332 is disposed to protrude from the upper surface of the substrate 301 so as to cover three sides of the gate insulating film 331, in other words, both side surfaces and the upper surface of the gate insulating film 331.

[0085] The source structure 310 includes a semiconductor layer 311, a source electrode 314 disposed within the semiconductor layer 311, a second silicide layer 313 disposed within the semiconductor layer 311 so as to surround the source electrode 314, and a first silicide layer 312 including a first silicide disposed within the semiconductor layer 311 so as to surround the second silicide layer 313. Similarly, the drain structure 340 includes a semiconductor layer 341, a drain electrode 344 disposed within the semiconductor layer 341, a second silicide layer 343 disposed within the semiconductor layer 341 so as to surround the drain electrode 344, and a first silicide layer 342 disposed within the semiconductor layer 341 so as to surround the second silicide layer 343.

[0086] The semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340 are arranged to protrude along the Z direction from the upper surface of the substrate 301. The semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340 include a relatively highly doped N-type semiconductor or a relatively highly doped P-type semiconductor. A part of the semiconductor layer 311 of the source structure 310 and a part of the semiconductor layer 341 of the drain structure 340 that are connected to the channel 320 extend in the Y direction. A part of the semiconductor layer 311 of the source structure 310 and a part of the semiconductor layer 341 of the drain structure 340 that are connected to the channel 320 may have the same width as the X-direction width of the channel 320. Also, another part of the semiconductor layer 311 of the source structure 310 and another part of the semiconductor layer 341 of the drain structure 340 that face the channel 320 may be larger than the width of the channel 320.

[0087] FIG. 19 is a cross-sectional view schematically showing the structure of the source structure 310 shown in FIG. 18, and schematically shows a cross-section of the source structure 310 cut in the A-A' direction. Referring to FIG. 19, the source electrode 314 can have a bar shape extending in the Z direction different from the direction in which the channel 320 extends. The source electrode 314 includes a first portion 314a located inside the semiconductor layer 311 and a second portion 314b protruding along the Z direction on the upper surface of the semiconductor layer 311. The second silicide layer 313 is disposed between the semiconductor layer 311 and the first portion 314a of the source electrode 314 so as to surround the first portion 314a of the source electrode 314. The first silicide layer 312 is disposed between the semiconductor layer 311 and the second silicide layer 313 so as to surround the second silicide layer 313. On the upper surface of the semiconductor layer 311, the second portion 314b of the source electrode 314 covers at least a part of the second silicide layer 313. For this reason, the diameter of the second portion 314b of the source electrode 314 is larger than the diameter of the first portion 314a. The structure of the source structure 310 described above is equally applicable to the drain structure 340.

[0088] When the field effect transistor 300 shown in FIGS. 18 and 19 is made to correspond to the semiconductor element 10 shown in FIG. 1, the semiconductor layer 11 can include the semiconductor layer 311 of the source structure 310 and the semiconductor layer 341 of the drain structure 340, the first silicide layer 12 can include the first silicide layer 312 of the source structure 310 and the first silicide layer 342 of the drain structure 340, the second silicide layer 13 can include the second silicide layer 313 of the source structure 310 and the second silicide layer 343 of the drain structure 340, and the metal layer 14 can include the source electrode 314 of the source structure 310 and the drain electrode 344 of the drain structure 340.

[0089] In FIGS. 18 and 19, the structure of a FinFET is exemplarily described. However, the source structure 310 and the drain structure 340 shown in FIGS. 18 and 19 may also be applied to, for example, GAAFET (gate-all-around FET) or MBCFET (multi bridge channel FET) in addition to FinFETs.

[0090] Further, the semiconductor device according to the exemplary embodiment may also be applied to a vertical structure type semiconductor device in which a metal layer is bonded to the side surface of a silicon semiconductor layer.

[0091] The semiconductor device or the field effect transistor described above may be used, for example, in a display driving integrated circuit, a CMOS inverter, a CMOS SRAM device, a CMOS NAND circuit, and / or other various electronic devices.

[0092] FIG. 20 is a schematic block diagram of a display driving integrated circuit (DDI) 500 and a display device 520 including the DDI 500 according to an exemplary embodiment. Referring to FIG. 19, the DDI 500 includes a controller 502, a power supply circuit 504, a driver block 506, and a memory block 508. The controller 502 receives and decodes commands applied from a main processing unit (MPU) 522, and controls each block of the DDI 500 to perform operations according to the commands. The power supply circuit 504 generates a driving voltage in response to the control of the controller 502. The driver block 506 drives a display panel 524 using the driving voltage generated by the power supply circuit 504 in response to the control of the controller 502. The display panel 524 is, for example, a liquid crystal display panel, an organic light emitting device (OLED) display panel, or a plasma display panel. The memory block 508 is a block that temporarily stores commands input to the controller 502 or control signals output from the controller 502, or stores necessary data, and includes memories such as a RAM and a ROM. The power supply circuit 504 and the driver block 506 include semiconductor elements or field effect transistors according to the exemplary embodiments described above with reference to FIGS. 1 to 19.

[0093] FIG. 21 is a circuit diagram of a CMOS inverter 600 according to an exemplary embodiment. Referring to FIG. 21, the CMOS inverter 600 includes a CMOS transistor 610. The CMOS transistor 610 includes a PMOS (positive-Channel Metal-Oxide Semiconductor) transistor 620 and an NMOS (negative-channel metal oxide semiconductor) transistor 630 connected between a power supply terminal Vdd and a ground terminal. The CMOS transistor 610 includes semiconductor elements or field effect transistors according to the exemplary embodiments described above with reference to FIGS. 1 to 19.

[0094] FIG. 22 is a circuit diagram of a CMOS SRAM element 700 according to an exemplary embodiment. Referring to FIG. 22, the CMOS SRAM element 700 includes a pair of drive transistors 710. The pair of drive transistors 710 each consists of a PMOS transistor 720 and an NMOS transistor 730 connected between a power supply terminal Vdd and a ground terminal. The CMOS SRAM element 700 further includes a pair of transmission transistors 740. The source of the transmission transistor 740 is cross-connected to the common node of the PMOS transistor 720 and the NMOS transistor 730 that constitute the drive transistor 710. The power supply terminal Vdd is connected to the source of the PMOS transistor 720, and the ground terminal is connected to the source of the NMOS transistor 730. A word line WL is connected to the gates of the pair of transmission transistors 740, and a bit line BL and an inverted bit line are respectively connected to the drains of each of the pair of transmission transistors 740. At least one of the drive transistor 710 and the transmission transistor 740 of the CMOS SRAM element 700 includes a semiconductor element or a field effect transistor according to the exemplary embodiments described above with reference to FIGS. 1 to 19.

[0095] FIG. 23 is a circuit diagram of a CMOS NAND circuit 800 according to an exemplary embodiment. Referring to FIG. 23, the CMOS NAND circuit 800 includes a pair of CMOS transistors to which different input signals are transmitted. The CMOS NAND circuit 800 includes a semiconductor element or a field effect transistor according to the exemplary embodiments described above with reference to FIGS. 1 to 19.

[0096] FIG. 24 is a block diagram showing an electronic device 900 according to an exemplary embodiment. Referring to FIG. 24, the electronic device 900 includes a memory 910 and a memory controller 920. The memory controller 920 controls the memory 910 to read data from / write data to the memory 910 in response to requests from a host 930. At least one of the memory 910 and the memory controller 920 includes a semiconductor element or a field effect transistor according to the exemplary embodiments described above with reference to FIGS. 1 to 19.

[0097] FIG. 25 is a block diagram of an electronic device 1000 according to an exemplary embodiment. Referring to FIG. 25, the electronic device 1000 constitutes a wireless communication device or a device capable of transmitting and / or receiving information in a wireless environment. The electronic device 1000 includes a controller 1010, an input / output device (I / O) 1020, a memory 1030, and a wireless interface 1040, which are interconnected via a bus 1050.

[0098] The controller 1010 includes at least one of a microprocessor, a digital signal processor, or a processing device similar thereto. The input / output device 1020 includes at least one of a keypad, a keyboard, or a display. The memory 1030 is used to store instructions executed by the controller 1010. For example, the memory 1030 is used to store user data. The electronic device 1000 uses the wireless interface 1040 to transmit / receive data via a wireless communication network. The wireless interface 1040 includes an antenna and / or a wireless transceiver. In some embodiments, the electronic device 1000 is used for the communication interface protocol of a third-generation communication system, such as CDMA (code division multiple access), GSM (global system for mobile communications), NADC (north American digital cellular), E-TDMA (extended-time division multiple access), and / or WCDMA (registered trademark) (wide band code division multiple access). The electronic device 1000 includes a semiconductor element or a field effect transistor according to the exemplary embodiments described above with reference to FIGS. 1 to 18.

[0099] The semiconductor element or the field effect transistor according to the exemplary embodiments can exhibit good electrical performance with a super-small structure, is applied to integrated circuit elements, and can achieve miniaturization, low power consumption, and high performance.

[0100] The above-described embodiments are merely exemplary, and those skilled in the art can make various modifications and equivalent other embodiments therefrom. Therefore, the true technical protection scope according to the exemplary embodiments must be determined by the technical idea of the invention described in the following claims.

Description of Reference Numerals

[0101] 10: Semiconductor element 11: Semiconductor layer 12: First silicide layer 13: Second silicide layer 14: Metal layer

Claims

1. A semiconductor layer containing silicon, A first silicide layer located on the semiconductor layer, A second silicide layer located on the first silicide layer, containing titanium and having a crystal structure, The first silicide layer contains a metal different from titanium, The second silicide layer is a semiconductor device including TiSi having a C54 crystal structure. ２ ​

2. The semiconductor device according to claim 1, wherein the first silicide layer contains at least one of hafnium silicide, zirconium silicide, nickel silicide, and cobalt silicide.

3. The semiconductor device according to claim 1 or 2, wherein the first silicide layer has a thickness in the range of 3 Å to 30 Å.

4. The semiconductor device according to claim 1 or 2, wherein the first silicide layer has a crystal structure.

5. The semiconductor device according to claim 1 or 2, wherein the second silicide layer has a thickness in the range of 5 Å or more and 70 Å or less.

6. The first silicide layer is ZrSi, ZrSi ２ , Zr ５ Si ３ , and Zr ３ Si ２ The semiconductor device according to claim 1 or 2, comprising at least one of them.

7. The semiconductor device according to claim 1 or 2, wherein the second silicide layer contains a Schottky barrier of 0.7 eV or less.

8. The semiconductor device according to claim 1 or 2, further including a metal layer located on the second silicide layer.

9. The metal layer contains magnesium (Mg), aluminum (Al), scandium (Sc), titanium (Ti), vanadium (V), chromium (Cr), manganese (Mn), nickel (Ni), copper (Cu), zinc (Zn), gallium (Ga), zirconium (Zr), niobium (Nb), molybdenum (Mo), lead (Pd), silver (Ag), cadmium (Cd), indium (In), tin (Sn), lanthanum (La), hafnium (Hf), tantalum (Ta), tungsten (W), iridium (Ir), platinum (Pt), gold (Au), bismuth (Bi), or any combination thereof. The semiconductor device according to claim 8.

10. The metal layer includes a source electrode located on one side of the channel layer and a drain electrode located opposite to the other side of the channel layer, The second silicide layer includes a second - 1 silicide layer located between the source electrode and the channel layer, and a second - 2 silicide layer located between the drain electrode and the channel layer. The first silicide layer includes a first - 1 silicide layer positioned between the second - 1 silicide layer and the channel layer, and a first - 2 silicide layer positioned between the second - 2 silicide layer and the channel layer. The semiconductor device according to claim 8.

11. The semiconductor layer includes a single - crystal or poly - crystal structure. The semiconductor device according to claim 1 or 2.

12. The first silicide layer is an undoped layer. The semiconductor device according to claim 1 or 2.

13. The second silicide layer is an undoped layer. The semiconductor device according to claim 1 or 2.

14. The first silicide layer is positioned so as to be in direct contact with the semiconductor layer. The semiconductor device according to claim 1 or 2.

15. The first silicide layer is positioned so as to be in direct contact with the second silicide layer. The semiconductor device according to claim 1 or 2.

16. The semiconductor layer, a well region doped with a first conductivity type, and a source region and a drain region doped with a second conductivity type that is electrically opposite to the first conductivity type. The semiconductor device according to claim 1 or 2.

17. A gate electrode and, a gate insulating film positioned on the gate electrode. Further comprising, the semiconductor layer includes a channel layer positioned on the gate insulating film. The semiconductor device according to claim 1 or 2.

18. The semiconductor layer includes a channel layer, The semiconductor device, a gate insulating film positioned on the upper surface of the channel layer, and a gate electrode positioned on the gate insulating film. Further comprising. The semiconductor device according to claim 1 or 2.

19. Forming a semiconductor layer containing silicon, Forming a first silicide layer on the semiconductor layer, Forming a second silicide layer containing titanium on the first silicide layer, Crystallizing the second silicide layer. Comprising, The first silicide layer contains a metal different from titanium, The second silicide layer has a TiSi having a C54 crystal structure ２ A method for manufacturing a semiconductor device, including the same.

20. The first silicide layer is ZrSi, ZrSi ２ , Zr ５ Si ３ , and Zr ３ Si ２ The method for manufacturing a semiconductor device according to claim 19, comprising at least one of them.

21. The second silicide layer has a C54 crystal structure in the range of 200 to 400 °C. The manufacturing method of the semiconductor device according to claim 19 or 20.

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