Semiconductor device

Abstract

To suppress breakage of an insulating film.SOLUTION: An insulating film 120 includes a tilt part 122 whose thickness gradually increases from an active region Ra side to a side opposite to the active region Ra. A corner part 121a at which the thickness of the insulating film 120 starts to increase is formed at one surface 120a on a side opposite to a semiconductor substrate 100 side. A gate electrode 109 is extracted from the active region Ra to an outer peripheral region Rb and is also disposed on the tilt part 122 in the insulating film 120. The outer peripheral region Rb of the semiconductor substrate 100 includes a part where a first semiconductor layer 102 of a first conductivity type and a second semiconductor layer 104 of a second conductivity type are stacked. The insulating film 120 is disposed on the second semiconductor layer 104. At a position corresponding to the corner part 121a in the second semiconductor layer 104, there is formed a detour layer 116 of the first conductivity type that forms a depletion layer between the detour layer and the second semiconductor layer 104.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a switching element having a gate electrode.

Background Art

[0002] Conventionally, for example, Patent Document 1 has proposed a semiconductor device including a switching element having a gate electrode. Specifically, this semiconductor device is configured using a semiconductor substrate and has an active region in which a switching element having a gate electrode is configured, and an outer peripheral region surrounding the active region. In the outer peripheral region, an insulating film is formed on one surface of the semiconductor substrate, and the gate electrode extends up to the insulating film.

[0003] Specifically, a sloped portion that gradually increases in thickness toward the side opposite to the active region side is formed in the portion of the insulating film on the active region side. The gate electrode extends along the sloped portion up to the portion where the insulating film is thick.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in such a semiconductor device, a corner portion is formed at a portion where the thickness of the sloped portion of the insulating film begins to increase. Therefore, when switching such as turning the semiconductor device from the on state to the off state is performed, a large electric field is applied to the corner portion of the insulating film, and the insulating film may be damaged.

[0006] An object of the present disclosure is to provide a semiconductor device capable of suppressing damage to the insulating film.

Means for Solving the Problem

[0007] According to one aspect of the present disclosure, there is provided a semiconductor device having an active region (Ra) in which a switching element is formed and an outer peripheral region (Rb) surrounding the outer periphery of the active region, the semiconductor device including: a semiconductor substrate (100) having the active region and the outer peripheral region; a switching element formed in the active region and having a gate electrode (109) with one direction as the longitudinal direction; and an insulating film (120) formed in the outer peripheral region. The insulating film has an inclined portion (122) whose thickness gradually increases from the active region side toward the side opposite to the active region, and a corner portion (121a) where the thickness of the insulating film starts to increase is formed on one surface (120a) opposite to the semiconductor substrate side. The gate electrode is drawn out from the active region to the outer peripheral region and is also disposed on the inclined portion of the insulating film. The outer peripheral region of the semiconductor substrate has a portion where a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer (104) of a second conductivity type are stacked. The insulating film is disposed on the second semiconductor layer, and a detour layer (116) having a first conductivity type and forming a depletion layer with the second semiconductor layer is formed at a position corresponding to the corner portion of the second semiconductor layer.

[0008] According to this, a detour layer in which a depletion layer is formed is formed in the second semiconductor layer of the outer peripheral region at a position corresponding to the corner portion. Therefore, when switching such as turning the semiconductor device from the on state to the off state is performed, the displacement current flowing therethrough flows around the detour layer. Accordingly, it is possible to suppress an increase in the electric field at the corner portion of the insulating film and suppress destruction of the insulating film.

[0009] Note that the reference numerals in parentheses attached to each component etc. show an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

[0012] (First Embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device of the present embodiment is preferably mounted on a vehicle and used for controlling various electronic components, for example.

[0013] As shown in FIG. 1, the semiconductor device of the present embodiment has an active region Ra and an outer peripheral region Rb located outside the active region Ra. A switching element as a semiconductor element is formed in the active region Ra. In the present embodiment, an example in which a vertical MOSFET is formed as the switching element will be described. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0014] More specifically, the semiconductor device of the present embodiment has a rectangular upper surface shape. The semiconductor device has an internal region including a central portion as an active region Ra, and an outer peripheral region Rb is arranged so as to surround the active region Ra. In FIG. 1, the region surrounded by the rectangle indicates the active region Ra. Further, the portion indicated by the thick solid line provided in the outer peripheral region Rb so as to surround the active region Ra in FIG. 1 shows a gate liner 13 constituted by a gate lead-out portion 109a of a gate electrode 109 described later and a gate wiring layer 113 in a vertical MOSFET. In the present embodiment, the gate liner 13 is arranged in the outer peripheral region Rb located on the outer periphery of the active region Ra.

[0015] The outer peripheral region Rb is provided with a temperature-sensitive element 11 composed of a temperature-sensitive diode or the like and a plurality of pads 12a to 12d. Each of the pads 12a to 12d is, for example, a cathode pad 12a, an anode pad 12b, a sense pad 12c, and a gate pad 12d from the left side of the drawing sheet. The semiconductor device can be electrically connected to the outside by connecting these pads 12a to 12d to bonding wires (not shown).

[0016] Next, the cross-sectional configuration of the semiconductor device will be described with reference to FIGS. 2 to 4.

[0017] The semiconductor device includes a semiconductor substrate 100, and the semiconductor substrate 100 includes an n-type substrate 101 made of a semiconductor substrate such as SiC or Si. Hereinafter, an example in which the substrate 101 is made of SiC will be described. In the present embodiment, the substrate 101 constitutes a drain region. + On the main surface of the substrate 101, an n-type drift layer 102 having a lower impurity concentration than the substrate 101 is epitaxially grown. P-type deep layers 103 are formed at predetermined intervals on the surface layer portion of the drift layer 102. A p-type base region 104 is formed on the drift layer 102 and the deep layer 103, and an n

[0018] type is formed on the base region 104. - type is formed on the base region 104.+ type source region 105 and p + type contact region 106 are formed. In this embodiment, the source region 105 is formed on a portion corresponding to the region where the deep layer 103 is not formed in the drift layer 102, and the contact region 106 is formed on a portion corresponding to the region where the deep layer 103 is formed in the drift layer 102.

[0019] In this embodiment, in this way, the semiconductor substrate 100 is composed of the substrate 101, the drift layer 102, the deep layer 103, the base region 104, the source region 105 and the contact region 106. Hereinafter, in the semiconductor substrate 100, the surface on the source region 105 and contact region 106 side is defined as one surface 100a, and the surface on the substrate 101 side is defined as the other surface 100b for explanation. In this embodiment, the drift layer 102 corresponds to the first semiconductor layer, the base region 104 corresponds to the second semiconductor layer, and the source region 105 corresponds to the third semiconductor layer.

[0020] On the semiconductor substrate 100, a gate trench 107 is formed from the one surface 100a side. Specifically, the gate trench 107 is formed so as to penetrate the source region 105 and the base region 104 and reach the drift layer 102. For this reason, the above-mentioned source region 105 and base region 104 are formed so as to be in contact with the side surface of the gate trench 107. Also, the above-mentioned contact region 106 is arranged on the side opposite to the gate trench 107 with the source region 105 interposed therebetween.

[0021] Note that the gate trench 107 is formed in a linear layout with the horizontal direction in the plane of FIG. 2 as the width direction, one direction normal to the plane of the paper as the longitudinal direction, and the vertical direction in the plane of the paper as the depth direction. Also, in FIG. 2, only one gate trench 107 is shown, but actually, a plurality of gate trenches 107 are arranged at equal intervals in the horizontal direction in the plane of the paper, and are arranged so as to be sandwiched between the deep layers 103 and are in a stripe shape.

[0022] The portion of the base region 104 located on the side surface of the gate trench 107 serves as a channel region that connects the source region 105 and the drift layer 102 during the operation of the vertical MOSFET. A gate insulating film 108 is formed on the inner wall surface of the gate trench 107 including this channel region. A gate electrode 109 made of doped Poly-Si is formed on the surface of the gate insulating film 108, and the gate insulating film 108 and the gate electrode 109 are embedded in the gate trench 107. Therefore, the gate electrode 109 also extends in the same one direction as the longitudinal direction of the gate trench 107. And with such a structure, a trench gate structure is configured.

[0023] As shown in FIG. 3, the trench gate structure extends in the left-right direction of the paper surface of FIG. 1. And as shown in FIG. 3, the trench gate structure is formed so as to protrude from the active region Ra to the outer peripheral region Rb. Note that the source region 105 is formed so as to be in contact with the side surface of the gate trench 107, but is formed only in the active region Ra and not in the outer peripheral region Rb. Therefore, the channel region is formed only within the active region Ra.

[0024] And at least on the side of the square-shaped active region Ra located at the tip of the trench gate structure, as shown in FIG. 3, a field insulating film 110 is formed at a position away from both tips of the gate trench 107 on the surface of the base region 104. The field insulating film 110 has a shape with an opening on the active region Ra side and has an end portion extending in a direction intersecting the longitudinal direction of the trench gate structure. That is, the field insulating film 110 has a shape in which the portions located on the left and right of the paper surface of FIG. 1 among the open ends are opposed to the tips of the respective trench gate structures. And although not shown in FIG. 3, the open ends of the field insulating film 110 are formed along the upper and lower sides of the square-shaped active region Ra in FIG. 1.

[0025] The field insulating film 110 is thickened so that it is difficult to be broken even when a high voltage is applied. And the gate insulating film 108 formed in the gate trench 107 is also formed outside the gate trench 107 and extends up to the surface of the field insulating film 110 in this embodiment.

[0026] Specifically, the field insulating film 110 has an inclined portion 110a whose end on the active region Ra side, that is, the trench gate structure side, is inclined obliquely. In this embodiment, the inclined portion 110a of the field insulating film 110 has a structure that gradually thickens from the active region Ra side toward the outer peripheral region Rb side. And in this embodiment, the gate insulating film 108 is formed on the surface of the field insulating film 110 including this inclined portion 110a.

[0027] The gate electrode 109 is drawn out not only inside the gate trench 107 but also from both longitudinal ends of the gate trench 107 to the outside of the gate trench 107 and to the position where the thickness of the field insulating film 110 is thickened, similar to the gate insulating film 108. And the portion of the gate electrode 109 drawn out to the outside of the gate trench 107 constitutes a gate lead-out portion 109a that is a part of the gate liner 13.

[0028] Specifically, the gate lead-out portion 109a of the gate electrode 109 is formed on the field insulating film 110 including the inclined portion 110a and is arranged so as to ride up to the thickened field insulating film 110. For this reason, the inclined portion 110a of the field insulating film 110 is positioned under the gate electrode 109.

[0029] Here, if the inclined portion 110a is not formed at the end of the field insulating film 110, at the step portion at the end of the field insulating film 110, the gate electrode 109 tends to become thin and step discontinuities are likely to occur. However, in the present embodiment, since the inclined portion 110a is formed at the end of the field insulating film 110, it is possible to suppress the gate electrode 109 from being step-discontinuous due to the step at the end of the field insulating film 110. In particular, the gate electrode 109 is likely to have step discontinuities when its thickness becomes thinner than that of the field insulating film 110. Even in such a case, the configuration of the present embodiment can suppress the occurrence of step discontinuities.

[0030] Note that since the gate insulating film 108 can be patterned as appropriate, it is not necessarily formed on the surface of the field insulating film 110. For example, the gate insulating film 108 may have a structure that terminates at the end of the field insulating film 110 and may not be disposed on the field insulating film 110. Also, the gate insulating film 108 may be formed on the base region 104, and the field insulating film 110 may be formed on the gate insulating film 108. That is, in the outer peripheral region Rb, the gate insulating film 108 may be disposed between the field insulating film 110 and the semiconductor substrate 100.

[0031] And in the present embodiment, as shown in FIGS. 3 and 4, in the outer peripheral region Rb, an n + -type bypass layer 116 is formed on the one surface 100a side of the semiconductor substrate 100. Hereinafter, in the outer peripheral region Rb, the insulating film located between the one surface 100a of the semiconductor substrate 100 and the gate electrode 109 will be simply described as the insulating film 120. Also, the surface of the insulating film 120 opposite to the one surface 100a side of the semiconductor substrate 100 will be described as the one surface 120a.

[0032] In addition, in the present embodiment, as described above, the gate insulating film 108 is also formed on the surface of the field insulating film 110. Therefore, the insulating film 120 of the present embodiment is configured to include the field insulating film 110 and the gate insulating film 108, and one surface 120a is formed of the gate insulating film 108. Further, FIG. 4 is an enlarged view of the region IV in FIG. 3, but for easy understanding, only the semiconductor substrate 100, the insulating film 120, and the gate electrode 109 are shown.

[0033] First, as described above, the insulating film 120 is configured such that the inclined portion 110a is formed at the end of the field insulating film 110, and the thickness gradually increases from the active region Ra side. Therefore, an inclined portion 122 corresponding to the inclined portion 110a is formed on one surface 120a of the insulating film 120, and a corner portion 121a is formed at a portion where the thickness begins to increase.

[0034] Then, a bypass layer 116 is formed at a position corresponding to the corner portion 121a on the one surface 100a side of the semiconductor substrate 100. The bypass layer 116 is formed at a position corresponding to the corner portion 121a and is formed along the upper and lower sides of the active region Ra having a rectangular shape in FIG. 1. Although not particularly shown, the bypass layer 116 is connected to an upper electrode 112 to be described later at a predetermined location and is maintained at the same potential as the source region 105. Further, as will be specifically described later, the bypass layer 116 is formed such that a depletion layer is formed between the bypass layer 116 and the base region 104. In the present embodiment, the bypass layer 116 is formed with a lower impurity concentration than the source region 105.

[0035] As shown in FIGS. 2 and 3, an interlayer insulating film 111 is formed on the surfaces of a source region 105, a contact region 106, and a gate electrode 109 including a gate lead-out portion 109a of a semiconductor device. On the interlayer insulating film 111, an upper electrode 112 as a source electrode shown in FIG. 2 and a gate wiring layer 113 shown in FIG. 3 are formed as conductor patterns. Here, the gate wiring layer 113 is a part constituting a part of the gate liner 13 described above. In the present embodiment, the gate liner 13 is configured to include the gate wiring layer 113 and the gate lead-out portion 109a. Further, contact holes 111a and 111b are formed in the interlayer insulating film 111. As shown in FIG. 2, the upper electrode 112 is electrically connected to the source region 105 and the contact region 106 through the contact hole 111a. As shown in FIG. 3, the gate wiring layer 113 is electrically connected to the gate lead-out portion 109a, that is, the gate electrode 109 through the contact hole 111b.

[0036] Further, in the semiconductor device, an outer peripheral region Rb is covered with a protective film 115. In the protective film 115, an opening in which a portion corresponding to the upper electrode 112 is removed and an opening in which positions corresponding to the respective pads 12a to 12d are removed are formed.

[0037] A lower electrode 114 as a drain electrode electrically connected to the substrate 101 is formed on the other surface 100b side of the semiconductor substrate 100. The semiconductor device of the present embodiment is configured by forming a vertical MOSFET having an n-channel type inversion trench gate structure in this way.

[0038] The above is the configuration of the semiconductor device in the present embodiment. In the present embodiment, the n-type corresponds to the first conductivity type and the p-type corresponds to the second conductivity type. Next, while explaining the operation of the semiconductor device, a more detailed structure will be described.

[0039] In the semiconductor device as described above, when a voltage higher than the upper electrode 112 is applied to the lower electrode 114, the PN junction formed between the base region 104 and the drift layer 102 becomes in a reverse conduction state and a depletion layer is formed. Then, when a gate voltage at a low level (for example, 0 V) less than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 109, no current flows between the upper electrode 112 and the lower electrode 114.

[0040] To turn on the semiconductor device (i.e., vertical MOSFET), with a voltage higher than the upper electrode 112 applied to the lower electrode 114, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 109. As a result, an inversion layer is formed in a portion of the base region 104 in contact with the gate trench 107 where the gate electrode 109 is disposed. Then, electrons are supplied from the source region 105 to the drift layer 102 through the inversion layer, and a current flows between the upper electrode 112 and the lower electrode 114, putting the device in an on state.

[0041] To turn off the semiconductor device, the gate voltage applied to the gate electrode 109 is made less than the threshold voltage Vth. As a result, the inversion layer formed in the base region 104 disappears and the semiconductor device enters an off state.

[0042] At this time, in the semiconductor device as in this embodiment, a rapid voltage change (dV / dt) occurs in the lower electrode 114, and a displacement current I flows to charge and discharge the capacitance C between the drift layer 102 and the base region 104.

[0043] Here, the configuration of the active region Ra and the like is the same as that of the first embodiment. As shown in FIG. 5, in the outer peripheral region Rb, a semiconductor device in which the bypass layer 116 is not formed in a portion corresponding to the corner portion 121a of one surface 100a of the semiconductor substrate 100 is used as a comparative example semiconductor device. Note that FIG. 5 is a cross-sectional view including a portion corresponding to FIG. 4 in the semiconductor device of the comparative example.

[0044] In this case, in the semiconductor device of the comparative example, as shown in FIG. 5, the displacement current I in the outer peripheral region Rb flows under the insulating film 120 so as to be discharged from the contact region 106 of the active region Ra. At this time, assuming that the displacement current is I and the resistance value of the semiconductor in the portion where the displacement current I flows is Rs, a voltage ΔV represented by the following mathematical formula 1 is applied to the insulating film 120.

[0045] (Equation 1) ΔV = I × Rs Note that the displacement current I is represented by the following mathematical formula 2, where C is the junction capacitance between the drift layer 102 and the base region 104 and Irr is the recovery current.

[0046] (Equation 2) I = C × dV / dt (+Irr) In the semiconductor device of the comparative example, an electric field is likely to concentrate on the corner portion 121a on the one surface 120a side of the insulating film 120, and there is a possibility that the insulating film 120 at this corner portion 121a is broken because it is thin. That is, in the semiconductor device of the comparative example, the dV / dt withstand voltage may be low.

[0047] Therefore, in the present embodiment, on the one surface 100a side of the semiconductor substrate 100, a bypass layer 116 that forms a depletion layer with the base region 104 is formed at a position corresponding to the corner portion 121a. As a result, the displacement current I in the semiconductor device of the present embodiment flows around the bypass layer 116 as shown in FIG. 6. Therefore, it is possible to suppress the increase in the electric field at the corner portion 121a.

[0048] Specifically, the bypass layer 116 has its length and depth in the width direction along the plane direction of the semiconductor substrate 100 adjusted so that a depletion layer is formed between the bypass layer 116 and the base region 104. Here, in the present embodiment, among the directions along the plane direction of the semiconductor substrate 100, the direction from the active region Ra side to the outer peripheral region Rb side is defined as the width direction, and the direction along the thickness direction of the semiconductor substrate 100 is defined as the depth direction. In FIG. 4, the left - right direction of the paper surface is the width direction, and the up - down direction of the paper surface is the depth direction. Further, in the present embodiment, with respect to the virtual line K along the normal direction to the plane direction of the semiconductor substrate 100 (hereinafter also simply referred to as the normal direction) passing through the corner portion 121a, the width from the virtual line K to the end on the active region Ra side in the bypass layer 116 is defined as the first width W1, and the width from the virtual line K to the end on the side opposite to the active region Ra side is defined as the second width W2. The depth of the bypass layer 116 is defined as depth d. And the depletion layer width Wdepl is represented by the following Equation 3.

[0049]

Equation

[0050] And in the present embodiment, the bypass layer 116 has the first width W1 equal to the depletion layer width Wdepl derived from the above Equation 3. Also, the second width W2 is made longer than the depletion layer width Wdepl and is formed substantially over the entire position facing the inclined portion 122. The depth d is equal to the depletion layer width Wdepl derived from the above Equation 3. Therefore, when the semiconductor device is off, a depletion layer is formed by the bypass layer 116. Accordingly, the displacement current I flows around the bypass layer 116, and the breakdown of the insulating film 120 due to the increase in the electric field at the corner portion 121a of the insulating film 120 is suppressed.

[0051] According to the present embodiment described above, a bypass layer 116 in which a depletion layer is formed between the base region 104 is formed at a position corresponding to the corner portion 121a on the semiconductor substrate 100. Therefore, by flowing the displacement current I around the bypass layer 116, it is possible to suppress an increase in the electric field at the corner portion 121a of the insulating film 120 and suppress the insulating film 120 from being broken.

[0052] (1) In the present embodiment, the bypass layer 116 has a first width W1 and a depth d, each of which is the depletion layer width Wdepl. Therefore, the resistance of the base region 104 can be made smaller than in the case where the first width W1 is wider than the depletion layer width Wdepl or the depth d is deeper than the depletion layer width Wdepl. Therefore, the switching speed can be increased.

[0053] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in the configuration of the bypass layer 116. Since the other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0054] In the semiconductor device of this embodiment, as shown in FIG. 7, the second width W2 in the bypass layer 116 is adjusted. Specifically, the second width W2 is the depletion layer width Wdepl derived from the above formula 3, similar to the first width W1.

[0055] According to the present embodiment described above, since the bypass layer 116 is formed on the semiconductor substrate 100, the same effects as those of the first embodiment can be obtained.

[0056] (1) In the present embodiment, the bypass layer 116 has a second width W2 that is the depletion layer width Wdepl. Therefore, compared with the first embodiment, the second width W2 is shortened. Therefore, according to the present embodiment, compared with the first embodiment, the base region 104 becomes wider and the resistance of the base region 104 can be made smaller. Therefore, the switching speed can be further increased.

[0057] (Third Embodiment) A third embodiment will be described. This embodiment is the same as the second embodiment except that the impurity concentration of the bypass layer 116 is changed. Since other aspects are the same as those of the second embodiment, the description thereof will be omitted here.

[0058] As shown in FIG. 8, in the semiconductor device of this embodiment, the impurity concentration of the bypass layer 116 is set to be equal to or higher than the impurity concentration of the source region 105. In FIG. 8, the bypass layer 116 is shown as an n with a higher impurity concentration than the source region 105. ++ shown as.

[0059] According to the embodiment described above, since the bypass layer 116 is formed on the semiconductor substrate 100, the same effects as those of the first embodiment can be obtained.

[0060] (1) In this embodiment, the impurity concentration of the bypass layer 116 is made higher than that of the source region 105. Therefore, compared with the first and second embodiments, the depletion layer width Wdepl derived from the above formula 3 becomes shorter as the impurity concentration of the bypass layer 116 increases. Thus, it is easier to shorten the first width W1 and the second width W2 and to make the depth d shallower. That is, it is easier to make the bypass layer 116 even smaller. For this reason, the switching speed can be further increased.

[0061] (Other embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and variations within an equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one element, or less than one element thereof, fall within the scope and spirit of the present disclosure.

[0062] For example, in each of the above embodiments, a vertical MOSFET is taken as an example of the switching element provided in the active region Ra. However, the switching element may be a vertical IGBT or the like, or may be configured by combining a plurality of types of elements. Further, the switching element may have a planar type instead of a trench gate structure. Furthermore, in each of the above embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0063] And in each of the above embodiments, an example in which SiC or Si is used as the semiconductor substrate 100 has been described. However, the semiconductor substrate 100 may be configured by, for example, a gallium nitride substrate or the like. However, SiC has a high operating voltage, and the voltage applied to the insulating film 120 is particularly likely to be high. For this reason, each of the above embodiments is particularly useful when the semiconductor substrate 100 is made of SiC.

[0064] Furthermore, in each of the above embodiments, the inclined portion 110a formed in the field insulating film 110 may be formed to have a stepped increase in thickness instead of a gradual increase in thickness.

[0065] Also, in each of the above embodiments, the insulating film 120 constituting the inclined portion 122 may be composed only of the field insulating film 110.

[0066] And in the first embodiment, the bypass layer 116 may have a first width W1 wider than the depletion layer width Wdepl, or a width d deeper than the depletion layer width Wdepl.

Description of Reference Numerals

[0067] 100 Semiconductor substrate 109 Gate electrode 120 Insulating film 120a One surface 121a Corner 122 Inclined portion 116 Bypass layer

Claims

1. A semiconductor device having an active region (Ra) in which a switching element is formed and an outer peripheral region (Rb) surrounding the outer periphery of the active region, a semiconductor substrate (100) having the active region and the outer peripheral region, the switching element formed in the active region and having a gate electrode (109) with one direction as the longitudinal direction, and an insulating film (120) formed in the outer peripheral region, wherein the insulating film has an inclined portion (122) whose thickness gradually increases from the active region side toward the side opposite to the active region, and a corner portion (121a) where the thickness of the insulating film starts to increase is formed on one surface (120a) on the side opposite to the semiconductor substrate side, the gate electrode is drawn out from the active region to the outer peripheral region and is also disposed on the inclined portion of the insulating film, the outer peripheral region of the semiconductor substrate has a portion where a first semiconductor layer (102) of a first conductivity type and a second semiconductor layer (104) of a second conductivity type are laminated, the insulating film is disposed on the second semiconductor layer, and a bypass layer (116) having a first conductivity type and forming a depletion layer with the second semiconductor layer is formed at a position corresponding to the corner portion in the second semiconductor layer.

2. The semiconductor device according to claim 1, wherein the width (W1) of the bypass layer from the virtual line (K) along the normal direction to the surface direction of the semiconductor substrate through the corner portion to the end on the active region side is the depletion layer width (W depl) derived based on the impurity concentrations of the second semiconductor layer and the bypass layer.

3. The semiconductor device according to claim 1, wherein the width (W2) of the bypass layer from the virtual line (K) along the normal direction to the surface direction of the semiconductor substrate through the corner portion to the end on the side opposite to the active region side is the depletion layer width (W depl) derived based on the impurity concentrations of the second semiconductor layer and the bypass layer.

4. The semiconductor device according to claim 1, wherein the depth (d) of the bypass layer is the depletion layer width (W depl) derived based on the impurity concentrations of the second semiconductor layer and the bypass layer.

5. The switching element includes the first semiconductor layer, the second semiconductor layer disposed on the first semiconductor layer, a third semiconductor layer (105) of a first conductivity type formed on a surface layer portion of the second semiconductor layer, and a gate electrode disposed on a surface of the second semiconductor layer sandwiched between the first semiconductor layer and the third semiconductor layer. The semiconductor device according to any one of claims 1 to 4, wherein the bypass layer has an impurity concentration equal to or higher than the impurity concentration of the third semiconductor layer.

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