Semiconductor device

Abstract

To suppress breakage of an insulating film.SOLUTION: An insulating film 120 includes a tilt part 122 whose thickness gradually increases from an active region Ra side to a side opposite to the active region Ra. A one-surface side corner part 121a at which the thickness of the insulating film 120 starts to increase is formed at one surface 120a on a side opposite to a semiconductor substrate 100 side. A gate electrode 109 is extracted from the active region Ra to an outer peripheral region Rb and is also disposed on the tilt part 122 in the insulating film 120. The semiconductor substrate 100 includes a concave part 130 having an opening end at a position corresponding to the one-surface side corner part 121a. In addition, the insulating film 120 is also disposed at the concave part 130 so as to cover the opening end and includes the other-surface side corner part 121b formed of a part covering the opening end on the other surface 120b side of the semiconductor substrate side 100.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device including a switching element having a gate electrode.

Background Art

[0002] Conventionally, for example, Patent Document 1 has proposed a semiconductor device including a switching element having a gate electrode. Specifically, this semiconductor device is configured using a semiconductor substrate and has an active region in which a switching element having a gate electrode is formed, and an outer peripheral region surrounding the active region. In the outer peripheral region, an insulating film is formed on one surface of the semiconductor substrate, and the gate electrode extends up to the insulating film.

[0003] Specifically, a sloped portion that gradually increases in thickness toward the side opposite to the active region side is formed in the portion of the insulating film on the active region side. The gate electrode extends along the sloped portion up to the portion where the insulating film is thick.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in such a semiconductor device, a corner is formed at a portion where the thickness of the sloped portion of the insulating film begins to increase. Therefore, when switching such as turning the semiconductor device from the on state to the off state is performed, a large electric field is applied to the corner of the insulating film, and the insulating film may be damaged.

[0006] An object of the present disclosure is to provide a semiconductor device capable of suppressing damage to the insulating film.

Means for Solving the Problem

[0007] According to one aspect of the present disclosure, there is provided a semiconductor device having an active region (Ra) in which a switching element is formed and an outer peripheral region (Rb) surrounding the outer periphery of the active region, the semiconductor device including: a semiconductor substrate (100) having the active region and the outer peripheral region; a switching element formed in the active region and having a gate electrode (109) with one direction as the longitudinal direction; and an insulating film (120) formed in the outer peripheral region. The insulating film has an inclined portion (122) whose thickness gradually increases from the active region side toward the side opposite to the active region, and a one-sided corner portion (121a) where the thickness of the insulating film starts to increase is formed on one surface (120a) on the side opposite to the semiconductor substrate side. The gate electrode is drawn out from the active region to the outer peripheral region and is also disposed on the inclined portion of the insulating film. The semiconductor substrate has a recess (130) having an open end at a position corresponding to the one-sided corner portion, and further, the insulating film is also disposed in the recess so as to cover the open end, and has an other-sided corner portion (121b) formed by a portion covering the open end on the other surface (120b) side of the semiconductor substrate side.

[0008] According to this, on the insulating film, an other-sided corner portion is formed at a position corresponding to the one-sided corner portion. For this reason, it is possible to increase the location where the electric field concentrates in the insulating film, and it is possible to reduce the maximum electric field applied to the insulating film, thereby suppressing the breakdown of the insulating film.

[0009] The reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13A

Figure 13B

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals and described.

[0012] (First Embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is preferably mounted on a vehicle, for example, and used to control various electronic components.

[0013] As shown in FIG. 1, the semiconductor device of the present embodiment has an active region Ra and an outer peripheral region Rb located outside the active region Ra. A switching element as a semiconductor element is formed in the active region Ra. In the present embodiment, an example in which a vertical MOSFET is formed as the switching element will be described. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor.

[0014] More specifically, the semiconductor device of the present embodiment has a square upper surface shape. The internal region including the central portion of the semiconductor device is the active region Ra, and the outer peripheral region Rb is arranged so as to surround the active region Ra. In FIG. 1, the region surrounded by the square shape indicates the active region Ra. Further, the portion indicated by the thick solid line provided in the outer peripheral region Rb so as to surround the active region Ra in FIG. 1 shows the gate liner 13 composed of a gate lead-out portion 109a of a gate electrode 109 described later in the vertical MOSFET and a gate wiring layer 113. In the present embodiment, the gate liner 13 is arranged in the outer peripheral region Rb located on the outer periphery of the active region Ra.

[0015] The outer peripheral region Rb is provided with a temperature-sensitive element 11 composed of a temperature-sensitive diode or the like and a plurality of pads 12a to 12d. Each of the pads 12a to 12d is, for example, a cathode pad 12a, an anode pad 12b, a sense pad 12c, and a gate pad 12d from the left side of the drawing. The semiconductor device can be electrically connected to the outside by connecting these pads 12a to 12d to bonding wires (not shown).

[0016] Next, the cross-sectional structure of the semiconductor device will be described with reference to FIGS. 2 to 4.

[0017] The semiconductor device includes a semiconductor substrate 100, and the semiconductor substrate 100 is an n-type semiconductor substrate composed of a semiconductor substrate such as SiC or Si +It includes a substrate 101 of a certain type. Hereinafter, an example in which the substrate 101 is made of SiC will be described. Also, in this embodiment, the substrate 101 constitutes a drain region.

[0018] On the main surface of the substrate 101, an n-type drift layer 102 with a lower impurity concentration than the substrate 101 is epitaxially grown. - On the surface layer portion of the drift layer 102, p-type deep layers 103 are formed at predetermined intervals. On the drift layer 102 and the deep layer 103, a p-type base region 104 is formed, and on the base region 104, an n-type source region 105 and a p-type contact region 106 are formed. + In this embodiment, the source region 105 is formed on the portion corresponding to the region of the drift layer 102 where the deep layer 103 is not formed, and the contact region 106 is formed on the portion corresponding to the region of the drift layer 102 where the deep layer 103 is formed. + In this embodiment, the semiconductor substrate 100 is thus composed of the substrate 101, the drift layer 102, the deep layer 103, the base region 104, the source region 105, and the contact region 106. Hereinafter, in the semiconductor substrate 100, the surface on the source region 105 and contact region 106 side will be referred to as one surface 100a, and the surface on the substrate 101 side will be referred to as the other surface 100b for explanation.

[0019] In this embodiment, the semiconductor substrate 100 is configured to include the substrate 101, the drift layer 102, the deep layer 103, the base region 104, the source region 105, and the contact region 106. Hereinafter, in the semiconductor substrate 100, the surface on the source region 105 and contact region 106 side will be referred to as one surface 100a, and the surface on the substrate 101 side will be referred to as the other surface 100b for explanation.

[0020] In the semiconductor substrate 100, a gate trench 107 is formed from the one surface 100a side. Specifically, the gate trench 107 is formed to penetrate the source region 105 and the base region 104 and reach the drift layer 102. For this reason, the above-mentioned source region 105 and base region 104 are formed to be in contact with the side surface of the gate trench 107. Also, the above-mentioned contact region 106 is arranged on the side opposite to the gate trench 107 with the source region 105 interposed therebetween.

[0021] Note that the gate trench 107 is formed in a linear layout with the horizontal direction of the paper of FIG. 2 as the width direction, one direction normal to the paper as the longitudinal direction, and the vertical direction of the paper as the depth direction. Also, in FIG. 2, only one gate trench 107 is shown, but actually, a plurality of gate trenches 107 are arranged at equal intervals in the horizontal direction of the paper and are arranged so as to be sandwiched between the deep layers 103 and are in a stripe shape.

[0022] The portion of the base region 104 located on the side surface of the gate trench 107 serves as a channel region that connects between the source region 105 and the drift layer 102 during the operation of the vertical MOSFET. And a gate insulating film 108 is formed on the inner wall surface of the gate trench 107 including this channel region. A gate electrode 109 made of doped Poly-Si is formed on the surface of the gate insulating film 108, and these gate insulating film 108 and gate electrode 109 are embedded in the gate trench 107. For this reason, the gate electrode 109 also extends in the same one direction as the longitudinal direction of the gate trench 107. And with such a structure, a trench gate structure is configured.

[0023] As shown in FIG. 3, the trench gate structure extends in the horizontal direction of the paper of FIG. 1. And as shown in FIG. 3, the trench gate structure is formed so as to project from the active region Ra to the outer peripheral region Rb. Note that the source region 105 is formed so as to be in contact with the side surface of the gate trench 107, but is formed only in the active region Ra and not in the outer peripheral region Rb. For this reason, the channel region is formed only within the active region Ra.

[0024] And on at least the side of the rectangular active region Ra located at the tip of the trench gate structure, as shown in FIG. 3, a field insulating film 110 is formed at positions away from both tips of the gate trench 107 on the surface of the base region 104. The field insulating film 110 has a shape with an opening on the active region Ra side, and has an end portion extending in a direction intersecting the longitudinal direction of the trench gate structure. That is, the field insulating film 110 has a shape in which the portions located on the left and right sides of the paper surface of FIG. 1 among the open ends are opposed to the tips of the respective trench gate structures. And although not shown in FIG. 3, the open ends of the field insulating film 110 are formed along the upper and lower sides of the rectangular active region Ra in FIG. 1.

[0025] The field insulating film 110 is made thick so as to be difficult to be broken even when a high voltage is applied. And the gate insulating film 108 formed in the gate trench 107 is also formed outside the gate trench 107 and extends up to the surface of the field insulating film 110 in this embodiment.

[0026] Specifically, the field insulating film 110 has an inclined portion 110a in which the end portion on the active region Ra side, that is, the trench gate structure side, is inclined obliquely. In this embodiment, the inclined portion 110a of the field insulating film 110 has a structure in which it gradually becomes thicker from the active region Ra side toward the outer peripheral region Rb side. And in this embodiment, the gate insulating film 108 is formed on the surface of the field insulating film 110 including this inclined portion 110a.

[0027] The gate electrode 109 is drawn out not only inside the gate trench 107 but also from both ends in the longitudinal direction of the gate trench 107 to the outside of the gate trench 107, and is drawn out to the position where the thickness of the field insulating film 110 is increased, similar to the gate insulating film 108. And the portion of the gate electrode 109 drawn out to the outside of the gate trench 107 constitutes a gate lead-out portion 109a that is a part of the gate liner 13.

[0028] Specifically, the gate lead-out portion 109a of the gate electrode 109 is formed on the field insulating film 110 including the inclined portion 110a and is arranged so as to ride up to the thickly formed field insulating film 110. For this reason, under the gate electrode 109, the inclined portion 110a of the field insulating film 110 is in a positioned state.

[0029] Here, if the inclined portion 110a is not formed at the end of the field insulating film 110, at the step portion at the end of the field insulating film 110, the gate electrode 109 is likely to become thin and a step break is likely to occur. However, in the present embodiment, since the inclined portion 110a is formed at the end of the field insulating film 110, it is possible to suppress the gate electrode 109 from being step-cut by the step at the end of the field insulating film 110. In particular, the gate electrode 109 is likely to have a step break when its thickness becomes thinner than the thickness of the field insulating film 110, but even in such a case, the step break can be suppressed by adopting the configuration of the present embodiment.

[0030] Note that since the gate insulating film 108 can be patterned as appropriate, it is not necessarily formed on the surface of the field insulating film 110. For example, the gate insulating film 108 may have a structure that terminates at the end of the field insulating film 110 and may not be disposed on the field insulating film 110. Further, the gate insulating film 108 may be formed on the base region 104, and the field insulating film 110 may be formed on the gate insulating film 108. That is, in the outer peripheral region Rb, the gate insulating film 108 may be disposed between the field insulating film 110 and the semiconductor substrate 100.

[0031] And in the present embodiment, as shown in FIGS. 3 and 4, in the outer peripheral region Rb, a recess 130 is formed on the one surface 100a side of the semiconductor substrate 100. Hereinafter, in the outer peripheral region Rb, the insulating film located between the one surface 100a of the semiconductor substrate 100 and the gate electrode 109 will be simply described as the insulating film 120. Also, the surface of the insulating film 120 on the side opposite to the one surface 100a side of the semiconductor substrate 100 will be described as the one surface 120a, and the surface of the insulating film 120 on the one surface 100a side of the semiconductor substrate 100 will be described as the other surface 120b.

[0032] Note that in the present embodiment, as described above, the gate insulating film 108 is also formed on the surface of the field insulating film 110. Therefore, the insulating film 120 of the present embodiment is configured to include the field insulating film 110 and the gate insulating film 108, and the one surface 120a is formed of the gate insulating film 108. Also, FIG. 4 is an enlarged view of the region IV in FIG. 3, but for easy understanding, only the semiconductor substrate 100, the insulating film 120, and the gate electrode 109 are shown. And it can be said that in the outer peripheral region Rb, the base region 104 as the second semiconductor layer is disposed on the drift layer 102 as the first semiconductor layer, and the insulating film 120 is disposed on the base region 104. Also, in the active region Ra, the source region 105 as the third semiconductor layer is formed in the surface layer portion of the base region 104, and the gate electrode 109 is disposed on the surface of the base region 104 sandwiched between the drift layer 102 and the source region 105.

[0033] First, as described above, the insulating film 120 is configured such that the inclined portion 110a is formed at the end of the field insulating film 110, and the thickness gradually increases from the active region Ra side. Therefore, the one surface 120a of the insulating film 120 is configured with the inclined portion 122 corresponding to the inclined portion 110a, and the one surface side corner portion 121a is formed at the portion where the thickness starts to increase.

[0034] On one surface 100a side of the semiconductor substrate 100, a recess 130 having an opening end is formed at a position corresponding to the one-surface-side corner portion 121a, and the insulating film 120 is disposed so as to fill the recess 130. Therefore, on the other surface 120b side of the insulating film 120, the other-surface-side corner portion 121b is formed at a portion disposed at the opening end of the recess 130. That is, in the present embodiment, the insulating film 120 is configured such that the one-surface-side corner portion 121a is formed on the one surface 120a side and the other-surface-side corner portion 121b is formed on the other surface 120b side. Note that the recess 130 is formed such that the bottom surface 130a is substantially parallel to the one surface 100a of the semiconductor substrate 100. In addition, the recess 130 of the present embodiment is formed such that the bottom surface 130a extends to the side opposite to the active region Ra side with respect to the other-surface-side corner portion 121b (that is, the one-surface-side corner portion 121a). The recess 130 is formed at a position corresponding to the one-surface-side corner portion 121a, and is formed along the upper and lower sides of the active region Ra having a rectangular shape in FIG. 1. The formation position of the other-surface-side corner portion 121b (that is, the formation position of the recess 130) and the shape of the recess 130 will be specifically described later.

[0035] As shown in FIGS. 2 and 3, an interlayer insulating film 111 is formed on the surfaces of a source region 105, a contact region 106, and a gate electrode 109 including a gate lead-out portion 109a of the semiconductor device. On the interlayer insulating film 111, an upper electrode 112 as a source electrode shown in FIG. 2 and a gate wiring layer 113 shown in FIG. 3 are formed as conductor patterns. Note that the gate wiring layer 113 here is a part of the gate liner 13 described above, and in the present embodiment, the gate liner 13 is configured to include the gate wiring layer 113 and the gate lead-out portion 109a. In addition, contact holes 111a and 111b are formed in the interlayer insulating film 111. As shown in FIG. 2, the upper electrode 112 is electrically connected to the source region 105 and the contact region 106 through the contact hole 111a. As shown in FIG. 3, the gate wiring layer 113 is electrically connected to the gate lead-out portion 109a, that is, the gate electrode 109 through the contact hole 111b.

[0036] Further, in the semiconductor device, the outer peripheral region Rb is covered with the protective film 115. The protective film 115 is formed with openings where portions corresponding to the upper electrode 112 are removed and openings where positions corresponding to the respective pads 12a to 12d are removed.

[0037] On the other surface 100b side of the semiconductor substrate 100, a lower electrode 114 is formed as a drain electrode that is electrically connected to the substrate 101. The semiconductor device of the present embodiment is configured by forming a vertical MOSFET having an n-channel type inversion type trench gate structure in this way.

[0038] The above is the configuration of the semiconductor device in the present embodiment. In the present embodiment, the n-type corresponds to the first conductivity type and the p-type corresponds to the second conductivity type. Next, while explaining the operation of the above semiconductor device, a more detailed structure will be described.

[0039] When a voltage higher than that of the upper electrode 112 is applied to the lower electrode 114 in the semiconductor device as described above, the PN junction formed between the base region 104 and the drift layer 102 becomes in a reverse conduction state and a depletion layer is formed. And when a gate voltage of a low level (for example, 0V) lower than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 109, no current flows between the upper electrode 112 and the lower electrode 114.

[0040] To turn on the semiconductor device (that is, the vertical MOSFET), with a voltage higher than that of the upper electrode 112 applied to the lower electrode 114, a high-level gate voltage equal to or higher than the threshold voltage Vth of the insulated gate structure is applied to the gate electrode 109. Thereby, an inversion layer is formed in a portion of the base region 104 that is in contact with the gate trench 107 where the gate electrode 109 is disposed. Then, electrons are supplied from the source region 105 to the drift layer 102 through the inversion layer, and a current flows between the upper electrode 112 and the lower electrode 114, resulting in an on state.

[0041] To turn off the semiconductor device, the gate voltage applied to the gate electrode 109 is made less than the threshold voltage Vth. As a result, the inversion layer formed in the base region 104 disappears and the semiconductor device turns off.

[0042] At this time, in the semiconductor device as in this embodiment, a rapid voltage change (dV / dt) occurs in the lower electrode 114, and a displacement current I flows to charge and discharge the capacitance C between the drift layer 102 and the base region 104.

[0043] Here, the configuration of the active region Ra and the like is the same as that of the first embodiment, and in the outer peripheral region Rb, as shown in FIG. 5, a semiconductor device in which the concave portion 130 is not formed on one surface 100a of the semiconductor substrate 100 is used as a comparative example semiconductor device. That is, a semiconductor device in which the other surface side corner portion 121b is not formed in the insulating film 120 is used as a comparative example semiconductor device. Note that FIG. 5 is a cross-sectional view of a portion corresponding to FIG. 4 in the semiconductor device of the comparative example.

[0044] In this case, in the semiconductor device of the comparative example, as shown in FIG. 6, the displacement current I in the outer peripheral region Rb flows below the insulating film 120 so as to be discharged from the contact region 106 of the active region Ra. At this time, assuming that the displacement current is I and the resistance value of the semiconductor at the portion where the displacement current I flows is Rs, a voltage ΔV represented by the following Equation 1 is applied to the insulating film 120.

[0045] (Equation 1) ΔV = I × Rs Note that the displacement current I is represented by the following Equation 2, assuming that the junction capacitance between the drift layer 102 and the base region 104 is C and the recovery current is Irr.

[0046] (Equation 2) I = C × dV / dt (+Irr) In the semiconductor device of the comparative example, an electric field is likely to concentrate on the one surface side corner portion 121a of the insulating film 120, and there is a possibility that the insulating film 120 at the one surface side corner portion 121a is broken because it is thin. That is, in the semiconductor device of the comparative example, the dV / dt tolerance may be low.

[0047] Therefore, in the present embodiment, a concave portion 130 is formed at a position corresponding to a corner portion 121a on one surface side of one surface 100a of the semiconductor substrate 100. And, on the insulating film 120, a corner portion 121b on the other surface side is formed on the other surface 120b side. Therefore, in the present embodiment, the maximum voltage applied to the insulating film 120 can be reduced.

[0048] Specifically, the inventors of the present invention intensively studied the electric field of a portion along the normal direction to the one surface 100a of the semiconductor substrate 100 (hereinafter, also simply referred to as the normal direction) passing through the corner portion 121a on the one surface side of the insulating film 120, and obtained the results shown in FIG. 7.

[0049] The electric field of the semiconductor device of the first embodiment in FIG. 7 shows the electric field of a portion along line VII-VII in FIG. 4. The electric field of the semiconductor device of the comparative example in FIG. 7 shows the electric field of a portion along line VII-VII in FIG. 5. Further, the semiconductor device of the comparative example in FIG. 7 is a semiconductor device in which the corner portion 121b on the other surface side is not formed on the insulating film 120 as described above. And, FIG. 7 shows the result when the corner portion 121b on the other surface side is formed to coincide with the virtual line K along the normal direction passing through the corner portion 121a on the one surface side as shown in FIG. 5. In FIG. 4, the virtual line K is shown slightly deviated from the corner portion 121a on the one surface side and the corner portion 121b on the other surface side, but actually, it is assumed that the corner portion 121a on the one surface side and the corner portion 121b on the other surface side coincide with the virtual line K.

[0050] Further, as shown in FIG. 7, the angle formed between the surface direction of one surface 100a of the semiconductor substrate 100 and the inclined portion 122 is defined as the one-surface-side taper angle θ1, and this is the result when the one-surface-side taper angle θ1 is 30°. FIG. 7 shows the result when the angle formed between the surface direction of one surface 100a of the semiconductor substrate 100 and the side surface of the concave portion 130 is defined as the other-surface-side taper angle θ2, and this other-surface-side taper angle θ2 is 60°. Further, FIG. 7 shows the result when the length from one surface 100a of the semiconductor substrate 100 to the bottom surface 130a of the concave portion 130 is defined as the depth d, and this depth d is 80 nm. Also, FIG. 7 shows the result when the measurement temperature is -40°C and dV / dt is 150 kV / μs. And FIG. 7 uses the maximum voltage applied to the insulating film 120 of the semiconductor device of the comparative example as a reference (i.e., the normalized electric field is 1).

[0051] As shown in FIG. 7, in the semiconductor device of the comparative example, since the one-surface-side corner portion 121a is formed only on one surface 120a of the insulating film 120, the electric field concentrates on the one-surface-side corner portion 121a of the insulating film 120. On the other hand, in the semiconductor device of the present embodiment, since the one-surface-side corner portion 121a and the other-surface-side corner portion 121b are formed on the insulating film 120, the electric field concentrates on the one-surface-side corner portion 121a and the other-surface-side corner portion 121b of the insulating film 120. Therefore, according to the semiconductor device of the present embodiment, by increasing the locations where the electric field concentrates, the maximum voltage applied to the insulating film 120 can be reduced, and the destruction of the insulating film 120 can be suppressed.

[0052] Further, the inventors of the present invention also intensively studied the depth d of the concave portion 130 and obtained the results shown in FIG. 8. Note that FIG. 8 shows the simulation results obtained under the same conditions as those of FIG. 7 above, except for the depth d. Also, FIG. 8 shows the result of examining the maximum voltage applied to the insulating film 120 of the semiconductor device of the present embodiment, with the maximum voltage applied to the insulating film 120 of the semiconductor device of the comparative example as a reference (i.e., the normalized electric field is 1).

[0053] As shown in FIG. 8, it is confirmed that in the range where the depth d of the concave portion 130 is shallower than 10 nm, the electric field sharply decreases as the depth d increases. And in the range where the depth d of the concave portion 130 is 10 nm or more, the electric field gradually decreases as the depth d increases. For this reason, the depth d of the concave portion 130 is preferably 10 nm or more.

[0054] Further, the inventors of the present invention earnestly studied the position of the other surface side corner portion 121b and obtained the results shown in FIG. 9. Note that FIG. 9 is a simulation result obtained under the same conditions as those in FIG. 7 described above, except for the position of the other surface side corner portion 121b. Also, FIG. 9 is a result of examining the maximum voltage applied to the insulating film 120 of the semiconductor device of the present embodiment with the maximum voltage applied to the insulating film 120 of the semiconductor device of the comparative example as a reference (that is, the normalized electric field is 1). And as shown in FIG. 4, for the position of the other surface side corner portion 121b in FIG. 9, when the other surface side corner portion 121b is located on the active region Ra side with respect to the virtual line K passing through the one surface side corner portion 121a, it is set as a negative value, and when the other surface side corner portion 121b is located on the side opposite to the active region Ra side, it is set as a positive value. That is, in FIG. 4, for the position of the other surface side corner portion 121b, when the other surface side corner portion 121b is located on the left side of the paper surface with respect to the virtual line K, it becomes a negative value, and when the other surface side corner portion 121b is located on the right side of the paper surface with respect to the virtual line K, it becomes a positive value. Note that since the other surface side corner portion 121b coincides with the virtual line K in FIG. 4, the position of the other surface side corner portion 121b in FIG. 9 becomes 0.

[0055] As shown in FIG. 9, it is confirmed that the electric field decreases when the position of the other surface side corner portion 121b becomes 0.5 μm or less, and sharply decreases when it becomes 0.2 μm or less. For this reason, the position of the other surface side corner portion 121b is preferably 0.5 μm or less, and more preferably 0.2 μm or less. Also, as shown in FIG. 9, it is confirmed that the other surface side corner portion 121b further decreases when it becomes a negative value. For this reason, the other surface side corner portion 121b may be located on the active region Ra side rather than the one surface side corner portion 121a. Note that the reason why the electric field further decreases when the other surface side corner portion 121b becomes a negative value is that the insulating film 120 located below the one surface side corner portion 121a becomes thick.

[0056] According to the present embodiment described above, on the insulating film 120, an other-side corner portion 121b is formed at a position corresponding to the one-side corner portion 121a. Therefore, the locations where the electric field concentrates in the insulating film 120 can be increased, and the maximum electric field applied to the insulating film 120 can be reduced, thereby suppressing the destruction of the insulating film 120.

[0057] (1) In the present embodiment, the recess 130 has a depth d of 10 nm or more. Therefore, it is easy to reduce the maximum voltage applied to the insulating film 120.

[0058] (2) In the present embodiment, the other-side corner portion 121b is formed at a position of 0.5 μm or less from the virtual line K, so that it is easy to reduce the maximum voltage applied to the insulating film 120. In this case, the other-side corner portion 121b is formed at a position of 0.2 μm or less from the virtual line K, so that it is further easy to reduce the maximum voltage applied to the insulating film 120.

[0059] (Second Embodiment) The second embodiment will be described. This embodiment is different from the first embodiment in that the shape of the recess 130 is changed. Since the other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0060] In the semiconductor device of the present embodiment, as shown in FIG. 10, the recess 130 is formed such that the bottom surface 130a extends toward the active region Ra side from the other-side corner portion 121b (that is, the one-side corner portion 121a). And, the surface of the one surface 100a of the semiconductor substrate 100 that faces the inclined portion 122 is a flat surface.

[0061] Thus, even if the recess 130 is formed to be located on the active region Ra side rather than the one-side corner portion 121a, the same effects as those of the first embodiment can be obtained. In the case of this embodiment, when the position of the other-side corner portion 121b is a positive value, the one-side corner portion 121a faces the recess 130. For this reason, by forming the position of the other-side corner portion 121b at a position of -0.5 μm or more from the virtual line K, the maximum voltage applied to the insulating film 120 can be easily reduced. In this case, by forming the other-side corner portion 121b at a position of -0.2 μm or more from the virtual line K, the maximum voltage applied to the insulating film 120 can be further easily reduced.

[0062] (Third Embodiment) The third embodiment will be described. In this embodiment, the shape of the recess 130 is changed with respect to the first embodiment. Since the other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0063] The semiconductor device of this embodiment has the same basic configuration as that of the first embodiment described above. And in this embodiment, the inclination angle of the other-side taper angle θ2 is defined.

[0064] Specifically, the inventors of the present invention earnestly studied the other-side taper angle θ2 and obtained the results shown in FIG. 11. Note that FIG. 11 is a simulation result obtained under the same conditions as those of FIG. 7 described above, except for the other-side taper angle θ2. Further, FIG. 11 is a result of examining the maximum voltage applied to the insulating film 120 of the semiconductor device of this embodiment, with the maximum voltage applied to the insulating film 120 of the semiconductor device of the comparative example as a reference (that is, the normalized electric field is 1).

[0065] As shown in FIG. 11, it is confirmed that the electric field tends to be smaller as the depth d of the recess 130 is greater. And it is confirmed that the electric field tends to be smaller as the taper angle θ2 on the other surface side is greater. More specifically, it is confirmed that when the depth d of the recess 130 is 5 nm or more, the electric field can be made sufficiently low if the taper angle θ2 on the other surface side is 5° or more. And since the electric field tends to be smaller as the depth d of the recess 130 is greater, it is confirmed that even when the depth d of the recess 130 is 10 nm or more, the electric field can be made sufficiently low if the taper angle θ2 on the other surface side is 5° or more. For this reason, in the present embodiment, the taper angle θ2 on the other surface side is set to 5° or more. Note that in order to suppress the manufacturing process from becoming complicated, the taper angle θ2 on the other surface side is preferably set to 90° or less.

[0066] According to the present embodiment described above, since the corner portion 121b on the other surface side is formed in the insulating film 120, the same effects as those of the first embodiment can be obtained.

[0067] (1) In the present embodiment, if the taper angle θ2 on the other surface side is 5° or more, it is easy to sufficiently reduce the electric field applied to the insulating film 120.

[0068] (Fourth Embodiment) The fourth embodiment will be described. In this embodiment, a plurality of recesses 130 are changed with respect to the first embodiment. Since the other aspects are the same as those of the first embodiment, the description thereof is omitted here.

[0069] As shown in FIG. 12, in the semiconductor device of the present embodiment, a plurality of recesses 130 are formed along the plane direction of one surface 100a of the semiconductor substrate 100. Note that in the present embodiment, one of the plurality of recesses 130 is formed so as to have a portion where the corner portion 121a on one surface side and the corner portion 121b on the other surface side coincide in the normal direction.

[0070] According to the present embodiment described above, since the other surface side corner portion 121b is formed in the insulating film 120, the same effects as those of the first embodiment can be obtained. And, as in the present embodiment, a plurality of recesses 130 may be formed along the surface direction of one surface 100a of the semiconductor substrate 100.

[0071] (Modification of the Fourth Embodiment) A modification of the fourth embodiment will be described. In the fourth embodiment, as shown in FIG. 13A, a plurality of recesses 130 may be formed such that a portion facing the one surface side corner portion 121a is the one surface 100a of the semiconductor substrate 100. Also, as shown in FIG. 13B, a plurality of recesses 130 may be formed such that a portion facing the one surface side corner portion 121a is the bottom surface 130a of the recess 130.

[0072] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within an equivalent range. In addition, various combinations and forms, and further, other combinations and forms including only one element, more than one element, or less than one element thereof, are within the scope and spirit of the present disclosure.

[0073] For example, in each of the above embodiments, a vertical MOSFET is taken as an example of the switching element provided in the active region Ra, but the switching element may be a vertical IGBT or the like, or may be configured by combining a plurality of types of elements. Also, the switching element may be of a planar type instead of a trench gate structure. Further, in each of the above embodiments, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0074] In each of the above embodiments, an example in which SiC or Si is used as the semiconductor substrate 100 has been described. However, the semiconductor substrate 100 may be formed of, for example, a gallium nitride substrate or the like. However, in the case of SiC, the operating voltage is high, and the voltage applied to the insulating film 120 is particularly likely to be high. Therefore, each of the above embodiments is particularly useful when the semiconductor substrate 100 is formed of SiC.

[0075] Furthermore, in each of the above embodiments, the inclined portion 110a formed in the field insulating film 110 may be formed so as to increase in thickness stepwise instead of gradually increasing in thickness.

[0076] Also, in each of the above embodiments, the insulating film 120 constituting the inclined portion 122 may be composed of only the field insulating film 110.

[0077] Furthermore, in each of the above embodiments, the depth d of the recess 130 may be set to 10 nm or less. Also, the position of the other surface side corner portion 121 may be appropriately changed. Even in such a semiconductor device, since the other surface side corner portion 121b is formed in the insulating film 120, the locations where the electric field concentrates in the insulating film 120 can be increased, and thus breakdown of the insulating film 120 can be suppressed.

[0078] And each of the above embodiments can be combined as appropriate. For example, the second embodiment may be combined with the third and fourth embodiments, or the third embodiment may be combined with the fourth embodiment.

Description of Reference Numerals

[0079] 100 Semiconductor substrate 109 Gate electrode 120 Insulating film 120a One surface 120b The other surface 121a One surface side corner portion 121b The other surface side corner portion 122 Inclined portion 130 Recess

Claims

1. A semiconductor device having an active region (Ra) in which a switching element is formed and an outer peripheral region (Rb) surrounding the outer periphery of the active region, a semiconductor substrate (100) having the active region and the outer peripheral region, the switching element formed in the active region and having a gate electrode (109) with one direction as the longitudinal direction, and an insulating film (120) formed in the outer peripheral region, wherein the insulating film has an inclined portion (122) whose thickness gradually increases from the active region side toward the side opposite to the active region, and a one-side corner portion (121a) where the thickness of the insulating film begins to increase is formed on one surface (120a) on the side opposite to the semiconductor substrate side, the gate electrode is drawn out from the active region to the outer peripheral region and is also disposed on the inclined portion of the insulating film, the semiconductor substrate has a recess (130) having an open end at a position corresponding to the one-side corner portion, and further, the insulating film is also disposed in the recess so as to cover the open end, and the semiconductor device has an other-side corner portion (121b) formed of a portion covering the open end on the other surface (120b) side on the semiconductor substrate side.

2. The semiconductor device according to claim 1, wherein the depth (d) of the recess from one surface of the semiconductor substrate is 10 nm or more.

3. The recess is formed such that the bottom surface (130a) is located on the side opposite to the active region side with respect to the other-side corner portion, when a virtual line (K) along the normal direction to the plane direction of one surface of the semiconductor substrate passing through the one-side corner portion is defined such that the side opposite to the active region side with respect to the virtual line is a positive value and the side on the active region side with respect to the virtual line is a negative value, the other-side corner portion is formed at a position of 0.5 μm or less from the virtual line. The semiconductor device according to claim 1 or 2.

4. The semiconductor device according to claim 3, wherein the other-side corner portion is formed at a position of 0.2 μm or less from the virtual line.

5. The recess is formed such that the bottom surface (130a) is located on the active region side with respect to the other-side corner portion, When a virtual line (K) passing through the one-side corner portion and along the normal direction with respect to the plane direction of one surface of the semiconductor substrate is defined such that the side opposite to the active region side from the virtual line has a positive value and the side of the active region side from the virtual line has a negative value, the other-side corner portion is formed at a position of -0.5 μm or more from the virtual line. The semiconductor device according to claim 1 or 2.

6. The semiconductor device according to claim 5, wherein the other-side corner portion is formed at a position of -0.2 μm or more from the virtual line.

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