Semiconductor device and radiation detection device

Abstract

To provide a semiconductor device for a radiation detection device with high reliability.SOLUTION: A semiconductor device includes a semiconductor layer provided on an insulating surface, a first gate electrode provided on the semiconductor layer and facing the semiconductor layer, a first insulating layer provided between the semiconductor layer and the first gate electrode and including silicon oxide covering a pattern end part of the semiconductor layer, a second insulating layer provided on the first insulating layer between the semiconductor layer and the first gate electrode, having a plane shape common to the first gate electrode, and including a first metal oxide, and a third insulating layer provided on the second insulating layer between the semiconductor layer and the first gate electrode, having a plane shape common to the first gate electrode, and including silicon nitride.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device and a radiation detection device. In particular, one embodiment of the present invention relates to a radiation detection device including a semiconductor device using an oxide semiconductor as a channel.

Background Art

[0002] In recent years, development of semiconductor devices using an oxide semiconductor as a channel has been underway in place of amorphous silicon, low-temperature polysilicon, and single-crystalline silicon (for example, Patent Document 1). A semiconductor device using an oxide semiconductor as a channel can be formed with a simple structure and a low-temperature process, similar to a semiconductor device using amorphous silicon as a channel. A semiconductor device using an oxide semiconductor as a channel is known to have higher mobility than a semiconductor device using amorphous silicon as a channel.

[0003] In order for a semiconductor device using an oxide semiconductor as a channel to operate stably, it is important to supply oxygen to the oxide semiconductor layer in its manufacturing process to reduce oxygen deficiencies formed in the oxide semiconductor layer. As one method of supplying oxygen to the oxide semiconductor layer, for example, a technique of forming an insulating layer covering the oxide semiconductor layer under conditions where the insulating layer contains more oxygen has been disclosed.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, an insulating layer formed under conditions containing more oxygen contains many defects. Due to this influence, characteristic variations of semiconductor devices in reliability tests are considered to be caused by holes being trapped in these defects. When a semiconductor device in which hole trapping has occurred is used as a radiation detection device, characteristic variations of the semiconductor device occur due to holes generated by the radiation being trapped. Suppressing such characteristic variations is required.

[0006] One of the problems to be solved by an embodiment of the present invention is to realize a semiconductor device for a highly reliable radiation detection device.

Means for Solving the Problems

[0007] A semiconductor device according to an embodiment of the present invention includes a semiconductor layer provided on an insulating surface, a first gate electrode provided on the semiconductor layer and facing the semiconductor layer, and a first insulating layer provided between the semiconductor layer and the first gate electrode and containing silicon oxide that covers a pattern end of the semiconductor layer. A second insulating layer provided on the first insulating layer between the semiconductor layer and the first gate electrode, having the same planar shape as the first gate electrode and containing a first metal oxide, and a third insulating layer provided on the second insulating layer between the semiconductor layer and the first gate electrode, having the same planar shape as the first gate electrode and containing silicon nitride.

Brief Description of the Drawings

[0008]

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MODE FOR CARRYING OUT THE INVENTION

[0009] Embodiments of the present invention will be described below with reference to the drawings. The following disclosure is merely an example. Configurations that can be easily conceived by those skilled in the art by appropriately changing the configurations of the embodiments while maintaining the gist of the invention are naturally included in the scope of the present invention. For the sake of clarity, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect. However, the illustrated shape is merely an example and does not limit the interpretation of the present invention. In this specification and each figure, configurations similar to those described above for the previously shown figures may be denoted by the same reference numerals, and detailed descriptions may be omitted as appropriate.

[0010] In each embodiment of the present invention, the direction from the substrate toward the oxide semiconductor layer is referred to as up or upward. Conversely, the direction from the oxide semiconductor layer toward the substrate is referred to as down or downward. Thus, for the sake of convenience in explanation, the terms up or downward are used for explanation. However, for example, the vertical relationship between the substrate and the oxide semiconductor layer may be arranged in a direction different from the illustration. In the following description, for example, the expression an oxide semiconductor layer on a substrate merely explains the vertical relationship between the substrate and the oxide semiconductor layer as described above, and other members may be arranged between the substrate and the oxide semiconductor layer. Up or downward means the stacking order in a structure in which a plurality of layers are stacked. When expressing a first member above a transistor, in a plan view, the positional relationship may be such that the transistor and the first member do not overlap. On the other hand, when expressing a first member directly above the transistor in a vertical direction, in a plan view, it means the positional relationship in which the transistor and the first member overlap.

[0011] In this specification, expressions such as "α includes A, B, or C", "α includes any one of A, B, and C", "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes a plurality of combinations of A to C unless otherwise specified. Furthermore, these expressions do not exclude the case where α includes other elements.

[0012] Note that the following embodiments can be combined with each other as long as no technical contradiction occurs.

[0013] [1. Configuration of Radiation Detection Device 10] With reference to FIGS. 1 and 2, the configuration of a radiation detection device 10 according to an embodiment of the present invention will be described. FIG. 1 is a cross-sectional view showing an overview of a radiation detection device according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing an overview of a radiation detection device according to an embodiment of the present invention.

[0014] As shown in FIG. 1, the radiation detection device 10 is provided on a substrate 100. The radiation detection device 10 includes a semiconductor device 20, a photoelectric conversion layer 300, and a wavelength conversion layer 400. In addition to the above members, the radiation detection device 10 includes a light shielding layer 210, connection wirings 220, an insulating layer 230, a lower electrode 310, an upper electrode 320, insulating layers 330, 340, and wirings 350, 360. The detailed structure of the semiconductor device 20 will be described later.

[0015] The uppermost layer of the semiconductor device 20 is an insulating layer 160. The light shielding layer 210 is provided on the insulating layer 160. The light shielding layer 210 is provided in a region that overlaps, in plan view, an oxide semiconductor layer 140 that constitutes a channel of the semiconductor device 20. In top view, the light shielding layer 210 is provided so as to cover at least the oxide semiconductor layer 140 in the channel region. The connection wiring 220 is provided on the insulating layer 160 and is connected to the semiconductor device 20. Although details will be described later, the connection wiring 220 is connected to a source electrode 201 of the semiconductor device 20.

[0016] An insulating layer 230 is provided on the insulating layer 160, the light shielding layer 210, and the connection wiring 220. The insulating layer 230 covers the pattern ends of the light shielding layer 210 and the connection wiring 220. The insulating layer 230 relaxes the step formed by the semiconductor device 20, the light shielding layer 210, and the connection wiring 220. The insulating layer 230 can be referred to as a planarization layer. An organic insulating layer is used as the insulating layer 230. An opening 231 is provided in the insulating layer 230. The opening 231 reaches the connection wiring 220.

[0017] A lower electrode 310 is provided above the insulating layer 230 and inside the opening 231. The lower electrode 310 is in contact with the connection wiring 220 at the bottom of the opening 231. A photoelectric conversion layer 300 and an upper electrode 320 are provided above the lower electrode 310. That is, the photoelectric conversion layer 300 is connected to the semiconductor device 20 via the lower electrode 310 and the connection wiring 220. The photoelectric conversion layer 300 includes an N-type semiconductor layer, a P-type semiconductor layer, and an intrinsic semiconductor layer. The intrinsic semiconductor layer is provided between the N-type semiconductor layer and the P-type semiconductor layer. One of the N-type semiconductor layer and the P-type semiconductor layer is in contact with the lower electrode 310, and the other is in contact with the upper electrode 320.

[0018] The photoelectric conversion layer 300 has a function of converting light energy into electrical energy. When light energy is absorbed by the intrinsic semiconductor layer of the photoelectric conversion layer 300, the semiconductor is photoexcited to generate pairs of electrons and holes. The generated electrons and holes flow to the lower electrode 310 and the upper electrode 320 through the N-type semiconductor layer and the P-type semiconductor layer. By detecting the current generated by the electrons and holes generated by photoexcitation, the intensity of the light irradiated on the photoelectric conversion layer 300 can be detected.

[0019] An insulating layer 330 is provided above the upper electrode 320. An opening 331 is provided in the insulating layer 330. The opening 331 reaches the upper electrode 320. An insulating layer 340 is provided above the insulating layer 330. An opening 341 is provided in the insulating layer 340. In a plan view, the opening 341 is larger than the opening 331. The opening 341 reaches a part of the upper electrode 320 and the insulating layer 330. An inorganic insulating layer is used as the insulating layer 330. An organic insulating layer is used as the insulating layer 340. The insulating layer 330 has a shape that reflects the step formed by the lower electrode 310, the photoelectric conversion layer 300, and the upper electrode 320. On the other hand, the insulating layer 340 relaxes the step. That is, the insulating layer 340 is a planarization layer.

[0020] On the insulating layer 340 and in a region that does not overlap with the photoelectric conversion layer 300 in plan view, a wiring 360 is provided. On the insulating layer 340, on the wiring 360, and inside the opening 341, a wiring 350 is provided. The wiring 350 is in contact with the upper electrode 320 at the bottom of the opening 341.

[0021] Although details will be described later, in order for the visible light emitted from the wavelength conversion layer 400 to efficiently reach the photoelectric conversion layer 300, a transparent conductive layer is used as the upper electrode 320 and the wiring 350. On the other hand, the wiring 360 is an opaque metal layer. The electrical resistance of the metal layer used as the wiring 360 is lower than the electrical resistance of the transparent conductive layer used as the wiring 350. However, a transparent conductive layer may be used as the wiring 360.

[0022] The wavelength conversion layer 400 is provided above the wiring 350 so as to face the photoelectric conversion layer 300. The wavelength conversion layer 400 may be adhered to the wiring 350 and the insulating layer 340 by an adhesive layer, or the positional relationship with the wiring 350 and the insulating layer 340 may be fixed by other fixing members. The wavelength conversion layer 400 has a function of converting radiation into visible light. For example, the wavelength conversion layer 400 contains a phosphor that absorbs X-rays, α-rays, or γ-rays and emits visible light. The wavelength conversion layer 400 can be referred to as a scintillator.

[0023] When radiation is incident on the wavelength conversion layer 400 from above, the radiation is converted into visible light by the wavelength conversion layer 400. When the converted visible light is incident on the photoelectric conversion layer 300, light energy is converted into electrical energy and detected as an electric current. Since there is a correlation between the intensity of the radiation incident on the wavelength conversion layer 400 and the detected electric current, the intensity of the radiation can be evaluated from the magnitude of the electric current.

[0024] As shown in FIG. 2, pixels 30 are arranged in a matrix in the radiation detection device 10. The pixel 30 includes a semiconductor device 20 and a photoelectric conversion layer 300. The gate electrode of the semiconductor device 20 is connected to the gate control line 109. The source electrode 201 of the semiconductor device 20 is connected to the cathode of the photoelectric conversion layer 300. The anode of the photoelectric conversion layer 300 is connected to the wiring 309. The drain electrode 203 of the semiconductor device 20 is connected to the wiring 209. The wiring 209 is connected to the charge amplifier circuit 500.

[0025] As described above, the radiation incident on the wavelength conversion layer 400 is converted into visible light, and the visible light is converted into electrical energy by the photoelectric conversion layer 300. Here, a bias voltage is supplied to the wiring 309 connected to the pixel 30 that detects radiation, and a signal for controlling the semiconductor device 20 to be in an on state is supplied to the gate control line 109 connected to the pixel 30. Thus, the electrical energy is detected as a current flowing through the semiconductor device 20. The current flowing through the semiconductor device 20 is supplied to the charge amplifier circuit 500 via the wiring 209. Then, the charge amplifier circuit 500 converts the charge signal into a voltage signal, and the voltage signal is output to the outside. By the above operation, the intensity of the radiation irradiated on the pixel 30 can be evaluated.

[0026] As shown in FIG. 1, ideally, all the radiation incident from above is absorbed by the wavelength conversion layer 400. However, in reality, a part of the radiation passes through the wavelength conversion layer 400. Further, ideally, the radiation that has passed through the wavelength conversion layer 400 is blocked by the light shielding layer 210. However, in reality, the radiation bypasses the light shielding layer 210 due to reflection by other members and reaches the oxide semiconductor layer 140. When the radiation enters the oxide semiconductor layer 140, electron-hole pairs are generated in the oxide semiconductor layer 140. When a hole trap is formed in the oxide insulating layer adjacent to the oxide semiconductor layer 140, the generated holes are trapped in the oxide insulating layer. Due to this effect, there may occur a problem that the electrical characteristics of the semiconductor device 20 shift in the negative direction.

[0027] [2. Configuration of Semiconductor Device 20] With reference to FIG. 3, the configuration of the semiconductor device 20 included in the radiation detection device 10 according to an embodiment of the present invention will be described. FIG. 3 is a cross-sectional view of a semiconductor device according to an embodiment of the present invention.

[0028] As shown in FIG. 3, the semiconductor device 20 is provided on a substrate 100 having an insulating surface. The semiconductor device 20 includes a gate electrode 105, gate insulating layers 110, 120, an insulating layer 130, an oxide semiconductor layer 140, gate insulating layers 510, 520, 530, a gate electrode 540, insulating layers 150, 160, a source electrode 201, and a drain electrode 203. The semiconductor device 20 is a transistor in which the oxide semiconductor layer 140 is used as a channel. Depending on the polarity of the transistor, the circuit configuration, and the potential of each node, the source electrode and the drain electrode of the aforementioned transistor may be interchanged. When the source electrode 201 and the drain electrode 203 are not particularly distinguished, they may be collectively referred to as a source / drain electrode 200. The semiconductor device 20 may be a transistor in which a semiconductor other than the oxide semiconductor is used as a channel.

[0029] In the present embodiment, as the semiconductor device 20, a dual-gate transistor in which the gate electrode 105 is provided below the oxide semiconductor layer 140 and the gate electrode 540 is provided above the oxide semiconductor layer 140 will be described. However, the semiconductor device 20 may be a bottom-gate transistor provided with only the gate electrode 105, or a top-gate transistor provided with only the gate electrode 540.

[0030] The gate electrode 105 is provided on the substrate 100. The gate electrode 105 faces the oxide semiconductor layer 140. The gate insulating layers 110 and 120 are provided between the gate electrode 105 and the oxide semiconductor layer 140. In other words, it can be said that the gate electrode 105 is provided between the substrate 100 and the oxide semiconductor layer 140. It can be said that the gate insulating layer 110 is provided between the gate electrode 105 and the oxide semiconductor layer 140. It can be said that the gate insulating layer 120 is provided between the gate insulating layer 110 and the oxide semiconductor layer 140. Although details will be described later, in this embodiment, the gate insulating layer 110 contains silicon nitride, and the gate insulating layer 120 contains silicon oxide. The gate electrode 105 may be referred to as the "second gate electrode". The gate insulating layer 110 may be referred to as the "fourth insulating layer". The gate insulating layer 120 may be referred to as the "fifth insulating layer".

[0031] The gate insulating layers 110 and 120 have a stacked structure. The insulating layer 130 is provided on the gate insulating layer 120. In other words, the insulating layer 130 is provided between the gate insulating layer 120 and the oxide semiconductor layer 140. The insulating layer 130 contains a metal oxide. The insulating layer 130 may be referred to as the "sixth insulating layer". The metal oxide contained in the insulating layer 130 may be referred to as the "second metal oxide".

[0032] The oxide semiconductor layer 140 is provided on the insulating layer 130. The insulating layer 130 and the oxide semiconductor layer 140 have a common planar shape. That is, the end portion of the insulating layer 130 substantially coincides with the end portion of the oxide semiconductor layer 140.

[0033] Here, the "common planar shape" means that each layer has substantially the same pattern in plan view. For example, when etching is performed on a plurality of different layers, a tapered shape may be formed at the pattern end portions of each of the plurality of layers by the etching. In this case, since the pattern of the upper layer is smaller than the pattern of the lower layer, these patterns are not exactly the same. However, even in such a case, it is said that the pattern of the upper layer and the pattern of the lower layer have a common planar shape.

[0034] The gate insulating layer 510 is provided over the oxide semiconductor layer 140 and over the gate insulating layer 120 exposed from the oxide semiconductor layer 140. The gate insulating layer 510 is formed from the upper surface of the oxide semiconductor layer 140 to the upper surface of the gate insulating layer 120 beyond the pattern end portion of the oxide semiconductor layer 140. A gate insulating layer 520, 530, and a gate electrode 540 are provided in this order over the gate insulating layer 510.

[0035] In other words, the above configuration is such that the gate electrode 540 is provided over the oxide semiconductor layer 140 and faces the oxide semiconductor layer 140. The gate insulating layer 510 is provided between the oxide semiconductor layer 140 and the gate electrode 540. The gate insulating layer 510 covers the pattern end portion of the oxide semiconductor layer 140. Although details will be described later, in this embodiment, the gate insulating layer 510 contains silicon oxide. The gate electrode 540 may be referred to as the "first gate electrode". The gate insulating layer 510 may be referred to as the "first insulating layer".

[0036] The gate insulating layers 520, 530, and the gate electrode 540 have a common planar shape. That is, the ends of the gate insulating layer 520, the ends of the gate insulating layer 530, and the ends of the gate electrode 540 substantially coincide. In the D1 direction connecting the source electrode 201 and the drain electrode 203, the lengths of the gate insulating layers 520, 530, and the gate electrode 540 are smaller than the length of the gate electrode 105.

[0037] In other words, the gate insulating layers 520, 530 are provided over the gate insulating layer 510 between the oxide semiconductor layer 140 and the gate electrode 540. The gate insulating layer 530 is provided over the gate insulating layer 520. Although details will be described later, in this embodiment, the gate insulating layer 520 contains a metal oxide, and the gate insulating layer 530 contains silicon nitride. The gate insulating layer 520 may be referred to as the "second insulating layer", and the gate insulating layer 530 may be referred to as the "third insulating layer". The metal oxide contained in the gate insulating layer 520 may be referred to as the "first metal oxide".

[0038] The insulating layers 150 and 160 are provided over the gate electrode 540 and the gate insulating layer 510. The insulating layers 150 and 160 have a stacked structure. The insulating layer 160 is provided over the insulating layer 150. The insulating layers 150 and 160 cover the gate electrode 540. In other words, the insulating layers 150 and 160 cover the pattern ends of the gate electrode 540. The insulating layer 150 is an insulating layer containing silicon nitride. The insulating layer 160 is an insulating layer containing silicon oxide. The insulating layer 150 may be referred to as the "seventh insulating layer". The insulating layer 160 may be referred to as the "eighth insulating layer".

[0039] Openings 161 and 163 are provided in the insulating layers 150 and 160 and the gate insulating layer 510. The openings 161 and 163 reach the oxide semiconductor layer 140. A source electrode 201 is provided over the insulating layer 160 and inside the opening 161. A drain electrode 203 is provided over the insulating layer 160 and inside the opening 163. The source electrode 201 and the drain electrode 203 are connected to the oxide semiconductor layer 140 at the bottoms of the openings 161 and 163, respectively. The source electrode 201 is in contact with the connection wiring 220 shown in FIG. 1.

[0040] The film thickness of the gate insulating layer 110 is, for example, 50 nm or more and 500 nm or less, 50 nm or more and 400 nm or less, 50 nm or more and 300 nm or less, 50 nm or more and 150 nm or less, or 50 nm or more and 100 nm or less. The film thickness of the gate insulating layer 120 is, for example, 10 nm or more and 200 nm or less or 10 nm or more and 100 nm or less. The total film thickness of the gate insulating layers 110 and 120 is, for example, 100 nm or more and 700 nm or less, 100 nm or more and 500 nm or less, 100 nm or more and 400 nm or less, 100 nm or more and 250 nm or less, 100 nm or more and 200 nm or less, or 100 nm or more and 150 nm or less.

[0041] The film thicknesses of the insulating layer 130 and the gate insulating layer 520 are, for example, 1 nm or more and 20 nm or less, or 1 nm or more and 10 nm or less. In this embodiment, aluminum oxide is used as the insulating layer 130 and the gate insulating layer 520. Aluminum oxide has a high barrier property against gases such as oxygen or hydrogen. The barrier property means a function of suppressing the permeation of gases such as oxygen or hydrogen through aluminum oxide. That is, even if a gas such as oxygen or hydrogen is released from the layer provided under the aluminum oxide film, the gas does not move to the layer provided above the aluminum oxide film. Or, even if a gas such as oxygen or hydrogen is released from the layer provided above the aluminum oxide film, the gas does not move to the layer provided under the aluminum oxide film.

[0042] The film thickness of the oxide semiconductor layer 140 is 10 nm or more and 50 nm or less, 10 nm or more and 40 nm or less, or 10 nm or more and 30 nm or less. The film thicknesses of the insulating layers 150 and 160 are 50 nm or more and 300 nm or less, 60 nm or more and 200 nm or less, or 70 nm or more and 150 nm or less.

[0043] The film thickness of the gate insulating layer 510 is, for example, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less. By the thickness of the gate insulating layer 510 being in the above range, as will be described later, the reliability of the semiconductor device 20 against visible light and radiation is improved.

[0044] The film thickness of the gate insulating layer 530 is, for example, 50 nm or more and 300 nm or less, 50 nm or more and 200 nm or less, or 50 nm or more and 100 nm or less. By the thickness of the gate insulating layer 530 being in the above range, it is possible to ensure the withstand voltage against the applied voltage of the gate insulating layer required for the semiconductor device 20.

[0045] [3. Materials of Each Member of the Radiation Detection Device 10] [3-1. Substrate] As the substrate 100, a rigid substrate having translucency, such as a glass substrate, a quartz substrate, and a sapphire substrate, is used. When the substrate 100 needs to have flexibility, a substrate containing resin, such as a polyimide substrate, an acrylic substrate, a siloxane substrate, and a fluororesin substrate, is used as the substrate 100. When a substrate containing resin is used as the substrate 100, impurities may be introduced into the above resin in order to improve the heat resistance of the substrate 100. As the substrate 100, a substrate that does not have translucency, such as a semiconductor substrate such as a silicon substrate, a silicon carbide substrate, and a compound semiconductor substrate, or a conductive substrate such as a stainless steel substrate, may be used.

[0046] [3-2. Conductive Layers such as Electrodes and Wiring] As the gate electrodes 105, 540, the source / drain electrodes 200, the light-shielding layer 210, the connection wiring 220, the lower electrode 310, and the wiring 360, a general metal material is used. For example, as these members, for example, aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof are used. As these electrodes and wiring, the above materials may be used in a single layer or in a laminated form. When the light-shielding layer 210 does not need to have conductivity, a black resin may be used as the light-shielding layer 210.

[0047] As the upper electrode 320 and the wiring 350, a transparent conductive layer is used. As the transparent conductive layer, a mixture of indium oxide and tin oxide (ITO) and a mixture of indium oxide and zinc oxide (IZO) can be used. As the transparent conductive layer, materials other than the above may be used.

[0048] [3-3. Insulating Layer] As the gate insulating layers 110, 120, 510, 530, and the insulating layers 150, 160, 330, general insulating materials are used. For example, as the gate insulating layers 120, 510, and the insulating layer 160, silicon oxide (SiO x ) and silicon oxynitride (SiOx N y ) Aluminum oxide (AlO x ) Aluminum oxynitride (AlO x N y ) and other inorganic insulating layers containing oxygen are used. As the gate insulating layers 110, 530 and the insulating layer 150, silicon nitride (SiN x ), silicon oxynitride (SiN x O y ), aluminum nitride (AlN x ), aluminum oxynitride (AlN x O y ) and other inorganic insulating layers containing nitrogen are used. However, as the gate insulating layer 110 and the insulating layer 150, the above-mentioned inorganic insulating layers containing oxygen may be used. As the gate insulating layers 120 and 160, the above-mentioned inorganic insulating layers containing nitrogen may be used.

[0049] As the gate insulating layer 510, an insulating layer having a function of releasing oxygen by heat treatment is used. That is, as the gate insulating layer 510, an oxide insulating layer containing an excessive amount of oxygen is used. The temperature of the heat treatment for the gate insulating layer 510 to release oxygen is, for example, 600 ° C or lower, 500 ° C or lower, 450 ° C or lower, or 400 ° C or lower. That is, the gate insulating layer 510 releases oxygen at the heat treatment temperature performed in the manufacturing process of the semiconductor device 20 when a glass substrate is used as the substrate 100, for example.

[0050] As the gate insulating layer 120, an insulating layer with few defects is used. For example, when comparing the oxygen composition ratio in the gate insulating layer 120 with the oxygen composition ratio in an insulating layer having the same composition as the gate insulating layer 120 (hereinafter referred to as "other insulating layer"), the oxygen composition ratio in the gate insulating layer 120 is closer to the stoichiometric ratio with respect to the insulating layer than the oxygen composition ratio in the other insulating layer. Specifically, silicon oxide (SiO xWhen [[ID=]] is used, the oxygen composition ratio in the silicon oxide used as the gate insulating layer 120 is closer to the stoichiometric ratio of silicon oxide than the oxygen composition ratio in the silicon oxide used as the gate insulating layer 510. For example, as the gate insulating layer 120, a layer in which no defects are observed when evaluated by the electron spin resonance method (ESR) may be used.

[0051] The above-mentioned SiO x N y and AlO x N y are silicon compounds and aluminum compounds containing nitrogen (N) in a ratio less than that of oxygen (O) (x > y). SiN x O y and AlN x O y are silicon compounds and aluminum compounds containing oxygen in a ratio less than that of nitrogen (x > y).

[0052] An organic insulating layer is used as the insulating layers 230 and 340. For example, as the organic insulating layer, a polyimide resin, an acrylic resin, an epoxy resin, a silicone resin, a fluororesin, and a siloxane resin are used.

[0053] A metal oxide mainly composed of aluminum is used as the insulating layers 130 and 520. For example, as the insulating layers 130 and 520, inorganic insulating layers such as aluminum oxide (AlO x ) and aluminum oxynitride (AlO x N y ) are used. "The insulating layers 130 and 520 mainly composed of aluminum" means that the ratio of aluminum contained in the insulating layers 130 and 520 is 1% or more of the entire metal oxide layer. The ratio of aluminum contained in the insulating layers 130 and 520 may be 5% or more and 70% or less, 10% or more and 60% or less, or 30% or more and 50% or less of the entire metal oxide layer. The above ratio may be a mass ratio or a weight ratio.

[0054] [3-4. Oxide semiconductor layer] As the oxide semiconductor layer 140, an oxide semiconductor containing two or more metals including indium (In) is used. For example, as the oxide semiconductor layer 140, an oxide semiconductor containing indium (In), gallium (Ga), zinc (Zn), and oxygen (O) may be used. For example, as the oxide semiconductor layer 140, an oxide semiconductor having a composition ratio of In:Ga:Zn:O = 1:1:1:4 may be used. However, the oxide semiconductor containing In, Ga, Zn, and O used in this embodiment is not limited to the above composition. As the oxide semiconductor, an oxide semiconductor having a composition different from the above may be used. For example, an oxide semiconductor layer in which the ratio of In is larger than the above may be used to improve mobility. On the other hand, an oxide semiconductor layer in which the ratio of Ga is larger than the above may be used to increase the bandgap and reduce the influence of light irradiation.

[0055] For example, as the oxide semiconductor layer 140 in which the ratio of In is larger than the above, an oxide semiconductor layer in which the ratio of indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more in atomic ratio may be used. As the oxide semiconductor layer 140, in addition to indium, gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconia (Zr), lanthanoids may be used. As the oxide semiconductor layer 140, elements other than the above may be used.

[0056] As the oxide semiconductor layer 140, other elements may be added to the oxide semiconductor containing In, Ga, Zn, and O, and for example, metal elements such as Al and Sn may be added. In addition to the above oxide semiconductors, oxide semiconductors containing In and Zn (IZO), oxide semiconductors containing In, Sn, and Zn (ITZO), oxide semiconductors containing In, Sn, Ga, and Zn (ITGZO), oxide semiconductors containing In and Ga (IGO), etc. may be used as the oxide semiconductor layer 140.

[0057] When the ratio of indium element is large, the oxide semiconductor layer 140 is likely to crystallize. As described above, in the oxide semiconductor layer 140, by using a material in which the ratio of indium element to all metal elements is 50% or more, the oxide semiconductor layer 140 having a polycrystalline structure can be easily obtained. As a metal element other than indium, it is preferable that the oxide semiconductor layer 140 contains gallium. Gallium belongs to the same Group 13 element as indium. Therefore, the crystallinity of the oxide semiconductor layer 140 is not inhibited by gallium, and the oxide semiconductor layer 140 has a polycrystalline structure.

[0058] As described above, when the ratio of indium element to all metal elements in the oxide semiconductor layer 140 is 50% or more, the oxide semiconductor layer 140 has translucency and a polycrystalline structure including a plurality of crystal grains. Although details will be described later, by using Poly-OS (Poly-crystalline Oxide Semiconductor) technology, the oxide semiconductor layer 140 having a polycrystalline structure can be formed. Hereinafter, the configuration of the oxide semiconductor layer 140 will be described. The oxide semiconductor having a polycrystalline structure may be referred to as Poly-OS in some cases.

[0059] The crystal grain size of the crystal grains included in Poly-OS is, for example, 0.1 μm or more, 0.3 μm or more, or 0.5 μm or more. The crystal grain size of the crystal grains can be obtained by using, for example, cross-sectional SEM observation, cross-sectional TEM observation, or Electron Back Scattered Diffraction (EBSD) method.

[0060] As described above, since the crystal grain size of the crystal grains included in Poly-OS is 0.1 μm or more, in the oxide semiconductor layer 140 having a film thickness of 10 nm or more and 30 nm or less, there is a region in which only one crystal grain is included along the film thickness direction.

[0061] The oxide semiconductor layer 140 can be formed by a sputtering method. The composition of the oxide semiconductor layer 140 formed by the sputtering method depends on the composition of the sputtering target. Even when the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the sputtering target and the composition of the oxide semiconductor layer 140 are substantially the same. In this case, the composition of the metal elements in the oxide semiconductor layer 140 can be specified based on the composition of the metal elements in the sputtering target.

[0062] When the oxide semiconductor layer 140 has a polycrystalline structure, the composition of the oxide semiconductor layer may be specified using an X-ray Diffraction (XRD) method. Specifically, based on the crystal structure and lattice constant of the oxide semiconductor layer obtained by the XRD method, the composition of the metal elements in the oxide semiconductor layer can be specified. Furthermore, the composition of the metal elements in the oxide semiconductor layer 140 can also be specified using fluorescence X-ray analysis or Electron Probe Micro Analyzer (EPMA) analysis, etc. However, since the oxygen element contained in the oxide semiconductor layer 140 changes depending on the sputtering process conditions, etc., there are cases where it cannot be specified by these methods.

[0063] [3-5.Poly-OS Technology] The Poly-OS contained in the oxide semiconductor layer can be formed using sputtering and heat treatment. Here, the method for forming the oxide semiconductor layer will be described.

[0064] First, an oxide semiconductor layer is formed by sputtering. The formed oxide semiconductor layer has an amorphous structure. Here, the amorphous structure refers to a structure in which there is no long-range order structure and no periodic crystal lattice arrangement can be observed. For example, when observing an oxide semiconductor layer having an amorphous structure using the XRD method, no specific peak based on the crystal structure can be obtained in the diffraction pattern. Note that an oxide semiconductor layer having an amorphous structure may have a short-range order structure in a minute region. However, since such an oxide semiconductor layer does not exhibit the characteristics of Poly-OS, it can be classified as an oxide semiconductor layer having an amorphous structure.

[0065] In Poly-OS technology, the oxide semiconductor layer is formed at a low temperature. For example, the temperature of the substrate on which the oxide semiconductor layer is formed is 150°C or lower, preferably 100°C or lower, and more preferably 50°C or lower. If the temperature of the substrate during the formation of the oxide semiconductor layer is high, microcrystals are likely to be generated in the formed oxide semiconductor. The oxygen partial pressure in the chamber during film formation is 1% or more and 10% or less, preferably 1% or more and 5% or less, and more preferably 2% or more and 4% or less. If the oxygen partial pressure is high, microcrystals are generated in the oxide semiconductor layer due to the excessive oxygen contained in the oxide semiconductor. On the other hand, under the condition that the oxygen partial pressure is less than 1%, the oxygen composition in the oxide semiconductor layer becomes non-uniform, and an oxide semiconductor layer containing many microcrystals or an oxide semiconductor layer that does not crystallize even after heat treatment is formed.

[0066] Next, the oxide semiconductor layer formed by sputtering is heat-treated. The heat treatment is performed in the air, but the atmosphere of the heat treatment is not limited to this. The temperature of the heat treatment is 300°C or higher and 500°C or lower, preferably 350°C or higher and 450°C or lower. The time of the heat treatment is 15 minutes or longer and 120 minutes or shorter, preferably 30 minutes or longer and 60 minutes or shorter. By performing the heat treatment, the oxide semiconductor layer having an amorphous structure is crystallized, and an oxide semiconductor layer containing Poly-OS is formed.

[0067] [4. Electrical Characteristics of Semiconductor Device 20] Figures 4 to 8 are cross-sectional views and electrical characteristics of a semiconductor device according to a comparative example. Figure 9 is a cross-sectional view and electrical characteristics of a semiconductor device according to an embodiment of the present invention. In Figures 4 to 9, the structure of the semiconductor device for which the electrical characteristics were evaluated is shown together with the electrical characteristics. By referring to the cross-sectional structure and electrical characteristics of the semiconductor devices according to each of the comparative example and the present embodiment using Figures 4 to 9, the effects obtained by the structure according to the present embodiment will be described.

[0068] The measurement conditions of the electrical characteristics shown in Figures 4 to 9 are as follows. The vertical axis of each electrical characteristic is the drain current value (Id [A]), and the horizontal axis is the gate voltage value (Vg [V]). · Size of channel region CH: W / L = 4.5μm / 3.0μm · Source-drain voltage: 0.1V (dotted line), 10V (solid line) · Gate voltage: -15V to +15V · Measurement environment: room temperature, dark room

[0069] [4-1. Conventional Semiconductor Device] Figure 4 shows a conventional semiconductor device and its electrical characteristics as a comparative example. The semiconductor device 20V shown in Figure 4 is similar to the semiconductor device 20 shown in Figure 3. However, the semiconductor device 20V is not provided with members corresponding to the gate insulating layers 520 and 530 of the semiconductor device 20, and the gate electrode 540V is in contact with the gate insulating layer 510V. The electrical characteristics of the semiconductor device 20V are good. However, in the semiconductor device 20V, for example, the threshold variation due to a radiation irradiation test using X-rays is large.

[0070] It is known that the threshold variation due to the radiation irradiation test occurs because holes generated in the oxide semiconductor layer 140V by the radiation irradiation are trapped by hole traps in the oxide insulating layer adjacent to the oxide semiconductor layer 140V. Therefore, in order to improve the resistance of the semiconductor device 20V to the radiation irradiation test, it is necessary to reduce the film thickness of the gate insulating layer 510V.

[0071] However, in the structure of the semiconductor device 20V, when the film thickness of the gate insulating layer 510V is small, not only is the breakdown voltage of the gate insulating layer 510V low, but it is also difficult to adjust the impurity implantation process for reducing the resistance of the oxide semiconductor layer 140V in the source region and the drain region that do not overlap with the gate electrode 540V in plan view. Therefore, a countermeasure of thinning the gate insulating layer 510V and adding an insulating layer containing silicon nitride between the gate insulating layer 510V and the gate electrode 540V can be considered.

[0072] [4-2. Semiconductor Device with Silicon Nitride Layer Added to Gate Insulating Layer] FIG. 5 shows, as a comparative example, a semiconductor device 20W in which a gate insulating layer 530W containing silicon nitride is provided between a gate insulating layer 510W and a gate electrode 540W, different from the conventional semiconductor device 20V, and its electrical characteristics. As shown in FIG. 5, in the semiconductor device 20W, the gate insulating layer 530W extends not only under the gate electrode 540W but also outside the pattern of the oxide semiconductor layer 140W, similar to the gate insulating layer 510W. The electrical characteristics of the semiconductor device 20W are poor, and the semiconductor device 20W does not have the function of a switching element (it does not turn off).

[0073] Since a large amount of hydrogen is contained in silicon nitride, hydrogen diffuses into the oxide semiconductor layer 140W during the formation of the gate insulating layer 530W and by heat treatment after the formation of the gate insulating layer 530W. When hydrogen reaches the oxide semiconductor layer 140W, the oxide semiconductor layer 140W becomes N-type due to the reducing action of hydrogen. As a result, as shown in FIG. 5, the semiconductor device 20W does not have a switching function. In particular, in the semiconductor device 20W, since the gate insulating layer 530W is formed over the entire surface, a large amount of hydrogen diffuses into the oxide semiconductor layer 140W.

[0074] As described above, the reason why the semiconductor device 20W does not have a switching function is the N-type conversion of the oxide semiconductor layer 140W due to the diffusion of hydrogen contained in silicon nitride into the oxide semiconductor layer 140W. Therefore, the above problem can be suppressed by reducing the amount of hydrogen diffusing into the oxide semiconductor layer 140W. Since the gate insulating layer 530W only needs to be provided between the gate insulating layer 510W and the gate electrode 540W, a countermeasure of reducing the amount of hydrogen by removing the gate insulating layer 530W other than between the gate insulating layer 510W and the gate electrode 540W can be considered.

[0075] [4-3. Semiconductor device with silicon nitride layer patterned according to gate electrode] FIG. 6 shows, as a comparative example, a semiconductor device 20X in which, unlike the semiconductor device 20W shown in FIG. 5, the gate insulating layer 530X in a region that does not overlap with the gate electrode 540X in plan view is removed, and its electrical characteristics. As shown in FIG. 6, in the semiconductor device 20X, the gate insulating layer 530X is provided only between the gate insulating layer 510X and the gate electrode 540X, and no gate insulating layer 530X is provided in a region that does not overlap with the gate electrode 540X in plan view. The electrical characteristics of the semiconductor device 20X are poor, and the semiconductor device 20X does not have a function as a switching element (it does not turn off).

[0076] FIG. 7 shows, as a comparative example, a semiconductor device 20Y in which, unlike the semiconductor device 20W shown in FIG. 5, the gate insulating layers 510Y and 530Y in a region that does not overlap with the gate electrode 540Y in plan view are removed, and its electrical characteristics. As shown in FIG. 7, in the semiconductor device 20Y, both the gate insulating layers 510Y and 530Y are formed in the same pattern as the gate electrode 540Y. The electrical characteristics of the semiconductor device 20Y are poor, and the semiconductor device 20Y does not have a function as a switching element (it does not turn off).

[0077] As described above, even when only the gate insulating layer 530X was removed in the region that does not overlap with the gate electrodes 540X and 540Y in plan view, or even when both the gate insulating layers 510Y and 530Y were removed, it was not possible to suppress the N-type conversion of the oxide semiconductor layers 140X and 140Y. Here, since a metal oxide mainly composed of aluminum can suppress the diffusion of hydrogen, for example, a countermeasure of providing the above metal oxide between the gate insulating layer 530X and the gate insulating layer 510X can be considered.

[0078] [4-4. Semiconductor device in which an aluminum oxide layer is provided between a silicon nitride layer and a silicon oxide layer] FIG. 8 shows, as a comparative example, a semiconductor device 20Z different from the semiconductor device 20X shown in FIG. 6, in which a gate insulating layer 520Z containing a metal oxide mainly composed of aluminum is provided between the gate insulating layer 510Z and the gate insulating layer 530Z, and its electrical characteristics. In the present embodiment, an example in which aluminum oxide is used as the metal oxide will be described. As shown in FIG. 8, in the semiconductor device 20Z, the gate insulating layer 520Z extends not only under the gate electrode 540Z but also to the outside of the pattern of the oxide semiconductor layer 140Z, similar to the gate insulating layer 530Z. The electrical characteristics of the semiconductor device 20Z are different from the electrical characteristics of the semiconductor devices 20W to 20Y and have a function as a switching element (can be switched between an on state and an off state). On the other hand, in the semiconductor device 20Z, a problem of low on-current occurs.

[0079] Although details will be described later, in the semiconductor device 20Z, a process of implanting impurities into the oxide semiconductor layer 140 is performed to reduce the resistance of the oxide semiconductor layer 140Z in the source region and the drain region. By this implantation of impurities, oxygen vacancies are formed in the oxide semiconductor layer 140Z. It has been found that the resistance reduction of the oxide semiconductor layer 140Z is realized by the diffusion of hydrogen from the insulating layer 150Z to these oxygen vacancies.

[0080] On one hand, in the structure of the semiconductor device 20Z shown in FIG. 8, a gate insulating layer 520Z (aluminum oxide) is provided over the entire surface under the insulating layer 150Z. Aluminum oxide suppresses the diffusion of hydrogen, so that the hydrogen contained in the insulating layer 150Z is suppressed from diffusing into the oxide semiconductor layer 140Z. As a result, even if oxygen vacancies are formed in the oxide semiconductor layer 140Z by impurity implantation, hydrogen does not diffuse into the oxygen vacancies, and thus the oxide semiconductor layer 140Z in the source region and the drain region is not made low-resistance. As a result, as shown in FIG. 8, in some semiconductor devices 20Z, a problem of low on-current occurs.

[0081] In consideration of the above results, as shown in FIG. 9, in the semiconductor device 20 according to the present embodiment, the gate insulating layer 520 in the source region and the drain region is removed so that the hydrogen contained in the insulating layer 150 diffuses into the oxide semiconductor layer 140 and the oxide semiconductor layer 140 in the source region and the drain region can be made low-resistance. As a result, the decrease in the on-current confirmed in FIG. 8 is eliminated, and the semiconductor device 20 has a function as a good switching element.

[0082] [5. Radiation resistance of semiconductor device 20] FIG. 10 is a diagram showing the results of a reliability test of a semiconductor device according to an embodiment of the present invention against radiation. The reliability test shown in FIG. 10 is the result of an X-ray irradiation test. The graph shown in FIG. 10 shows the amount of change in the threshold voltage Vth obtained from the electrical characteristics before and after X-ray irradiation.

[0083] The conditions of the X-ray irradiation test are as follows. · Channel region size: W / L = 4.5 μm / 3.0 μm · Number of evaluation transistors: 4 · X-ray irradiation device: MBR-1520R-3 (manufactured by Hitachi Power Solutions) · X-ray irradiation conditions: 90 Gy (continuous irradiation at 20 mA) · X-ray irradiation conditions: Filter Al = 1 mm

[0084] The vertical axis (ΔVth@90Gy) in FIG. 10 represents the variation in the threshold voltage Vth before and after X-ray irradiation. In FIG. 10, the semiconductor device according to the embodiment is the semiconductor device 20 shown in FIG. 3. The film thicknesses of the gate insulating layers 510 (silicon oxide) and 530 (silicon nitride) of the semiconductor device 20 are both 50 nm. The semiconductor device according to the comparative example is the semiconductor device 20V shown in FIG. 4. The film thickness of the gate insulating layer 510V (silicon oxide) of the semiconductor device 20V is 75 nm.

[0085] As shown in FIG. 10, the threshold variation before and after the X-ray irradiation test of the semiconductor device 20 according to the embodiment is smaller than that of the semiconductor device 20V according to the comparative example before and after the X-ray irradiation test. This result is due to the fact that, due to the difference in the film thicknesses of the gate insulating layer 510 and the gate insulating layer 510V, the amount of hole traps contained in the gate insulating layer 510 in the embodiment is less than the amount of hole traps contained in the gate insulating layer 510V in the comparative example.

[0086] [6. Manufacturing Method of Semiconductor Device 20] The manufacturing method of the semiconductor device according to an embodiment of the present invention will be described with reference to FIGS. 11 to 18. FIGS. 11 to 18 are cross-sectional views showing the manufacturing method of the semiconductor device according to an embodiment of the present invention. In the following description of the manufacturing method, a manufacturing method of the semiconductor device 20 in which silicon nitride is used as the gate insulating layers 110 and 530, silicon oxide is used as the gate insulating layers 120 and 510, and aluminum oxide is used as the insulating layer 130 and the gate insulating layer 520 will be described.

[0087] As shown in FIG. 11, a gate electrode 105 is formed as a bottom gate on the substrate 100, and gate insulating layers 110 and 120 are formed on the gate electrode 105. As the gate insulating layer 110, silicon nitride is formed. As the gate insulating layer 120, silicon oxide is formed. The gate insulating layers 110 and 120 are formed by a CVD (Chemical Vapor Deposition) method.

[0088] By using silicon nitride as the gate insulating layer 110, the gate insulating layer 110 can block impurities that diffuse, for example, from the substrate 100 side toward the oxide semiconductor layer 140.

[0089] An insulating layer 130 and an oxide semiconductor layer 140 are formed over the gate insulating layer 120. Aluminum oxide is used as the insulating layer 130. The oxide semiconductor layer 140 is formed to be in contact with the insulating layer 130. The insulating layer 130 and the oxide semiconductor layer 140 are formed by a sputtering method or an atomic layer deposition method (ALD: Atomic Layer Deposition).

[0090] A resist mask is formed over the oxide semiconductor layer 140, and the insulating layer 130 and the oxide semiconductor layer 140 are etched using the resist mask. As the etching of the oxide semiconductor layer 140, wet etching may be used, or dry etching may be used. As the wet etching, etching may be performed using an acidic etchant. For example, as the etchant, an etching solution containing phosphoric acid as a main component or hydrofluoric acid may be used.

[0091] Thereafter, using the patterned oxide semiconductor layer 140 as a mask, the insulating layer 130 is etched. As the etching of the insulating layer 130, wet etching may be used, or dry etching may be used. For example, as the wet etching, diluted hydrofluoric acid (DHF) is used. As described above, by etching the insulating layer 130 using the oxide semiconductor layer 140 as a mask, the photolithography process can be omitted.

[0092] A gate insulating layer 510 is formed over the insulating layer 130 and the oxide semiconductor layer 140 patterned as described above. Silicon oxide is formed as the gate insulating layer 510. The gate insulating layer 510 is formed by a CVD method. For example, in order to form an insulating layer with few defects as described above as the gate insulating layer 510, the gate insulating layer 510 may be formed at a film formation temperature of 350°C or higher.

[0093] In this embodiment, a configuration in which the insulating layer 130 is provided under the oxide semiconductor layer 140 is illustrated, but the insulating layer 130 may be omitted.

[0094] As shown in FIG. 12, a gate insulating layer 520 is formed on the gate insulating layer 510. The gate insulating layer 520 is formed by a sputtering method. By forming the gate insulating layer 520, oxygen and the process gas used in the sputtering method are implanted into the gate insulating layer 510. Argon is often used as the process gas in the sputtering method. Therefore, the gate insulating layer 510 may contain argon.

[0095] As shown in FIG. 13, a gate insulating layer 530 is formed on the gate insulating layer 520. Silicon nitride is formed as the gate insulating layer 530. The gate insulating layer 530 is formed by a CVD method.

[0096] As shown in FIG. 14, a conductive layer is formed on the gate insulating layer 530, a photoresist PR is formed on the conductive layer, and the conductive layer and the gate insulating layer 530 are etched using the photoresist PR as a mask. The gate electrode 540 is formed by this etching.

[0097] For example, when an alloy of molybdenum and tungsten (MoW) is used as the gate electrode 540, dry etching using SF6 and O2 as process gases is used for etching MoW. The dry etching has a high etching rate for silicon nitride but a low etching rate for aluminum oxide. Therefore, as shown in FIG. 14, the gate electrode 540 and the gate insulating layer 530 are etched together using the photoresist PR as a mask, and the gate insulating layer 520 functions as a stopper for the etching.

[0098] As the gate electrode 540, in addition to a MoW monolayer, a stack of titanium (lower layer) and MoW (upper layer) may be used. As the gate electrode 540, a material other than MoW may be used as a monolayer or may be used in a stack. The conductive layer constituting the gate electrode 540 is formed by a sputtering method.

[0099] As shown in FIG. 15, using the photoresist PR, the gate electrode 540, and the gate insulating layer 530 as masks, the gate insulating layer 520 is etched. By this etching, a configuration in which the pattern ends of each of the gate electrode 540, the gate insulating layer 530, and the gate insulating layer 520 are aligned is obtained. That is, by the above etching, a configuration in which the gate insulating layer 520 has the same planar shape as the gate electrode 540 and the gate insulating layer 530 is obtained.

[0100] When MoW is used as the gate electrode 540, the etching of the gate insulating layer 520 may be performed with the photoresist PR formed, or may be performed with the photoresist PR removed.

[0101] As shown in FIG. 16, after the photoresist PR is removed, ion implantation is performed on the oxide semiconductor layer 140. As shown in FIG. 16, since the gate insulating layer 510 is formed on the oxide semiconductor layer 140, ions that have passed through the gate insulating layer 510 are implanted into the oxide semiconductor layer 140. However, since the implanted ions are blocked by the gate electrode 540, no ions are implanted into the region overlapping the gate electrode 540 in plan view.

[0102] For example, by ion implantation, boron (B) is implanted into the oxide semiconductor layer 140 as an impurity element. However, instead of boron, other impurity elements such as phosphorus (P) may be implanted into the oxide semiconductor layer 140.

[0103] By the above-described ion implantation, impurity elements are implanted into the oxide semiconductor layer 140 in the source region and the drain region. In the oxide semiconductor layer 140 in the source region and the drain region, oxygen defects are formed by the implantation of the impurity elements. When hydrogen is trapped by this oxygen deficiency, the oxide semiconductor layer 140 in the source region and the drain region has a lower resistance.

[0104] In the oxide semiconductor layer 140 containing Poly-OS, even in the source region and the drain region where impurity elements are implanted, the oxide semiconductor layer 140 may have crystallinity. This is also one of the characteristics of Poly-OS. In this case, the crystal structure of each of the source region and the drain region is the same as the crystal structure of the channel region overlapping the gate electrode 540 in plan view.

[0105] As shown in FIG. 17, insulating layers 150 and 160 are formed as an interlayer film on the gate insulating layer 510 and the gate electrode 540. The insulating layers 150 and 160 are formed by a CVD method. Silicon nitride is formed as the insulating layer 150, and silicon oxide is formed as the insulating layer 160. The materials used as the insulating layers 150 and 160 are not limited to the above.

[0106] As shown in FIG. 18, openings 161 and 163 are formed in the insulating layers 150 and 160 and the gate insulating layer 510. The openings 161 and 163 are formed so as to expose the oxide semiconductor layer 140, respectively. A conductive layer 208 is formed on the insulating layer 160 and inside the openings 161 and 163, and by patterning the conductive layer 208, a source electrode 201 and a drain electrode 203 are formed as shown in FIG. 3.

[0107] Each of the embodiments described above as embodiments of the present invention can be implemented in appropriate combination as long as they do not contradict each other. Also, based on the semiconductor device and the radiation detection device of each embodiment, those in which a person skilled in the art appropriately adds, deletes, or changes the design of components, or adds, omits, or changes the conditions of the process, are also included in the scope of the present invention as long as they have the gist of the present invention.

[0108] Even if there are other operational effects different from those brought about by the aspects of the above-described embodiments, those that are obvious from the description in this specification or can be easily predicted by those skilled in the art shall naturally be construed as being brought about by the present invention.

Explanation of Reference Numerals

[0109] 10: Radiation detection device, 20: Semiconductor device, 30: Pixel, 100: Substrate, 105: Gate electrode, 109: Gate control line, 110: Gate insulating layer, 120: Gate insulating layer, 130, 150, 160: Insulating layer, 140: Oxide semiconductor layer, 161, 163: Opening, 200: Source-drain electrode, 201: Source electrode, 203: Drain electrode, 208: Conductive layer, 209: Wiring, 210: Light-shielding layer, 220: Connection wiring, 230: Insulating layer, 231: Opening, 300: Photoelectric conversion layer, 309: Wiring, 310: Lower electrode, 320: Upper electrode, 330, 340: Insulating layer, 331, 341: Opening, 350, 360: Wiring, 400: Wavelength conversion layer, 500: Charge amplifier circuit, 510, 520, 530: Gate insulating layer, 540: Gate electrode, PR: Photoresist

Claims

1. A semiconductor layer provided on an insulating surface, a first gate electrode provided on the semiconductor layer and facing the semiconductor layer, a first insulating layer provided between the semiconductor layer and the first gate electrode and containing silicon oxide that covers a pattern end of the semiconductor layer, a second insulating layer provided on the first insulating layer between the semiconductor layer and the first gate electrode, having the same planar shape as the first gate electrode, and containing a first metal oxide, a third insulating layer provided on the second insulating layer between the semiconductor layer and the first gate electrode, having the same planar shape as the first gate electrode, and containing silicon nitride, and a semiconductor device having the same.

2. A second gate electrode provided between the insulating surface and the semiconductor layer, and a fourth insulating layer provided between the second gate electrode and the semiconductor layer, the semiconductor device according to claim 1, further comprising the same.

3. The semiconductor device according to claim 1, wherein the semiconductor layer contains an oxide semiconductor.

4. The semiconductor device according to claim 1, wherein the semiconductor layer contains an oxide semiconductor having a polycrystalline structure.

5. A second gate electrode provided between the insulating surface and the semiconductor layer, a fourth insulating layer provided between the second gate electrode and the semiconductor layer and containing silicon nitride, a fifth insulating layer provided between the fourth insulating layer and the semiconductor layer and containing silicon oxide, and a sixth insulating layer provided between the fifth insulating layer and the semiconductor layer and containing a second metal oxide, further comprising the same, The semiconductor device according to claim 1, wherein the semiconductor layer contains an oxide semiconductor having a polycrystalline structure.

6. The semiconductor device according to claim 5, wherein the first metal oxide and the second metal oxide are metal oxides mainly composed of aluminum.

7. The semiconductor device according to claim 6, wherein the thickness of the second insulating layer is 1 nm or more and 20 nm or less.

8. The thickness of the first insulating layer is 50 nm or more and 200 nm or less, The semiconductor device according to claim 5, wherein the thickness of the third insulating layer is 50 nm or more and 300 nm or less.

9. A seventh insulating layer provided on the first gate electrode, covering a pattern end of the first gate electrode, and containing silicon nitride, and an eighth insulating layer provided on the seventh insulating layer and containing silicon oxide, the semiconductor device according to claim 5, further comprising the same.

10. The semiconductor device according to any one of claims 1 to 9, and A photoelectric conversion layer connected to the semiconductor device, A radiation detection device having a wavelength conversion layer that faces the photoelectric conversion layer and emits visible light based on the absorbed radiation.

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