Semiconductor device

Abstract

To provide a semiconductor device that permits stable data input and output while not requiring calibration of an output buffer having an ODT function.SOLUTION: This semiconductor device includes: an input and output pad that inputs and outputs data; an input buffer that temporarily holds an input data signal from the input and output pad; an output buffer that is configured to temporarily hold an output data signal outputted to the input and output pad and forms a terminating resistor in a period of disuse for data output; a replica circuit that has the same configuration as that of the output buffer; and a switching circuit that selectively supplies the input buffer with, as a threshold voltage, a first reference voltage outputted by the replica circuit and a second reference voltage based on a supply voltage.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] In a semiconductor device that inputs and outputs data via input / output pads to a large-scale semiconductor integrated circuit such as a DRAM (Dynamic Random Access Memory), it is known that an output buffer becomes an open end, causing signal reflection and degrading signal quality. Therefore, a technique (On-Die Termination, ODT) for suppressing signal reflection by causing an output buffer that is unused during a write operation to function as a termination resistor is widely known. By using ODT, it becomes unnecessary to provide a termination resistor on the motherboard, the number of components in the semiconductor device can be reduced, and signal reflection can be more effectively prevented, thereby improving the signal quality on the external bus.

[0003] To maintain communication quality, calibration of an output buffer having an ODT function is required. For example, a calibration mechanism that refers to an external resistor or the like is separately mounted, and calibration of the output buffer is executed based on reference data. Thereby, even when the manufacturing conditions and usage conditions of the circuit and system fluctuate, the output characteristics of the output buffer can be made constant. However, when calibration is performed at the time of starting up the DRAM, there is a problem that the start-up time increases and the operating performance of the DRAM deteriorates. The same problem can occur in semiconductor devices other than DRAMs.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] An object of the present invention is to provide a semiconductor device that enables stable data input / output without requiring calibration of an output buffer having an ODT function.

Means for Solving the Problems

[0006] The semiconductor device according to the present invention includes an input / output pad for inputting and outputting data, an input buffer for temporarily holding an input data signal from the input / output pad, and an output buffer configured to temporarily hold an output data signal output to the input / output pad and configured to form a termination resistor during a period when it is not used for data output, a replica circuit having the same configuration as the output buffer, a first reference voltage output by the replica circuit, and a switching circuit that selectively supplies the first reference voltage and a second reference voltage based on a power supply voltage to the input buffer as a threshold voltage.

[0007] According to the present invention, it is possible to provide a semiconductor device that enables stable data input / output without requiring calibration of an output buffer having an ODT function.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 4A

Figure 4B

Figure 5

Best Mode for Carrying Out the Invention

[0009] Hereinafter, each embodiment for carrying out the present invention will be described with reference to the drawings. The same or similar parts are denoted by the same or similar reference numerals, and redundant descriptions are omitted. Note that various plan views and cross-sectional views may be drawn at dimensional ratios different from those of the actual product in the horizontal plane and the cross-section for ease of understanding. Also, in the plan view and the cross-sectional view, they may be illustrated at different dimensional ratios for ease of understanding and ease of illustration.

[0010] [First Embodiment] First, with reference to FIG. 1, a semiconductor device according to the first embodiment will be described. This semiconductor device is, as an example, a Dynamic Random Access Memory (DRAM) 10. The DRAM 10 is roughly composed of a memory core 11, an input buffer 12, an output buffer 13, an ODT control circuit 14, a replica circuit 15, a switching circuit 16, and an input / output pad Td. The DRAM 10 includes a plurality of input / output pads Td, and an input buffer 12 and an output buffer 13 are provided for each input / output pad Td. However, in FIG. 1, for simplicity of illustration, only one input / output pad Td, input buffer 12, and output buffer 13 are shown. Also, the elements 11 to 16 shown in FIG. 1 may be integrally formed on a single chip, or may be formed by being divided into a plurality of chips. Hereinafter, the DRAM will be described as an example, but the configurations described in the following embodiments can also be adopted in semiconductor devices other than the DRAM.

[0011] The memory core 11 includes, in addition to a memory cell array in which DRAM memory cells are arranged, a decoder for selecting memory cells, a sense amplifier, a latch circuit, and the like. The input buffer 12 is a data holding circuit that temporarily holds write data input for writing data to the memory core 11. For example, an operational amplifier circuit that amplifies the difference between an input voltage and a reference voltage and outputs it can be used as the input buffer 12. Also, the output buffer 13 is a data holding circuit that temporarily holds read data read from the memory core 11. As an example, the output buffer 13 includes a first transistor T1, a pull-up resistor R1, a pull-down resistor R2, and a second transistor T2 connected in series, and a plurality of such series circuits are connected in parallel across a first power supply node to which a power supply voltage VDDQ is applied and a second power supply node to which a ground voltage VSSQ (= 0V) is applied.

[0012] The pull-up resistor R1 and the pull-down resistor R2 are given resistance values Rpu and Rpd. When Rpu = Ppd, the output buffer 13 can output a voltage VDDQ / 2 from the output node.

[0013] The ODT control circuit 14 outputs an activation signal EN for activating the ODT function in accordance with the ODT signal ODTen. When the activation signal EN = "H", the output buffer 13 is used as a termination resistor. When the activation signal EN = "L", the output buffer 13 is disconnected from the data bus and is not used as a termination resistor.

[0014] The replica circuit 15 has the same configuration as the output buffer 13. As an example, similar to the output buffer 13, between the first power supply node (power supply voltage VDDQ) and the second power supply node (ground voltage VSSQ), there are a first transistor T1r having the same characteristics as the first transistor T1, a pull-up resistor R1r having the same characteristics as the pull-up resistor R1, a pull-down resistor R2r having the same characteristics as the pull-down resistor R2, and a series circuit of a second transistor T2r having the same characteristics as the second transistor T2 connected in parallel over a plurality of stages. The replica circuit 15 outputs the same voltage VTT_R as the voltage VTT output by the output buffer 13 under the same bias conditions.

[0015] When the ODT function is turned off, the switching circuit 16 sets the reference voltage Vref supplied to the input buffer 12 to VDDQ / 2 (second reference voltage), which is half of the power supply voltage VDDQ. On the other hand, when the ODT function is turned on, the switching circuit 16 sets the reference voltage Vref to the voltage VTT_R (first reference voltage) output by the replica circuit 15. Thus, the switching circuit 16 has a function of switching the value of the reference voltage Vref supplied to the input buffer 12 between VTT_R and VDDQ / 2 according to the on / off state of the ODT function.

[0016] An example of the circuit configuration of the switching circuit 16 will be described with reference to FIG. 2. As an example, the switching circuit 16 is composed of transfer gates 111, 112, and an inverter 113. The transfer gate 111 is supplied with the voltage VTT_R output by the replica circuit 15 at the input terminal, and the output terminal is the output terminal to the input buffer 12. An activation signal EN is applied to one gate (gate of the NMOS transistor) of the transfer gate 111, and an activation signal / EN is applied to the other gate (gate of the PMOS transistor) via the inverter 113.

[0017] The transfer gate 112 is supplied with the voltage VDDQ / 2 at its input terminal, and its output terminal serves as the output terminal to the input buffer 12. An activation signal / EN is applied to one gate (the gate of the NMOS transistor) of the transfer gate 112 via an inverter 113, and the activation signal EN is applied to the other gate (the gate of the PMOS transistor). Thereby, the reference voltage Vref applied to the input buffer 113 is selectively switched to VTT_R or VDDQ / 2 according to the on / off of the ODT function.

[0018] Here, with reference to FIGS. 3A and 3B, the operation of the comparative example will be described. The DRAM 10 of the comparative example has no replica circuit 15 and switching circuit 16, and the reference voltage Vref applied to the input buffer 12 is fixed at VDDQ / 2. Therefore, in the comparative example, when the ODT function is off (FIG. 3A) or when the ODT function is on (FIG. 3B), the reference voltage Vref supplied to the input buffer 12 is fixed at VDDQ / 2.

[0019] A calibration operation is performed in the output buffer 13. For example, if the resistance values Rpu and Rpd of the pull-up resistor R1 and the pull-down resistor R2 are adjusted to be equal to each other, the voltage VTT output by the output buffer 13 will be equal to VDDQ / 2. However, if the calibration is not performed, for example, when Rpu≠Rpd, the voltage VTT may deviate from VDDQ / 2. In this case, in the input buffer 12, the signal waveform of the write data will oscillate centered around a voltage VTT different from VDDQ / 2, and there is a risk that normal data reception will not be possible.

[0020] Referring to FIGS. 4A and 4B, the operation of the DRAM 10 of the first embodiment will be described. In order to address the problems of the above-described comparative example, the DRAM 10 of the first embodiment has a replica circuit 15 and a switching circuit 16. The operation when the ODT function is off is the same as that of the comparative example, and the voltage supplied from the switching circuit 16 is VDDQ / 2 (FIG. 4A). However, when the ODT function is on, the switching circuit 16 supplies the voltage VTT_R output by the replica circuit 15 to the input buffer 12.

[0021] Since the replica circuit 15 has the same configuration as the output buffer 13 as described above, the output voltage VTT_R is also a replica of the voltage VTT output by the output buffer 13. Without performing calibration of the output buffer 13, the threshold voltage of the input buffer 12 becomes equal to the threshold voltage of the output buffer 13, and the accuracy of data reception when the ODT function is on can be improved.

[0022] As described above, according to the DRAM 10 of the first embodiment, the accuracy of data reception is improved and stable data input / output becomes possible without requiring calibration of the output buffer 13 having the ODT function.

[0023] [Second Embodiment] Next, the DRAM 10 of the second embodiment will be described with reference to FIG. 5. Since the same components as those in FIG. 1 are denoted by the same reference numerals in FIG. 5, redundant descriptions will be omitted below. The DRAM 10 of the second embodiment further includes an output buffer adjustment control circuit 17 for controlling the adjustment of the output buffer 13, which is different from the DRAM 10 of the first embodiment in this regard.

[0024] The output buffer adjustment control circuit 17 adjusts the resistance values Rpu and Rpd of the pull-up resistor R1 and the pull-down resistor R2 of the output buffer 13 and the replica circuit 15 according to the ODT signal ODTen, for example, so that Rpu≈Rpd. Thereby, the thresholds of the output buffer 13 and the replica circuit 15 are controlled to be the same, for example, VDDQ / 2. When the ODT function is turned on, since the output buffer 13 and the replica circuit 15 having the same configuration are similarly controlled to follow by the output buffer adjustment circuit 17, the voltages output by both become equal.

[0025] The present invention is not limited to the above-described embodiments, and various modifications can be made and implemented without departing from the gist of the present invention. And all of them are included in the technical idea of the present invention.

Explanation of reference numerals

[0026] 10 ··· DRAM (semiconductor device) 11 ··· Memory core 12 ··· Input buffer 13 ··· Output buffer 14 ··· ODT control circuit 15 ··· Replica circuit 16 ··· Switching circuit 17 ··· Input / output pad

Claims

1. an input / output pad for inputting and outputting data; an input buffer for temporarily holding an input data signal from the input / output pad; an output buffer configured to temporarily hold an output data signal output to the input / output pad and configured to form a termination resistor during a period when it is not used for data output; a replica circuit having the same configuration as the output buffer; a switching circuit that selectively supplies a first reference voltage output by the replica circuit and a second reference voltage based on a power supply voltage to the input buffer as a threshold voltage A semiconductor device comprising:

2. The semiconductor device according to claim 1, further comprising an output buffer adjustment control circuit that outputs an adjustment signal to the output buffer to adjust a pull-up resistor and a pull-down resistor of the output buffer.

3. The output buffer includes a first transistor connected in series between a first power supply terminal and a second power supply terminal, the pull-up resistor, the pull-down resistor, and a second transistor, and a resistance value of the pull-up resistor or the pull-down resistor is adjusted by the output buffer adjustment control circuit. The semiconductor device according to claim 2.

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