Manufacturing method of semiconductor device

Abstract

To avoid a damage of a semiconductor chip by preventing a contact of the semiconductor chip with a dowel of a lead frame in a manufacturing step.SOLUTION: A manufacturing method of a semiconductor device, sequentially executes: a mounting step of mounting a chip or the like to a horizontal tool; a reflow step of solidifying them after melting and cooling them by heating an upper solder and a lower solder, and thus integrating an upper lead frame, a chip, and a lower lead frame; and a cutting step of cutting an unnecessary portion of the upper lead frame and the lower lead frame. The upper lead frame includes an upper dowel to be projected toward the chip to a position opposite to the chip, and the lower lead frame includes a lower dowel to be projected toward the chip at a position opposite to the chip. In the reflow step, the upper lead frame is held so that a lower surface of the upper dowel and an upper surface of a lower dowel are parallel by a pair of vertical parts. In the cutting step, one side of the vertical parts is cut as an unnecessary portion.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device in which a semiconductor chip is disposed between lead frames.

Background Art

[0002] As a semiconductor device in which a semiconductor chip is disposed between lead frames, the semiconductor device of Patent Document 1 is known. For example, in the abstract of the same document, it is described that "a dabo 2 which is a mounting table is formed on a lead frame 1, and electrodes 6 on both surfaces of a semiconductor chip 3 are fixed to both dabos 2 with solder 4 respectively. Further, the shape of the dabo 2 is a quadrangle substantially similar to the electrode of the semiconductor chip 3. The area of this dabo is set to be 80% or more of the area of the electrode of the semiconductor chip, and the height of the dabo is set to be at least 0.15 mm."

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Regarding the method for manufacturing a semiconductor device, in paragraph 0002 of Patent Document 1, it is described that "in FIG. 4, the lead frame 1 has a dabo 2 which is a mounting table for fixing the semiconductor chip 3 and has a size that is fixed to the electrode of the planar semiconductor chip 3 and does not contact the surface protection film of the semiconductor chip 3." That is, the dabo in Patent Document 1 is described as not being intended to contact the surface protection film of the semiconductor chip. This is presumably to avoid damage to the surface of the semiconductor chip when the metal dabo contacts the semiconductor chip.

[0005] However, Patent Document 1 does not specifically explain how to prevent contact between the dabo of the lead frame and the semiconductor chip during the manufacturing process of the semiconductor device.

[0006] Therefore, an object of the present invention is to provide a method for manufacturing a semiconductor device that can avoid damage to a semiconductor chip by preventing contact between a dabo of a lead frame and the semiconductor chip during the manufacturing process of the semiconductor device.

Means for Solving the Problems

[0007] To solve the above problems, a method for manufacturing a semiconductor device according to the present invention includes a mounting step of mounting a lower lead frame, a lower solder, a chip, an upper solder, and an upper lead frame in this order on a horizontal jig, and after heating and melting the upper solder and the lower solder and then cooling and solidifying them, a reflow step of integrating the upper lead frame, the chip, and the lower lead frame, and a cutting step of cutting unnecessary portions of the upper lead frame and the lower lead frame. In the reflow step, the upper lead frame is held such that the lower surface of the upper dabo and the upper surface of the lower dabo are parallel by a pair of vertical portions. In the cutting step, one of the vertical portions is cut as an unnecessary portion.

Effects of the Invention

[0008] According to the method for manufacturing a semiconductor device of the present invention, contact between the dabo of the lead frame and the semiconductor chip during the manufacturing process can be prevented, and damage to the semiconductor chip can be avoided.

Brief Description of the Drawings

[0009]

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Embodiments for Carrying Out the Invention

[0010] Hereinafter, embodiments of the method for manufacturing a semiconductor device of the present invention will be described with reference to the drawings.

Examples

[0011] First, with reference to FIGS. 1 to 6, a method for manufacturing a semiconductor device according to Example 1 of the present invention will be described.

[0012] <Schematic Structure of Semiconductor Device 100> FIG. 1 is an external perspective view of a semiconductor device 100 manufactured by the manufacturing method of this embodiment, and FIG. 2 is a cross-sectional view of the semiconductor device 100 taken along plane A of FIG. 1. As shown in FIG. 2, the semiconductor device 100 has an upper lead frame 1, an upper solder 2, a chip 3, a lower solder 4, a lower lead frame 5, and a sealing resin 6. Each will be sequentially described below.

[0013] The chip 3 is a semiconductor element according to the function of the semiconductor device 100, and is, for example, a Zener diode.

[0014] The upper lead frame 1 is a rigid body such as copper that is electrically connected to the upper surface of the chip 3 via the upper solder 2. In order to adjust the coating area and thickness of the upper solder 2, a circular upper boss 1a protruding toward the chip 3 is provided at a position facing the chip 3.

[0015] The lower lead frame 5 is a rigid body such as copper that is electrically connected to the lower surface of the chip 3 via the lower solder 4. In order to adjust the coating area and thickness of the lower solder 4, a circular lower boss 5a protruding toward the chip 3 is provided at a position facing the chip 3.

[0016] The sealing resin 6 is an insulator that seals the upper lead frame 1, the chip 3, and the lower lead frame 5 after electrically connecting the three by a reflow process.

[0017] <Manufacturing Procedure of Semiconductor Device 100> Here, the manufacturing procedure of the semiconductor device 100 will be briefly described.

[0018] First, a mounting process is performed using a mounter to mount the lower lead frame 5, the lower solder 4, the chip 3, the upper solder 2, and the upper lead frame 1 in this order on a horizontal jig. Note that the forms of the upper lead frame 1 and the lower lead frame 5 at this point will be described later.

[0019] Next, using a reflow apparatus, the upper solder 2 and the lower solder 4 are heated and melted, and then cooled and solidified to perform a reflow process for integrating the upper lead frame 1, the chip 3, and the lower lead frame 5.

[0020] Thereafter, using a cutting apparatus, a cutting process is performed to cut unnecessary portions of the upper lead frame 1 and the lower lead frame 5.

[0021] Finally, using a resin encapsulation apparatus, the integrated upper lead frame 1 to the lower lead frame 5 is encapsulated with an encapsulation resin 6, and using a bending apparatus, a finishing process is performed to bend the terminals of the upper lead frame 1 and the lower lead frame 5 protruding from the encapsulation resin 6 into a desired shape.

[0022] By the above manufacturing procedure, the semiconductor device 100 in the state illustrated in FIGS. 1 and 2 can be manufactured.

[0023] <Problems Caused by Abnormality in Parallelism between Chip 3 and Lead Frame> Next, problems caused by an abnormality in the parallelism between the chip 3 and the upper and lower lead frames will be described.

[0024] FIG. 3 is an enlarged cross-sectional view of the semiconductor device 100 during the reflow process by a conventional manufacturing method, and illustrates an ideal state in which the upper lead frame 1, the chip 3, and the lower lead frame 5 are arranged in parallel. As shown in the figure, when the height of the upper boss 1a of the upper lead frame 1 is x1, the film thickness of the upper solder 2 is y1, the thickness of the chip 3 is T, the film thickness of the lower solder 4 is y2, and the height of the lower boss 5a of the lower lead frame 5 is x2, the relationship between these and the distance L between the upper and lower lead frames excluding the boss portions is expressed by the following Equation 1.

[0025] L = x1 + y1 + T + y2 + x2 ··· (Equation 1) Therefore, if the distance L is maintained, the lower surface of the upper die 1a is parallel to the upper surface of the chip 3, and the lower surface of the chip 3 is parallel to the upper surface of the lower die 5a, and the arrangement of the upper and lower lead frames during the reflow process can be maintained, the upper and lower solder film thicknesses of the chip 3 will be uniformly the designed solder film thicknesses x1 and x2. Therefore, the chip 3 will not come into contact with the upper die 1a or the lower die 5a and be damaged.

[0026] However, if the reflow process is started with the upper lead frame 1 and the lower lead frame 5 inclined with respect to the upper and lower surfaces of the chip 3, above the chip 3, the lower end corner of the upper die 1a that has moved downward within the molten upper solder 2 may come into contact with the chip 3 and damage the upper surface of the chip 3. Similarly, below the chip 3, the chip 3 that has moved downward within the molten lower solder 4 may come into contact with the upper end corner of the lower die 5a and damage the lower surface of the chip 3.

[0027] Therefore, during the reflow process, it is necessary to avoid contact between the chip 3 and the upper and lower lead frames caused by the melting of the upper and lower solders by maintaining the parallelism between the chip 3 and the upper and lower lead frames normally. Hereinafter, a method for manufacturing the semiconductor device 100 of the present embodiment that realizes normal maintenance of the parallelism between the chip 3 and the upper and lower lead frames during the reflow process will be described.

[0028] <Method for manufacturing a semiconductor device of the present embodiment> FIG. 4 is a cross-sectional view showing the reflow process of the manufacturing method of the present embodiment, and the reference symbol C indicates the position where the upper and lower lead frames are cut in the subsequent cutting process. Note that the upper and lower lead frames in FIG. 4 are assumed to be mounted on a horizontal jig (not shown).

[0029] As shown here, a pair of vertical portions 1b are formed on the upper lead frame 1 during the reflow process. The vertical portion 1b on the right side in the figure is longer by the thickness of the lower lead frame 5 compared to the vertical portion 1b on the left side in the figure. Therefore, the heights of the upper ends of the vertical portion 1b on the right side on the horizontal jig and the upper ends of the vertical portion 1b on the left side on the lower lead frame 5 are equal, and the upper surface of the upper lead frame 1 and the lower surface of the upper dowel 1a become horizontal. Also, since the lower lead frame 5 is mounted on a horizontal jig, the lower surface of the lower lead frame 5 and the upper surface of the lower dowel 5a become horizontal. As a result, the lower surface of the upper dowel 1a and the upper surface of the lower dowel 5a are parallel, and the chip 3 disposed therebetween and sandwiched by the melted upper and lower solder is also parallel to the lower surface of the upper dowel 1a and the upper surface of the lower dowel 5a.

[0030] By the above mechanism, during the reflow process of the manufacturing method of this embodiment, contact between the chip 3 and the upper and lower dowels is prevented, and breakage of the chip 3 can be avoided.

[0031] <Shape of the lead frame before cutting> Next, with reference to FIGS. 5 and 6, the shape of the lead frame before cutting will be described.

[0032] FIG. 5 is a plan view (left figure) and a side view (right figure) of the upper lead frame 1 before cutting. As shown in the plan view, a plurality of terminals are formed on the upper lead frame 1, and an upper dowel 1a is formed on each terminal. Also, as shown in the side view, a pair of vertical portions 1b are formed on each terminal.

[0033] FIG. 6 is a plan view (left figure) and a side view (right figure) of the lower lead frame 5 before cutting. As shown in the plan view, a plurality of terminals are formed on the lower lead frame 5, and a lower dowel 5a is formed on each terminal. Also, as shown in the side view, each terminal is formed flat.

[0034] <Effect of this embodiment> According to the manufacturing method of the semiconductor device of this embodiment described above, contact between the dowel of the lead frame and the semiconductor chip during the manufacturing process can be prevented, and breakage of the semiconductor chip can be avoided.

Example

[0035] Next, with reference to FIGS. 7 to 9, a method for manufacturing a semiconductor device according to Example 2 of the present invention will be described. Note that redundant descriptions of the common points with Example 1 will be omitted.

[0036] FIG. 7 is a cross-sectional view showing a reflow process of the manufacturing method of this example. As shown here, on the upper lead frame 1 during the reflow process, a pair of vertical portions 1b are formed. In Example 1, as shown in FIG. 4, the vertical portion 1b on the right side in the figure was directly mounted on a jig, but in this example, the vertical portion 1b on the right side in the figure is mounted on the lower lead frame 5. Therefore, in Example 1, the lengths of the left and right vertical portions 1b were different, but in this example, the lengths of the left and right vertical portions 1b are made equal. In this case, although the cutting locations of the lower lead frame 5 in the cutting process increase, the parallelism between the upper die 1a and the lower die 5a can be further improved, so the possibility of damaging the chip 3 can be further suppressed.

[0037] FIG. 8 is a plan view (left figure) and a side view (right figure) of the upper lead frame 1 before cutting. The upper lead frame 1 shown here has the same form as the upper lead frame 1 in FIG. 5, except that the lengths of the pair of vertical portions 1b provided at each terminal are equal.

[0038] FIG. 9 is a plan view (left figure) and a side view (right figure) of the lower lead frame 5 before cutting. The lower lead frame 5 shown here has the same form as the lower lead frame 5 in FIG. 6, except that the tips of each terminal are extended.

Example

[0039] Next, with reference to FIGS. 10 to 12, a method for manufacturing a semiconductor device according to Example 3 of the present invention will be described. Note that redundant descriptions of the common points with the above-described examples will be omitted.

[0040] FIG. 10 is a cross-sectional view showing the reflow process of the manufacturing method of this embodiment. As shown here, in the upper lead frame 1 during the reflow process, a vertical portion 1b is formed on the right side in the figure, and in the lower lead frame 5, a vertical portion 5b is formed on the left side in the figure. The structure combining the vertical portion 1b and the vertical portion 5b in this embodiment undertakes the same function as the pair of vertical portions 1b in Embodiment 1. Therefore, the lower surface of the upper die 1a and the upper surface of the lower die 5a can be made parallel by the same mechanism as in Embodiment 1, and damage to the chip 3 can be prevented. Furthermore, compared with Embodiment 1, the number of cutting locations in the subsequent cutting process can also be reduced.

[0041] FIG. 11 is a plan view (left figure) and a side view (right figure) of the upper lead frame 1 before cutting. The upper lead frame 1 shown here has the same form as the upper lead frame 1 in FIG. 5, except that a vertical portion 1b is not provided at the tip side of each terminal.

[0042] FIG. 12 is a plan view (left figure) and a side view (right figure) of the lower lead frame 5 before cutting. The lower lead frame 5 shown here has the same form as the lower lead frame 5 in FIG. 6, except that a portion for forming the vertical portion 5b extends between each terminal.

Embodiment

[0043] Next, with reference to FIGS. 13 to 15, a manufacturing method of a semiconductor device according to Embodiment 4 of the present invention will be described. Note that duplicate descriptions of the common points with the above-described embodiments will be omitted.

[0044] FIG. 13 is a cross-sectional view showing the reflow process of the manufacturing method of this embodiment. As shown here, in the upper lead frame 1 during the reflow process, a vertical portion 1b is formed on the right side in the figure, and in the lower lead frame 5, a vertical portion 5b is formed on the left side in the figure. In Embodiment 3, the vertical portion 1b was directly mounted on a horizontal jig, but in this embodiment, similar to Embodiment 2, the vertical portion 1b is mounted on the lower lead frame 5. Therefore, in this embodiment, both the effects according to Embodiment 2 and the effects according to Embodiment 3 can be obtained.

[0045] Figure 14 is a plan view (left figure) and a side view (right figure) of the upper lead frame 1 before cutting. The upper lead frame 1 shown here has the same form as the upper lead frame 1 in FIG. 11.

[0046] Figure 15 is a plan view (left figure) and a side view (right figure) of the lower lead frame 5 before cutting. The lower lead frame 5 shown here has the same form as the lower lead frame 5 in FIG. 12, except that the tips of the respective terminals are extended.

Explanation of reference numerals

[0047] 100 Semiconductor device 1 Upper lead frame 1a Upper boss 1b Vertical part 2 Upper solder 3 Chip 4 Lower solder 5 Lower lead frame 5a Lower boss 5b Vertical part 6 Encapsulating resin

Claims

1. A mounting step of mounting a lower lead frame, a lower solder, a chip, an upper solder, and an upper lead frame in this order on a horizontal jig, a reflow step of heating and melting the upper solder and the lower solder and then cooling and solidifying them to integrate the upper lead frame, the chip, and the lower lead frame, and a cutting step of cutting unnecessary portions of the upper lead frame and the lower lead frame, which is a method for manufacturing a semiconductor device in which the steps are sequentially performed, wherein the upper lead frame has an upper stud protruding toward the chip at a position facing the chip, the lower lead frame has a lower stud protruding toward the chip at a position facing the chip, in the reflow step, the upper lead frame is held such that the lower surface of the upper stud and the upper surface of the lower stud are parallel by a pair of vertical portions, and in the cutting step, one of the vertical portions is cut as an unnecessary portion, which is a method for manufacturing a semiconductor device.

2. In the method for manufacturing a semiconductor device according to Claim 1, the pair of vertical portions are provided at terminals of the upper lead frame so as to sandwich the upper stud, which is a method for manufacturing a semiconductor device.

3. In the method for manufacturing a semiconductor device according to Claim 2, one of the pair of vertical portions is mounted on the horizontal jig, and the other of the pair of vertical portions is mounted on the lower lead frame, which is a method for manufacturing a semiconductor device.

4. In the method for manufacturing a semiconductor device according to Claim 2, both of the pair of vertical portions are mounted on the lower lead frame, which is a method for manufacturing a semiconductor device.

5. In the method for manufacturing a semiconductor device according to Claim 1, one of the pair of vertical portions is provided at a terminal of the upper lead frame, and the other of the pair of vertical portions is provided between terminals of the lower lead frame, which is a method for manufacturing a semiconductor device.

6. In the method for manufacturing a semiconductor device according to Claim 5, both of the pair of vertical portions are mounted on the horizontal jig, which is a method for manufacturing a semiconductor device.

7. In the method for manufacturing a semiconductor device according to Claim 5, one of the pair of vertical portions is mounted on the lower lead frame, and the other of the pair of vertical portions is mounted on the horizontal jig, which is a method for manufacturing a semiconductor device.

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