Transparent display device

Abstract

To provide a transparent display device having a high light transmittance and capable of improving reflection characteristics.SOLUTION: A transparent display device according to one or more embodiments of this specification may include a substrate including a non-transmissive area having a light-emitting area in which a light-emitting element is arranged and a transmissive area, at least one gate line crossing the non-transmissive area and the transmissive area on the substrate, and a gate bridge pattern arranged in the transmissive area on the substrate and at least partially overlapping at least one gate line.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a transparent display device.

Background Art

[0002] As the information society develops, the requirements for display devices for displaying images are increasing in various forms. Accordingly, in recent years, display devices such as liquid crystal displays (LCDs), organic light-emitting displays (OLEDs), micro light-emitting diode displays (Micro LED Displays), and quantum dot displays (QDs) have been utilized.

[0003] Recently, research on transparent display devices that can not only display images for users but also transmit light to view things and images located on the back side of the display device has been actively conducted. The transparent display device includes a display area where an image is displayed and a non-display area, and the display area can include a transmissive area and a non-transmissive area that can transmit external light. The transparent display device can have a high light transmittance in the display area through the transmissive area.

[0004] Such transparent display devices have high applicability in various fields in that images and backgrounds can be viewed together, but due to the diverse fields and applications to which they are applied, it is necessary to manufacture them in multiple varieties (or various sizes). However, when manufacturing transparent display devices in multiple varieties (or various sizes), there is a problem that the manufacturing cost and production energy increase due to an increase in the number of processes.

Summary of the Invention

Problems to be Solved by the Invention

[0005] One problem to be solved by one or more embodiments of the present specification is to provide a transparent display device having a high light transmittance and capable of improving reflectance characteristics.

[0006] One problem to be solved by one or more embodiments of the present specification is to provide a transparent display device that can be manufactured in multiple varieties (or various sizes).

[0007] The problems to be solved by one or more embodiments of the present specification are not limited to the above problems, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] A transparent display device according to one or more embodiments of the present specification may include a substrate including a non-transmissive region and a transmissive region including a light-emitting region where light-emitting elements are arranged, at least one gate line crossing the non-transmissive region and the transmissive region on the substrate, and a gate bridge pattern arranged in the transmissive region on the substrate and at least partially overlapping with the at least one gate line.

[0009] Specific matters according to various examples of the present specification other than the means for solving the problems mentioned above are included in the following description and drawings.

[0010] According to an embodiment of the present specification, a transparent display device having a high light transmittance and capable of improving reflectance characteristics can be provided.

[0011] According to an embodiment of the present specification, a transparent display device that can be manufactured in multiple varieties (or various sizes) can be provided.

[0012] The effects of the present specification are not limited to the effects mentioned above, and other effects not mentioned will be clearly understood by those skilled in the art from the following description.

[0013] The content of the invention described in the problem to be solved, the means for solving the problem, and the effects above does not specify the essential features of the claims. Therefore, the scope of rights of the claims is not limited by the matters described in the content of the invention.

Brief Description of the Drawings

[0014]

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Mode for Carrying Out the Invention

[0015] The advantages and features of this specification, and the methods for achieving them, will become apparent by referring to the embodiments described in detail hereinafter together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, but can be embodied in various different forms, and the present embodiments are merely provided to make the disclosure of this specification complete and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of the invention. This specification is only defined by the scope of the claims.

[0016] The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, and this specification is not limited to the matters shown in the drawings. Throughout the specification, the same reference numerals refer to the same components. Also, in the description of this specification, when it is determined that a specific description of related known technologies may unnecessarily obscure the gist of this specification, the detailed description thereof will be omitted.

[0017] When terms such as "including", "having", "consisting of", etc. mentioned in this specification are used, other parts can be added unless "only" is used. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0018] In interpreting a component, even if there is no separate explicit description of the error range, it is interpreted as including the error range.

[0019] In the case of an explanation of the positional relationship, for example, when the positional relationship between two parts is explained by "on", "above", "below", "beside", etc., unless an expression such as "immediately" or "directly" is used, one or more other parts can also be located between the two parts.

[0020] In the case of an explanation regarding the relationship of time, for example, when the chronological relationship is explained by expressions such as "after ~", "subsequent to ~", "next to ~", "before ~", etc., unless the expressions "immediately" or "directly" are used, it can include cases that are not continuous.

[0021] The first, second, etc. are used to explain various components, but these components are not limited by these terms. These terms are merely used to distinguish one component from another. Therefore, the first component mentioned below may be the second component within the technical idea of this specification.

[0022] In explaining the components of this specification, terms such as the first, second, A, B, (a), or (b) can be used. Such terms are only for distinguishing the component from other components, and the essence, order, sequence, or number of the component, etc. are not limited by the terms.

[0023] When a component is described as "connected", "coupled", "joined", or "attached" to another component, the component can be directly connected, coupled, joined, or attached to the other component, but it should be understood that other components may "intervene" between the components that can be indirectly connected, coupled, joined, or attached without specific explicit description.

[0024] When a component or layer is described as "contacting" or "overlapping" another component or layer, the component or layer can directly contact or overlap the other component or layer, but it should be understood that other components may intervene between the components that can indirectly contact or overlap without specific explicit description.

[0025] The term "at least one" shall be understood to include all combinations of one or more of the related components. For example, the meaning of "at least one of the first, second, and third components" can include not only the first, second, or third component alone, but also all combinations of two or more of the first, second, and third components.

[0026] The features of each of several embodiments herein can be combined or combined with each other partially or wholly, various linkages and drives are technically possible, and each embodiment can be implemented independently of each other or implemented together in an associated relationship.

[0027] Hereinafter, the embodiments herein will be described in detail through the accompanying drawings and examples. The scale of the components shown in the drawings has a scale different from the actual one for the convenience of explanation, and thus is not limited to the scale shown in the drawings.

[0028] FIG. 1 is a diagram showing a transparent display device according to an embodiment herein. FIG. 2 is a circuit diagram of a sub-pixel of the transparent display device according to an embodiment herein.

[0029] Hereinafter, the X-axis indicates a direction parallel to the scan line, the Y-axis indicates a direction parallel to the data line, and the Z-axis indicates the height direction of the transparent display device.

[0030] The transparent display device according to an embodiment herein has been mainly described as being implemented by an Organic Light Emitting Display (OLED), but it can also be implemented by a Liquid Crystal Display (LCD), a Micro Light Emitting Diode (Micro LED Display), a Quantum Dot Display (QD), etc.

[0031] Referring to FIGS. 1 and 2, a transparent display device according to an embodiment of the present specification may include a transparent display panel 110 including a display area (DA) where pixels are formed to display an image and a non-display area (NDA) where no image is displayed.

[0032] The display area (DA) of the transparent display panel 110 may include a first signal line (SL1), a second signal line (SL2), and pixels, and the non-display area (NDA) may include a pad area (PA) where pads are disposed and at least one gate driving unit 205.

[0033] The first signal line (SL1) may extend in a first direction (or Y-axis direction) and may intersect the second signal line (SL2) in the display area (DA). The second signal line (SL2) may extend in a second direction (or X-axis direction). The pixels are disposed in an area where the first signal line (SL1) and the second signal line (SL2) intersect and may emit predetermined light to display an image.

[0034] The gate driving unit 205 may be connected to a scan line to supply a scan signal. Such a gate driving unit 205 may be implemented in a GIP (gate driver in panel) method or a TAB (tape automated bonding) method in a non-display area (NDA) outside one or both sides of the display area (DA) of the transparent display panel 110.

[0035] In the pad area (PA) of the transparent display panel 110, a source drive integrated circuit, a circuit board, or a timing control unit, etc., which are connected via a flexible circuit film, may be electrically connected.

[0036] Referring to FIG. 2, each pixel may include a plurality of sub-pixels that constitute a unit pixel, and each of the plurality of sub-pixels may include a circuit element having a 3T (Transistor) 1C (Capacitor) structure including a first switching transistor (TR1), a second switching transistor (TR2), a driving transistor (DTR), and a capacitor (Cst), and a light emitting element (ED), but is not necessarily limited thereto. Each sub-pixel may further include a compensation circuit, and in such a case, may have various structures such as 4T2C, 5T2C, 6T1C, 6T2C, 7T1C, 7T2C, etc.

[0037] Each of the transistors (DTR, TR1, TR2) of each sub-pixel may include a gate electrode, a source electrode, and a drain electrode. Since the source electrode and the drain electrode are not fixed and can be changed according to the direction of the voltage and current applied to the gate electrode, either one of the source electrode and the drain electrode can be represented by a first electrode, and the remaining one can be represented by a second electrode. Each of the transistors (DTR, TR1, TR2) of each sub-pixel may use at least one of a polysilicon semiconductor, an amorphous silicon semiconductor, and an oxide semiconductor. The transistors (DTR, TR1, TR2) may be P-type or N-type, or may mix P-type and N-type.

[0038] The first switching transistor (TR1) can serve to supply the data voltage (Vdata) supplied from the data line (DL) to the driving transistor (DTR). For example, the first switching transistor (TR1) can charge the capacitor (Cst) with the data voltage (Vdata) supplied from the data line (DL). For this purpose, the gate electrode of the first switching transistor (TR1) can be connected to the scan line (SCANL) (or gate line), and the first electrode can be connected to the data line (DL). Also, the second electrode of the first switching transistor (TR1) can be connected to one end of the capacitor (Cst) and the gate electrode of the driving transistor (DTR).

[0039] The first switching transistor (TR1) can be turned on in response to a scan signal (Scan) applied via a scan line (SCANL) (or a gate line). When the first switching transistor (TR1) is turned on, a data voltage (Vdata) applied via a data line (DL) can be transmitted to one end of a capacitor (Cst).

[0040] The second switching transistor (TR2) can serve to supply a reference voltage (Vref) supplied from a reference line (REFL) to a driving transistor (DTR). For example, the second switching transistor (TR2) can have its gate electrode connected to the scan line (SCANL) (or the gate line) and its first electrode connected to the reference line (REFL). Also, the second switching transistor (TR2) can have its second electrode connected to the first electrode of the driving transistor (DTR) and the other end of the capacitor (Cst).

[0041] The second switching transistor (TR2) can be turned on in response to a scan signal (Scan) applied via a scan line (SCANL) (or a gate line). When the second switching transistor (TR2) is turned on, the reference voltage (Vref) applied via the reference line (REFL) can be transmitted to the other end of the capacitor (Cst). Also, the reference voltage (Vref) can be applied to the source electrode of the driving transistor (DTR).

[0042] The capacitor (Cst) can serve to maintain the data voltage (Vdata) supplied to the drive transistor (DTR) for one frame. For example, for the capacitor (Cst), the first electrode can be connected to the gate electrode of the drive transistor (DTR), and the second electrode can be connected to the source electrode of the drive transistor (DTR). The capacitor (Cst) can store a voltage corresponding to the data voltage (Vdata) transmitted through the first switching transistor (TR1), and turn on the drive transistor (DTR) with the stored voltage.

[0043] The drive transistor (DTR) can serve to generate a data current from the first power supply (EVDD) supplied from the pixel power supply line (VDDL) and supply it to the anode electrode of the light-emitting element (ED). For example, for the drive transistor (DTR), the gate electrode can be connected to one end of the capacitor (Cst), and the first electrode can be connected to the pixel power supply line (VDDL). Also, the drive transistor (DTR) can connect the second electrode to the anode electrode of the light-emitting element (OLED).

[0044] The drive transistor (DTR) can be turned on by the data voltage charged in the capacitor (Cst). When the drive transistor (DTR) is turned on, the first power supply (EVDD) applied through the pixel power supply line (VDDL) can be transmitted to the anode electrode of the light-emitting element (ED).

[0045] The light-emitting element (ED) can include an anode electrode connected to a driving transistor (DTR), a cathode electrode receiving supply of a second power source (EVSS) from a common power supply line (VSSL), and a light-emitting layer between the anode electrode and the cathode electrode. The anode electrode is an independent electrode for each light-emitting element, while the cathode electrode can be a common electrode shared by the entire light-emitting element. When a driving current is supplied to the light-emitting element (ED) from the driving transistor (DTR), electrons from the cathode electrode are injected into the light-emitting layer, holes from the anode electrode are injected into the light-emitting layer, and fluorescence or phosphorescence substances are caused to emit light by recombination of electrons and holes in the light-emitting layer, thereby generating light of brightness proportional to the current value of the driving current.

[0046] The anode electrode of the light-emitting element (ED) can be connected to the second electrode of the driving transistor (DTR), and the cathode electrode can be connected to the common power supply line (VSSL). The light-emitting element (ED) can emit light corresponding to the driving current generated by the driving transistor (DTR).

[0047] FIG. 3 is a diagram showing the A region shown in FIG. 1 according to an embodiment of the present specification. FIG. 4 is a diagram showing the B region shown in FIG. 3 according to an embodiment of the present specification.

[0048] Referring to FIGS. 3 and 4 in conjunction with FIGS. 1 and 2, the transparent display panel 110 according to an embodiment of the present specification can include a display region (DA) and a non-display region (NDA). The display region (DA) can include a transmissive region (TA) and a non-transmissive region (NTA). The transmissive region (TA) is a region that allows most of the light incident from the outside to pass through, and the non-transmissive region (NTA) can be a region that does not allow most of the light incident from the outside to pass through. For example, the transmissive region (TA) is a region where the light transmittance is greater than α%, and the non-transmissive region (NTA) can be a region where the light transmittance is less than β%. Here, α can be a value greater than β. The transparent display panel 110 allows viewing of things or backgrounds located on the back (or rear surface) of the transparent display panel 110 through the transmissive region (TA).

[0049] The non-transmissive area (NTA) can include a first non-transmissive area (NTA1), a second non-transmissive area (NTA2), and a pixel (P).

[0050] The first non-transmissive area (NTA1) can extend in a first direction (or Y-axis direction) in the display area (DA) and be arranged so as to at least partially overlap with the light-emitting areas (EA1, EA2, EA3, EA4). The first non-transmissive area (NTA1) can be composed of a plurality of them. The plurality of first non-transmissive areas (NTA1) can extend in the first direction (or Y-axis direction) and be arranged spaced apart from each other in a second direction (or X-axis direction). Two adjacent first non-transmissive areas (NTA1) can be arranged spaced apart from each other with the transmissive area (TA) therebetween. For example, the transmissive area (TA) can be arranged between two adjacent first non-transmissive areas (NTA1). A first signal line (SL1) extending in the first direction (or Y-axis direction) can be arranged in the first non-transmissive area (NTA1). For example, the first signal line (SL1) can be arranged so as to overlap with the first non-transmissive area (NTA1).

[0051] The first signal line (SL1) can include at least one of a pixel power supply line (VDDL), a common power supply line (VSSL), a reference line (REFL), and data lines (DL1, DL2, DL3, DL4). For example, the first signal line (SL1) can further include a touch sensor line (TL), but the embodiments of this specification are not limited thereto.

[0052] The pixel power supply line (VDDL) can supply a first power supply (EVDD) to each driving transistor (DTR) of the sub-pixels (SP1, SP2, SP3, SP4) provided in the display area (DA).

[0053] The common power supply line (VSSL) can supply a second power supply (EVSS) to the cathode electrodes of the sub-pixels (SP1, SP2, SP3, SP4) provided in the display area (DA). Here, the second power supply (EVSS) can be a common power supply commonly supplied to the sub-pixels (SP1, SP2, SP3, SP4).

[0054] The reference line (REFL) can supply an initialization voltage (or reference voltage) to each driving transistor (DTR) of the sub-pixels (SP1, SP2, SP3, SP4) provided in the display area (DA). For example, the reference line (REFL) can be arranged between a plurality of data lines (DL1, DL2, DL3, DL4). For example, the reference line (REFL) can be arranged at the center of a plurality of data lines (DL1, DL2, DL3, DL4).

[0055] Each of the data lines (DL1, DL2, DL3, DL4) can supply a data voltage (Vdata) to the sub-pixels (SP1, SP2, SP3, SP4). For example, the first data line (DL1) supplies a first data voltage to the first driving transistor of the first sub-pixel (SP1), the second data line (DL2) supplies a second data voltage to the second driving transistor of the second sub-pixel (SP2), the third data line (DL3) supplies a third data voltage to the third driving transistor of the third sub-pixel (SP3), and the fourth data line (DL4) supplies a fourth data voltage to the fourth driving transistor of the fourth sub-pixel (SP4).

[0056] The touch sensor lines (TL) can be arranged in at least two or more in the first non-transmissive region (NTA1). In the transparent display panel 110, when a plurality of touch sensor lines (TL) are arranged in the transmissive region (TA), the light transmittance may be reduced by the plurality of touch sensor lines (TL). For such a reason, the touch sensor lines (TL) can be arranged in the first non-transmissive region (NTA1) rather than in the transmissive region (TA). For example, the touch sensor lines (TL) can be arranged to overlap at least one of the pixel power supply line (VDDL) and the common power supply line (VSSL) in the first non-transmissive region (NTA1). For example, the touch sensor lines (TL) can be arranged in a layer different from the pixel power supply line (VDDL) and the common power supply line (VSSL). The touch sensor lines (TL) do not need to overlap with the circuit regions (CA1, CA2, CA3, CA4) where circuit elements are arranged, and can be arranged to overlap at least one of the pixel power supply line (VDDL) and the common power supply line (VSSL) or arranged adjacent to each other. For example, a plurality of touch sensor lines can be arranged in the first non-transmissive region (NTA1). For example, when arranging four touch sensor lines, two touch sensor lines can be arranged to overlap or be adjacent to the pixel power supply line (VDDL), and the other two touch sensor lines can be arranged to overlap or be adjacent to the common power supply line (VSSL), but the embodiments of this specification are not limited thereto.

[0057] The second non-transmissive region (NTA2) can be arranged to extend in the second direction (or the X-axis direction) in the display region (DA) so as to at least partially overlap with the light-emitting regions (EA1, EA2, EA3, EA4). For example, the second non-transmissive region (NTA2) can extend in the second direction (or the X-axis direction) between two adjacent first non-transmissive regions (NTA1). The second non-transmissive region (NTA2) can be composed of a plurality of elements. The plurality of second non-transmissive regions (NTA2) can extend in the second direction (or the X-side direction) and be arranged to be spaced apart from each other in the first direction (or the Y-axis direction). Two adjacent second non-transmissive regions (NTA2) can be arranged to be spaced apart from each other with the transmissive region (TA) interposed therebetween. For example, the transmissive region (TA) can be arranged between two adjacent second non-transmissive regions (NTA2). A second signal line (SL2) extending in the second direction (or the X-axis direction) can be arranged in the second non-transmissive region (NTA2). For example, the second signal line (SL2) can be arranged to overlap with the second non-transmissive region (NTA2).

[0058] The second signal line (SL2) can extend in the second direction (or the X-axis direction) and include a scan line (SCANL) (or a gate line). The scan line (SCANL) can supply a scan signal to the sub-pixels (SP1, SP2, SP3, SP4) of the pixel (P).

[0059] Pixels (P) are arranged for each intersection region where the first non-transmissive region (NTA1) and the second non-transmissive region (NTA2) intersect, and can emit light to display an image. Each of the pixels (P) is arranged between adjacent transmissive regions (TA), and the pixel (P) can include light-emitting regions (EA1, EA2, EA3, EA4) where light-emitting elements are arranged to emit light. The light-emitting regions (EA1, EA2, EA3, EA4) can correspond to the regions that emit light in the pixel (P). Since the area of the non-transmissive region (NTA) of the transparent display panel 110 is small, the circuit elements can be arranged so as to overlap with the light-emitting regions (EA1, EA2, EA3, EA4). For example, the light-emitting regions (EA1, EA2, EA3, EA4) can at least partially overlap with circuit regions (CA1, CA2, CA3, CA4) where circuit elements are arranged. For example, the circuit regions (CA1, CA2, CA3, CA4) can include a first circuit region (CA1) where a circuit element connected to the first sub-pixel (SP1) is arranged, a second circuit region (CA2) where a circuit element connected to the second sub-pixel (SP2) is arranged, a third circuit region (CA3) where a circuit element connected to the third sub-pixel (SP3) is arranged, and a fourth circuit region (CA4) where a circuit element connected to the fourth sub-pixel (SP4) is arranged.

[0060] The first to fourth light-emitting regions (EA1, EA2, EA3, EA4) can all emit light of different colors. For example, the first light-emitting region (EA1) can emit green light, the second light-emitting region (EA2) can emit red light, and the third light-emitting region (EA3) can emit blue light. And the fourth light-emitting region (EA4) can emit white light, but is not necessarily limited to this. Also, the arrangement order and arrangement form of each sub-pixel (SP1, SP2, SP3, SP4) can be changed in various ways.

[0061] The transparent display panel 110 according to the embodiments of this specification may include a light-emitting region in which the light-emitting regions (EA1, EA2, EA3, EA4) included in each of the plurality of sub-pixels (SP1, SP2, SP3, SP4) are divided into a plurality. For example, each of the first to fourth light-emitting regions (EA1, EA2, EA3, EA4) may include a first divided light-emitting region and a second divided light-emitting region that are divided into two, but the embodiments of this specification are not limited thereto.

[0062] Each pixel circuit (CA1, CA2, CA3, CA4) of the plurality of sub-pixels (SP1, SP2, SP3, SP4) may include a capacitor (Cst), at least one thin-film transistor (DTR, TR1, TR2), and a light-emitting element (ED), as shown in FIG. 2. For example, at least one thin-film transistor (DTR, TR1, TR2) may include a driving transistor (DTR), a first switching transistor (TR1), and a second switching transistor (TR2). Further, the light-emitting element (ED) may include a first electrode (or an anode electrode, a pixel electrode), a light-emitting layer (or an organic light-emitting layer), and a second electrode (or a cathode electrode, a common electrode).

[0063] The transparent display panel 110 according to the embodiments of this specification may further include at least one undercut line (UCL) extending in a first direction (or the Y-axis direction) in the transmission region (TA).

[0064] At least one undercut line (UCL) can serve to isolate a light-emitting layer (or an organic light-emitting layer) formed in a transmissive region (TA). At least one undercut line (UCL) can be composed of a part of at least one protective layer (for example, a planarization layer and a passivation layer). For example, at least one undercut line (UCL) can be formed by removing at least a part of at least one protective layer (for example, a planarization layer and a passivation layer). A scan line (SCANL) (or a gate line) crossing the transmissive region (TA) can be disposed below at least one undercut line (UCL). A block pattern (BP) can further be included at a portion where at least one undercut line (UCL) and the scan line (SCANL) intersect. For example, the block pattern (BP) can prevent damage to the scan line (SCANL) intersecting below at least one undercut line (UCL) during the process of forming at least one undercut line (UCL).

[0065] At least one undercut line (UCL) can be arranged in the transmissive area (TA) with at least two or more. At least one undercut line (UCL) can be arranged to be adjacent to at least one of the pixel power line (VDDL) and the common power line (VSSL) in the transmissive area (TA). For example, at least one undercut line (UCL) can be arranged to be adjacent to each of the pixel power line (VDDL) and the common power line (VSSL) in the transmissive area (TA). For example, at least one undercut line (UCL) can be composed of a plurality of undercut lines (UCL1, UCL2) in one transmissive area (TA). The plurality of undercut lines (UCL1, UCL2) can include a first undercut line (UCL1) and a second undercut line (UCL2). For example, the first undercut line (UCL1) can be arranged to be adjacent to the pixel (P1) on one side of the transmissive area (TA), and the second undercut line (UCL2) can be arranged to be adjacent to the pixel (P2) on the other side of the transmissive area (TA).

[0066] The first undercut line (UCL1) can sever the light-emitting layer (or organic light-emitting layer) extending from the pixel (P1) on one side of the transmission region (TA), and the second undercut line (UCL2) can sever the light-emitting layer (or organic light-emitting layer) extending from the pixel (P2) on the other side of the transmission region (TA). The region between the first undercut line (UCL1) and the second undercut line (UCL2) can be a region severed from the light-emitting layers (or organic light-emitting layers) of the respective pixels (P1, P2) on one side and the other side of the transmission region (TA). For example, the first undercut line (UCL1) and the second undercut line (UCL2) can be formed by removing at least a part of at least one protective layer (e.g., a planarization layer and a passivation layer). For example, the at least one protective layer can include an organic insulating layer, and the first undercut line (UCL1) and the second undercut line (UCL2) can be configured by removing at least a part of the organic insulating layer to sever the organic insulating layer. Thereby, moisture permeation can be prevented between the pixel (P1) on one side of the transmission region (TA) and the transmission region (TA) by the first undercut line (UCL1), and moisture permeation can be prevented between the pixel (P2) on the other side of the transmission region (TA) and the transmission region (TA) by the second undercut line (UCL2). Therefore, even if the region between the first undercut line (UCL1) and the second undercut line (UCL2) is cut by a cutting device such as a laser or a wheel, moisture permeation to the respective pixels (P1, P2) on one side and the other side of the transmission region (TA) can be prevented.

[0067] According to an embodiment of the present specification, the transparent display panel 110 is configured such that a first undercut line (UCL1) and a second undercut line (UCL2) extend in a first direction (or the Y-axis direction) within a transmissive region (TA), so that moisture permeating toward adjacent pixels (P1) can be prevented by the first undercut line (UCL1), and moisture permeating toward adjacent pixels (P2) can be prevented by the second undercut line (UCL2). Accordingly, the space between the first undercut line (UCL1) and the second undercut line (UCL2) can be a cuttable region that can prevent moisture permeation toward the pixels (P1, P2) even when cut (or separated). Therefore, the transparent display panel 110 according to an embodiment of the present specification can embody or realize a cuttable transparent display panel that can be divided into various sizes for manufacturing according to the fields and applications to which the transparent display panel 110 is applied by providing a cuttable region by an undercut line (UCL) in the transmissive region (TA).

[0068] FIG. 5 is a view showing the C region shown in FIG. 4 according to an embodiment of the present specification. FIG. 6 is a cross-sectional view taken along line I-I' shown in FIG. 5 according to an embodiment of the present specification.

[0069] Referring to FIGS. 5 and 6, the transparent display panel 110 according to an embodiment of the present specification can include at least one first signal line (e.g., a data line (DL), a touch sensor line (TL), a common power supply line (VSSL)) disposed in a non-transmissive region (NTA) and extending in a first direction (or the Y-axis direction), at least one second signal line (e.g., a scan line (SCANL)) extending in a second direction (or the X-axis direction) across the transmissive region (TA), and at least one undercut line (UCL) disposed in the transmissive region (TA) and extending in the first direction (or the Y-axis direction).

[0070] Specifically, on the substrate 111, touch sensor lines (TL) among the first signal lines can be arranged. The touch sensor lines (TL) can be arranged to extend in the first direction (or the Y-axis direction) in the non-transmissive region (NTA). For example, the touch sensor lines (TL) can be arranged to overlap at least one of the pixel power supply line (VDDL) and the common power supply line (VSSL). For example, the touch sensor lines (TL) can be arranged in a layer different from the pixel power supply line (VDDL) and the common power supply line (VSSL). For example, the touch sensor lines (TL) can be arranged to overlap the common power supply line (VSSL).

[0071] The touch sensor lines (TL) can be arranged at the lowermost end of the substrate 111. The touch sensor lines (TL) can be formed of the same material in the same layer as the light-shielding layer arranged on the substrate 111. For example, the light-shielding layer can serve to block external light incident on the active layer of the thin film transistor. The light-shielding layer can be composed of a single layer or a multilayer made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof. For example, the first signal line formed of the same material in the same layer as the light-shielding layer on the substrate 111 can form at least one of the touch sensor lines (TL), the pixel power supply line (VDDL), the common power supply line (VSSL), the reference line (REFL), and the data line (DL), but the embodiments of this specification are not limited thereto.

[0072] On the substrate 111 where the touch sensor lines (TL) and the light-shielding layer are arranged, a buffer layer (BF) can be arranged. The buffer layer (BF) is for protecting the thin film transistor from moisture that penetrates through the substrate 111 which may be vulnerable to moisture permeation, and can be formed of a single layer or a multilayer containing an inorganic insulating material such as silicon oxide (SiO X ), silicon nitride (SiN X ), and aluminum oxide (Al2O3).

[0073] On the buffer layer (BF), a scan line (SCANL), which is a second signal line, can be arranged. The scan line (SCANL) can be arranged in a non-transmissive region (NTA) and a transmissive region (TA). For example, at least a part of the scan line (SCANL) can be arranged to extend in a second direction (or X-axis direction) so as to cross the transmissive region (TA). At least a part of the scan line (SCANL) can be arranged to cross at least one of a pixel power supply line (VDDL), a common power supply line (VSSL), and a touch sensor line (TL). For example, the scan line (SCANL) can be arranged in a layer different from the pixel power supply line (VDDL), the common power supply line (VSSL), and the touch sensor line (TL). The scan line (SCANL) can include a portion bent at least once and extending in a first direction (or Y-axis direction).

[0074] The scan line (SCANL) can be formed of the same material in the same layer as the gate electrode of the thin film transistor arranged on the buffer layer (BF). For example, a thin film transistor can be arranged on the buffer layer (BF). The thin film transistor can include an active layer, a gate insulating layer, a gate electrode, and a source / drain electrode arranged on the buffer layer (BF). The gate insulating layer can be arranged between the active layer and the gate electrode. For example, the gate insulating layer can be formed only in a region where the gate electrode is arranged. An interlayer insulating layer (ILD) can be arranged between the gate electrode and the source / drain electrode of the thin film transistor.

[0075] On the same layer as the scan line (SCANL), a repair line (RL) for repairing dark spots of the light-emitting element can be arranged. For example, the first electrode (or anode electrode) of the light-emitting element can be divided into a first divided electrode and a second divided electrode, and the repair line (RL) can electrically connect the divided first and second divided electrodes to the pixel circuit. For example, the repair line (RL) can be arranged to intersect with the touch sensor line (TL) arranged on the substrate 111. The repair line (RL) can be composed of a different material in a layer different from the touch sensor line (TL). For example, the touch sensor line (TL) is composed of the same material as the light-shielding layer, and the repair line (RL) and the touch sensor line (TL) can be separated from each other with the buffer layer (BF) in between.

[0076] On the substrate 111 where the scan line (SCANL) and the repair line (RL) are arranged, an interlayer insulating layer (ILD) can be arranged. The interlayer insulating layer (ILD) can be formed of a single layer or a multilayer including inorganic insulating materials such as silicon oxide (SiO X ) and silicon nitride (SiN X ), and aluminum oxide (Al2O3).

[0077] On the interlayer insulating layer (ILD), the source / drain electrodes of the thin-film transistor can be arranged. On the same layer as the source / drain electrodes, at least a part of the touch sensor line (TL), the pixel power supply line (VDDL), the common power supply line (VSSL), the reference line (REFL), and the data line (DL) can be formed. For example, the source / drain electrodes can be formed of the same material in the same layer as the data line (DL), but the embodiments of this specification are not limited thereto.

[0078] On the interlayer insulating layer (ILD) where the source / drain electrodes and the data line (DL) are arranged, a first passivation layer (PAS1) can be arranged. On the first passivation layer (PAS1), a second passivation layer (PAS2) can be arranged. The first passivation layer (PAS1) and the second passivation layer (PAS2) are formed of a single layer or multiple layers including inorganic insulating materials such as silicon oxide (SiO X ), silicon nitride (SiN X ), aluminum oxide (Al2O3).

[0079] On the first passivation layer (PAS1), a pixel power supply line (VDDL) and a common power supply line (VSSL) can be arranged. For example, the pixel power supply line (VDDL) and the common power supply line (VSSL) can be arranged between the first passivation layer (PAS1) and the second passivation layer (PAS2). The pixel power supply line (VDDL) and the common power supply line (VSSL) can be arranged so as to overlap with the touch sensor line (TL) on the substrate 111.

[0080] On the second passivation layer (PAS2), a planarization layer (PLN) for planarizing the steps caused by the thin film transistor and the plurality of signal lines can be arranged. The planarization layer (PLN) can be formed of an organic substance such as an acrylic resin, an epoxy resin, a phenol resin, a polyamide resin, or a polyimide resin.

[0081] According to the embodiments of this specification, the transparent display panel 110 can form an undercut line (UCL) using a planarization layer (PLN) and a second passivation layer (PAS2). For example, the undercut line (UCL) can be formed to extend in the first direction (or Y-axis direction) in the transmission region (TA). The undercut line (UCL) can be formed by removing at least a part of the planarization layer (PLN) and the second passivation layer (PAS2). For example, the undercut line (UCL) forms a line-shaped structure extending along the first direction (or Y-axis direction) by removing a part of the planarization layer (PLN), and can be formed into a pillar structure that supports the planarization layer (PLN) in a line-shaped eaves structure by removing a part of the second passivation layer (PAS2) inside the planarization layer (PLN). For example, the undercut line (UCL) can be formed of a pillar structure made of the second passivation layer (PAS2) and an eaves structure made of the planarization layer (PLN) on the upper surface of the second passivation layer (PAS2) of the pillar structure.

[0082] A scan line (SCANL) (or gate line) crossing the transmission region (TA) can be arranged below the undercut line (UCL). A block pattern (BP) can be arranged at the intersection of the undercut line (UCL) and the scan line (SCANL). For example, the block pattern (BP) can be formed at the intersection of the undercut line (UCL) and the scan line (SCANL).

[0083] The block pattern (BP) is used to prevent the scan line (SCANL) from being damaged by the etching solution used when the undercut line (UCL) is formed. For example, the block pattern (BP) can be formed between the undercut line (UCL) and the scan line (SCANL). The block pattern (BP) can be formed on the first passivation layer (PAS1). For example, the block pattern (BP) can be formed of the same material as other signal lines formed on the first passivation layer (PAS1). For example, the block pattern (BP) can be formed of the same material on the same layer as the pixel power line (VDDL) and the common power line (VSSL).

[0084] The transparent display panel 110 according to the embodiments of the present specification can implement or realize a cuttable transparent display panel that can be manufactured in various sizes according to the fields and applications to which the transparent display panel 110 is applied by providing a cuttable area by the undercut line (UCL) in the transmission area (TA). By the way, in the transparent display panel 110 according to the embodiments of the present specification, the light transmittance may be reduced or the reflectance characteristics may be reduced by at least one scan line (SCANL) crossing the transmission area (TA) and the block pattern (BP) disposed in the transmission area (TA). Therefore, the inventors of the present specification have invented a transparent display device with a new structure that can improve the light transmittance of the transparent display panel 110 and improve the reflectance characteristics through various studies and experiments.

[0085] Hereinafter, with reference to FIGS. 7 to 15, a transparent display device according to another embodiment of the present specification that can improve the light transmittance of the transparent display panel 110 and improve the reflectance characteristics will be described more specifically.

[0086] FIG. 7 is a diagram showing the B region shown in FIG. 3 according to another embodiment of the present specification. FIG. 8 is a diagram showing the D region shown in FIG. 7 according to another embodiment of the present specification. FIG. 9 is a cross-sectional view taken along line II-II' shown in FIG. 8 according to another embodiment of the present specification. FIGS. 7 to 9 are obtained by changing the configuration of the scan lines in the transparent display panel 110 described with reference to FIGS. 1 to 6. Therefore, in the following description, the same reference numerals are given to the remaining identical configurations except for the configurations related to the scan lines, and the overlapping descriptions thereof are omitted or briefly described.

[0087] Referring to FIGS. 7 to 9, the transparent display panel 110 according to another embodiment of the present specification can include at least one scan line (SCANL) and a gate bridge pattern (GBP).

[0088] At least one scan line (SCANL) can include a first scan line (SCANL1) and a second scan line (SCANL2). For example, the first scan line (SCANL1) and the second scan line (SCANL2) can be connected to respective pixels (P) corresponding to adjacent horizontal lines. For example, a horizontal line can mean that a plurality of pixels (P) are arranged in parallel along a second direction (or X-axis direction). For example, the first scan line (SCANL1) can be connected to pixels (P) corresponding to the lower horizontal line of two adjacent horizontal lines. For example, the lower horizontal line can be a horizontal line corresponding to pixels (P) located below with reference to the pixels (P) shown in FIG. 7. The second scan line (SCANL2) can be connected to pixels (P) corresponding to the upper horizontal line of two adjacent horizontal lines. For example, the upper horizontal line can be a horizontal line corresponding to the pixels (P) shown in FIG. 7, but the embodiments of the present specification are not limited thereto. For example, the first scan line (SCANL1) and the second scan line (SCANL2) can also provide different scan signals to pixels (P) corresponding to one horizontal line. For example, different scan signals can be provided to pixels (P) corresponding to the horizontal line corresponding to the pixels (P) shown in FIG. 7.

[0089] The first scan line (SCANL1) can be disposed in the non-transmissive region (NTA). For example, at least a part of the first scan line (SCANL1) can extend in the second direction (or the X-axis direction) in the non-transmissive region (NTA). The first scan line (SCANL1) can be bent at least once in the non-transmissive region (NTA) and extend in the first direction (or the Y-axis direction). For example, the first scan line (SCANL1) can be disposed to overlap at least one of the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL) in the non-transmissive region (NTA). The first scan line (SCANL1) can be disposed in a layer different from the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL). The first scan line (SCANL1) can include disconnection portions (DP) spaced apart from each other in the non-transmissive region (NTA). For example, the disconnection portion (DP) of the first scan line (SCANL1) can be formed at a portion intersecting with a repair line (RL) for repairing the darkening of the light-emitting element. The disconnection portions (DP) of the first scan line (SCANL1) can be electrically connected by a connection pattern (CP).

[0090] The second scan line (SCANL2) can be arranged in the non-transmissive region (NTA) and the transmissive region (TA). For example, at least a part of the second scan line (SCANL2) can be arranged to extend in the second direction (or X-axis direction) across the transmissive region (TA). At least a part of the second scan line (SCANL2) can be arranged to intersect at least one of the pixel power line (VDDL), the common power line (VSSL), and the touch sensor line (TL). For example, the second scan line (SCANL2) can be arranged in a layer different from the pixel power line (VDDL), the common power line (VSSL), and the touch sensor line (TL). The second scan line (SCANL2) can include a portion that is bent at least once and extends in the first direction (or Y-axis direction). The second scan line (SCANL2) can be formed of the same material in the same layer as the first scan line (SCANL1). The second scan line (SCANL2) can be electrically separated from each other in the same layer as the first scan line (SCANL1) and spaced apart from each other.

[0091] The gate bridge pattern (GBP) can be disposed in the transmission area (TA). The gate bridge pattern (GBP) can at least partially overlap with at least one scan line (SCANL). Also, the gate bridge pattern (GBP) can be electrically connected to at least one scan line (SCANL). For example, the gate bridge pattern (GBP) can at least partially overlap with the first scan line (SCANL1) and the second scan line (SCANL2). The gate bridge pattern (GBP) can be electrically connected to the first scan line (SCANL1) and electrically separated from the second scan line (SCANL2). For example, the gate bridge pattern (GBP) can be disposed in a layer different from the first scan line (SCANL1) and the second scan line (SCANL2). The gate bridge pattern (GBP) can overlap with the tip of the first scan line (SCANL1) and be electrically connected to the tip of the first scan line (SCANL1) through a contact hole that penetrates the insulating layer between the first scan line (SCANL1) and the gate bridge pattern (GBP). The gate bridge pattern (GBP) can extend parallel to the second scan line (SCANL2). The gate bridge pattern (GBP) is not in direct contact with the second scan line (SCANL2) and can be separated from the second scan line (SCANL2) with at least one insulating layer in between. The gate bridge pattern (GBP) can extend so as to overlap with the second scan line (SCANL2) in the second direction (or X-axis direction) in the transmission area (TA).

[0092] Specifically, a touch sensor line (TL) and a gate bridge pattern (GBP) can be arranged on the substrate 111. The touch sensor line (TL) can be arranged to extend in the first direction (or Y-axis direction) in the non-transmissive region (NTA). For example, the touch sensor line (TL) can be arranged to overlap at least one of the pixel power line (VDDL) and the common power line (VSSL). The gate bridge pattern (GBP) can be arranged to extend in the first direction (or Y-axis direction) in the non-transmissive region (NTA), be bent in the second direction (or X-axis direction), and extend across the transmissive region (TA). For example, the touch sensor line (TL) and the gate bridge pattern (GBP) can be formed of the same material in the same layer. The touch sensor line (TL) and the gate bridge pattern (GBP) can be arranged in a layer different from the first scan line (SCANL1), the second scan line (SCANL2), the pixel power line (VDDL), and the common power line (VSSL). For example, the touch sensor line (TL) can be arranged to overlap the common power line (VSSL). The gate bridge pattern (GBP) can be arranged to at least partially overlap the first scan line (SCANL1) and the second scan line (SCANL2).

[0093] The touch sensor line (TL) and the gate bridge pattern (GBP) can be arranged at the lowermost end of the substrate 111. The touch sensor line (TL) and the gate bridge pattern (GBP) can be formed of the same material in the same layer as the light-shielding layer arranged on the substrate 111. For example, the light-shielding layer can serve to block external light incident on the active layer of the thin film transistor. The light-shielding layer can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or an alloy thereof.

[0094] On a substrate 111 on which a touch sensor line (TL), a gate bridge pattern (GBP), and a light-shielding layer are disposed, a buffer layer (BF) can be disposed. The buffer layer (BF) is for protecting a thin film transistor from moisture that penetrates through the substrate 111 which may be vulnerable to moisture permeation, and is silicon oxide (SiO X ), silicon nitride (SiN X ), aluminum oxide (Al2O3), or the like, and can be formed of a single layer or multiple layers including an inorganic insulating material.

[0095] On the buffer layer (BF), a first scan line (SCANL1) and a second scan line (SCANL2) can be disposed. The first scan line (SCANL1) can be disposed in a non-transmissive region (NTA), and the second scan line (SCANL2) can be disposed in the non-transmissive region (NTA) and the transmissive region (TA).

[0096] The first scan line (SCANL1) can be disposed so as to extend in a second direction (or X-axis direction) in the non-transmissive region (NTA) and be bent and extended in a first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower horizontal line among two adjacent horizontal lines. For example, the first scan line (SCANL1) is connected to a pixel (P) corresponding to the lower horizontal line among two adjacent horizontal lines, extends in the second direction (or X-axis direction), is bent in the first direction (or Y-axis direction), and can be extended so as to at least partially overlap with the touch sensor line (TL). For example, a part of the first scan line (SCANL1) can be extended so as to overlap with the touch sensor line (TL) in the first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be disposed so as to at least partially overlap with at least one of a touch sensor line (TL), a pixel power line (VDDL), and a common power line (VSSL) that extend in the first direction (or Y-axis direction).

[0097] In the same layer as the first scan line (SCANL1), a repair line (RL) for repairing the darkening of the light-emitting element can be arranged. For example, the first electrode (or anode electrode) of the light-emitting element can be divided into a first divided electrode and a second divided electrode that are divided into two, and the repair line (RL) can electrically connect the divided first and second divided electrodes to the pixel circuit. The first scan line (SCANL1) can include a dividing portion (DP) spaced at regular intervals in a portion extending in the first direction (or Y-axis direction). The dividing portion (DP) of the first scan line (SCANL1) can be formed at a portion intersecting the repair line (RL) arranged in the same layer. The first scan line (SCANL1) can be separated from the repair line (RL) by the dividing portion (DP) and electrically separated.

[0098] The tip of the first scan line (SCANL1) can overlap with the gate bridge pattern (GBP) on the substrate 111. The tip of the first scan line (SCANL1) can be electrically connected to the gate bridge pattern (GBP) through a contact hole that penetrates the buffer layer (BF) to expose the gate bridge pattern (GBP). The gate bridge pattern (GBP) electrically connected to the first scan line (SCANL1) can play a role of transmitting the same signal as the first scan line (SCANL1).

[0099] The second scan line (SCANL2) can be arranged in the non-transmissive region (NTA) and the transmissive region (TA). At least a part of the second scan line (SCANL2) can be arranged to extend in the second direction (or X-axis direction) across the transmissive region (TA). At least a part of the second scan line (SCANL2) can be arranged to intersect at least one of the pixel power line (VDDL), the common power line (VSSL), and the touch sensor line (TL). For example, the second scan line (SCANL2) can be arranged in a layer different from the pixel power line (VDDL), the common power line (VSSL), and the touch sensor line (TL). The scan line (SCANL) can include a portion that is bent at least once and extends in the first direction (or Y-axis direction).

[0100] A portion of the second scan line (SCANL2) that extends across the transmissive region (TA) in the second direction (or X-axis direction) can overlap with the gate bridge pattern (GBP). At least a part of the second scan line (SCANL2) can overlap with the gate bridge pattern (GBP) and extend in parallel. The second scan line (SCANL2) can be separated and electrically isolated from the gate bridge pattern (GBP) that serves as the first scan line (SCANL1) with the buffer layer (BF) in between. The second scan line (SCANL2) and the gate bridge pattern (GBP) can further secure the margin of the transmissive region (TA) by sharing the region across the transmissive region (TA) with each other, thereby improving the light transmittance of the transparent display panel 110.

[0101] The first scan line (SCANL1), the second scan line (SCANL2), and the repair line (RL) can be formed of the same material in the same layer as the gate electrode of the thin film transistor disposed on the buffer layer (BF). For example, a thin film transistor can be disposed on the buffer layer (BF). The thin film transistor can include an active layer, a gate insulating layer, a gate electrode, and source / drain electrodes disposed on the buffer layer (BF). The gate insulating layer can be disposed between the active layer and the gate electrode. For example, the gate insulating layer can be formed only in the region where the gate electrode is disposed. An interlayer insulating layer (ILD) can be disposed between the gate electrode and the source / drain electrodes of the thin film transistor.

[0102] An interlayer insulating layer (ILD) can be disposed on the substrate 111 on which the first scan line (SCANL1), the second scan line (SCANL2), and the repair line (RL) are disposed. The interlayer insulating layer (ILD) can be formed of a single layer or a multilayer including an inorganic insulating material such as silicon oxide (SiO X ), silicon nitride (SiN X ), or aluminum oxide (Al2O3).

[0103] A connection pattern (CP) for electrically connecting the divided portion (DP) of the first scan line (SCANL1) can be disposed on the interlayer insulating layer (ILD). The connection pattern (CP) can be formed of the same material in the same layer as the source / drain electrodes of the thin film transistor disposed on the interlayer insulating layer (ILD). For example, the connection pattern (CP) and the source / drain electrodes can be formed of the same material in the same layer as the data line (DL), but the embodiments of the present specification are not limited thereto.

[0104] The connection pattern (CP) can overlap with at least a part of the first scan line (SCANL1) and a repair line (RL) passing through the disconnection part (DP) of the first scan line (SCANL1). One end and the other end of the connection pattern (CP) can be connected to one end and the other end of the first scan line (SCANL1) separated from each other with the disconnection part (DP) therebetween through contact holes that penetrate the interlayer insulating layer (ILD) and expose a part of the first scan line (SCANL1). One end and the other end of the first scan line (SCANL1) separated by the disconnection part (DP) can be electrically connected to each other by the connection pattern (CP).

[0105] On the interlayer insulating layer (ILD) on which the connection pattern (CP), the source / drain electrode, and the data line (DL) are arranged, a first passivation layer (PAS1) can be arranged. On the first passivation layer (PAS1), a second passivation layer (PAS2) can be arranged. The first passivation layer (PAS1) and the second passivation layer (PAS2) can be formed of a single layer or a multilayer including inorganic insulating materials such as silicon oxide (SiO X ), silicon nitride (SiN X ), and aluminum oxide (Al2O3).

[0106] On the first passivation layer (PAS1), a pixel power line (VDDL) and a common power line (VSSL) can be arranged. For example, the pixel power line (VDDL) and the common power line (VSSL) can be arranged between the first passivation layer (PAS1) and the second passivation layer (PAS2). The pixel power line (VDDL) and the common power line (VSSL) can be arranged to overlap with the touch sensor line (TL) on the substrate 111. Also, the pixel power line (VDDL) and the common power line (VSSL) can be arranged to overlap with the first scan line (SCANL1) arranged between the buffer layer (BF) and the interlayer dielectric layer (ILD). For example, the pixel power line (VDDL) and the common power line (VSSL) can be arranged to overlap with a part of the first scan line (SCANL1) extending in the first direction (or the Y-axis direction).

[0107] On the second passivation layer (PAS2), a planarization layer (PLN) for planarizing the steps due to the thin film transistor and the plurality of signal lines can be arranged. The planarization layer (PLN) can be formed of an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0108] The undercut line (UCL) can be formed to extend in the first direction (or the Y-axis direction) in the transmission region (TA) using the planarization layer (PLN) and the second passivation layer (PAS2). The undercut line (UCL) can be formed by removing at least a part of the planarization layer (PLN) and the second passivation layer (PAS2).

[0109] Below the undercut line (UCL), a second scan line (SCANL2) and a gate bridge pattern (GBP) that cross the transmission area (TA) can be arranged. A block pattern (BP) can be arranged at the intersection of the undercut line (UCL), the second scan line (SCANL2), and the gate bridge pattern (GBP). For example, the block pattern (BP) can be formed at the intersection of the undercut line (UCL), the second scan line (SCANL2), and the gate bridge pattern (GBP).

[0110] The transparent display panel 110 according to other embodiments of the present specification can embody or realize a cuttable transparent display panel that can be manufactured by being divided into various sizes according to the fields and applications to which the transparent display panel 110 is applied, by providing a cuttable area by the undercut line (UCL) in the transmission area (TA). Also, the transparent display panel 110 according to other embodiments of the present specification can electrically connect the gate bridge pattern (GBP) to the first scan line (SCANL1) to replace the role of the first scan line (SCANL1). By sharing the area that crosses the second scan line (SCANL2) and the transmission area (TA) with each other, the arrangement of the first scan line (SCANL1) that crosses the transmission area (TA) can be omitted, so that a margin of the transmission area (TA) can be further secured, thereby improving the light transmittance of the transparent display panel 110. Also, the transparent display panel 110 according to other embodiments of the present specification can block external light incident through the substrate 111 by the gate bridge pattern (GBP) arranged to overlap with the second scan line (SCANL2) in the transmission area (TA), thereby improving the reflectance characteristics of the transparent display panel 110.

[0111] FIG. 10 is a diagram showing region B shown in FIG. 3 according to another embodiment of the present specification. FIG. 11 is a diagram showing region E shown in FIG. 10 according to another embodiment of the present specification. FIG. 12 is a cross-sectional view taken along line III-III' shown in FIG. 11 according to another embodiment of the present specification. FIGS. 10 to 12 show a modified configuration of the scan lines in the transparent display panel 110 described with reference to FIGS. 1 to 6. Therefore, in the following description, the same reference numerals are given to the remaining identical configurations except for the configurations related to the scan lines, and the overlapping descriptions thereof are omitted or briefly described.

[0112] Referring to FIGS. 10 to 12, the transparent display panel 110 according to another embodiment of the present specification can include at least one scan line (SCANL) and a gate bridge pattern (GBP).

[0113] The at least one scan line (SCANL) can include a first scan line (SCANL1) and a second scan line (SCANL2).

[0114] The first scan line (SCANL1) can be disposed in the non-transmissive region (NTA). For example, at least a part of the first scan line (SCANL1) can extend in the second direction (or X-axis direction) in the non-transmissive region (NTA). The first scan line (SCANL1) can be bent at least once in the non-transmissive region (NTA) and extend in the first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be disposed so as to intersect at least one of the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL) in the non-transmissive region (NTA). The first scan line (SCANL1) can be disposed in a layer different from the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL).

[0115] The first scan line (SCANL1) can extend in the second direction (or X-axis direction) in the non-transmissive region (NTA) to cross and pass through the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL), and can be arranged to bend and extend in the first direction (or Y-axis direction). For example, the first scan line (SCANL1) can be connected to a pixel (P) corresponding to the lower horizontal line among two adjacent horizontal lines. For example, the first scan line (SCANL1) is connected to a pixel (P) corresponding to the lower horizontal line among two adjacent horizontal lines, extends in the second direction (or X-axis direction) to cross and pass through the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL), and can bend in the first direction (or Y-axis direction) and extend in parallel adjacent to at least one of the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL). For example, a part of the first scan line (SCANL1) can be arranged in parallel adjacent to at least a part of the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL) that extend in the first direction (or Y-axis direction).

[0116] According to other embodiments of this specification, the transparent display panel 110 can be embodied or realized as a cuttable transparent display panel that can be manufactured in various sizes by providing a cuttable area with an undercut line (UCL) in the transmissive area (TA), depending on the field and application to which the transparent display panel 110 is applied. Also, according to other embodiments of this specification, the transparent display panel 110 can further secure a margin in the transmissive area (TA) by sharing the area where the second scan line (SCANL2) and the gate bridge pattern (GBP) cross the transmissive area (TA) with each other, thereby improving the light transmittance of the transparent display panel 110. Further, according to other embodiments of this specification, the transparent display panel 110 can block external light incident through the substrate 111 by the gate bridge pattern (GBP) arranged to overlap the second scan line (SCANL2) in the transmissive area (TA), thereby improving the reflectance characteristics of the transparent display panel 110. Also, according to other embodiments of this specification, the transparent display panel 110 can prevent the generation of parasitic capacitance by minimizing the area where the first scan line (SCANL1) overlaps with the touch sensor line (TL), the pixel power line (VDDL), and the common power line (VSSL). Thereby, the driving reliability of the transparent display panel 110 can be improved.

[0117] FIG. 13 is a diagram showing region B shown in FIG. 3 according to other embodiments of this specification. FIG. 14 is a diagram showing region F shown in FIG. 13 according to other embodiments of this specification. FIG. 15 is a cross-sectional view taken along line IV-IV' shown in FIG. 14 according to other embodiments of this specification. FIGS. 13 to 15 show a change in the configuration of the scan lines in the transparent display panel 110 described with reference to FIGS. 1 to 6. Therefore, in the following description, the same reference numerals are given to the remaining identical configurations except for the configurations related to the scan lines, and the overlapping descriptions thereof are omitted or briefly described.

[0118] Referring to FIGS. 13 to 16, the transparent display panel 110 according to other embodiments of the present specification can include at least one scan line (SCANL) and a connection bridge pattern (CBP).

[0119] At least one scan line (SCANL) can be disposed in the non-transmissive region (NTA) and the transmissive region (TA). At least a part of at least one scan line (SCANL) can be disposed to extend in the second direction (or the X-axis direction) across the transmissive region (TA).

[0120] The undercut line (UCL) can be formed to extend in the first direction (or the Y-axis direction) in the transmissive region (TA) using the planarization layer (PLN) and the second passivation layer (PAS2). The undercut line (UCL) can be formed by removing at least a part of the planarization layer (PLN) and the second passivation layer (PAS2).

[0121] At least one scan line (SCANL) can be disposed below the undercut line (UCL) across the transmissive region (TA). At least one scan line (SCANL) can include a segmentation part (DP) spaced at regular intervals at the intersection with the undercut line (UCL). The segmentation part (DP) of at least one scan line (SCANL) can be electrically connected by the connection bridge pattern (CBP).

[0122] Specifically, a connection bridge pattern (CBP) formed of the same material in the same layer as the light shielding layer can be disposed on the substrate 111. The connection bridge pattern (CBP) can be disposed at a portion where one scan line (SCANL) intersects with an undercut line (UCL) in the transmission area (TA). For example, the connection bridge pattern (CBP) can be formed of a single layer or multiple layers made of any one of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu), or an alloy thereof.

[0123] A buffer layer (BF) can be disposed on the substrate 111 on which the connection bridge pattern (CBP) and the light shielding layer are disposed. The buffer layer (BF) is for protecting the thin film transistor from moisture that penetrates through the substrate 111 which may be vulnerable to moisture permeation, and is formed of a single layer or multiple layers including an inorganic insulating material such as silicon oxide (SiO X ), silicon nitride (SiN X ), aluminum oxide (Al2O3).

[0124] At least one scan line (SCANL) can be disposed on the buffer layer (BF). The at least one scan line (SCANL) can be disposed in the non-transmissive region (NTA) and the transmissive region (TA). For example, at least a part of the at least one scan line (SCANL) can be disposed to extend in the second direction (or the X-axis direction) across the transmissive region (TA). The at least one scan line (SCANL) can include segmentation parts (DP) spaced at regular intervals at a portion where it intersects the undercut line (UCL) in the transmissive region (TA). The segmentation parts (DP) of the at least one scan line (SCANL) can be formed to be spaced apart from each other with the undercut line (UCL) therebetween. One end and the other end of the at least one scan line (SCANL) spaced apart with the segmentation part (DP) therebetween can be connected to the connection bridge pattern (CBP) through contact holes that penetrate the buffer layer (BF) to expose a part of the connection bridge pattern (CBP). One end and the other end of the at least one scan line (SCANL) separated by the segmentation part (DP) can be electrically connected to each other by the connection bridge pattern (CBP).

[0125] An interlayer insulating layer (ILD), a first passivation layer (PAS1), a second passivation layer (PAS2), and a planarization layer (PLN) can be disposed on the substrate 111 on which the at least one scan line (SCANL) is disposed.

[0126] The undercut line (UCL) can be formed to extend in the first direction (or the Y-axis direction) in the transmissive region (TA) using the planarization layer (PLN) and the second passivation layer (PAS2). The undercut line (UCL) can be formed by removing at least a part of the planarization layer (PLN) and the second passivation layer (PAS2).

[0127] At least one scan line (SCANL) intersecting the undercut line (UCL) can be separated from the undercut line (UCL) with an interlayer dielectric (ILD) and a first passivation layer (PAS1) therebetween. Accordingly, the transparent display panel 110 according to other embodiments of the present specification can prevent at least one scan line (SCANL) from being damaged by an etching solution used when the undercut line (UCL) is formed, without forming a separate block pattern.

[0128] The transparent display panel 110 according to other embodiments of the present specification can provide a cuttable region by the undercut line (UCL) in the transmission region (TA), and thus can embody or realize a cuttable transparent display panel that can be manufactured in various sizes according to the fields and applications to which the transparent display panel 110 is applied. Further, the transparent display panel 110 according to other embodiments of the present specification can eliminate the formation of a separate block pattern at a portion where the undercut line (UCL) and at least one scan line (SCANL) intersect, thereby further securing a margin of the transmission region (TA), and thus improving the light transmittance of the transparent display panel 110.

[0129] The transparent display device according to one or more embodiments of the present specification can be described as follows.

[0130] The transparent display device according to one or more embodiments of the present specification can include a substrate including a non-transmissive region and a transmissive region including a light-emitting region where light-emitting elements are disposed, at least one gate line crossing the non-transmissive region and the transmissive region on the substrate, and a gate bridge pattern disposed in the transmissive region on the substrate and at least partially overlapping with at least one gate line.

[0131] According to one or more embodiments of the present specification, the gate bridge pattern can be electrically connected to at least one gate line.

[0132] According to one or more embodiments of the present specification, at least one gate line includes a first gate line and a second gate line, and the gate bridge pattern can be electrically connected to the first gate line and electrically separated from the second gate line.

[0133] According to one or more embodiments of the present specification, the first gate line is disposed in a non-transmissive region, and the second gate line can be disposed in the non-transmissive region and the transmissive region.

[0134] According to one or more embodiments of the present specification, the first gate line is connected to a pixel corresponding to a lower horizontal line among two adjacent horizontal lines, and the second gate line can be connected to a pixel corresponding to an upper horizontal line among two adjacent horizontal lines.

[0135] According to one or more embodiments of the present specification, the gate bridge pattern can extend parallel to the second gate line in the transmissive region and overlap the second gate line.

[0136] According to one or more embodiments of the present specification, the gate bridge pattern can be separated from the second gate line with at least one insulating layer interposed therebetween.

[0137] According to one or more embodiments of the present specification, the gate bridge pattern can be connected to the first gate line through a contact hole penetrating at least one insulating layer.

[0138] According to one or more embodiments of the present specification, it further includes at least one power line extending in a first direction on the substrate, and at least one gate line can include a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction.

[0139] According to one or more embodiments of the present specification, at least one power line and a first gate line are disposed in a non-transmissive region, and a second gate line can be disposed in the non-transmissive region and the transmissive region.

[0140] According to one or more embodiments of the present specification, the first gate line can overlap at least one power line in the non-transmissive region.

[0141] According to one or more embodiments of the present specification, the first gate line can extend in parallel adjacent to at least one power line in the non-transmissive region.

[0142] According to one or more embodiments of the present specification, the first gate line can include segmented portions spaced apart from each other in the non-transmissive region and a connection pattern for electrically connecting the segmented portions.

[0143] According to one or more embodiments of the present specification, other metal patterns in the non-transmissive region can be disposed at the segmented portions of the first gate line.

[0144] According to one or more embodiments of the present specification, the gate bridge pattern can be electrically connected to the first gate line, electrically separated from the second gate line, and extend in parallel.

[0145] According to one or more embodiments of the present specification, the gate bridge pattern is disposed on the substrate, and at least one gate line can be disposed on a first insulating layer covering the gate bridge pattern.

[0146] According to one or more embodiments of the present specification, at least one gate line includes segmented portions spaced apart from each other and a connection pattern for electrically connecting the segmented portions. The connection pattern is disposed on a second insulating layer covering at least one gate line, and the segmented portions can be electrically connected through contact holes penetrating the second insulating layer.

[0147] According to one or more embodiments of the present specification, it further includes at least one power line extending in a first direction on a substrate, and the at least one power line can be disposed on a third insulating layer covering a connection pattern with at least one gate line.

[0148] According to one or more embodiments of the present specification, it can further include at least one undercut line disposed in a transmission region on a substrate and extending in a first direction.

[0149] According to one or more embodiments of the present specification, the at least one undercut line includes a first undercut line and a second undercut line. The first undercut line can be disposed adjacent to pixels on one side of the transmission region, and the second undercut line can be disposed adjacent to pixels on the other side of the transmission region.

[0150] According to one or more embodiments of the present specification, the at least one undercut line can be configured to isolate an organic light-emitting layer constituting a light-emitting element.

[0151] According to one or more embodiments of the present specification, the at least one undercut line can be constituted by a part of at least one protective layer on at least one gate line.

[0152] According to one or more embodiments of the present specification, the at least one undercut line can be formed by removing a part of at least one protective layer.

[0153] According to one or more embodiments of the present specification, it can further include a block pattern disposed at a portion where at least one gate line and at least one undercut line intersect.

[0154] According to one or more embodiments of the present specification, the block pattern can be between at least one undercut line and at least one gate line.

[0155] The transparent display device according to one or more embodiments of the present specification includes a substrate including a non-transmissive region and a transmissive region including a light-emitting region where light-emitting elements are disposed, at least one undercut line disposed on the substrate in the transmissive region and extending in a first direction, and at least one gate line disposed on the substrate across the non-transmissive region and the transmissive region and including divided portions spaced apart at regular intervals at a portion intersecting the at least one undercut line in the transmissive region, and may include a connection bridge pattern disposed at a portion where the at least one gate line and the at least one undercut line are disposed and electrically connecting the divided portions of the at least one gate line.

[0156] According to one or more embodiments of the present specification, the connection bridge pattern may be disposed on the substrate, and the at least one gate line may be disposed on an insulating layer covering the connection bridge pattern.

[0157] According to one or more embodiments of the present specification, one end and the other end of the at least one gate line separated by the divided portions may be electrically connected to the connection bridge pattern through contact holes penetrating the insulating layer.

[0158] According to one or more embodiments of the present specification, the at least one undercut line may be configured to disconnect an organic light-emitting layer constituting the light-emitting element.

[0159] According to one or more embodiments of the present specification, the at least one undercut line may be formed of a part of at least one protective layer on the at least one gate line.

[0160] According to one or more embodiments of the present specification, the at least one undercut line may be formed by removing a part of the at least one protective layer.

[0161] The embodiments of the present specification have been described in more detail above with reference to the attached drawings. However, the present specification is not necessarily limited to such embodiments, and various modifications can be made and implemented without departing from the technical idea of the present specification. Therefore, the embodiments disclosed in the present invention are not intended to limit the technical idea of the present specification but to explain it, and the scope of the technical idea of the present specification is not limited by such embodiments. Therefore, it must be understood that the above-described embodiments are illustrative in all respects and not restrictive. The protection scope of the present specification must be interpreted by the scope of the claims, and all technical ideas within the equivalent scope must be construed as being included in the scope of rights of the present specification.

Explanation of Reference Numerals

[0162] 110: Display panel 205: Gate driving unit DA: Display area NDA: Non-display area SL1: First signal line SL2: Second signal line

Claims

1. A substrate including a non-transmissive region and a transmissive region including a light-emitting region where a light-emitting element is disposed, at least one gate line crossing the non-transmissive region and the transmissive region on the substrate, and a transparent display device including a gate bridge pattern disposed in the transmissive region and at least partially overlapping the at least one gate line.

2. The transparent display device according to claim 1, wherein the gate bridge pattern is electrically connected to the at least one gate line.

3. The at least one gate line includes a first gate line and a second gate line, The transparent display device according to claim 1, wherein the gate bridge pattern is electrically connected to the first gate line and electrically separated from the second gate line.

4. The first gate line is disposed in the non-transmissive region, The transparent display device according to claim 3, wherein the second gate line is disposed in the non-transmissive region and the transmissive region.

5. The first gate line is connected to a pixel corresponding to a lower horizontal line among two adjacent horizontal lines, The transparent display device according to claim 3, wherein the second gate line is connected to a pixel corresponding to an upper horizontal line among the two adjacent horizontal lines.

6. The transparent display device according to claim 4, wherein the gate bridge pattern extends parallel to the second gate line in the transmissive region and overlaps the second gate line.

7. The transparent display device according to claim 6, wherein the gate bridge pattern is separated from the second gate line with at least one insulating layer interposed therebetween.

8. The transparent display device according to claim 3, wherein the gate bridge pattern is connected to the first gate line through a contact hole penetrating at least one insulating layer.

9. Further including at least one power line extending in a first direction on the substrate, The transparent display device according to claim 1, wherein the at least one gate line includes a first gate line extending parallel to the first direction and a second gate line extending in a second direction intersecting the first direction.

10. The at least one power line and the first gate line are disposed in the non-transmissive region, The transparent display device according to claim 9, wherein the second gate line is disposed in the non-transmissive region and the transmissive region.

11. The transparent display device according to claim 10, wherein the first gate line overlaps with the at least one power line in the non-transmissive region.

12. The transparent display device according to claim 10, wherein the first gate line extends in parallel adjacent to the at least one power line in the non-transmissive region.

13. The first gate line includes a divided portion spaced apart from each other in the non-transmissive region, and a connection pattern that electrically connects the divided portions, the transparent display device according to claim 4 or 10.

14. The transparent display device according to claim 13, wherein another metal pattern in the non-transmissive region is disposed on the divided portion of the first gate line.

15. The transparent display device according to claim 10, wherein the gate bridge pattern is electrically connected to the first gate line and extends in parallel while being electrically separated from the second gate line.

16. The gate bridge pattern is disposed on the substrate, and the at least one gate line is disposed on a first insulating layer covering the gate bridge pattern, the transparent display device according to claim 1.

17. The at least one gate line includes a divided portion spaced apart from each other and a connection pattern that electrically connects the divided portions, the connection pattern is disposed on a second insulating layer covering the at least one gate line, and electrically connects the divided portions through a contact hole penetrating the second insulating layer, the transparent display device according to claim 16.

18. Further including at least one power line extending in a first direction on the substrate, the at least one power line is disposed on a third insulating layer covering the at least one gate line and the connection pattern, the transparent display device according to claim 17.

19. The transparent display device according to claim 1, further including at least one undercut line disposed in the transmissive region on the substrate and extending in a first direction.

20. The at least one undercut line includes a first undercut line and a second undercut line, the first undercut line is disposed adjacent to a pixel on one side of the transmissive region, and the second undercut line is disposed adjacent to a pixel on the other side of the transmissive region, the transparent display device according to claim 19.

21. The transparent display device according to claim 19, wherein the at least one undercut line is configured to cut off an organic light-emitting layer constituting the light-emitting element.

22. The transparent display device according to claim 19, wherein the at least one undercut line is composed of a part of at least one protective layer on the at least one gate line.

23. The transparent display device according to claim 22, wherein the at least one undercut line is formed by removing at least a part of the at least one protective layer.

24. The transparent display device according to claim 19, further comprising a block pattern disposed at a portion where the at least one gate line intersects the at least one undercut line.

25. The transparent display device according to claim 24, wherein the block pattern is between the at least one undercut line and the at least one gate line.

26. A substrate including a non-transmissive region and a transmissive region including a light-emitting region where a light-emitting element is disposed, At least one undercut line disposed in the transmissive region on the substrate and extending in a first direction, At least one gate line crossing the non-transmissive region and the transmissive region on the substrate and including a dividing portion spaced apart at regular intervals at a portion where the at least one gate line intersects the at least one undercut line in the transmissive region, and A transparent display device including a connection bridge pattern disposed at a portion where the at least one gate line and the at least one undercut line are disposed, and electrically connecting the dividing portions of the at least one gate line.

27. The connection bridge pattern is disposed on the substrate, The transparent display device according to claim 26, wherein the at least one gate line is disposed on an insulating layer covering the connection bridge pattern.

28. The transparent display device according to claim 27, wherein one end and the other end of the at least one gate line separated by the dividing portion are electrically connected to the connection bridge pattern through contact holes penetrating the insulating layer.

29. The transparent display device according to claim 26, wherein the at least one undercut line is configured to cut off an organic light-emitting layer constituting the light-emitting element.

30. The transparent display device according to claim 26, wherein the at least one undercut line is composed of a part of at least one protective layer on the at least one gate line.

31. The transparent display device according to claim 30, wherein the at least one undercut line is formed by removing at least a part of the at least one protective layer.

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