Game machine

Abstract

To provide a game machine capable of suitably performing management of a game machine.SOLUTION: An MPU 62 includes not only a main-side CPU 63 but also a management IC 66. The main-side CPU 63 is electrically connected to the management IC 66, and a detection result of each ball entry detection sensor is transmitted from the main-side CPU 63 to the management IC 66. In this case, the detection result of each ball entry detection sensor is transmitted to the management IC 66 through each corresponding signal path, and a corresponding relationship between each ball entry detection sensor and the signal path is supplied from the main-side CPU 63 to the management IC 66 when starting to supply operating power. The management IC 66 stores information on the detection result of each ball entry detection sensor in a history memory 117 as history information. A management-side CPU 112 calculates each kind of parameter by utilizing history information of the history memory 117 in occurrence of an operation opportunity. The history information and each kind of parameter are outputted to the outside through a reading terminal 102.SELECTED DRAWING: Figure 13

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines and slot machines are known. For example, a pachinko machine has a dish storage section for storing game balls given to a player on the front part of the gaming machine, and the game balls stored in the dish storage section are guided to a game ball launching device and launched toward a game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry section provided in the game area, game balls are paid out from a payout device to the dish storage section. Also, in a pachinko machine, a configuration having an upper dish storage section and a lower dish storage section as the dish storage section is also known. In this case, the game balls stored in the upper dish storage section are guided to the game ball launching device, and the surplus game balls in the upper dish storage section are discharged to the lower dish storage section (see, for example, Patent Document 1).

[0003] Also, in a slot machine, when a new game is started by operating a start lever in a situation where medals are bet, a lottery process is executed by control means. Further, when the lottery process is executed, rotation start control is executed by the control means to start the rotation of the reel, and when a stop button is operated during the rotation of the reel, rotation stop control is executed by the control means to stop the rotation of the reel. Then, when the stop result after the rotation of the reel stops corresponds to the winning combination of the lottery process, a privilege corresponding to the winning combination is given to the player.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in the gaming machine as exemplified above, it is necessary to suitably manage the gaming machine, and there is still room for improvement in this regard.

[0006] The present invention has been made in view of the above-exemplified circumstances and the like, and an object thereof is to provide a gaming machine capable of suitably managing a gaming machine.

Means for Solving the Problems

[0007] In order to solve the above problems, the invention according to claim 1 executes a predetermined storage process for causing a predetermined storage means to store information corresponding to a predetermined event when the predetermined event occurs as a result of a game, so that predetermined information is stored in the predetermined storage means. A predetermined storage execution means, Information calculation means for calculating mode information corresponding to the result of a game in a predetermined period by using the predetermined information each time a predetermined calculation trigger occurs, Result storage execution means for sequentially storing the mode information obtained by the calculation by the information calculation means in a calculation result storage means, comprising, The result storage execution means includes means for causing the mode information to be stored in the calculation result storage means to be in a state where the mode information to be stored among the mode information obtained by the calculation by the information calculation means is stored in the calculation result storage means, Among the mode information obtained by the calculation by the information calculation means, the mode information that is not the storage target is not configured to be stored in the calculation result storage means, This gaming machine is A predetermined control means capable of executing a predetermined process including a predetermined progress process for progressing a game and the predetermined storage process, Means for generating a specific advantageous period when a specific trigger occurs, Means for causing the predetermined information in the predetermined storage means to be erased after the calculation of the mode information by the information calculation means is completed, Notification means capable of notifying the content corresponding to the mode information stored in the arithmetic result storage means comprises In one process cycle of the predetermined process, the predetermined storage process is executed after the predetermined progress process is executed The information arithmetic means is characterized in that it calculates the mode information by using the predetermined information in the specific advantageous period as the mode information corresponding to the result of the game in the predetermined period

Effect of the Invention

[0008] According to the present invention, it becomes possible to suitably manage a gaming machine

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

Figure 17

Figure 18

Figure 19

Figure 20

Figure 21

Figure 22

Figure 23

Figure 24

Figure 25

Figure 26

Figure 27

Figure 28

Figure 29

Figure 30

Figure 31

Figure 32

Figure 33

Figure 34

Figure 35

Figure 36

Figure 37

Figure 38

Figure 39

Figure 40

Figure 41

Figure 42

Figure 43

Figure 44

Figure 45

Figure 46

Figure 47

Figure 48

Figure 49

Figure 50

Figure 51

Figure 52

Figure 53

Figure 54

Figure 55

Figure 56

Figure 57

Figure 58

Figure 59

Figure 60

Figure 61

Figure 62

Figure 63

Figure 64

Figure 65

Figure 66

Figure 67

Figure 68

Figure 69

Figure 70

Figure 71

Figure 72

Figure 73

Figure 74

Figure 75

Figure 76

Figure 77

Figure 78

Figure 79

Figure 80

Figure 81

Figure 82

Figure 83

Figure 84

Figure 85

Figure 86

Figure 87

Figure 88

Figure 89

Figure 90

Figure 91

Figure 92

Figure 93

Figure 94

Figure 95

Figure 96

Figure 97

Figure 98

Figure 99

Figure 100

Figure 101

Figure 102

Figure 103

Figure 104

Figure 105

Figure 106

Figure 107

Figure 108

Figure 109

Figure 110

Figure 111

Figure 112

Figure 113

Figure 114

Mode for Carrying Out the Invention

[0010] <The First Embodiment> Hereinafter, a first embodiment of a pachinko game machine (hereinafter referred to as a "pachinko machine"), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main components of the pachinko machine 10 disassembled. In FIG. 2, for convenience, the components within the game area PA of the pachinko machine 10 are omitted.

[0011] As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine body 12 that is rotatably attached to the front of the outer frame 11. The outer frame 11 is formed by connecting wooden boards on four sides and has a rectangular frame shape. The pachinko machine 10 is installed in the game hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and it may be configured such that the outer frame 11 is provided in the island equipment of the game hall.

[0012] As shown in FIG. 2, the game machine body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. Among the game machine body 12, the inner frame 13 is rotatably supported by the outer frame 11. Specifically, when viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, the inner frame 13 is rotatable forward.

[0013] The front door frame 14 is rotatably supported by the inner frame 13, and when viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, it is rotatable forward. Also, the back pack unit 15 is rotatably supported by the inner frame 13, and when viewed from the front, with the left side as the rotation base end side and the right side as the rotation tip end side, it is rotatable backward.

[0014] Note that the game machine body 12 is provided with a locking device at its rotation tip end, and has a function of locking the game machine body 12 in a non-openable state with respect to the outer frame 11, and also has a function of locking the front door frame 14 in a non-openable state with respect to the inner frame 13. These locked states are each released by performing an unlocking operation using an unlocking key on a cylinder lock 17 provided to be exposed on the front surface of the pachinko machine 10.

[0015] Next, the configuration on the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front surface of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be described with reference to FIG. 3. FIG. 3 is a front view of the game board 24.

[0018] An inner rail portion 25 and an outer rail portion 26 are attached to the game board 24 so as to partition a part of the outer edge of the game area PA, and a guide rail as a guiding means is constituted by these inner rail portion 25 and outer rail portion 26. The game balls launched from a game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies the game balls stored in an upper tray 55a described later onto the launching rail 27a, and a solenoid 27c that is an electric actuator for launching the game balls supplied onto the launching rail 27a toward the guide rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] The game board 24 is formed with a plurality of large and small openings penetrating in the front-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special figure unit 37, a general figure unit 38, and the like. A total of four general winning openings 31 are provided, and the others are provided one by one.

[0021] Even if a game ball enters the through gate 35, the payout of the game ball is not executed. On the other hand, when a game ball enters the general winning opening 31, the special electric winning device 32, the first operating opening 33, or the second operating opening 34, a predetermined number of game balls are paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one bonus ball is paid out. When one game ball enters the general winning opening 31, 10 bonus balls are paid out. When one game ball enters the special electric winning device 32, 15 bonus balls are paid out.

[0022] Note that the number of the bonus balls is arbitrary. For example, the second operating opening 34 may be configured to have fewer bonus balls than the first operating opening 33, or the second operating opening 34 may be configured to have more bonus balls than the first operating opening 33.

[0023] In addition, an out port 24a is provided at the lowermost part of the game board 24, and the game balls that do not enter various winning openings and the like are discharged from the game area PA through the out port 24a. Further, a large number of nails 24b are implanted in the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various members such as a windmill are arranged.

[0024] Here, "entering the ball" means that the game ball passes through a predetermined opening, and it includes not only the mode of being discharged from the game area PA after passing through the opening, but also the mode of continuing to flow down in the game area PA without being discharged from the game area PA after passing through the opening. However, in the following description, in order to clearly distinguish it from the entry of the game ball into the out-port 24a, the entry of the game ball into the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 is also expressed as "winning".

[0025] The first operating port 33 and the second operating port 34 are unitized as an operating port device and installed on the game board 24. Both the first operating port 33 and the second operating port 34 are open upward. Also, the two operating ports 33, 34 are arranged in the vertical direction with the first operating port 33 above. A general electric accessory 34a as a guide piece composed of a pair of left and right movable pieces is provided at the second operating port 34. In the closed state of the general electric accessory 34a, the game ball cannot win at the second operating port 34, and when the general electric accessory 34a is in the open state, winning at the second operating port 34 becomes possible.

[0026] A through gate 35 is provided on the upstream side in the flowing direction of the game ball from the second operating port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that wins at the through gate 35 flows down in the game area PA after winning. Thereby, it is possible for the game ball that wins at the through gate 35 to win at the second operating port 34.

[0027] Based on winning at the through gate 35, the general electric accessory 34a of the second operating port 34 is switched from the closed state to the open state. Specifically, an internal lottery is conducted triggered by winning at the through gate 35, and a variation display of the pattern is performed on the general pattern display section 38a of the general pattern unit 38 provided at the lower right corner, which is an area where the game ball does not pass through in the game area PA. Then, when the result of the internal lottery is a winning for electric accessory opening and the stop result corresponding to the result is displayed and the variation display of the general pattern display section 38a ends, it shifts to the general electric open state. In the general electric open state, the general electric accessory 34a is in the open state in a predetermined mode.

[0028] The map display unit 38a is composed of a segment display in which a plurality of segment light-emitting parts are arranged in a predetermined manner, but is not limited thereto, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. As for the pattern displayed variably on the map display unit 38a, a configuration in which a plurality of characters are displayed variably, a configuration in which a plurality of symbols are displayed variably, a configuration in which a plurality of characters are displayed variably, or a configuration in which a plurality of colors are displayed in a switched manner may be considered.

[0029] In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. The number of game balls that enter the through gate 35 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

[0030] A winning lottery is held by triggering a winning entry into the first operating port 33 or the second operating port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special chart unit 37 in detail, the special chart unit 37 is provided with a special chart display section 37a. The display area of ​​the special chart display section 37a is narrower than the display surface 41a of the pattern display device 41. In the special chart display section 37a, a winning lottery is held by triggering the winning of the first operating port 33 or the winning of the second operating port 34, and a variable display or a predetermined display of the pattern is performed. Then, a result corresponding to the lottery result is displayed. The special chart display section 37a is composed of a segment display device in which a plurality of segment light-emitting sections are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. In addition, as the pattern displayed on the special chart display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed may be considered.

[0032] In the special figure unit 37, a special figure hold display unit 37b is provided at a position adjacent to the special figure display unit 37a. The number of winning game balls that enter the first operation port 33 or the second operation port 34 is held up to a maximum of 4, and the held number is displayed by lighting the special figure hold display unit 37b.

[0033] Regarding the symbol display device 41 in detail, the symbol display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display content is controlled by a display control device described later. Note that the symbol display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display.

[0034] In the symbol display device 41, when a variable display of a pattern or a predetermined display is performed at the special figure display unit 37a based on winning at the first operation port 33 or winning at the second operation port 34, a variable display of the pattern or a predetermined display is performed accordingly. For example, on the display surface 41a of the symbol display device 41, three symbol columns in the upper, middle, and lower stages are set as a plurality of display areas, and main symbols with numbers from "1" to "9" are arranged in ascending or descending order and scrolled and displayed in each symbol column. In this scroll display, first, the scroll display in all symbol columns is started, and the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally, it ends with a predetermined symbol being statically displayed in each symbol column. And, for example, in a game round where the game result is a big win result, a predetermined combination of symbols is stopped and displayed on an effective line preset on the display surface 41a of the symbol display device 41.

[0035] Note that in the symbol display device 41, not only the display effects triggered by winning at the first operation port 33 or the second operation port 34, but also the display effects during the opening / closing execution mode that transitions after winning or hitting are performed. Also, based on winning at any of the operation ports 33, 34, the display is started by the special figure display unit 37a and the symbol display device 41, and one game round corresponds to the period from when the display starts until a predetermined result is displayed and the process ends. Also, the mode of the variable display of symbols in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol columns, the direction of the variable display of symbols in the symbol column, the number of symbols in each symbol column, etc. can be changed as appropriate. Also, the symbols that are variably displayed by the symbol display device 41 are not limited to the symbols as described above, and for example, a configuration where only numbers are variably displayed as symbols may be used.

[0036] When winning a jackpot in the winning lottery based on winning at the first operation port 33 or the second operation port 34, a transition is made to the opening / closing execution mode in which winning at the special electric winning device 32 becomes possible. The special electric winning device 32 includes a large winning port (not shown) that leads to the back side of the game board 24, and an opening / closing door 32a that opens and closes the large winning port. The opening / closing door 32a is arranged in either a closed state or an open state. Specifically, the opening / closing door 32a is normally in a closed state where game balls cannot win, and is switched to an open state where game balls can win when winning in the internal lottery to transition to the opening / closing execution mode. Incidentally, the opening / closing execution mode is a mode that transitions when a winning result occurs. Note that it may be configured such that winning is not impossible in the closed state, but it is a state where winning is less likely to occur than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration related to the discharge of game balls that have flowed down in the game area PA.

[0038] As described above, the game ball that has entered any one of the general winning opening 31, the special winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a is discharged from the game area PA. In other words, the game ball launched from the game ball launching mechanism 27 and flowing into the game area PA is discharged from the game area PA by entering any one of the general winning opening 31, the special winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a. The game ball that has entered any one of the general winning opening 31, the special winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a is guided to the back side of the game board 24.

[0039] On the back of the game board 24, discharge passage portions 42 to 48 are formed corresponding to the general winning opening 31, the special winning device 32, the first operation opening 33, the second operation opening 34, and the out opening 24a, respectively. The game balls that have flowed into the discharge passage portions 42 to 48 flow down the discharge passage portions 42 to 48 into which they have flowed, and thus are guided to the lower end portion of the game board 24 on the back side of the game board 24 and collected by a discharge ball collection portion (not shown). Then, the game balls collected by the discharge ball collection portion are discharged to the ball circulation device of the island facility where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage portions 42 to 48 is provided with various detection sensors 42a to 48a for detecting game balls. These discharge passage portions 42 to 48 and detection sensors 42a to 48a will be described below. Since four general winning openings 31 are provided as already described, there are discharge passage portions 42 to 44 corresponding to each of these four. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage portion 42 corresponding to the leftmost general winning opening 31 and the second discharge passage portion 43 corresponding to the general winning opening 31 adjacent to its right. Specifically, the first winning opening detection sensor 42a is provided at an intermediate position in the first discharge passage portion 42 such that a detection range exists, and the second winning opening detection sensor 43a is provided at an intermediate position in the second discharge passage portion 43 such that a detection range exists. A game ball that has entered the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage portion 42, and a game ball that has entered the general winning opening 31 adjacent to its right is detected by the second winning opening detection sensor 43a while passing through the second discharge passage portion 43. Further, a third discharge passage portion 44 is provided for the two general winning openings 31 on the right side so as to merge at an intermediate position. The third discharge passage portion 44 has an entrance side region corresponding to each of the two general winning openings 31, and has one exit side region by the merging of these entrance side regions in the middle. The third winning opening detection sensor 44a is provided at an intermediate position in the exit side region of the third discharge passage portion 44 such that a detection range exists. A game ball that has entered any of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage portion 44.

[0041] There is a fourth discharge passage portion 45 corresponding to the special-electric winning device 32. A special-electric detection sensor 45a is provided such that a detection range exists at an intermediate position of the fourth discharge passage portion 45. A game ball that has entered the special-electric winning device 32 is detected by the special-electric detection sensor 45a while passing through the fourth discharge passage portion 45. There is a fifth discharge passage portion 46 corresponding to the first operation port 33. A first operation port detection sensor 46a is provided such that a detection range exists at an intermediate position of the fifth discharge passage portion 46. A game ball that has entered the first operation port 33 is detected by the first operation port detection sensor 46a while passing through the fifth discharge passage portion 46. There is a sixth discharge passage portion 47 corresponding to the second operation port 34. A second operation port detection sensor 47a is provided such that a detection range exists at an intermediate position of the sixth discharge passage portion 47. A game ball that has entered the second operation port 34 is detected by the second operation port detection sensor 47a while passing through the sixth discharge passage portion 47. There is a seventh discharge passage portion 48 corresponding to the out port 24a. An out port detection sensor 48a is provided such that a detection range exists at an intermediate position of the seventh discharge passage portion 48. A game ball that has entered the out port 24a is detected by the out port detection sensor 48a while passing through the seventh discharge passage portion 48.

[0042] Note that a game ball detected by any one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. Also, a gate detection sensor 49a is provided for the through gate 35, and a game ball passing through the through gate 35 while flowing down in the game area PA is detected by the gate detection sensor 49a.

[0043] As various detection sensors 42a to 49a, electromagnetic induction type proximity sensors are all used, but the sensors to be used are arbitrary as long as they can individually detect the game balls. Further, the various detection sensors 42a to 49a are electrically connected to a main control device 60 described later, and the detection results of the various detection sensors 42a to 49a are output to the main control device 60. Specifically, the various detection sensors 42a to 49a output a LOW level signal in a situation where no game ball is detected, and output a HI level signal in a situation where a game ball is detected. Note that it is not limited to this, and the relationship between HI and LOW may be reversed.

[0044] As shown in FIG. 2, a front door frame 14 is provided so as to cover the entire front side of an inner frame 13 in which the game board 24 having the above-described configuration is attached to a resin base 21. As shown in FIG. 1, a window portion 51 is formed in the front door frame 14 so that substantially the entire game area PA can be visually recognized from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted therein. The window panel 52 is formed of glass to be colorless and transparent, but is not limited thereto, and may be formed of synthetic resin to be colorless and transparent, or may be formed of colored transparent as long as the game area PA can be visually recognized through the window panel 52 from the front of the pachinko machine 10.

[0045] A display light emitting portion 53 is provided above the window portion 51. Further, a pair of left and right speaker portions 54 that output effect sounds and the like according to the game state are provided. Further, below the window portion 51, an upper bulging portion 55 bulging forward and a lower bulging portion 56 are provided side by side vertically. An upper dish 55a that opens upward is provided inside the upper bulging portion 55, and a lower dish 56a that also opens upward is provided inside the lower bulging portion 56. The upper dish 55a has a function of temporarily storing the game balls paid out from a payout device described later and guiding them to the game ball launching mechanism 27 side while aligning them in a row. Further, the lower dish 56a has a function of storing the surplus game balls in the upper dish 55a.

[0046] Next, the configuration on the back side of the game machine main body 12 will be described.

[0047] As shown in FIG. 2, on the back surface of the inner frame 13 (specifically, the game board 24), a main control device 60 that controls the main game operations is mounted. The main control device 60 includes a main control board 61 housed in a board box 60a. Note that a trace means for leaving a trace of its opening or a trace structure for leaving a trace of its opening may be provided on the board box 60a. As the trace means, a configuration of a joint portion that inseparably couples a plurality of case bodies constituting the board box 60a and requires destruction of a predetermined portion when separated, or a configuration in which a sealing tape that leaves a trace of being peeled off by leaving an adhesive layer on an adhesion target when peeled off is attached so as to straddle the boundary between the plurality of case bodies can be considered. As the trace structure, a configuration in which an adhesive is applied to the boundary between a plurality of case bodies constituting the board box 60a can be considered.

[0048] A back pack unit 15 is installed so as to cover the back side of the inner frame 13 including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a synthetic resin having transparency, and a payout mechanism unit 73 and a control device assembly unit 74 are attached to the back pack 72.

[0049] The payout mechanism unit 73 includes a tank 75 to which game balls supplied from the island equipment in the game hall are sequentially replenished, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through a payout passage provided on the downstream side of the payout device 76. Note that the payout mechanism unit 73 is supplied with, for example, a main power supply of 24 volts AC, and a back pack board having a power switch for performing ON and OFF operations of the power supply is mounted thereon.

[0050] The control device set unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined power required by various control devices and the like, and controls the launch of the game balls accompanying the operation of the launch operation device 28 by the player. The payout control device 77 and the power supply / launch control device 78 are arranged one on top of the other in the front - rear direction so that the payout control device 77 is at the rear of the pachinko machine 10.

[0051] <Electrical Configuration of Pachinko Machine 10> FIG. 5 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0052] The main control device 60 includes a main control board 61 that controls the main game, and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. In the MPU 62, in addition to the main - side CPU 63 which is an arithmetic processing device including a control unit and an arithmetic unit, a main - side ROM 64, a main - side RAM 65, and a management IC 66 are built - in. In addition to the above elements, the MPU 62 also has a built - in interrupt circuit, a timer circuit, a data input / output circuit, and various counter circuits as random number generators.

[0053] The main - side ROM 64 is a memory (i.e., non - volatile storage means) such as a NOR - type flash memory and a NAND - type flash memory that does not require external power supply for memory retention, and is used as read - only. The main - side ROM 64 stores various control programs and fixed - value data executed by the main - side CPU 63.

[0054] The main - side RAM 65 is a memory (i.e., volatile storage means) such as an SRAM and a DRAM that requires external power supply for memory retention, and is used for both reading and writing. The main - side RAM 65 allows random access, and when compared with the same data capacity, it takes less time to read than the main - side ROM 64. The main - side RAM 65 temporarily stores various data for the execution of the control programs stored in the main - side ROM 64.

[0055] The management IC 66 is a management device that manages the ball entry mode of game balls in the game area PA based on the information supplied from the main CPU 63. Although details will be described later, the management IC 66 grasps the ball entry history of game balls into the general winning opening 31, special electric winning device 32, first operation opening 33, second operation opening 34, and out opening 24a, and according to the grasped ball entry history, the ball entry frequencies into the general winning opening 31, special electric winning device 32, first operation opening 33, and second operation opening 34 are grasped.

[0056] The MPU 62 is provided with an input port and an output port respectively. On the input side of the MPU 62, a power failure monitoring board 67 and a payout control device 77 provided in the main control device 60 are connected. A power supply / emission control device 78 having a function of supplying operating power is connected to the power failure monitoring board 67, and operating power is supplied to the MPU 62 via the power failure monitoring board 67.

[0057] On the input side of the MPU 62, various sensors such as various ball entry detection sensors 42a to 49a are connected. As already described, the various ball entry detection sensors 42a to 49a are the first winning opening detection sensor 42a, the second winning opening detection sensor 43a, the third winning opening detection sensor 44a, the special electric detection sensor 45a, the first operation opening detection sensor 46a, the second operation opening detection sensor 47a, the out opening detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 performs ball entry determination for each ball entry part. Also, in the main CPU 63, various lotteries are executed based on winning at the first operation opening 33, and various lotteries are executed based on winning at the second operation opening 34.

[0058] On the output side of the MPU 62, a power failure monitoring board 67, a payout control device 77, and an audio / light emission control device 81 are connected. To the payout control device 77, for example, a bonus ball command is output based on the fact that a game ball has entered a bonus ball corresponding ball entry part among the above ball entry parts where the occurrence of ball entry corresponds to the payout of game balls. Various commands such as a variation command, a type command, and an opening command are output to the audio / light emission control device 81.

[0059] On the output side of the MPU62, a special power drive unit 32b for opening and closing the opening / closing door 32a of the special power winning device 32, a general power drive unit 34b for opening and closing the general power component 34a of the second operation port 34, a special diagram unit 37, and a general diagram unit 38 are connected. Incidentally, the special diagram unit 37 is provided with a special diagram display unit 37a and a special diagram hold display unit 37b, and all of these are connected to the output side of the MPU62. Similarly, the general diagram unit 38 is provided with a general diagram display unit 38a and a general diagram hold display unit 38b, and all of these are connected to the output side of the MPU62. Various driver circuits are provided on the main control board 61, and through the driver circuits, the MPU62 executes drive control of various drive units and various display units.

[0060] That is, in the opening / closing execution mode, drive control of the special power drive unit 32b is executed in the main CPU63 so that the special power winning device 32 is opened and closed. Also, when the general power component 34a wins in the open state, drive control of the general power drive unit 34b is executed in the main CPU63 so that the general power component 34a is opened and closed. Also, in each game round, display control of the special diagram display unit 37a is executed in the main CPU63. Also, when indicating the lottery result of whether to set the general power component 34a to the open state, display control of the general diagram display unit 38a is executed in the main CPU63. Also, when a winning occurs at the first operation port 33 or the second operation port 34, or when variable display starts in the special diagram display unit 37a, display control of the special diagram hold display unit 37b is executed in the main CPU63, and when a winning occurs at the through gate 35, or when variable display starts in the general diagram display unit 38a, display control of the general diagram hold display unit 38b is executed in the main CPU63.

[0061] The power failure monitoring board 67 relays the main control board 61 and the power supply / transmission control device 78, and monitors the voltage of 24 volts of DC stabilized power, which is the maximum voltage output from the power supply / transmission control device 78. The payout control device 77 performs payout control of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0062] The power supply and emission control device 78 is connected to, for example, a commercial power supply (external power supply) in a game hall or the like. Then, based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., respectively, and supplies the generated operating power. Incidentally, the power supply and emission control device 78 is provided with a power supply unit for power failure such as a backup capacitor. Even when the power of the pachinko machine 10 is in the OFF state, power for storage and retention is supplied from the power supply unit for power failure to the main side RAM 65 of the main control device 60 and the payout control device 77. Further, the power supply and emission control device 78 is responsible for the emission control of the game ball emission mechanism 27, and the game ball emission mechanism 27 is driven when predetermined emission conditions are met.

[0063] The voice and light emission control device 81 drives and controls the display light emission unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and controls the display control device 82. The display control device 82 executes the display control of the symbol display device 41 based on the commands received from the voice and light emission control device 81.

[0064] <Electrical configuration for performing various lotteries by the main side CPU 63> Next, the electrical configuration for performing various lotteries by the main side CPU 63 will be described with reference to FIG. 6.

[0065] During the game, the main CPU 63 uses various counter information to perform jackpot generation lottery, setting of the display of the special figure display unit 37a, setting of the symbol display of the symbol display device 41, setting of the display of the normal figure display unit 38a, etc. Specifically, as shown in FIG. 6, a jackpot random number counter C1 used for the lottery of jackpot occurrence, a jackpot type counter C2 used for determining the jackpot type, a reach random number counter C3 used for the reach generation lottery when the symbol display device 41 fluctuates out of range, a random number initial value counter CINI used for setting the initial value of the jackpot random number counter C1, and a variation type counter CS for determining the display duration in the special figure display unit 37a and the symbol display device 41 are used. Further, a general electric accessory release counter C4 used for the lottery of whether to put the general electric accessory 34a of the second operation port 34 in the general electric open state is used. Note that the above counters C1 to C3, CINI, CS, and C4 are provided in various counter areas 65b of the main RAM 65.

[0066] Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that is incremented by 1 from the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short time intervals. Information corresponding to the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in a hold storage area 65a provided as acquisition information storage means in the main RAM 65 when a winning occurs at the first operation port 33 or the second operation port 34.

[0067] The hold storage area 65a includes a hold area RE and an execution area AE. The hold area RE includes a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. In accordance with the winning history at the first operation port 33 or the second operation port 34, a combination of the numerical information of the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in any one of the hold areas RE1 to RE4.

[0068] In this case, when a winning entry into the first operation port 33 or the second operation port 34 occurs continuously multiple times, each numerical information is stored in chronological order in the first hold area RE1 → the second hold area RE2 → the third hold area RE3 → the fourth hold area RE4. By providing these four hold areas RE1 to RE4 in this way, the winning history of the game balls entering the first operation port 33 or the second operation port 34 can be held and stored up to a maximum of four.

[0069] Note that the number that can be held and stored is not limited to four and can be arbitrary, and can be other plural numbers such as two, three, or five or more, or can be a single number.

[0070] The execution area AE is an area for moving each numerical information stored in the first hold area RE1 of the hold area RE when starting the variable display of the special drawing display unit 37a. At the start of one game round, a win / loss determination or the like is performed based on various numerical information stored in the execution area AE.

[0071] The above-mentioned each counter will be described in detail.

[0072] First, the general electric accessory release counter C4 will be described. The general electric accessory release counter C4 is configured to be incremented by 1 in order within a range of, for example, 0 to 250, and return to "0" after reaching the maximum value. The general electric accessory release counter C4 is updated regularly and is stored in the general electric hold area 65c of the main side RAM65 at the timing when a game ball wins the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether to control the general electric accessory 34a to an open state based on the value of the stored general electric accessory release counter C4.

[0073] In this pachinko machine 10, a plurality of types of support modes are set so that the support modes by the general-electric accessory 34a are different from each other. Specifically, in the support modes, when compared in a situation where the shooting of the game balls continues in the same manner in the game area PA, the high-frequency support mode and the low-frequency support mode are set so that the frequency at which the general-electric accessory 34 of the second operation port 34 becomes the open state per unit time is relatively high or low.

[0074] In the high-frequency support mode and the low-frequency support mode, the probability of winning the general-electric open state in the general-electric open lottery using the general-electric open counter C4 is the same (for example, both are 4 / 5). However, in the high-frequency support mode, the number of times the general-electric accessory 34a becomes the open state when winning the general-electric open state is set to be larger than that in the low-frequency support mode, and further, the opening time for one time is set to be longer. In this case, when winning the general-electric open state in the high-frequency support mode and the open state of the general-electric accessory 34a occurs multiple times, the closing time from the end of one open state to the start of the next open state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, the guaranteed time (that is, the display duration for one time in the general diagram display section 38a) that is minimally guaranteed for the next general-electric open lottery to be conducted after one general-electric open lottery is set to be shorter than that in the low-frequency support mode.

[0075] As described above, in the high-frequency support mode, the probability of winning the second operation port 34 is higher than that in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of winning the first operation port 33 is higher than that of the second operation port 34, but in the high-frequency support mode, the probability of winning the second operation port 34 is higher than that of the first operation port 33. When winning the second operation port 34 occurs, a predetermined number of game balls are paid out. Therefore, in the high-frequency support mode, the player can play the game while not reducing the number of balls in hand too much.

[0076] Incidentally, the configuration for making the frequency of the general power release state per unit time higher in the high-frequency support mode than in the low-frequency support mode is not limited to the above, and for example, it may be a configuration for increasing the probability of winning the general power release state in the general power release lottery. Also, in a configuration where a plurality of types of guaranteed times (for example, the time of the variable display executed by the general drawing display unit 38a based on winning in the through gate 35) are prepared for ensuring the next general power release lottery after one general power release lottery is performed, in the high-frequency support mode, a shorter guaranteed time may be more likely to be selected or the average guaranteed time may be set to be shorter than in the low-frequency support mode. Furthermore, by applying any one condition or an arbitrary combination of conditions among increasing the number of release times, increasing the release time, shortening the guaranteed time ensured for the next general power release lottery after one general power release lottery is performed, shortening the average time of such guaranteed times, and increasing the winning probability, the advantage of the high-frequency support mode over the low-frequency support mode may be enhanced.

[0077] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in order within a range of, for example, 0 to 599, and after reaching the maximum value, it returns to "0". In particular, when the winning random number counter C1 makes one full cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. Note that the random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is periodically updated and stored in the reserved storage area 65a of the main-side RAM 65 at the timing when the game ball wins in the first operating port 33 or the second operating port 34.

[0078] The values of the random numbers for winning the big hit are stored in the main-side ROM 64 as a hit / miss table. As the hit / miss table, a hit / miss table for the low-probability mode and a hit / miss table for the high-probability mode are set. That is, in this pachinko machine 10, a low-probability mode and a high-probability mode are set as the lottery modes in the hit / miss lottery means.

[0079] In a gaming state where the pass / fail table for the low-probability mode is referred to during the above lottery, the number of random numbers that result in a big win is two. On the other hand, in a gaming state where the pass / fail table for the high-probability mode is referred to during the above lottery, the number of random numbers that result in a big win is twenty. Note that if the winning probability of the high-probability mode is higher than that of the low-probability mode, the number of random numbers that result in a win is arbitrary.

[0080] The big win type counter C2 is configured to be incremented by one in sequence within the range of 0 to 29 and return to "0" after reaching the maximum value. The big win type counter C2 is updated periodically and stored in the hold storage area 65a at the timing when a game ball wins at the first activation port 33 or the second activation port 34.

[0081] In this pachinko machine 10, a plurality of big win results are set. These plurality of big win results are set by providing differences in three conditions: (1) the opening / closing control mode of the special electric winning device 32 in the opening / closing execution mode, (2) the lottery mode in the pass / fail lottery means after the end of the opening / closing execution mode, and (3) the support mode in the general electric accessory 34a of the second activation port 34 after the end of the opening / closing execution mode.

[0082] As the opening / closing control mode of the special electric winning device 32 in the opening / closing execution mode, a high-frequency winning mode and a low-frequency winning mode are set so that the frequency of winning at the special electric winning device 32 becomes relatively high or low from the start to the end of the opening / closing execution mode. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the round games up to a predetermined number of times are executed as the upper limit.

[0083] Here, a round game is a game that continues until either a predetermined upper limit duration elapses or a predetermined upper limit number of game balls win in the special electric winning device 32. Also, the number of round games in the opening / closing execution mode triggered by a big win result is the same fixed number of rounds regardless of the type of big win result that triggered the transition. Specifically, the upper limit number of rounds of the round game is set to 15 rounds regardless of which big win result occurs.

[0084] Further, in this pachinko machine 10, a plurality of types are set by making the release duration of one release mode of the special electric winning device 32 different from the release duration from when the special electric winning device 32 is released until it is closed. Specifically, a long-duration mode set to 29 seconds with a long release duration and a short-duration mode set to 0.06 seconds with a short release duration shorter than the above long duration are set.

[0085] In this pachinko machine 10, in a situation where the launch operation device 28 is being operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. Also, the upper limit number of the end condition of the round game is set to 9. Then, in the long-duration mode among the above release modes, a release duration longer than the product of the launch cycle of the game ball and one round game is set. On the other hand, in the short-duration mode, a release duration shorter than the product of the launch cycle of the game ball and one round game, more specifically, a release duration shorter than the launch cycle of the game ball is set. Therefore, when one release is performed in the long-duration mode, it is expected that the number of wins corresponding to the upper limit number in one round game will occur for the special electric winning device 32, and when one release is performed in the short-duration mode, it is expected that no win will occur for the special electric winning device 32 or, if a win occurs, it will be about one.

[0086] In the high-frequency winning mode, the special power winning device 32 is opened once in each round game in a long-time mode. On the other hand, in the low-frequency winning mode, the special power winning device 32 is opened once in each round game in a short-time mode.

[0087] Note that the number of openings and closings of the special power winning device 32, the number of round games, the opening duration for one opening, and the upper limit number in one round game in the high-frequency winning mode and the low-frequency winning mode are not limited to the above values and are arbitrary as long as the winning occurrence frequency for the special power winning device 32 is higher in the high-frequency winning mode than in the low-frequency winning mode from the start to the end of the opening / closing execution mode.

[0088] The distribution destination of the game result for the jackpot type counter C2 is stored as a distribution table in the main ROM64. And as such distribution destinations, a low-probability jackpot result, a low-winning high-probability jackpot result, and a most advantageous jackpot result are set.

[0089] The low-probability jackpot result is a jackpot result where the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the low-probability mode and the support mode becomes the high-frequency support mode. However, this high-frequency support mode shifts to the low-frequency support mode when the number of game times reaches the end reference number of times (specifically, 100 times) after the transition.

[0090] The low-winning high-probability jackpot result is a jackpot result where the opening / closing execution mode becomes the low-frequency winning mode, and after the end of the opening / closing execution mode, the win / loss lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / loss lottery becomes a jackpot state win and a transition to the jackpot state occurs.

[0091] The most favorable jackpot result is a jackpot result in which the opening / closing execution mode becomes the high-frequency winning mode, and after the end of the opening / closing execution mode, the winning / losing lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the winning / losing lottery becomes a jackpot state win and a transition to the jackpot state occurs due to that.

[0092] In addition, in relation to each of the above game states, the normal game state refers to a state in which the winning / losing lottery mode is not the opening / closing execution mode, but rather the low-probability mode, and the support mode is the low-frequency support mode. Also, as a game result configuration, a low-winning high-probability jackpot result may not be set. Further, in the opening / closing execution mode of the low-winning high-probability jackpot result, the number of rounds of the round game may be set to be less than that in the case of the low-probability jackpot result and the most favorable jackpot result.

[0093] In the payout table, among the values of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to the low-probability jackpot result, "10 to 14" correspond to the low-winning high-probability jackpot result, and "15 to 29" correspond to the most favorable jackpot result.

[0094] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by 1 in order within a range of, for example, 0 to 238, and return to "0" after reaching the maximum value. Here, in this pachinko machine 10, an expected effect is set as a type of display effect in the symbol display device 41. The expected effect refers to a display state in a gaming machine equipped with a symbol display device 41 capable of performing variable display of symbols, in which, in a game round that results in a predetermined jackpot result and the final stop result becomes a result corresponding to the award, before the stop result is derived and displayed after the start of the variable display of the symbols in the symbol display device 41, it makes the player think that it is a variable display state in which the result corresponding to the award is likely to occur. Specifically, for the result corresponding to the award, a combination of symbols with the same number attached on any of the valid lines is stopped and displayed.

[0095] For the anticipated performance, two types are set: a reach display and a preview display for anticipating the occurrence of the reach display and the occurrence of the result of dealing with the granting of the reach display at a stage prior to the occurrence of the reach display.

[0096] The reach display includes a display state in which, for some of the plurality of symbol columns displayed on the display surface 41a of the symbol display device 41, symbols are stopped and displayed to show a combination of reach symbols, and in that state, the symbols in the remaining symbol columns are variably displayed. Further, in the state where the combination of reach symbols is displayed as described above, while variably displaying the symbols in the remaining symbol columns, a reach effect is performed by displaying a predetermined character or the like as a moving image on the background screen, or a reach effect is performed by reducing or hiding the combination of reach symbols and then displaying a predetermined character or the like as a moving image over substantially the entire display surface 41a.

[0097] The preview display includes a mode of displaying a character separately from the symbols on the symbol column in a situation where the variable display of symbols has started on the display surface 41a of the symbol display device 41, in a situation where the symbols are variably displayed in all the symbol columns, or in a situation where the symbols are variably displayed in some of the symbol columns, that is, in a plurality of symbol columns. Also included are those that change the background screen to a predetermined mode different from the previous mode and those that change the symbols on the symbol column to a predetermined mode different from the previous mode. Such a preview display can occur in any game round whether or not a reach display is performed, but is set to occur with a higher probability when a reach display is performed than when a reach display is not performed.

[0098] The reach display is executed regardless of the value of the reach random number counter C3 in a game round where the same combination of symbols is finally stopped and displayed. Also, in a game round corresponding to a jackpot result where the same combination of symbols is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Further, in a game round corresponding to a non-winning result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0099] On the other hand, the determination of whether to perform a preview display is not made by the main control device 60, but by the audio-visual control device 81. In this case, the audio-visual control device 81 executes a lottery process for the preview display so as to satisfy at least one of the conditions that a preview display is more likely to occur in a game round corresponding to any jackpot result than in a game round corresponding to a non-winning result, and that a preview display with a low appearance rate is more likely to occur. Incidentally, this lottery result is reflected when an effect for the game is executed by the symbol display device 41.

[0100] Next, the variable type counter CS will be described. The variable type counter CS is configured to be incremented by 1 in order within a range of, for example, 0 to 198, and return to "0" after reaching the maximum value. The variable type counter CS is used in the main CPU 63 to determine the display duration in the special figure display section 37a and the display duration of the symbols in the symbol display device 41. The variable type counter CS is updated once each time the normal process described later is executed, and is repeatedly updated even within the remaining time in the normal process. Then, the buffer value of the variable type counter CS is acquired when determining the variable pattern at the start of the variable display in the special figure display section 37a and at the start of the symbol variation by the symbol display device 41.

[0101] <Regarding the processing configuration of the main CPU 63> Next, each process executed to advance the game by the main CPU 63 will be described. The processes of such main CPU 63 are roughly classified into a main process that is started with power-on and a timer interrupt process that is started periodically (at a cycle of 4 msec in this embodiment).

[0102] <Main Process> First, the main process will be described with reference to the flowchart of FIG. 7.

[0103] First, a power-on wait process is executed (step S101). In the power-on wait process, for example, the process waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 sec) has elapsed since the main process was started. The operation start and initial setting of the symbol display device 41 will be completed during the execution period of such power-on wait process. Thereafter, access to the main RAM 65 is permitted (step S102), and the internal function registers of the main CPU 63 are set (step S103).

[0104] Thereafter, it is determined whether the RAM erase switch provided in the power / launch control device 78 has been manually operated (step S104), and further, it is determined whether “1” is set in the power failure flag of the main RAM 65 (step S105). Also, a checksum calculation process for calculating a checksum is executed (step S106), and it is determined whether the checksum matches the checksum saved at the time of power-off, that is, the validity of the stored data is determined (step S107).

[0105] In this pachinko machine 10, for example, when initializing the RAM data at the start of business in the game hall, the power is turned on while pressing the RAM erase switch. Therefore, if the RAM erase switch is pressed, the process proceeds to step S108. Also, when the power-off occurrence information is not set or when an abnormality in the data stored and held by the checksum is confirmed, the process similarly proceeds to step S108. In step S108, the main RAM 65 is cleared. Thereafter, the process proceeds to step S109.

[0106] On the other hand, when the RAM erase switch is not pressed, proceeding to step S109 without executing the process of step S108 on the condition that the power failure flag is set to "1" and the checksum is normal. In step S109, a power-on setting process is executed. In the power-on setting process, a predetermined area of the main-side RAM 65 such as initialization of the power failure flag is set to an initial value, and a command corresponding to the current gaming state is transmitted to the audio / light emission control device 81. Further, after executing the process of step S109, a recognition process (step S110) for causing the management IC 66 to recognize various information and a data output process for outputting various data to a reading device connected to the MPU 62 are executed (step S111). Details of these recognition process and data output process will be described later.

[0107] Note that the main-side CPU 63 is configured to periodically execute timer interrupt processing, but the generation of timer interrupt processing is prohibited at the stage when the main processing is started. The state in which the generation of this timer interrupt processing is prohibited is released at the timing before the process of step S112 is executed after the process of step S111 is completed, and the execution of the timer interrupt processing is permitted. Thereby, when the supply of operating power to the main-side CPU 63 is started, the timer interrupt processing is not executed until the stage before the process of step S112 is started after the data output process of step S111 is completed. Therefore, until such a situation occurs, the process for advancing the game by the main-side CPU 63 is not started.

[0108] Thereafter, the process proceeds to the remaining processes of steps S112 to S115. That is, although the main CPU 63 is configured to periodically execute timer interrupt processing, a remaining time will occur between one timer interrupt processing and the next timer interrupt processing. This remaining time will vary according to the processing completion time of each timer interrupt processing, but the remaining processes of steps S112 to S115 are repeatedly executed using such irregular time. In this regard, it can be said that the remaining processes of steps S112 to S115 are non-periodic processes that are executed non-periodically.

[0109] In the remaining process, first, in step S112, a setting for interrupt prohibition is performed to prohibit the occurrence of timer interrupt processing. In the subsequent step S113, a random number initial value update process for updating the random number initial value counter CINI is executed, and a variable counter update process for updating the variation type counter CS is executed in step S114. In these update processes, the current numerical information is read from the corresponding counter in the main RAM 65, and after executing a process of adding 1 to the read numerical information, a process of overwriting the original counter is executed. In this case, when the counter value reaches the maximum value, each is cleared to "0". Thereafter, in step S115, a setting for interrupt permission is performed to switch from a state where the occurrence of timer interrupt processing is prohibited to a permitted state. After executing the process of step S115, the process returns to step S112, and the processes of steps S112 to S115 are repeated.

[0110] <Timer Interrupt Processing> Next, the timer interrupt processing will be described with reference to the flowchart of FIG. 8. The timer interrupt processing is executed periodically (for example, at a cycle of 4 msec).

[0111] First, execute the power failure information storage process (step S201). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of a power cut is received from the power failure monitoring board 67. When the occurrence of a power failure is identified, an infinite loop occurs after executing the power failure processing. In the power failure processing, a "1" is set in the power failure flag of the main-side RAM 65, a checksum is calculated, and the calculated checksum is saved.

[0112] After that, execute the lottery random number update process (step S202). In the lottery random number update process, the update of the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power accessory release counter C4 is executed. Specifically, the current numerical information is sequentially read out from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power accessory release counter C4, and after executing the process of adding 1 to each of the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value reaches the maximum value, it is cleared to "0" respectively. After that, in step S203, the random number initial value update process is executed in the same manner as step S113, and in step S204, the variable counter update process is executed in the same manner as step S114.

[0113] After that, execute the fraud detection process of monitoring whether a predetermined event set as a monitoring target for fraud has occurred (step S205). In the fraud detection process, the occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, a "1" is set in the game stop flag provided in the main-side RAM 65. In the subsequent step S206, by determining whether a "1" is set in the game stop flag, it is determined whether the game is in a stopped state. When a negative determination is made in step S206, the processes after step S207 are executed.

[0114] In step S207, port output processing is executed. In the port output processing, when output information is set in the previous timer interrupt processing, processing for performing an output corresponding to the output information to various drive units 32b and 34b is executed. For example, when information indicating that the special electric winning device 32 should be switched to the open state is set, the output of a drive signal to the special electric drive unit 32b is started, and when information indicating that it should be switched to the closed state is set, the output of the drive signal is stopped. Also, when information indicating that the general electric accessory 34a of the second operating port 34 should be switched to the open state is set, the output of a drive signal to the general electric drive unit 34b is started, and when information indicating that it should be switched to the closed state is set, the output of the drive signal is stopped.

[0115] Thereafter, reading processing is executed (step S208). In the reading processing, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in subsequent processing.

[0116] Thereafter, ball entry detection processing is executed (step S209). In the ball entry detection processing, signals received from the respective ball entry detection sensors 42a to 49a are read, and based on the read results, the presence or absence of balls entering the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 is specified. Details of the ball entry detection processing will be described later.

[0117] Thereafter, timer update processing for collectively updating the numerical information of a plurality of types of timer counters provided in the main side RAM 65 is executed (step S210). In this case, the timer counters whose stored numerical information is updated by subtraction are aggregated and handled, but it may also be configured to collectively perform both the update of the subtraction type timer counter and the update of the addition type timer counter.

[0118] Thereafter, a launch control process for controlling the launch of game balls is executed (step S211). In a situation where the launch operation to the launch operation device 28 continues, one game ball is launched at a predetermined launch cycle of 0.6 seconds. In the subsequent step S212, as input state monitoring processing, based on the information read in the reading process of step S208, disconnection confirmation of each ball entry detection sensor 42a to 49a and opening confirmation of the game machine main body 12 and the front door frame 14 are performed.

[0119] After that, a special drawing and special electric control process for executing the execution control of the game round and the execution control of the opening / closing execution mode is executed (step S213). In this special drawing and special electric control process, when a winning occurs at the first operation port 33 or the second operation port 34 in a situation where the number of reservation information stored in the reservation storage area 65a is less than the upper limit number, the numerical information of the hit random number counter C1, the big hit type counter C2, and the reach random number counter C3 at that time is used as reservation information, and a process of storing it in the reservation storage area 65a in time series is executed. Also, in the special drawing and special electric control process, under the condition that it is not during the game round and the opening / closing execution mode and reservation information is stored, a validity determination process for determining whether the reservation information corresponds to a big hit win, and a distribution determination process for determining which big hit result the reservation information corresponds to when it corresponds to a big hit win are executed. Also, in the special drawing and special electric control process, not only the validity determination process and the distribution determination process, but also when the reservation information does not correspond to a big hit win, a reach determination process for determining whether the reservation information corresponds to the occurrence of a reach is executed, and a process of selecting the continuation time of the game round using the numerical information of the variation type counter CS at that time is executed. Then, a variation command including information on the continuation time corresponding to the results of these respective processes and a type command including information on the game result are transmitted to the sound and light control device 81, and the variation display of the pattern on the special drawing display unit 37a is started. The sound and light control device 81 starts a game-related effect corresponding to the content of these commands on the display and light emission unit 53 and the speaker unit 54 by receiving the variation command and the type command. Also, the sound and light control device 81 transmits a variation pattern command corresponding to the content of the variation command and the type command to the display control device 82. The display control device 82 starts the variation display of the pattern corresponding to the content of the variation pattern command on the pattern display device 41 by receiving the variation pattern command. Thereby, a state where one game round is started is achieved.

[0120] In the special drawing special power control process, during the execution of one game round, it is determined whether the duration of the game round determined at the start of the game round has elapsed, thereby determining whether it is the end timing of that game round. If it is the end timing, the process of ending that game round is executed in a state where a display corresponding to the game result is performed. In this case, if the current game round corresponds to the occurrence of any jackpot result, the symbol corresponding to the type of that jackpot result is stopped and displayed on the special drawing display unit 37a. If the current game round corresponds to a losing result, the symbol corresponding to the losing result is stopped and displayed on the special drawing display unit 37a. Also, a final stop command indicating that the game round should be ended is transmitted to the audio-visual control device 81. The audio-visual control device 81 ends the production for the current game round in the display and lighting unit 53 and the speaker unit 54 by receiving the final stop command. Also, the audio-visual control device 81 transmits the final stop command to the display control device 82. The display control device 82 ends the production for the current game round in the symbol display device 41 by receiving the final stop command.

[0121] In the special drawing special power control process, when the result of a game round is a result corresponding to a transition to the opening / closing execution mode, a process for starting the opening / closing execution mode is executed. At the start, an opening command indicating that the opening / closing execution mode is to be started is transmitted to the audio-visual control device 81. Also, in the special drawing special power control process, a process for starting each round game and a process for ending each round game are executed. When a round game is started, the special power winning device 32 is in an open state, and when a round game ends, the special power winning device 32 is in a closed state. In each of these processes, an open command indicating that a round game is started is transmitted to the audio-visual control device 81, and a close command indicating that a round game is ended is transmitted to the audio-visual control device 81. Also, in the special drawing special power control process, when ending the opening / closing execution mode, an ending command indicating that is transmitted to the audio-visual control device 81. The audio-visual control device 81 causes the display / lighting unit 53 and the speaker unit 54 to perform an effect for the opening / closing execution mode in a manner corresponding to various commands received during the opening / closing execution mode. Also, the audio-visual control device 81 transmits a command corresponding to the command received during the opening / closing execution mode to the display control device 82. The display control device 82 causes the symbol display device 41 to perform an effect for the opening / closing execution mode in a manner corresponding to various commands received during the opening / closing execution mode. Also, in the special drawing special power control process, when ending the opening / closing execution mode, a process is executed so that the winning / losing lottery mode and the support mode after the end of the opening / closing execution mode become modes corresponding to the type of jackpot result that triggered the execution of the opening / closing execution mode.

[0122] After executing the special drawing and special power control process in step S213 in the timer interrupt process, execute the general drawing and general power control process (step S214). In the general drawing and general power control process, when a winning entry to the through gate 35 occurs, a process for acquiring the hold information on the general drawing side is executed, and when the hold information on the general drawing side is stored, a release determination is made for the hold information, and further, a process for performing an effect for the general drawing is executed based on the release determination. Also, based on the result of the release determination, a process for opening and closing the general power device 34a of the second operating port 34 is executed. In this case, if the support mode is the low-frequency support mode, the corresponding process is executed, and if the support mode is the high-frequency support mode, the corresponding process is executed. Also, in the case of the open / close execution mode, even if the immediately preceding support mode was the high-frequency support mode, it becomes the low-frequency support mode.

[0123] In the subsequent step S215, based on the processing results of the immediately preceding steps S213 and S214, output information for reflecting the increase or decrease in the number of hold information items related to the special drawing display section 37a in the special drawing hold display section 37b is set, and output information for reflecting the increase or decrease in the number of hold information items related to the general drawing display section 38a in the general drawing hold display section 38b is set. Also, in step S215, based on the processing results of the immediately preceding steps S213 and S214, output information for updating the display content of the special drawing display section 37a is set, and output information for updating the display content of the general drawing display section 38a is set.

[0124] Thereafter, the content of the commands and signals received from the payout control device 77 is confirmed, and a payout state reception process for performing processing corresponding to the confirmation result is executed (step S216). Further, a payout output process for setting a prize ball command as an output target is executed (step S217). Further, an external information setting process for controlling the start and end of the output of an external signal according to the processing result of various processes executed in the current timer interrupt process is executed (step S218). Thereafter, a management output process for outputting information corresponding to the result of the entry of game balls in the game area PA to the management IC 66 is executed (step S219). Details of the management output process will be described later.

[0125] Next, the main CPU 63 will explain the configuration for specifying the presence or absence of game balls entering the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the through gate 35 based on the detection results of the respective ball entry detection sensors 42a to 49a. FIG. 9 is an explanatory diagram for explaining a configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0126] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so as to be able to handle 8 types of signals simultaneously. And an area where information of "0" or "1" is stored according to the voltage of each signal is provided in a one-to-one correspondence with each terminal. That is, as the said area, it is equipped with the 0th bit D0~the 7th bit D7. Further, although more than 8 types of signals will be input to the input port 63a, in order to limit the simultaneous input targets to 8 types, the signal group to be input to the input port 63a is switched through the switching control by the driver IC.

[0127] In the ball entry detection process (step S209) of the timer interrupt process (Figure 8), the signal group to be input to the input port 63a is set to the signal groups from the respective ball entry detection sensors 42a to 49a. In such a set situation, the information corresponding to the detection signal from the first winning port detection sensor 42a is stored in the 0th bit D0, the information corresponding to the detection signal from the second winning port detection sensor 43a is stored in the 1st bit D1, the information corresponding to the detection signal from the third winning port detection sensor 44a is stored in the 2nd bit D2, the information corresponding to the detection signal from the special power detection sensor 45a is stored in the 3rd bit D3, the information corresponding to the detection signal from the first operation port detection sensor 46a is stored in the 4th bit D4, the information corresponding to the detection signal from the second operation port detection sensor 47a is stored in the 5th bit D5, the information corresponding to the detection signal from the out port detection sensor 48a is stored in the 6th bit D6, and the information corresponding to the detection signal from the gate detection sensor 49a is stored in the 7th bit D7.

[0128] When each of the above-mentioned ball entry detection sensors 42a to 49a does not detect the passage of the game ball, it outputs a LOW-level signal indicating non-detection as the detection signal, and when it detects the passage of the game ball, it outputs a HI-level signal indicating detection as the detection signal. Then, at the input port 63a, when a LOW-level signal is received, "0" information is stored in the corresponding bit, and when a HI-level signal is received, "1" information is stored in the corresponding bit. That is, in a situation where the passage of the game ball is not detected by the ball entry detection sensors 42a to 49a, "0" information corresponding to the information indicating non-detection is stored in the corresponding bit, and in a situation where the passage of the game ball is detected, "1" information corresponding to the information indicating detection is stored in the corresponding bit.

[0129] Figure 10 is a flowchart showing the ball entry detection process executed in step S209 of the timer interrupt process (Figure 8).

[0130] When it is confirmed that the situation has switched from the state where the information "0" is stored in the 0th bit D0 to the state where the information "1" is stored, it is determined that one game ball has been detected by the first winning port detection sensor 42a (step S301: YES). In this case, "1" is set to the first output flag provided in the main-side RAM 65 (step S302), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S303). The first output flag is a flag for the main CPU 63 to specify that the management IC 66 should execute information output indicating that one game ball has been detected by the first winning port detection sensor 42a. The 10 prize ball counter is a counter for the main CPU 63 to specify the number of times to execute the payout of 10 game balls. When the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (Figure 8), and when the 10 prize ball command has been output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0131] When it is confirmed that the situation has switched from the state where the information "0" is stored in the 1st bit D1 to the state where the information "1" is stored, it is determined that one game ball has been detected by the second winning port detection sensor 43a (step S304: YES). In this case, "1" is set to the second output flag provided in the main-side RAM 65 (step S305), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S306). The second output flag is a flag for the main CPU 63 to specify that the management IC 66 should execute information output indicating that one game ball has been detected by the second winning port detection sensor 43a.

[0132] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the second bit D2 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the third winning opening detection sensor 44a (step S307: YES). In this case, "1" is set in the third output flag provided in the main side RAM 65 (step S308), and the value of the ten prize ball counter provided in the main side RAM 65 is incremented by 1 (step S309). The third output flag is a flag for the main CPU 63 to specify to the management IC 66 the information output indicating that one game ball has been detected by the third winning opening detection sensor 44a to be executed.

[0133] When it is confirmed that the situation has switched from the state where the information "0" is stored in the third bit D3 to the state where the information "1" is stored, it is determined that one game ball has been detected by the special power detection sensor 45a (step S310: YES). In this case, "1" is set to the special power winning flag provided in the main-side RAM 65 (step S311), "1" is set to the fourth output flag provided in the main-side RAM 65 (step S312), and further, the value of the 15 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S313). The special power winning flag is a flag for the main-side CPU 63 to identify that one game ball has entered the special power winning device 32 in the round game of the opening / closing execution mode. In the special power control process (step S213) of the timer interrupt process (Figure 8), by confirming that "1" is set in the special power winning flag, it is identified that one game ball has entered the special power winning device 32, and the remaining number of possible balls entering the special power winning device 32 in the round game is decremented by 1. When the process of decrementing the number of possible balls entering by 1 is executed, the special power winning flag is cleared to "0". The fourth output flag is a flag for the main-side CPU 63 to identify that the information output indicating that one game ball has been detected by the special power detection sensor 45a should be executed for the management IC 66. The 15 prize ball counter is a counter for the main-side CPU 63 to identify the number of times the payout of 15 game balls should be executed. When the value of the 15 prize ball counter is 1 or more, in the payout output process of step S217 in the timer interrupt process (Figure 8), a 15 prize ball command is output to the payout control device 77, and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0134] When it is confirmed that the situation has switched from the situation where the information of "0" is stored in the 4th bit D4 to the situation where the information of "1" is stored, it is determined that one game ball has been detected by the first operation port detection sensor 46a (step S314: YES). In this case, "1" is set to the first operation winning flag provided in the main side RAM 65 (step S315), "1" is set to the fifth output flag provided in the main side RAM 65 (step S316), and further, the value of the single prize ball counter provided in the main side RAM 65 is incremented by 1 (step S317). The first operation winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the first operation port 33. In the special figure special power control process (step S213) of the timer interrupt process (Figure 8), by confirming that "1" is set in the first operation winning flag, the process of newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4. When it is confirmed in the special power special power control process (step S213) that "1" is set in the first operation winning flag and the process corresponding to the confirmation is executed, the first operation winning flag is cleared to "0". The fifth output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the first operation port detection sensor 46a should be executed for the management IC 66. The single prize ball counter is a counter for the main side CPU 63 to identify the number of times to execute the payout of one game ball. When the value of the single prize ball counter is 1 or more, in the payout output process of step S217 in the timer interrupt process (Figure 8), a single prize ball command is output to the payout control device 77, and when a single prize ball command is output once, the value of the single prize ball counter is decremented by 1. When the payout control device 77 receives a single prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0135] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the 5th bit D5 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the second operation port detection sensor 47a (step S318: YES). In this case, "1" is set to the second operation winning flag provided in the main side RAM 65 (step S319), "1" is set to the sixth output flag provided in the main side RAM 65 (step S320), and further, the value of the one winning ball counter provided in the main side RAM 65 is incremented by 1 (step S321). The second operation winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the second operation port 34. In the special figure special power control process (step S213) of the timer interrupt process (Figure 8), by confirming that "1" is set in the second operation winning flag, a process of newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4. When it is confirmed in the special power special power control process (step S213) that "1" is set in the second operation winning flag and the process corresponding to the confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the second operation port detection sensor 47a should be executed for the management IC 66.

[0136] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the 6th bit D6 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the out port detection sensor 48a (step S322: YES). In this case, "1" is set to the seventh output flag provided in the main side RAM 65 (step S323). The seventh output flag is a flag for the main side CPU 63 to identify that the information output indicating that one game ball has been detected by the out port detection sensor 48a should be executed for the management IC 66.

[0137] When it is confirmed that the situation has switched from the state where the information "0" is stored in the 7th bit D7 to the state where the information "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S324: YES). In this case, "1" is set in the gate winning flag provided in the main RAM 65 (step S325). The gate winning flag is a flag for the main CPU 63 to identify that one game ball has entered the through gate 35. In the general diagram general power control process (step S214) of the timer interrupt process (FIG. 8), by confirming that "1" is set in the gate winning flag, on the condition that the number of pieces of reservation information on the general diagram side stored in the general power reservation area 65c is less than the upper limit number of 4 pieces, the process of storing the numerical information of the current general power accessory release counter C4 as the reservation information on the general diagram side in the general power reservation area 65c is executed. When it is confirmed in the general diagram general power control process (step S214) that "1" is set in the gate winning flag and the process corresponding to the confirmation is executed, the gate winning flag is cleared to "0".

[0138] Note that since the timer interrupt process (FIG. 8) is started at a cycle of 4 msec as already described, when the detection of one game ball is started by one of the ball entry detection sensors 42a to 49a, in the situation where the detection of that one game ball is continued by the ball entry detection sensors 42a to 49a, the main CPU 63 specifies that one game ball has been detected by the ball entry detection sensors 42a to 49a. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0139] Next, the processing content executed by the payout control device 77 will be described. First, the electrical configuration of the payout control device 77 and various devices that communicate with the payout control device 77 will be described with reference to the block diagram of FIG. 11.

[0140] The payout control device 77 includes an MPU 91. In the MPU 91, in addition to the payout side CPU 92 which is an arithmetic processing device including a control unit and an arithmetic unit, a payout side ROM 93, a payout side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, etc. are built-in.

[0141] The payout-side ROM 93 is a memory that does not require external power supply for data retention, such as a NOR-type flash memory and a NAND-type flash memory (i.e., non-volatile storage means), and is used as read-only. The payout-side ROM 93 stores various control programs and fixed-value data executed by the payout-side CPU 92.

[0142] The payout-side RAM 94 is a memory that requires external power supply for data retention, such as SRAM and DRAM (i.e., volatile storage means), and is used for both reading and writing. The payout-side RAM 94 allows random access and has a shorter read time than the payout-side ROM 93 when compared with the same data capacity. The payout-side RAM 94 temporarily stores various data for the execution of the control programs stored in the payout-side ROM 93.

[0143] The payout-side CPU 92 can communicate bidirectionally with the main-side CPU 63. When the payout-side CPU 92 receives a prize ball command from the main-side CPU 63, it drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. Further, the payout-side CPU 92 monitors whether the game balls can be paid out normally, and if it is determined that the payout is not possible, it stops the payout device 76 even if the number of unpayout prize balls is stored in the payout-side RAM 94. In addition, the payout-side CPU 92 transmits a payout restriction command indicating that the payout cannot be performed normally to the main-side CPU 63. When the main-side CPU 63 receives the payout restriction command, it transmits a notification command to the audio-visual control device 81 so that a notification indicating that the game balls cannot be paid out normally is executed by the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54. The states in which the game balls cannot be paid out normally include a full state in which the lower tray 56a is full of game balls, a ballless state in which the tank 75 is not replenished with game balls, a payout abnormality state in which the payout device 76 does not operate normally, a main body open state in which the game machine main body 12 is opened from the outer frame 11, and a front door open state in which the front door frame 14 is opened from the inner frame 13.

[0144] A full detection sensor (not shown) is provided at an intermediate position of the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full detection sensor is input to the payout-side CPU 92. When the full detection sensor continuously detects game balls, the payout-side CPU 92 determines that it is in a full state, and when the state in which the full detection sensor continuously detects game balls is released, the payout-side CPU 92 determines that the full state has been released.

[0145] A ball non-detection sensor (not shown) is provided at an intermediate position in the game ball passage leading from the tank 75 to the payout device 76, and the detection result of the ball non-detection sensor is input to the payout-side CPU 92. When the ball non-detection sensor does not continuously detect a game ball, the payout-side CPU 92 specifies that it is in a ball non-state. When the state where the ball non-detection sensor does not continuously detect a game ball is released, the payout-side CPU 92 specifies that the ball non-state has been released.

[0146] The payout device 76 is provided with a payout detection sensor (not shown) for detecting the game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout-side CPU 92. When the payout detection sensor detects a game ball, the payout-side CPU 92 specifies that one game ball has been paid out from the payout device 76. Further, even though the payout-side CPU 92 is driving and controlling the payout device 76 to pay out game balls, when the payout detection sensor does not continuously detect a game ball, the payout-side CPU 92 specifies that it is in a payout abnormal state. When the state where the payout detection sensor does not continuously detect a game ball is released, the payout-side CPU 92 specifies that the payout abnormal state has been released.

[0147] A front door opening sensor 95 is provided on the front surface of the inner frame 13 (see FIG. 2), and the detection result of the front door opening sensor 95 is input to the dispensing side CPU 92. In this case, when the front door frame 14 is in the closed state with respect to the inner frame 13, the front door opening sensor 95 transmits a closed detection signal to the dispensing side CPU 92, and when the front door frame 14 is in the open state with respect to the inner frame 13, the front door opening sensor 95 transmits an open detection signal to the dispensing side CPU 92. The dispensing side CPU 92 identifies that the front door frame 14 is in the closed state when receiving a closed detection signal from the front door opening sensor 95, and identifies that the front door frame 14 is in the open state when receiving an open detection signal from the front door opening sensor 95. Further, the dispensing side CPU 92 transmits a front door opening command to the main side CPU 63 at the timing when it is identified that the front door frame 14 has changed from the closed state to the open state, and transmits a front door closing command to the main side CPU 63 at the timing when it is identified that the front door frame 14 has changed from the open state to the closed state. The main side CPU 63 identifies that the front door frame 14 is in the open state when receiving the front door opening command, and identifies that the front door frame 14 is in the closed state when receiving the front door closing command.

[0148] A main body opening sensor 96 is provided on the front surface of the back pack unit 15 (see Fig. 2), and the detection result of the main body opening sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state with respect to the outer frame 11, the main body opening sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state with respect to the outer frame 11, the main body opening sensor 96 transmits an open detection signal to the payout side CPU 92. The payout side CPU 92 identifies that the gaming machine main body 12 is in a closed state when receiving a closed detection signal from the main body opening sensor 96, and identifies that the gaming machine main body 12 is in an open state when receiving an open detection signal from the main body opening sensor 96. Further, the payout side CPU 92 transmits a main body opening command to the main side CPU 63 at the timing when it is identified that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body closing command to the main side CPU 63 at the timing when it is identified that the gaming machine main body 12 has changed from an open state to a closed state. The main side CPU 63 identifies that the gaming machine main body 12 is in an open state when receiving the main body opening command, and identifies that the gaming machine main body 12 is in a closed state when receiving the main body closing command.

[0149] Referring to the time chart of Fig. 12, the timer interrupt process executed by the payout side CPU 92 will be described. The timer interrupt process is repeatedly started at a predetermined period (for example, 2 msec).

[0150] First, the full state process is executed (step S401). In the full state process, as already described, it is determined whether it is in a full state based on the detection result of the full state detection sensor. When it is in a full state, a process for stopping the payout of the game balls is executed, and a command indicating that it is in a full state is transmitted to the main side CPU 63. Also, when the full state is released, a process for enabling the payout of the game balls is executed, and a command indicating that the full state has been released is transmitted to the main side CPU 63.

[0151] Thereafter, a ball useless process is executed (step S402). In the ball useless process, as already described, it is specified whether it is in a ball useless state based on the detection result of the ball useless detection sensor. When it is in a ball useless state, a process for stopping the payout of the game ball is executed, and a command indicating that it is in a ball useless state is transmitted to the main CPU 63. Further, when the ball useless state is released, a process for enabling the payout of the game ball is executed, and a command indicating that the ball useless state has been released is transmitted to the main CPU 63.

[0152] Thereafter, a payout abnormality monitoring process is executed (step S403). In the payout abnormality monitoring process, as already described, it is specified whether it is in a payout abnormality state based on the detection result of the payout detection sensor. When it is in a payout abnormality state, a process for stopping the payout of the game ball is executed, and a command indicating that it is in a payout abnormality state is transmitted to the main CPU 63. Further, when the payout abnormality state is released, a process for enabling the payout of the game ball is executed, and a command indicating that the payout abnormality state has been released is transmitted to the main CPU 63.

[0153] Thereafter, a front door opening monitoring process is executed (step S404). In the front door opening monitoring process, as already described, it is specified whether the front door frame 14 is in an open state based on the detection result of the front door opening sensor 95. When the front door frame 14 is in an open state, a process for stopping the payout of the game ball is executed, and a front door opening command is transmitted to the main CPU 63. Further, when the front door frame 14 is closed, a process for enabling the payout of the game ball is executed, and a front door closing command is transmitted to the main CPU 63.

[0154] After that, the main body opening monitoring process is executed (step S405). In the main body opening monitoring process, as already described, it is specified whether the gaming machine main body 12 is in an open state based on the detection result of the main body opening sensor 96. When the gaming machine main body 12 is in an open state, a process of stopping the payout of game balls is executed, and a main body opening command is transmitted to the main CPU 63. Also, when the gaming machine main body 12 is closed, a process of enabling the payout of game balls is executed, and a main body closing command is transmitted to the main CPU 63.

[0155] After that, the command reading process is executed (step S406). In the command reading process, a process of reading the bonus ball command transmitted by the main CPU 63 is executed. Then, the bonus ball command is stored in the payout-side RAM 94. And after executing a bonus ball setting process for adding the number corresponding to the received bonus ball command to the number of un-paid bonus balls information in the payout-side RAM 94 (step S407), a payout control process for executing control of the payout of game balls by the payout device 76 is executed (step S408). In the payout control process, when the number of un-paid bonus balls information stored in the payout-side RAM 94 is a value of 1 or more, drive control of the payout device 76 is performed, and when one game ball is detected by the payout detection sensor, the value of the bonus ball number information is decreased by 1. And when the value of the bonus ball number information becomes "0", the drive control of the payout device 76 is stopped. After that, an external information setting process for controlling the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process is executed (step S409).

[0156] Next, a configuration for externally outputting information from the pachinko machine 10 to the hall computer HC provided in the game hall will be described.

[0157] As shown in FIG. 2, an external terminal board 97 is provided in the back pack unit 15. A number of external terminals are provided on the external terminal board 97. A plurality of some of the external terminals are electrically connected to the main CPU 63, and a plurality of some of the external terminals are electrically connected to the payout CPU 92. Since each of the main CPU 63 and the payout CPU 92 is electrically connected to the external terminal board 97 in this way, as shown in FIG. 11, the main CPU 63 and the payout CPU 92 can externally output information to the whole computer HC.

[0158] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the details of this electrical connection configuration, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 toward the payout CPU 92. A branch path SL2 is provided on the signal relay board 98 by branching from the signal path SL1 from the front door open sensor 95 toward the payout CPU 92. And the branch path SL2 is connected to the external terminal for front door opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the payout CPU 92 but also to the external terminal for front door opening on the external terminal board 97. Thereby, it becomes possible to externally output a signal indicating whether or not the front door frame 14 is in an open state to the whole computer HC without going through the control by the payout CPU 92.

[0159] Regarding the main body opening sensor 96 in detail, on the signal relay board 98, a branch path SL4 is provided by branching from the signal path SL3 directed from the main body opening sensor 96 toward the payout-side CPU 92. And the branch path SL4 is connected to the external terminal for main body opening on the external terminal board 97. Therefore, the electrical signal corresponding to the detection result in the main body opening sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main body opening on the external terminal board 97. Thereby, it becomes possible to externally output a signal indicating whether or not the game machine main body 12 is in an open state to the hall computer HC without going through the control by the payout-side CPU 92.

[0160] Next, the content of the information externally output from the main-side CPU 63 and the payout-side CPU 92 to the hall computer HC will be described. First, the content of the information externally output from the main-side CPU 63 to the hall computer HC will be described.

[0161] The main-side CPU 63 performs output setting of information to each external terminal assigned to the main-side CPU 63 on the external terminal board 97 in the external information setting process (step S218) in the timer interrupt process (FIG. 8). Information output from the main-side CPU 63 to the external terminal board 97 includes information indicating that it is in the opening / closing execution mode, information indicating that the support mode is in the high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (for example, 100) of game balls have been discharged from the game area PA through any one of the out ports 24a, general winning ports 31, special electric winning devices 32, first operation ports 33, and second operation ports 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

[0162] The payout-side CPU 92 performs output setting of information to each external terminal assigned to the payout-side CPU 92 on the external terminal board 97 in the external information setting process (step S409) in the timer interrupt process (FIG. 12). Information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0163] In the hall computer HC, it is possible to grasp the execution mode of paying out game balls in the pachinko machine 10 according to various information received from the pachinko machine 10 through the external terminal board 97. For example, · The ball payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10 · The ball payout rate in the normal game state that is not the opening / closing execution mode and the high-frequency support mode (hereinafter, this ball payout rate is referred to as "B") · The ball payout rate in the opening / closing execution mode · The ball payout rate in the high-frequency support mode · The number of game rounds executed until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S") · B - S × "the number of bonus balls for winning at the first operation port 33 and the second operation port 34" · The number of game balls entering the first operation port 33 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S1") · The number of game balls entering the second operation port 34 until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S2") · B - (S1 × "the number of bonus balls for winning at the first operation port 33" + S2 × "the number of bonus balls for winning at the second operation port 34") etc. are calculated. As a result, it becomes possible to manage the ball entry mode in the game area PA of the pachinko machine 10 in the hall computer HC. Note that the number of bonus balls refers to the number of game balls paid out when one game ball enters the corresponding ball entry part.

[0164] <Configuration for managing the winning mode of game balls> Next, a configuration for managing the winning mode of game balls using the management IC66 will be described. First, the electrical configuration of the management IC66 will be described with reference to the block diagram of FIG. 13.

[0165] As described above, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I / F 101 and a reading terminal 102.

[0166] The I / F 101 is an interface for transmitting and receiving signals between the MPU 62 and external devices. The I / F 101 is electrically connected to the main CPU 63 via an internal bus 103. Detection results from sensors such as the respective ball-in detection sensors 42a to 49a and commands from the payout-side CPU 92 are input to the MPU 62 through the input port of the I / F 101, and various processes are executed by the main CPU 63 based on the input detection results and command contents as described above. Also, when a signal output is performed to a device such as the special power drive unit 32b as a result of various processes being executed by the main CPU 63, the signal output is performed through the output port of the I / F 101. When a command output is performed to the payout-side CPU 92 and the sound and light control device 81 as a result of various processes being executed by the main CPU 63, the command output is performed through the output port of the I / F 101.

[0167] The reading terminal 102 is a terminal for electrically connecting a reading device, which is an external device of the pachinko machine 10, to the MPU62, and is provided such that a connection terminal portion is exposed on the surface of the MPU62. However, as already described, the main control board 61 on which the MPU62 is mounted is housed in the board box 60a, and the reading terminal 102 faces the wall portion of the board box 60a so as not to be exposed outside the main control device 60. Therefore, in order to electrically connect the reading device to the reading terminal 102, it is necessary to open the board box 60a to expose the MPU62. This makes it possible to prevent the electrical connection of the reading device to the reading terminal 102 from being performed illegally. Note that the present invention is not limited to this, and an opening for exposing the reading terminal 102 to the outside of the main control device 60 may be formed in the board box 60a, and a configuration may be adopted in which the reading device can be electrically connected to the reading terminal 102 without requiring destruction of the board box 60a.

[0168] The management IC66 includes a management-side I / F111, a management-side CPU112, a management-side ROM113, a management-side RAM114, an RTC115, a correspondence-relation memory 116, and a history memory 117. These devices are connected so as to be capable of two-way communication through an internal bus 66a provided in the management IC66.

[0169] The management-side I / F111 is an interface for receiving various signals from the main-side CPU63 via a unidirectional communication signal path group 118 built in the MPU62 and transmitting various signals to the reading terminal 102 via a unidirectional communication signal path group 119 built in the MPU62. Various signals from the main-side CPU63 are input to the input port of the management-side I / F111, and various signals to the reading terminal 102 are output from the output port of the management-side I / F111. Note that the main-side CPU63 is electrically connected to the reading terminal 102 via a two-way communication signal path group 120 built in the MPU62.

[0170] The management-side CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management-side ROM 113 is a memory that does not require external power supply for storage retention, such as a NOR-type flash memory and a NAND-type flash memory (i.e., non-volatile storage means), and is used as read-only. The management-side ROM 113 stores various control programs and fixed-value data executed by the management-side CPU 112. The management-side RAM 114 is a memory that requires external power supply for storage retention, such as SRAM and DRAM (i.e., volatile storage means), and is used for both reading and writing. The management-side RAM 114 allows random access and has a shorter read time than the management-side ROM 113 when compared with the same data capacity. The management-side RAM 114 temporarily stores various data and the like for the execution of the control programs stored in the management-side ROM 113.

[0171] The RTC 115 is a real-time clock, which is configured to constantly measure the year / month / day information and time information and output the measured year / month / day information and time information according to an instruction from the management-side CPU 112. Note that the RTC 115 is provided with a backup power supply, and it is possible to measure the year / month / day information and time information even when the power of the pachinko machine 10 is cut off.

[0172] The correspondence relation memory 116 is a memory that requires external power supply for storage retention, such as SRAM and DRAM (i.e., volatile storage means), and is used for both reading and writing. The correspondence relation memory 116 is used to store information on the correspondence relation between each buffer 122a to 122p provided in the input port 121 of the management-side I / F 111 and the types of signals input to these buffers 122a to 122p. Details of the content of the correspondence relation memory 116 will be described later.

[0173] The history memory 117 is a memory that does not require external power supply for data retention, such as a NOR type flash memory and a NAND type flash memory (i.e., non-volatile storage means), and is used for both reading and writing. The history memory 117 is used to store information regarding the entry of game balls received from the host CPU 63 through the management side I / F 111. Details of the content of the history memory 117 will be described later.

[0174] Next, the configuration of the input port 121 provided in the management side I / F 111 will be described. FIG. 14 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0175] A plurality of buffers 122a to 122p are provided in the input port 121. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can receive one type of signal through signal paths 118a to 118p. When the signal to be input is at the LOW level, the information "0" is stored as the first data in each of the first to sixteenth buffers 122a to 122p, and when the signal to be input is at the HI level, the information "1" is stored as the second data. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0176] A first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a. In this case, the host CPU 63 outputs a LOW-level first signal when the first winning port detection sensor 42a does not detect a new game ball, and outputs a HI-level first signal for a specific period when the first winning port detection sensor 42a detects one game ball. This specific period is sufficient for the management side CPU 112 to identify that a HI-level first signal is input to the first buffer 122a.

[0177] A second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a second signal of LOW level when no new game ball is detected by the second winning port detection sensor 43a, and outputs a second signal of HI level for a specific period when one game ball is detected by the second winning port detection sensor 43a. This specific period is a period sufficient for the management-side CPU 112 to specify that the second buffer 122b has a HI-level second signal input thereto.

[0178] A third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a third signal of LOW level when no new game ball is detected by the third winning port detection sensor 44a, and outputs a third signal of HI level for a specific period when one game ball is detected by the third winning port detection sensor 44a. This specific period is a period sufficient for the management-side CPU 112 to specify that the third buffer 122c has a HI-level third signal input thereto.

[0179] A fourth signal corresponding to the detection result of the special power detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a fourth signal of LOW level when no new game ball is detected by the special power detection sensor 45a, and outputs a fourth signal of HI level for a specific period when one game ball is detected by the special power detection sensor 45a. This specific period is a period sufficient for the management-side CPU 112 to specify that the fourth buffer 122d has a HI-level fourth signal input thereto.

[0180] A fifth signal corresponding to the detection result of the first operation port detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a LOW-level fifth signal when no new game ball is detected by the first operation port detection sensor 46a, and outputs a HIGH-level fifth signal for a specific period when one game ball is detected by the first operation port detection sensor 46a. This specific period is long enough for the management-side CPU 112 to identify that a HIGH-level fifth signal is input to the fifth buffer 122e.

[0181] A sixth signal corresponding to the detection result of the second operation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW-level sixth signal when no new game ball is detected by the second operation port detection sensor 47a, and outputs a HIGH-level sixth signal for a specific period when one game ball is detected by the second operation port detection sensor 47a. This specific period is long enough for the management-side CPU 112 to identify that a HIGH-level sixth signal is input to the sixth buffer 122f.

[0182] A seventh signal corresponding to the detection result of the out-port detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW-level seventh signal when no new game ball is detected by the out-port detection sensor 48a, and outputs a HIGH-level seventh signal for a specific period when one game ball is detected by the out-port detection sensor 48a. This specific period is long enough for the management-side CPU 112 to identify that a HIGH-level seventh signal is input to the seventh buffer 122g.

[0183] An eighth signal corresponding to whether it is during the opening / closing execution mode is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs a LOW-level eighth signal when it is not in the opening / closing execution mode, and continuously outputs a HIGH-level eighth signal when it is in the opening / closing execution mode.

[0184] A ninth signal corresponding to whether it is during the high-frequency support mode is input to the ninth buffer 122i. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when it is not in the high-frequency support mode, and continuously outputs a HI-level ninth signal when it is in the high-frequency support mode.

[0185] A tenth signal corresponding to whether the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a LOW-level tenth signal when the front door frame 14 is in the closed state, and continuously outputs a HI-level tenth signal when the front door frame 14 is in the open state.

[0186] An output instruction signal for causing the management-side CPU 112 to recognize an opportunity to output the history information stored in the history memory 117 to the read terminal 102 is input to the sixteenth buffer 122p. In this case, the main CPU 63 outputs a LOW-level output instruction signal when there is no need to output the history information, and outputs a HI-level output instruction signal over a specific period when there is a need to output the history information. This specific period is sufficient for the management-side CPU 112 to specify that a HI-level output instruction signal is input to the sixteenth buffer 122p.

[0187] The 11th buffer 122k, the 12th buffer 122l, the 13th buffer 122m, the 14th buffer 122n, and the 15th buffer 122o can receive signals from the main CPU 63, but are blank and do not receive normal signals in the pachinko machine 10. In this way, since more buffers 122a to 122p are provided as the input ports 121 of the management-side I / F 111 in the pachinko machine 10 than the types of signals output from the main CPU 63 to the management IC 66, the management IC 66 can be used in models different from the pachinko machine 10. This makes it possible to enhance the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and each of the 1st to 16th buffers 122a to 122p so as to correspond one-to-one, but it is not limited to this, and signal paths 118k to 118o may not be formed between the buffers 122k to 122o to be blanked.

[0188] The input of the output instruction signal to the 16th buffer 122p at the input port 121 of the management-side I / F 111 is determined at the design stage of the management IC 66. Without receiving an instruction from the main CPU 63, the management-side CPU 112 can identify that the output instruction signal is input to the 16th buffer 122p. On the other hand, the types of signals input to the 1st to 15th buffers 122a to 122o are not determined at the design stage of the management IC 66, and the types of these signals are identified by the management-side CPU 112 upon receiving an instruction from the main CPU 63. The identification of the types of these signals by the management-side CPU 112 is performed, although details will be described later, when control is started in the main CPU 63 and the management-side CPU 112 with the supply of operating power to the MPU 62, by the main CPU 63 transmitting a type identification command to the management-side CPU 112. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management-side CPU 112 identifies the types of various signals in a situation where operating power is supplied, the information stored in the correspondence memory 116 is referred to.

[0189] FIG. 15 is an explanatory diagram for explaining the configuration of the correspondence memory 116. In the correspondence memory 116, first to fifteenth correspondence areas 123a to 123o are provided in one-to-one correspondence with first to fifteenth buffers 122a to 122o provided in the input port 121 of the management-side I / F 111.

[0190] In the first correspondence area 123a, information indicating that it is the general winning port 31 is stored as information for specifying the type of signal input to the first buffer 122a by the management-side CPU 112. Further, in the first correspondence area 123a, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the second correspondence area 123b, information indicating that it is the general winning port 31 is stored as information for specifying the type of signal input to the second buffer 122b by the management-side CPU 112. Further, in the second correspondence area 123b, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the third correspondence area 123c, information indicating that it is the general winning port 31 is stored as information for specifying the type of signal input to the third buffer 122c by the management-side CPU 112. Further, in the third correspondence area 123c, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored.

[0191] In the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 is stored as information for the management-side CPU 112 to identify the type of signal input to the fourth buffer 122d. Also, in the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 and information on the number of game balls (15) to be paid out when one game ball enters the special electric winning device 32 are also stored. In the fifth correspondence area 123e, information indicating that it is the first operation port 33 is stored as information for the management-side CPU 112 to identify the type of signal input to the fifth buffer 122e. Also, in the fifth correspondence area 123e, information indicating that it is the first operation port 33 and information on the number of game balls (1) to be paid out when one game ball enters the first operation port 33 are also stored. In the sixth correspondence area 123f, information indicating that it is the second operation port 34 is stored as information for the management-side CPU 112 to identify the type of signal input to the sixth buffer 122f. Also, in the sixth correspondence area 123f, information indicating that it is the second operation port 34 and information on the number of game balls (1) to be paid out when one game ball enters the second operation port 34 are also stored. In the seventh correspondence area 123g, information indicating that it is the out port 24a is stored as information for the management-side CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0192] In the eighth correspondence area 123h, information indicating that it is the opening / closing execution mode is stored as information for the management-side CPU 112 to identify the type of signal input to the eighth buffer 122h. In the ninth correspondence area 123i, information indicating that it is the high-frequency support mode is stored as information for the management-side CPU 112 to identify the type of signal input to the ninth buffer 122i. In the tenth correspondence area 123j, information indicating that it is the front door frame 14 is stored as information for the management-side CPU 112 to identify the type of signal input to the tenth buffer 122j.

[0193] In the 11th correspondence area 123k, information indicating that it is a blank corresponding to none is stored as information for the management-side CPU 112 to identify the type of signal input to the 11th buffer 122k. In the 12th correspondence area 123l, information indicating that it is a blank corresponding to none is stored as information for the management-side CPU 112 to identify the type of signal input to the 12th buffer 122l. In the 13th correspondence area 123m, information indicating that it is a blank corresponding to none is stored as information for the management-side CPU 112 to identify the type of signal input to the 13th buffer 122m. In the 14th correspondence area 123n, information indicating that it is a blank corresponding to none is stored as information for the management-side CPU 112 to identify the type of signal input to the 14th buffer 122n. In the 15th correspondence area 123o, information indicating that it is a blank corresponding to none is stored as information for the management-side CPU 112 to identify the type of signal input to the 15th buffer 122o.

[0194] As described above, by adopting a configuration in which the management-side CPU 112 identifies what types of signals are input to the 1st to 15th buffers 122a to 122o by receiving an instruction from the main-side CPU 63, the management IC 66 can be reused for models different from this pachinko machine 10. As a result, the versatility of the management IC 66 can be enhanced.

[0195] Further, instead of outputting information for recognizing the type of a signal every time a signal output corresponding to the storage of history information is performed to the first to fifteenth buffers 122a to 122o, information for recognizing the type of the signal is output in advance, and information for specifying the type of the signal input to the first to fifteenth buffers 122a to 122o based on the output information is stored in the correspondence memory 116 by the management CPU 112. Thereby, compared with a configuration in which information for recognizing the type of a signal is output every time a signal output corresponding to the storage of history information is performed to the first to fifteenth buffers 122a to 122o, it is possible to suppress the amount of information output from the main CPU 63 to the management CPU 112 at the time of each signal output.

[0196] Further, the output of information for specifying the type of the signal input to the first to fifteenth buffers 122a to 122o is performed by the management CPU 112 at the start of the supply of the operating power. Thereby, in a situation where a game is started in the pachinko machine 10, it is possible to specify the type of the signal input to the first to fifteenth buffers 122a to 122o by the management CPU 112.

[0197] Further, information setting for the input of an output instruction signal to the sixteenth buffer 122p is performed at the design stage of the management IC 66. Thereby, for an output instruction signal that is surely used not only in the pachinko machine 10 but also in other models of pachinko machines using the management IC 66, it is possible to omit the process for specifying the type of the signal input to the sixteenth buffer 122p. Therefore, it is possible to suppress the processing load of the process for specifying the type of such a signal.

[0198] Next, the history memory 117 of the management IC 66 will be described. FIG. 16 is an explanatory diagram for explaining the configuration of the history memory 117.

[0199] The history memory 117 is provided with a history area 124 for sequentially storing history information. In the history area 124, a plurality of pointer information is set in consecutive numbers, and a history information storage area 125 is set in a one-to-one correspondence with each pointer information. The history information storage area 125 can store a combination of RTC information and correspondence relationship information. In this case, each history information storage area 125 has a data capacity of 2 bytes, a data capacity of 1 byte is allocated as an area for storing RTC information, and a data capacity of 1 byte is allocated as an area for storing correspondence relationship information. When it is necessary to store correspondence relationship information according to the signals input to the first to fifteenth buffers 122a to 122o (in the actual pachinko machine 10, the first to tenth buffers 122a to 122j), first, the year, month, day information and time information measured by the current RTC 115 are stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information that is currently the write target. After that, the correspondence relationship information corresponding to the buffers 122a to 122o that triggered this information storage is read from the correspondence relationship areas 123a to 123o corresponding to the buffers 122a to 122o in the correspondence relationship memory 116, and the read correspondence relationship information is stored in the area for storing correspondence relationship information in the history information storage area 125 corresponding to the pointer information that is currently the write target.

[0200] Specifically regarding the correspondence information stored in the history information storage area 125, as described above, signals corresponding to the detection results of the ball entry detection sensors 42a to 48a are input to the first to seventh buffers 122a to 122g. Therefore, information corresponding to the types of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g in the correspondence memory 116. More specifically, information corresponding to the types of the ball entry parts corresponding to each of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. In this pachinko machine 10, as described above, since the first to third winning port detection sensors 42a to 44a all detect the game balls that have entered the general winning port 31, information indicating that it is the general winning port 31 is stored in the first to third correspondence areas 123a to 123c corresponding to these first to third winning port detection sensors 42a to 44a. Also, information indicating that it is the special winning device 32 is stored in the fourth correspondence area 123d, information indicating that it is the first operating port 33 is stored in the fifth correspondence area 123e, information indicating that it is the second operating port 34 is stored in the sixth correspondence area 123f, and information indicating that it is the out port 24a is stored in the seventh correspondence area 123g. When the buffers 122a to 122o that triggered this information storage are any of the first to seventh buffers 122a to 122g, the information on the type of the ball entry part corresponding to that buffer 122a to 122g is read from any of the first to seventh correspondence areas 123a to 123g, and the read information on the type of the ball entry part is directly stored in the area for storing the correspondence information in the history information storage area 125.

[0201] On the one hand, a signal indicating whether the eighth buffer 122h is in the open / close execution mode is input, a signal indicating whether the ninth buffer 122i is in the high-frequency support mode is input, and a signal indicating whether the front door frame 14 is open is input to the tenth buffer 122j. Therefore, information indicating that it is in the open / close execution mode is stored in the eighth corresponding relationship area 123h, information indicating that it is in the high-frequency support mode is stored in the ninth corresponding relationship area 123i, and information indicating that it is the front door frame 14 is stored in the tenth corresponding relationship area 123j.

[0202] As described above, the main CPU 63 continuously outputs the eighth signal at the LOW level in a situation where it is not in the open / close execution mode, and continuously outputs the eighth signal at the HI level in a situation where it is in the open / close execution mode. Therefore, the management CPU 112 can identify that the open / close execution mode has started when the eighth signal changes from the LOW level to the HI level, and can identify that the open / close execution mode has ended when the eighth signal changes from the HI level to the LOW level. And in both cases where the eighth signal changes from the LOW level to the HI level and from the HI level to the LOW level, the management CPU 112 identifies that an opportunity to store the corresponding relationship information in the history information storage area 125 has occurred. That is, when the eighth signal changes from the LOW level to the HI level, not only the information indicating that it is in the open / close execution mode read from the eighth corresponding relationship area 123h but also the start information are stored together in the area for storing the corresponding relationship information in the history information storage area 125. Also, when the eighth signal changes from the HI level to the LOW level, not only the information indicating that it is in the open / close execution mode read from the eighth corresponding relationship area 123h but also the end information are stored together in the area for storing the corresponding relationship information in the history information storage area 125.

[0203] As described above, when the master CPU 63 is not in the high-frequency support mode, it continuously outputs the LOW-level ninth signal, and when it is in the high-frequency support mode, it continuously outputs the HI-level ninth signal. Therefore, when the ninth signal changes from LOW level to HI level, the management CPU 112 can identify that the high-frequency support mode has started, and when the ninth signal changes from HI level to LOW level, the management CPU 112 can identify that the high-frequency support mode has ended. And in both cases where the ninth signal changes from LOW level to HI level and from HI level to LOW level, the management CPU 112 identifies that an opportunity to store the correspondence information in the history information storage area 125 has occurred. That is, when the ninth signal changes from LOW level to HI level, not only the information indicating that it is in the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored together in the area for storing the correspondence information in the history information storage area 125. Also, when the ninth signal changes from HI level to LOW level, not only the information indicating that it is in the high-frequency support mode read from the ninth correspondence area 123i but also the end information are stored together in the area for storing the correspondence information in the history information storage area 125.

[0204] As described above, the main CPU 63 continuously outputs the 10th signal at LOW level when the front door frame 14 is in the closed state, and continuously outputs the 10th signal at HI level when the front door frame 14 is in the open state. Therefore, the management CPU 112 can identify that the front door frame 14 has been opened when the 10th signal changes from LOW level to HI level, and can identify that the front door frame 14 has been closed when the 10th signal changes from HI level to LOW level. And in both cases where the 10th signal changes from LOW level to HI level and from HI level to LOW level, the management CPU 112 identifies that an opportunity has occurred to store the correspondence information in the history information storage area 125. That is, when the 10th signal changes from LOW level to HI level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening start information are together stored in the area for storing the correspondence information in the history information storage area 125. Also, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening end information are together stored in the area for storing the correspondence information in the history information storage area 125.

[0205] The history information storage area 125 is provided with several minutes that can store all the history information generated during that period even if the business days in which the shooting of game balls in the pachinko machine 10 continues from opening to closing are continuously 10 days. For example, if 60,000 pieces of history information are generated in one day, more than 600,000 history information storage areas 125 are provided. Thereby, it is possible to store and hold all the history information in the history memory 117 for at least 10 days.

[0206] In the history memory 117, a pointer area 126 is provided separately from the history area 124. The pointer area 126 stores information for the management CPU 112 to identify the pointer information that is currently the write target in the history memory 117. Specifically, at the shipment stage of the pachinko machine 10, information designating the pointer information of "0" as the write target is set in the pointer area 126. Then, each time one piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information that is the write target is incremented by 1. When the pointer information of the last order becomes the write target and history information is stored in the history information storage area 125 corresponding to the pointer information of the last order, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. As a result, when a trigger for storing history information occurs exceeding the number of history information that can be stored, the old history information is overwritten with new history information in order from the history information storage area 125 where the old history information is stored.

[0207] Also, when the reading device reads history information from the history memory 117, the history information storage area 125 is all cleared to "0", and the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. This makes it possible to prevent the history information that has once been the reading target from becoming the reading target again.

[0208] Next, a specific processing configuration for managing the winning mode of game balls using the management IC 66 will be described. First, a processing configuration for storing in the correspondence relationship memory 116 information on the correspondence relationship between the first to fifteenth buffers 122a to 122o provided in the input port 121 of the management side I / F 111 and the types of signals will be described. FIG. 17 is a flowchart showing the recognition processing executed by the main CPU 63. Note that the recognition processing is executed in step S110 in the main processing (FIG. 7).

[0209] First, set "15" to the recognition output counter provided in the main-side RAM 65 (step S501). The recognition output counter is a counter for the main-side CPU 63 to specify the remaining required number of times of information output for the management-side CPU 112 to recognize which type of signal each buffer 122a to 122p of the input port 121 in the management-side I / F 111 corresponds to. As already described, since the 15 buffers 122a to 122o of the first to fifteenth are the objects of recognition of the signal type, "15" is set to the recognition output counter.

[0210] Thereafter, the output process of the identification start command is executed (step S502). The host CPU 63 outputs various commands to the management CPU 112 in order to make the management CPU 112 recognize which type of signal the first to fifteenth buffers 122a to 122o correspond to. When outputting this command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 of the opportunity to store history information, a command output is performed to make the management CPU 112 recognize which type of signal the first to fifteenth buffers 122a to 122o correspond to. Thereby, compared with a configuration in which the signal path for performing this command output is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p, the number of signal paths can be reduced and the configuration can be simplified. The identification start command has a data capacity of 8 bits, and the data of each bit is input to the first to eighth buffers 122a to 122h as the first to eighth signals respectively. Also, in the output process of the identification start command, in order to make the management CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification start command. Also, the output period of the identification start command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management CPU 112 to recognize these identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 specifies that it should start the process of storing the information on the correspondence relationship between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence relationship memory 116.

[0211] After that, a type identification command corresponding to the current value of the recognition output counter of the main-side RAM 65 is read from the main-side ROM 64 (step S503). In this case, the first buffer 122a is first set as the target for signal type setting, and then the (n + 1)-th buffer is set as the target for signal type setting after the n-th buffer. Thus, recognition settings for signal types corresponding to the first to fifteenth buffers 122a to 122o are performed. Therefore, if the recognition output counter is "15" to "13", a type identification command indicating that it is the general winning port 31 and the number of winning balls is read. If the recognition output counter is "12", a type identification command indicating that it is the special electric winning device 32 and the number of winning balls is read. If the recognition output counter is "11", a type identification command indicating that it is the first operation port 33 and the number of winning balls is read. If the recognition output counter is "10", a type identification command indicating that it is the second operation port 34 and the number of winning balls is read. If the recognition output counter is "9", a type identification command indicating that it is the out port 24a is read. If the recognition output counter is "8", a type identification command indicating the open / close execution mode is read. If the recognition output counter is "7", a type identification command indicating the high-frequency support mode is read. If the recognition output counter is "6", a type identification command indicating that it is the front door frame 14 is read. If the recognition output counter is "5" to "1", a type identification command indicating that it is blank is read.

[0212] After that, the output process of the read type identification command is executed (step S504). The type identification command has a data capacity of 8 bits, similar to the identification start command, and the data of each bit is input into the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Also, in the output process of the identification type command, in order to make the management-side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification type command. Also, the output period of the identification type command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management-side CPU 112 to recognize these identification type commands and the output state of the ninth signal. By receiving the identification type command, the management-side CPU 112 stores the information corresponding to the identification type command in the correspondence areas 123a to 123o corresponding to the buffers that are the current setting targets among the first to fifteenth buffers 122a to 122o.

[0213] After that, the value of the recognition output counter in the main-side RAM 65 is decremented by 1 (step S505), and it is determined whether the value of the recognition output counter after the decrement by 1 is "0" (step S506). If the value of the recognition output counter is 1 or more (step S506: NO), the process for outputting the type identification command corresponding to the value of the recognition output counter after the decrement by 1 is executed (steps S503 and S504).

[0214] On the other hand, when the value of the recognition output counter is "0" (step S506: YES), the output process of the identification end command is executed (step S507). The identification end command has a data capacity of 8 bits, and the data of each bit is input into the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Also, in the output process of the identification end command, in order to make the management-side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification end command. Also, the output period of the identification end command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management-side CPU 112 to recognize these identification end command and the output state of the ninth signal. By receiving the identification end command, the management-side CPU 112 identifies that the process for storing the information on the correspondence between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence memory 116 has been completed.

[0215] Next, the management process executed by the management-side CPU 112 will be described with reference to the flowchart of FIG. 18. The management process starts when the supply of operating power to the management-side CPU 112 is started. Note that the processing speed of the management-side CPU 112 is faster than the processing speed of the main-side CPU 63, and the combination of the processes after step S606 in the management process is executed 16 times or more from the start of one timer interrupt process (FIG. 8) in the main-side CPU 63 until the start of the next timer interrupt process (FIG. 8).

[0216] When the management-side CPU 112 receives the identification start command from the main-side CPU 63 (step S601: YES), the value of the setting target counter provided in the management-side RAM 114 is cleared to "0" (step S602). The setting target counter is a counter for the management-side CPU 112 to identify the types of the buffers 122a to 122o that are the setting targets of the signal types. The first buffer 122a is the first to be the setting target of the signal type, and thereafter, the (n + 1)-th buffer is the setting target of the signal type after the n-th buffer.

[0217] After that, on the condition that the main CPU 63 has received a type identification command (step S603: YES), correspondence relationship setting processing is executed (step S604). In the correspondence relationship setting processing, among the first to fifteenth correspondence relationship areas 123a to 123o of the correspondence relationship memory 116, the information on the signal type set in the type identification command received this time is stored in the correspondence relationship area corresponding to the current value in the setting target counter of the management side RAM 114. After that, the value of the setting target counter of the management side RAM 114 is incremented by 1 (step S605).

[0218] If a negative determination is made in step S603, or if the process of step S605 is executed, it is determined whether an identification end command has been received from the main CPU 63 (step S606). If the identification end command has not been received (step S606: NO), the process returns to step S603, and on the condition that a new type identification command is received from the main CPU 63 (step S603: YES), the processes of step S604 and step S605 are executed again.

[0219] If an identification end command has been received from the main CPU 63 (step S606: YES), the processes of step S607 and step S608 are repeatedly executed. Although the details will be described later, in step S607, history setting processing for storing the history information corresponding to the type of the signal received from the main CPU 63 in the history memory 117 is executed. Although the details will be described later, in step S608, external output processing for outputting the history information stored in the history memory 117 to the reading terminal 102 is executed.

[0220] FIG. 19 is a time chart showing a state in which information on the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is stored in the correspondence memory 116. FIG. 19(a) shows a period during which a command is output from the host CPU 63 to the management CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), FIG. 19(b) shows a period during which the output state of the ninth signal is at the HI level, FIG. 19(c) shows an execution period of an identification state in which a process for identifying the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is executed, and FIG. 19(d) shows a timing at which the correspondence setting process (step S604) is executed by the management CPU 112.

[0221] By starting the supply of operating power to the host CPU 63 and the management CPU 112, the output of the identification start command using the first to eighth signals starts at timing t1 as shown in FIG. 19(a). Also, at the timing t1, the output state of the ninth signal is changed from the LOW level to the HI level as shown in FIG. 19(b). Thereafter, at timing t2 when the output of the identification start command is being continued, the output state of the ninth signal is changed from the HI level to the LOW level as shown in FIG. 19(b). The management CPU 112 specifies that a command is being transmitted from the host CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the host CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the management CPU 112 enters the identification state by making an affirmative determination in step S601 of the management process (FIG. 18). Thereafter, the output of the identification start command stops at timing t3 as shown in FIG. 19(a).

[0222] Thereafter, at the timing of t4, as shown in FIG. 19(a), the output of the first type identification command using the first to eighth signals is started. Also, at the timing of t4, as shown in FIG. 19(b), the output state of the ninth signal is changed from the LOW level to the HI level. Thereafter, at the timing of t5 when the output of the type identification command is continuing, as shown in FIG. 19(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command is being received, the management-side CPU 112 executes the correspondence relationship setting process as shown in FIG. 19(d) at the timing of t5. In the correspondence relationship setting process, information indicating that it is the general winning opening 31 and information on the number of winning balls are stored in the first correspondence area 123a of the correspondence relationship memory 116. Thereafter, at the timing of t6, as shown in FIG. 19(a), the output of the type identification command is stopped.

[0223] Thereafter, at each of the timings from t7 to t9, from t10 to t12, from t13 to t15, and from t16 to t18, in the same manner as the timings from t4 to t6, the management-side CPU 112 executes the correspondence relationship setting process corresponding to the type identification command output from the main-side CPU 63. In this case, at the timings from t16 to t18, the correspondence relationship setting process corresponding to the 15th type identification command is completed.

[0224] Thereafter, at the timing of t19, as shown in FIG. 19(a), the output of the identification end command using the first to eighth signals is started. Also, at the timing of t19, as shown in FIG. 19(b), the output state of the ninth signal is changed from the LOW level to the HI level. Thereafter, at the timing of t20 when the output of the identification end command is continuing, as shown in FIG. 19(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification end command is received, the identification state of the management-side CPU 112 ends as shown in FIG. 19(c) at the timing of t20. Thereafter, at the timing of t21, as shown in FIG. 19(a), the output of the identification end command is stopped.

[0225] With the configuration that allows the management-side CPU 112 to recognize whether or not a command is being output using the ninth signal as described above, even in a configuration where a command output is performed using the first to eighth signals (i.e., the first to eighth signal paths) that are used to instruct the management-side CPU 112 of the timing for storing history information, it is possible to clearly make the management-side CPU 112 recognize that a command is being output.

[0226] Next, a processing configuration for storing the history information in the history memory 117 will be described. FIG. 20 is a flowchart showing the management output process executed by the main-side CPU 63. Note that the management output process is executed in step S219 in the timer interrupt process (FIG. 8).

[0227] First, set "10" to the counter to be managed provided in the main-side RAM 65 (step S701). The counter to be managed is a counter for the main-side CPU 63 to identify whether there is a management target that is not the target to be identified for changing the signal output state to the management-side CPU 112 in the current management output process, and to identify for which management target the signal output state to the management-side CPU 112 should be changed. In one management output process, the management targets for which the main-side CPU 63 determines whether to change the signal output state to the management-side CPU 112 are a total of 10, including the seven ball-in detection sensors 42a to 48a, the presence or absence of execution of the open / close execution mode, the presence or absence of execution of the high-frequency support mode, and the presence or absence of opening and closing of the front door frame 14. Therefore, first set "10" to the counter to be managed.

[0228] Thereafter, it is determined whether the output state of the signal to the management-side CPU 112 for the management target corresponding to the current value of the counter to be managed is at the HI level (step S702). If it is not at the HI level (step S702: NO), it is determined whether the value of the counter to be managed is 4 or more, thereby identifying whether the management target corresponding to the value of the counter to be managed is any of the seven ball-in detection sensors 42a to 48a (step S703).

[0229] If an affirmative determination is made in step S703, it is determined whether "1" is set in the output flag of the main-side RAM 65 corresponding to the value of the counter to be managed (step S704). Specifically, when the value of the counter to be managed is "10" and corresponds to the first winning port detection sensor 42a, it is determined whether "1" is set in the first output flag. When the value of the counter to be managed is "9" and corresponds to the second winning port detection sensor 43a, it is determined whether "1" is set in the second output flag. When the value of the counter to be managed is "8" and corresponds to the third winning port detection sensor 44a, it is determined whether "1" is set in the third output flag. When the value of the counter to be managed is "7" and corresponds to the special power detection sensor 45a, it is determined whether "1" is set in the fourth output flag. When the value of the counter to be managed is "6" and corresponds to the first operating port detection sensor 46a, it is determined whether "1" is set in the fifth output flag. When the value of the counter to be managed is "5" and corresponds to the second operating port detection sensor 47a, it is determined whether "1" is set in the sixth output flag. When the value of the counter to be managed is "4" and corresponds to the out port 24a, it is determined whether "1" is set in the seventh output flag. Note that, as already described, "1" is set in these first to seventh output flags in the ball entry detection process (Figure 10).

[0230] When "1" is set in the output flag corresponding to the value of the counter to be managed (step S704: YES), the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals is set to the HI level (step S705). Then, the output flag corresponding to the value of the counter to be managed is cleared to "0" (step S706).

[0231] When a negative determination is made in step S703, it is determined whether or not an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the HI level (step S707). Specifically, when the value of the counter to be managed is "3", it is determined whether or not a transition to the open / close execution mode has occurred, and when the value of the counter to be managed is "2", it is determined whether or not a transition to the high-frequency support mode has occurred. When the value of the counter to be managed is "1", it is determined whether or not the front door frame 14 is in the open state. When an affirmative determination is made in step S707, the output state of the signal corresponding to the value of the counter to be managed is set to the HI level (step S708).

[0232] When an affirmative determination is made in step S702, it is determined whether or not an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S709). Specifically, when the value of the counter to be managed is 4 or more and the current management target is any of the ball entry detection sensors 42a to 48a, it is determined whether or not the HI output duration (specifically, 10 msec) has elapsed after switching the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals from the LOW level to the HI level. This HI output duration is set to a period longer than the longest processing interval of the history setting process (step S607) of the management process (FIG. 18) in the management side CPU 112, and is a period during which the management side CPU 112 can surely identify the output state of the signal switched from the LOW level to the HI level. Also, when the value of the counter to be managed is "3" and the current management target is the open / close execution mode, it is determined whether or not the open / close execution mode has ended. When the value of the counter to be managed is "2" and the current management target is the high-frequency support mode, it is determined whether or not the high-frequency support mode has ended. When the value of the counter to be managed is "1" and the current management target is the front door frame 14, it is determined whether or not the front door frame 14 is in the closed state. When an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S709: YES), the output state of the signal corresponding to the value of the counter to be managed is set to the LOW level (step S710).

[0233] If a negative determination is made in step S704, if the process of step S706 is executed, if a negative determination is made in step S707, if the process of step S708 is executed, if a negative determination is made in step S709, or if the process of step S710 is executed, the value of the management target counter in the host-side RAM 65 is decremented by 1 (step S711). Then, it is determined whether the value of the management target counter after the decrement by 1 is "0" (step S712). If the value of the management target counter is 1 or more (step S712: NO), for the management target corresponding to the new value of the management target counter, the processes after step S702 are executed.

[0234] Next, the history setting process executed by the management-side CPU 112 will be described with reference to the flowchart of FIG. 21. The history setting process is executed in step S607 of the management process (FIG. 18).

[0235] First, the number of buffers to be confirmed by the management-side CPU 112 among the first to fifteenth buffers 122a to 122o is set in the confirmation target counter provided in the management-side RAM 114 (step S801). Specifically, the number of correspondence relationship areas in which information other than the information indicating blank is stored among the first to fifteenth correspondence relationship areas 123a to 123o in the correspondence relationship memory 116 is specified, and the information of the specified number is set in the confirmation target counter. In this pachinko machine 10, as already described, information other than the information indicating blank is stored in the first to tenth correspondence relationship areas 123a to 123j. Therefore, in step S801, "10" is set in the confirmation target counter.

[0236] Thereafter, by checking whether the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fifteenth buffers 122a to 122o has been changed from "0" to "1", it is determined whether the output state of the input signal from the master CPU 63 to the buffer has been switched from the LOW level to the HI level (step S802). When the value of the confirmation target counter is "n", the nth buffers 122a to 122o are the targets for checking the numerical information. For example, when the value of the confirmation target counter is "10", the 10th buffer 122j is the target for checking the numerical information, and when the value of the confirmation target counter is "5", the 5th buffer 122e is the target for checking the numerical information.

[0237] If an affirmative determination is made in step S802, the RTC information, which is the year / month / day information and time information, is read from the RTC 115 (step S803). Then, a writing process to the history memory 117 is executed (step S804). In this writing process, by referring to the pointer area 126 of the history memory 117, the pointer information of the history area 124 that is currently the write target is specified, and the RTC information read in step S803 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information that is the write target. Also, the correspondence information is read from the correspondence areas 123a to 123o corresponding to the value of the current confirmation target counter, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information that is the write target. Further, when the correspondence information is any one of the information indicating the open / close execution mode, the information indicating the high-frequency support mode, and the information indicating the front door frame 14, not only the correspondence information but also the start information is written to the history information storage area 125 corresponding to the pointer information that is the write target. When the value of the confirmation target counter is "n", the nth correspondence areas 123a to 123o are the targets for reading the correspondence information. For example, when the value of the confirmation target counter is "10", the 10th correspondence area 123j is the target for reading the correspondence information, and when the value of the confirmation target counter is "5", the 5th correspondence area 123e is the target for reading the correspondence information.

[0238] When the writing process is executed as described above, if the value of the counter to be confirmed is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information and the correspondence information indicating that it is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is stored as the history information. Further, if the value of the counter to be confirmed is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the start information is stored as the history information.

[0239] Thereafter, an update process for the target pointer is executed (step S805). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read out and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new pointer information to be written. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0240] When a negative determination is made in step S802 or when the process of step S805 is executed, it is determined whether correspondence relation information to be checked for whether the signal output has been switched to the LOW level is stored in the correspondence relation areas 123a to 123o corresponding to the value of the current confirmation target counter (step S806). Specifically, when the value of the current confirmation target counter is from "8" to "10", since any one of the information indicating the open / close execution mode, the information indicating the high-frequency support mode, and the information indicating the front door frame 14 is stored in the corresponding correspondence relation areas 123h to 123j, an affirmative determination is made in step S806.

[0241] If an affirmative determination is made in step S806, it is determined whether or not the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fifteenth buffers 122a to 122o has been changed from "1" to "0", thereby determining whether or not the output state of the input signal from the host CPU 63 to the buffer has been switched from the HI level to the LOW level (step S807). If an affirmative determination is made in step S807, the RTC information is read in the same manner as in step S803 (step S808), and further, a writing process to the history memory 117 is executed (step S809). In the writing process, the RTC information read in step S808 is written into the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. Also, the correspondence information is read from the correspondence areas 123a to 123o corresponding to the value of the current confirmation target counter, and the correspondence information is written into the history information storage area 125 corresponding to the pointer information to be written. Also, not only the correspondence information but also the end information is written into the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this way, when the value of the confirmation target counter is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, in the history information storage area 125 corresponding to the pointer information to be written, a combination of the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the end information is stored as the history information. Thereafter, the update process of the target pointer is executed in the same manner as in step S805 (step S810).

[0242] If a negative determination is made in step S806, if a negative determination is made in step S807, or if the process of step S810 is executed, the value of the confirmation target counter in the management side RAM 114 is decremented by 1 (step S811). Then, it is determined whether or not the value of the confirmation target counter after the decrement by 1 is "0" (step S812). If the value of the confirmation target counter is 1 or more (step S812: NO), for the confirmation target corresponding to the new value of the confirmation target counter, the processes after step S802 are executed.

[0243] Next, the state in which the history information is stored in the history memory 117 will be described with reference to the time chart of FIG. 22. FIG. 22(a) shows the period during which a signal of HI level is input to any one of the first to seventh buffers 122a to 122g, FIG. 22(b) shows the period during which a signal of HI level is input to the eighth buffer 122h, FIG. 22(c) shows the period during which a signal of HI level is input to the ninth buffer 122i, FIG. 22(d) shows the period during which a signal of HI level is input to the tenth buffer 122j, and FIG. 22(e) shows the writing timing of the history information to the history memory 117.

[0244] At the timing of t1, as shown in FIG. 22(a), the output state of the signal input to any one of the first to seventh buffers 122a to 122g is switched from the LOW level to the HI level. Therefore, at the timing of t1, as shown in FIG. 22(e), the history information is written into the history memory 117. After that, at the timing of t2, as shown in FIG. 22(a), the signal switched to the HI level at the timing of t1 is switched to the LOW level. However, since the signal is a signal input to any one of the first to seventh buffers 122a to 122g and the switching to the LOW level is not the target for storing the history information, the writing of the history information is not executed at the timing of t2 as shown in FIG. 22(e).

[0245] Thereafter, at each of the timings of t3, t5, t6, t9, t10, t13, and t14, as shown in FIG. 22(a), the output state of the signal input to any one of the first to seventh buffers 122a to 122g is switched from the LOW level to the HI level. Therefore, history information is written as shown in FIG. 22(e) at each of these timings.

[0246] As shown in FIG. 22(b), from the timing of t4 to the timing of t7, the output state of the signal input to the eighth buffer 122h becomes the HI level. This eighth buffer 122h corresponds to the presence or absence of the occurrence of the opening / closing execution mode. Therefore, at the timing of t4, which is the timing when the output state of the signal input to the eighth buffer 122h switches to the HI level, and at the timing of t7, which is the timing when the output state of the signal switches to the LOW level, as shown in FIG. 22(e), history information is written. In this case, the history information written at the timing of t4 includes start information, and the history information written at the timing of t7 includes end information. Thus, it becomes possible to grasp the execution period of the opening / closing execution mode by checking the history information in the history memory 117.

[0247] Also, history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode. Further, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode by comparing the RTC information.

[0248] As shown in FIG. 22(c), from the timing of t8 to the timing of t11, the output state of the signal input to the ninth buffer 122i becomes the HI level. This ninth buffer 122i corresponds to the presence or absence of the occurrence of the high-frequency support mode. Therefore, at the timing of t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to the HI level as shown in FIG. 22(e), and at the timing of t11, which is the timing when the output state of the signal switches to the LOW level, history information is written. In this case, the history information written at the timing of t8 includes start information, and the history information written at the timing of t11 includes end information. Thereby, it becomes possible to grasp the execution period of the high-frequency support mode by checking the history information in the history memory 117.

[0249] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the high-frequency support mode. Further, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the high-frequency support mode by comparing the RTC information.

[0250] As shown in FIG. 22(d), from the timing of t12 to the timing of t15, the output state of the signal input to the tenth buffer 122j becomes the HI level. This tenth buffer 122j corresponds to the presence or absence of the opening of the front door frame 14. Therefore, as shown in FIG. 22(e), at the timing of t12 when the output state of the signal input to the tenth buffer 122j switches to the HI level, and at the timing of t15 when the output state of the signal switches to the LOW level, history information is written. In this case, the history information written at the timing of t12 includes start information, and the history information written at the timing of t15 includes end information. Thereby, by checking the history information in the history memory 117, it becomes possible to grasp the period during which the front door frame 14 is in the open state.

[0251] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening of the front door frame 14. Further, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening of the front door frame 14 by comparing the RTC information.

[0252] Next, a processing configuration for outputting the history information stored in the history memory 117 to a reading device electrically connected to the reading terminal 102 of the MPU 62 will be described. FIG. 23 is a flowchart showing the data output processing executed by the main CPU 63. Note that the data output processing is executed in step S111 in the main processing (FIG. 7).

[0253] In the data output process, first, it is determined whether a connection signal indicating that a reading device is electrically connected to the reading terminal 102 is received from the reading terminal 102 (step S901). The reading device is configured to output a connection signal when it is electrically connected to the reading terminal 102, and a positive determination is made in step S901 when the connection signal is received through the reading terminal 102.

[0254] If a negative determination is made in step S901, the data output process is terminated as it is. In this case, in order to execute the data output process, it is necessary to restart the supply of operating power to the MPU62. Thus, in order to perform the external output of the history information, it is necessary to start the supply of operating power to the MPU62 with the reading device electrically connected to the reading terminal 102. Since the power operation unit for performing the stop operation and start operation of the supply of operating power to the MPU62 is provided on the back surface of the back pack unit 15, in order to perform these stop operation and start operation, it is necessary to open the gaming machine main body 12 with respect to the outer frame 11 to expose the back surface of the back pack unit 15. In such circumstances, by adopting a configuration that requires the supply of operating power to the MPU62 to be started with the reading device electrically connected to the reading terminal 102 in order to perform the external output of the history information, even if someone other than the administrator of the game hall tries to perform the operation of reading the history information, it can be made difficult to do so.

[0255] When a positive determination is made in step S901, it is determined whether a signal for control information confirmation is being received from the reading terminal 102, thereby determining whether the current connection of the reading device to the reading terminal 102 corresponds to the confirmation of the control information (program and data) of the main ROM 64 (step S902). The reading device is configured to be able to perform both confirmation of control information and confirmation of history information. When confirmation of control information is selected by a manual operation on the reading device, a signal for control information confirmation is transmitted from the reading device. When confirmation of history information is selected by a manual operation on the reading device, a signal for history confirmation is transmitted from the reading device. Note that it is not limited to this, and a configuration may be adopted in which the reading device for control information confirmation and the reading device for history confirmation are separate. In this case, when a reading device for control information confirmation is electrically connected to the reading terminal 102, a signal for control information confirmation is transmitted from the reading device. When a reading device for history confirmation is electrically connected to the reading terminal 102, a signal for history confirmation is transmitted from the reading device.

[0256] When a positive determination is made in step S902, output processing for control information confirmation is executed (step S903). In the output processing, the program and data are read out as control information from the main ROM 64, and the read control information is output to the reading terminal 102. As a result, it becomes possible to read the control information in the reading device electrically connected to the reading terminal 102, and it becomes possible to confirm whether the control information is regular or normal.

[0257] When a negative determination is made in step S902, an output instruction signal is transmitted to the management-side CPU 112 (step S904). Specifically, the output state of the output instruction signal is switched from the LOW level to the HI level. This HI-level output state is continued for a specific period. This specific period is a period sufficient for the management-side CPU 112 to identify that a HI-level output instruction signal is input to the 16th buffer 122p. When the output state of the output instruction signal is switched to the HI level, a process for outputting history information is executed in the management-side CPU 112. This process will be described in detail later.

[0258] When the process of step S903 is executed, or when the process of step S904 is executed, it is determined whether the electrical connection of the reading device to the reading terminal 102 is continued (step S905). If it is continued (step S905: YES), it waits at step S905 as it is. Thereby, until the electrical connection of the reading device to the reading terminal 102 is released, it is possible to prevent the processes set in the execution order after the data output process from being executed. When the electrical connection of the reading device to the reading terminal 102 is released (step S905: NO), this data output process is terminated.

[0259] Next, the external output process executed by the management-side CPU 112 will be described with reference to the flowchart of FIG. 24. The external output process is executed in step S608 of the management process (FIG. 18).

[0260] When the output state of the output instruction signal received from the master CPU 63 is switched from the LOW level to the HI level (step S1001: YES), the process for outputting the history information after step S1002 is executed. Specifically, first, by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where the correspondence information indicating that it is the output port 24a is stored, the number of balls entering the output port 24a is calculated (step S1002). Also, by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where the correspondence information indicating that it is the general winning port 31 is stored, the number of balls entering the general winning port 31 is calculated (step S1003). Also, by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where the correspondence information indicating that it is the special electric winning device 32 is stored, the number of balls entering the special electric winning device 32 is calculated (step S1004). Also, by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where the correspondence information indicating that it is the first operation port 33 is stored, the number of balls entering the first operation port 33 is calculated (step S1005). Also, by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 where the correspondence information indicating that it is the second operation port 34 is stored, the number of balls entering the second operation port 34 is calculated (step S1006).

[0261] After that, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which the correspondence information and end information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117, the number of balls entering each of the out ports 24a, general winning ports 31, special electric winning devices 32, first operating ports 33, and second operating ports 34 that occurred in the situation where the front door frame 14 is in the open state is calculated (step S1007). The period between the history information storage area 125 in which the correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which the correspondence information and end information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which the correspondence information and end information indicating that it is the front door frame 14 are stored, the number of balls entering for each total of those sections is calculated. Also, although there is a history information storage area 125 in which the correspondence information and start information indicating that it is the front door frame 14 are stored, if the correspondence information and start information indicating that it is the front door frame 14 are not stored in the history information storage area 125 storing RTC information corresponding to a time after the history information storage area 125, all of the history information in the history information storage area 125 storing RTC information corresponding to a time after the history information storage area 125 in which the correspondence information and start information indicating that it is the front door frame 14 are stored is treated as being in the state where the front door frame 14 is open.

[0262] After that, various parameters are calculated using the calculation results of steps S1002 to S1007 (step S1008). Specifically, first, the number of balls entering the front door frame 14 calculated in step S1007 during the open state is subtracted from the number of balls entering calculated in each of steps S1002 to S1006. Then, the following parameters are calculated using the number of balls entering after the subtraction. The difference between the number of balls entering the outlet 24a calculated in step S1007 and the number of balls entering calculated in step S1002 is defined as the number of balls entering K1. The difference between the number of balls entering the general winning opening 31 calculated in step S1007 and the number of balls entering calculated in step S1003 is defined as the number of balls entering K2. The difference between the number of balls entering the special electric winning device 32 calculated in step S1007 and the number of balls entering calculated in step S1004 is defined as the number of balls entering K3. The difference between the number of balls entering the first operating opening 33 calculated in step S1007 and the number of balls entering calculated in step S1005 is defined as the number of balls entering K4. The difference between the number of balls entering the second operating opening 34 calculated in step S1007 and the number of balls entering calculated in step S1006 is defined as the number of balls entering K5. · First parameter: The ratio of the total number of payout game balls (K2 × "number of prize balls for winning at the general winning opening 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operating opening 33" + K5 × "number of prize balls for winning at the second operating opening 34") to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D1") · Second parameter: The ratio of the total number of game balls entering the general winning opening 31, K2, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) · Third parameter: The ratio of the total number of game balls entering the special electric winning device 32, K3, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) · Fourth parameter: The ratio of the total number of game balls entering the first operating opening 33, K4, to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D2") · Fifth parameter: Ratio of the total number of game balls K5 entering the second operation port 34 to the total number of game balls (K1 + K2 + K3 + K4 + K5) discharged from the game area PA (hereinafter, this ratio is referred to as "D3") · Sixth parameter: D1 - (D2 × "number of prize balls for winning at the first operation port 33" + D3 × "number of prize balls for winning at the second operation port 34") · Seventh parameter: Ratio of (K3 × "number of prize balls for winning at the special electric winning device 32" + K5 × "number of prize balls for winning at the second operation port 34") to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") · Eighth parameter: Ratio of K3 × "number of prize balls for winning at the special electric winning device 32" to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") After that, in the history area 124 of the history memory 117, the total time required until all the history information targeted for this calculation is extracted is calculated using the oldest RTC information and the newest RTC information (step S1009). Then, the first output process is executed (step S1010). In the first output process, all the history information stored in the history area 124 of the history memory 117 is sequentially output to the reading terminal 102. Also, the various parameters calculated in step S1008 are sequentially output to the reading terminal 102, and the total time calculated in step S1009 is output to the reading terminal 102. As a result, in the reading device electrically connected to the reading terminal 102, each piece of information targeted for output in the first output process is read.

[0263] After that, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored in the history area 124 of the history memory 117, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, the number of balls entering each of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 that occurred in the open / close execution mode is calculated (step S1011). The period between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored in the history area 124 of the history memory 117, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the serial pointer information, when there are a plurality of sections between the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored, and the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the end information are stored, the number of balls entering each is calculated for the total of those sections. Further, although the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored exists, if the correspondence information indicating the open / close execution mode and the start information are not stored in the history information storage area 125 corresponding to the time after the history information storage area 125, all the history information in the history information storage area 125 corresponding to the time after the history information storage area 125 in which the correspondence information indicating the open / close execution mode and the start information are stored is treated as being in the open / close execution mode.

[0264] After that, during the period of the opening / closing execution mode specified in step S1011, the number of game balls entering each of the out-port 24a, general winning port 31, special-electric winning device 32, first operation port 33, and second operation port 34 that occurred in the situation where the front door frame 14 was in the open state is calculated (step S1012). The method of calculating these numbers of game balls entering is the same as in the case of step S1007, except that it is based on the period of the opening / closing execution mode specified in step S1011.

[0265] After that, various parameters are calculated using the calculation results of steps S1011 and S1012 (step S1013). Specifically, first, the number of game balls entering during the opening of the front door frame 14 calculated in step S1012 is subtracted from each number of game balls entering calculated in step S1011. Then, the following parameters are calculated using the number of game balls entering after the subtraction. Note that the difference between the number of game balls entering the out-port 24a calculated in step S1012 and the number of game balls entering the out-port 24a calculated in step S1011 is defined as the number of game balls K11, the difference between the number of game balls entering the general winning port 31 calculated in step S1012 and the number of game balls entering the general winning port 31 calculated in step S1011 is defined as the number of game balls K12, the difference between the number of game balls entering the special-electric winning device 32 calculated in step S1012 and the number of game balls entering the special-electric winning device 32 calculated in step S1011 is defined as the number of game balls K13, the difference between the number of game balls entering the first operation port 33 calculated in step S1012 and the number of game balls entering the first operation port 33 calculated in step S1011 is defined as the number of game balls K14, and the difference between the number of game balls entering the second operation port 34 calculated in step S1012 and the number of game balls entering the second operation port 34 calculated in step S1011 is defined as the number of game balls K15. · 11th parameter: The ratio of the total number of game balls paid out ((K12 × "number of prize balls for winning at the general winning port 31") + (K13 × "number of prize balls for winning at the special-electric winning device 32") + (K14 × "number of prize balls for winning at the first operation port 33") + (K15 × "number of prize balls for winning at the second operation port 34")) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio is referred to as "D11") · 12th parameter: Ratio of the total number of game balls K12 entering the general winning opening 31 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA · 13th parameter: Ratio of the total number of game balls K13 entering the special electric winning device 32 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA · 14th parameter: Ratio of the total number of game balls K14 entering the first activation opening 33 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA (hereinafter, this ratio is referred to as "D12") · 15th parameter: Ratio of the total number of game balls K15 entering the second activation opening 34 to the total number of game balls (K11 + K12 + K13 + K14 + K15) discharged from the game area PA (hereinafter, this ratio is referred to as "D13") · 16th parameter: D11 - (D12 × "number of prize balls for winning at the first activation opening 33" + D13 × "number of prize balls for winning at the second activation opening 34") · 17th parameter: Ratio of (K13 × "number of prize balls for winning at the special electric winning device 32" + K15 × "number of prize balls for winning at the second activation opening 34") to the total number of game balls paid out (K12 × "number of prize balls for winning at the general winning opening 31" + K13 × "number of prize balls for winning at the special electric winning device 32" + K14 × "number of prize balls for winning at the first activation opening 33" + K15 × "number of prize balls for winning at the second activation opening 34") · 18th parameter: Ratio of K13 × "number of prize balls for winning at the special electric winning device 32" to the total number of game balls paid out (K12 × "number of prize balls for winning at the general winning opening 31" + K13 × "number of prize balls for winning at the special electric winning device 32" + K14 × "number of prize balls for winning at the first activation opening 33" + K15 × "number of prize balls for winning at the second activation opening 34") Thereafter, the second output process is executed (step S1014). In the second output process, the various parameters calculated in step S1013 are sequentially output to the reading terminal 102. As a result, in the reading device electrically connected to the reading terminal 102, each piece of information that is the output target in the second output process is read.

[0266] Thereafter, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117, the number of balls entering each of the out-port 24a, general winning port 31, special electric winning device 32, first operation port 33, and second operation port 34 occurring in the situation of the high-frequency support mode is calculated (step S1015). The period between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Further, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the high-frequency support mode are stored, the number of balls entering for each total of those sections is calculated. Also, although there is a history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored, when the correspondence information and start information indicating the high-frequency support mode are not stored in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125, all the history information in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125 in which the correspondence information and start information indicating the high-frequency support mode are stored is treated as being in the high-frequency support mode.

[0267] After that, among the periods of the high-frequency support mode specified in step S1015, the number of game balls entering each of the out ports 24a, general winning ports 31, special winning devices 32, first operating ports 33, and second operating ports 34 that occurred when the front door frame 14 was in the open state is calculated (step S1016). The method of calculating these numbers of game balls entering is the same as in the case of step S1007, except that it is based on the period of the high-frequency support mode specified in step S1015.

[0268] After that, various parameters are calculated using the calculation results of steps S1015 and S1016 (step S1017). Specifically, first, from each number of game balls entering calculated in step S1015, the number of game balls entering calculated in step S1016 that occurred while the front door frame 14 was open is subtracted. Then, the following parameters are calculated using the number of game balls entering after the subtraction. Note that the difference between the number of game balls entering the out port 24a calculated in step S1016 and the number of game balls entering the out port 24a calculated in step S1015 is defined as the number of game balls entering K21, the difference between the number of game balls entering the general winning port 31 calculated in step S1016 and the number of game balls entering the general winning port 31 calculated in step S1015 is defined as the number of game balls entering K22, the difference between the number of game balls entering the special winning device 32 calculated in step S1016 and the number of game balls entering the special winning device 32 calculated in step S1015 is defined as the number of game balls entering K23, the difference between the number of game balls entering the first operating port 33 calculated in step S1016 and the number of game balls entering the first operating port 33 calculated in step S1015 is defined as the number of game balls entering K24, and the difference between the number of game balls entering the second operating port 34 calculated in step S1016 and the number of game balls entering the second operating port 34 calculated in step S1015 is defined as the number of game balls entering K25. · 21st parameter: The ratio of the total number of paid-out game balls (K22 × "number of prize balls for winning in the general winning port 31" + K23 × "number of prize balls for winning in the special winning device 32" + K24 × "number of prize balls for winning in the first operating port 33" + K25 × "number of prize balls for winning in the second operating port 34") to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D11") · 22nd parameter: Ratio of the total number of game balls K22 that have entered the general winning opening 31 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 23rd parameter: Ratio of the total number of game balls K23 that have entered the special electric winning device 32 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 24th parameter: Ratio of the total number of game balls K24 that have entered the first activation opening 33 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D22") · 25th parameter: Ratio of the total number of game balls K25 that have entered the second activation opening 34 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D23") · 26th parameter: D21 - (D22 × "number of bonus balls for winning at the first activation opening 33" + D23 × "number of bonus balls for winning at the second activation opening 34") Thereafter, the third output process is executed (step S1018). In the third output process, the various parameters calculated in step S1017 are sequentially output to the reading terminal 102. As a result, in the reading device electrically connected to the reading terminal 102, each piece of information that is the output target in the third output process is read. Thereafter, a clear process is executed (step S1019). In the clear process, all of the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is cleared to "0". As a result, the history area 124 is in an initialized state.

[0269] According to the present embodiment described in detail above, the following excellent effects are achieved.

[0270] When a game ball enters any of the general winning opening 31, special electric winning device 32, first operation opening 33, and second operation opening 34, the game ball is paid out. Therefore, the player plays the game while expecting the game ball to enter any of these ball entry parts. In this configuration, when a game ball enters any of the out opening 24a, general winning opening 31, special electric winning device 32, first operation opening 33, and second operation opening 34 (hereinafter also referred to as the history target ball entry parts), the corresponding history information is stored in the history memory 117 of the management IC 66. As a result, it becomes possible for the pachinko machine 10 to store and hold information for managing the number of game balls entering or the frequency of entry of game balls into each history target ball entry part, and by using this managed information, it becomes possible to appropriately manage the entry mode of game balls into each history target ball entry part. Also, since the history information is stored and held by the pachinko machine 10 itself, it becomes possible to prevent unauthorized access to and unauthorized modification of the history information.

[0271] All ball entry parts that discharge game balls from the game area PA are subject to the execution of the storage process of the history information and the management using the history information. As a result, it becomes possible to manage the entry frequency of any history target ball entry part by using the history information. Also, it becomes possible to manage the ratio of the number of game balls entering each history target ball entry part to the number of game balls discharged from the game area PA by using the history information.

[0272] The history information includes RTC information, which is information corresponding to the timing when a game ball enters the history target ball entry part that triggered the storage of the history information. As a result, by using the history information, it becomes possible to grasp in detail the entry history of game balls into the history target ball entry part.

[0273] The history memory 117 stores not only history information corresponding to the entry of a game ball into the target entry section for history, but also history information indicating whether it is in the open / close execution mode, history information indicating whether it is in the high-frequency support mode, and history information indicating whether the front door frame 14 is open. As a result, it becomes possible to manage the entry state of the game ball into the target entry section for history by distinguishing whether or not each of these situations exists.

[0274] It is possible to output the history information stored in the history memory 117 to a reading device which is a device external to the pachinko machine 10. As a result, it becomes possible to read the history information with the reading device and analyze the entry state of the game ball into the target entry section for history using the read history information.

[0275] The MPU 62 is provided with a reading terminal 102, and it is possible to read a program from the main-side ROM 64 by a reading device electrically connected to the reading terminal 102. As a result, it becomes possible to confirm whether the program is normal. In this configuration, the history information stored in the history memory 117 is externally output using the reading terminal 102 for externally outputting the program. As a result, it becomes possible to externally output the history information while preventing the configuration from becoming complicated.

[0276] It is specified which of the program and the history information is the information to be output from the reading terminal 102, and the information on the corresponding side of the specified result is externally output through the reading terminal 102. As a result, in the configuration in which the history information is externally output using the reading terminal 102 for externally outputting the program, it is specified on the pachinko machine 10 side which of the program and the history information is the information to be externally output, and the specified information is externally output. Therefore, even in a configuration in which the reading terminal 102 is used in common, it becomes possible to read only the necessary information.

[0277] Based on the information received from the reading device electrically connected to the reading terminal 102, it is specified whether the information to be output from the reading terminal 102 is either the program or the history information. Thereby, it becomes possible to prevent the configuration regarding the selection of the information to be externally output from becoming complicated.

[0278] The MPU 62 having the main side ROM 64 that stores the program in advance has the management IC 66 and the reading terminal 102. Thereby, it becomes possible to aggregate the signal path to the reading terminal 102 within the MPU 62. Therefore, it becomes possible to achieve the excellent effects as described above while making it difficult to perform unauthorized access to the signal path to the reading terminal 102.

[0279] A management side CPU 112 is provided separately from the main side CPU 63 that executes a process for paying out a game ball based on the entry of the game ball into any one of the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34, and a process for storing the history information in the history memory 117 is executed by the management side CPU 112. Thereby, it becomes possible to manage the entry state of the game ball into each history target entry part while preventing the processing load of the main side CPU 63 from increasing extremely.

[0280] The main side CPU 63 and the management side CPU 112 are provided on the same chip as the MPU 62. Thereby, it becomes possible to prevent unauthorized access to the communication path between the main side CPU 63 and the management side CPU 112.

[0281] The main CPU 63 transmits information corresponding to the detection results of each of the ball entry detection sensors 42a to 48a to each of the buffers 122a to 122g of the input port 121 of the management IC 66 using the signal paths corresponding to each of the ball entry detection sensors 42a to 48a. As a result, the type of information transmitted from the main CPU 63 corresponds to each of the buffers 122a to 122g (i.e., each signal path), and it becomes possible to simplify the configuration for distinguishing the types of each information by the management-side CPU 112.

[0282] The main CPU 63 transmits information corresponding to whether it is in the open / close execution mode, information corresponding to whether it is in the high-frequency support mode, and information corresponding to whether the front door frame 14 is open, to each of the buffers 122h to 122j of the input port 121 of the management IC 66 using the signal paths corresponding to each of these situations. As a result, the type of information corresponding to each of these situations corresponds to each of the buffers 122h to 122j (i.e., each signal path), and it becomes possible to simplify the configuration for distinguishing the types of each information by the management-side CPU 112.

[0283] The main CPU 63 transmits correspondence relationship information indicating which type of information each of the buffers 122a to 122j (i.e., each signal path 118a to 118j) corresponds to, to the management-side CPU 112. As a result, it is not necessary to store the correspondence relationship information in advance in the management IC 66. Therefore, it becomes possible to enhance the versatility of the management IC 66.

[0284] When the supply of operating power to the main CPU 63 is started, the correspondence relationship information is transmitted from the main CPU 63 to the management IC 66. As a result, in a situation where a game ball can enter the ball entry part to be subjected to history, it becomes possible to specify the correspondence relationship between the information transmitted from the main CPU 63 and the ball entry part to be subjected to history by the management IC 66.

[0285] Using signal paths 118a to 118g for transmitting information indicating whether or not a game ball has entered the history target ball entry section, the correspondence information is transmitted from the main CPU 63 to the management IC 66. As a result, it becomes possible to simplify the configuration related to communication compared to a configuration in which a dedicated signal path for transmitting the correspondence information is provided.

[0286] The management IC 66 is provided with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. As a result, it is not necessary to provide, each time information on the detection results of the main CPU 63 to the detection results of the respective ball entry detection sensors 42a to 48a is transmitted, information that enables the management IC 66 to specify the history target ball entry section corresponding to the information to be transmitted. Therefore, it becomes possible to suppress the amount of information on the detection results of the respective ball entry detection sensors 42a to 48a transmitted from the main CPU 63.

[0287] When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from the LOW level to the HI level, information output from the management IC 66 to the read terminal 102 is performed. In this case, the fact that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal can be specified by the management side CPU 112 without receiving the correspondence information from the main CPU 63. As a result, it becomes possible to prevent the configuration related to the transmission of the correspondence information from becoming extremely complicated.

[0288] The management IC 66 is provided with a larger number of buffers 122a to 122p that can receive information from the main CPU 63 than the number of types of information that need to be transmitted from the main CPU 63 to the management IC 66. As a result, even when the number of types of such information increases or decreases according to the model of the pachinko machine 10, it becomes possible to cope without changing the configuration related to the buffers 122a to 122p. Therefore, it becomes possible to enhance the versatility of the management IC 66.

[0289] When history information is transmitted from the management IC 66 to the reading terminal 102, correspondence relationship information indicating the type of the history target ball entry part corresponding to the history information is included in each history information. Thereby, it becomes possible to specify the entry mode of the game balls into each history target ball entry part by using the read history information.

[0290] In the management IC 66, by using the history information stored in the history memory 117, various parameters (parameters 1 to 8, 11 to 18, 21 to 26) corresponding to the entry mode of the game balls in the game area PA in a predetermined period are calculated. Thereby, it becomes possible to externally output various parameters which are the results calculated by using the history information.

[0291] The various parameters are calculated in a state where the history information corresponding to the situation where the front door frame 14 is open is excluded. Thereby, it becomes possible to derive various parameters in a normal situation where the front door frame 14 is in the closed state. In addition, various parameters corresponding to each of the situation of the opening / closing execution mode and the situation of the high-frequency support mode are calculated. Thereby, it becomes possible for the administrator of the game hall or the like to grasp the entry mode of the game balls according to each situation.

[0292] When the various parameters are calculated, the history memory 117 is initialized by executing the clear process of the history memory 117. Thereby, it becomes possible to make it difficult for an event to occur in which history information exceeding the storage capacity of the history memory 117 becomes a storage target in the history memory 117 and the history information that should originally be stored and held is erased by overwriting.

[0293] When outputting the various parameters to the reading terminal 102, the history information stored in the history memory 117 is also output to the reading terminal 102. Thereby, when analyzing the entry mode of the game balls in the game area PA by reading the various parameters, it becomes possible to refer not only to the various parameters but also to the history information that is the basis for the calculation of the various parameters.

[0294] When a reading device is electrically connected to the reading terminal 102, the management-side CPU 112 calculates various parameters. This makes it possible to reduce the frequency of calculating various parameters.

[0295] When the main-side CPU 63 determines that a reading device is electrically connected to the reading terminal 102 and information on an output instruction is transmitted from the main-side CPU 63, the management IC 66 calculates various parameters, and the various parameters of the calculation result and the like are output to the reading terminal 102. This makes it possible to output various parameters to a reading device outside the pachinko machine 10 based on an instruction from the main-side CPU 63.

[0296] When it is determined whether a reading device is electrically connected to the reading terminal 102 in the process of starting the supply of operating power executed by the main-side CPU 63, and it is determined that the reading device is electrically connected, information on an output instruction is transmitted from the main-side CPU 63 to the management IC 66. Thus, in a situation where the process of starting the supply of operating power is being executed by the main-side CPU 63 or the like, that is, in a situation before the normal process for advancing the game is started by the main-side CPU 63, the calculation of various parameters and the external output of the various parameters of the calculation result are completed. Therefore, it is possible to prevent the calculation of various parameters and the external output of the calculation result from being performed in a situation where a game ball can enter the history target ball entry section, and it is possible to reduce the processing load on the management IC 66.

[0297] In a configuration where an external output corresponding to the entry of a game ball into the first operation port 33 or the second operation port 34 is performed through the external terminal board 97 when the entry of the game ball into the first operation port 33 or the second operation port 34 occurs, history information is stored in the history memory 117. Thereby, while easily grasping the number of game balls entering the first operation port 33 and the second operation port 34 and the entry frequency by using the information externally output through the external terminal board 97, it becomes possible to accurately grasp the number of game balls entering the history target entry part and the entry frequency by using the history information stored in the history memory 117.

[0298] <Second Embodiment> In this embodiment, among the first to sixteenth buffers 122a to 122p of the input port 121 in the management side I / F 111, the types of buffers in which the types of input signals are determined at the design stage of the management IC 66 are different from those in the first embodiment. Also, the processing configuration executed by the main CPU 63 to specify the types of input signals to the management side CPU 112 is different from that in the first embodiment. Hereinafter, the configuration different from the first embodiment will be described. Note that the description of the same configuration as that in the first embodiment will be basically omitted.

[0299] FIG. 25 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0300] The same types of signals as those in the first embodiment are input to the first to seventh buffers 122a to 122g and the sixteenth buffer 122p. Specifically, a first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a, a second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b, a third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c, a fourth signal corresponding to the detection result of the special power detection sensor 45a is input to the fourth buffer 122d, a fifth signal corresponding to the detection result of the first operating port detection sensor 46a is input to the fifth buffer 122e, a sixth signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a seventh signal corresponding to the detection result of the out port detection sensor 48a is input to the seventh buffer 122g, and an output instruction signal is input to the sixteenth buffer 122p.

[0301] On the other hand, in the first embodiment, a signal corresponding to the opening / closing execution mode is input as an eighth signal to the eighth buffer 122h, a signal corresponding to the high-frequency support mode is input as a ninth signal to the ninth buffer 122i, and a signal corresponding to the front door frame 14 is input as a tenth signal to the tenth buffer 122j. However, in this embodiment, the buffers to which these signals are input are different. Specifically, the signal corresponding to the opening / closing execution mode is input as a signal during the opening / closing execution mode to the thirteenth buffer 122m, the signal corresponding to the high-frequency support mode is input as a signal during the high-frequency support mode to the fourteenth buffer 122n, and the signal corresponding to the front door frame 14 is input as a signal during door opening to the fifteenth buffer 122o.

[0302] The signal during the open / close execution mode is input to the 13th buffer 122m, the signal during the high-frequency support mode is input to the 14th buffer 122n, the signal during the door opening is input to the 15th buffer 122o, and the output instruction signal is input to the 16th buffer 122p, which are determined at the design stage of the management IC66. Without receiving an instruction from the main CPU 63, the management CPU 112 can identify that the above-mentioned signals corresponding to the 13th to 16th buffers 122m to 122p are input respectively. On the other hand, what kind of signals are input to the 1st to 12th buffers 122a to 122l is not determined at the design stage of the management IC66, and the types of these signals are identified by the management CPU 112 by receiving an instruction from the main CPU 63. The process for identifying the types of these signals is executed when the supply of operating power to the main CPU 63 and the management CPU 112 is started, similar to the first embodiment.

[0303] FIG. 26 is a flowchart showing the recognition process of this embodiment executed by the main CPU 63. The recognition process is executed in step S110 in the main process (FIG. 7) in the same manner as in the first embodiment.

[0304] First, set "12", which is the number of the 1st to 12th buffers 122a to 122l that are the recognition targets of the signal types, to the recognition output counter in the main RAM 65 (step S1101). Then, execute the output process of the identification start signal (step S1102). In this output process, the output state of each of the 1st signal input to the 1st buffer 122a, the signal during the open / close execution mode input to the 13th buffer 122m, and the signal during the high-frequency support mode input to the 14th buffer 122n is set to the HI level to start the output of the identification start signal. The period for maintaining these signals at the HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

[0305] Thereafter, information on the number of output times corresponding to the current value of the recognition output counter of the main-side RAM 65 is read from the main-side ROM 64, and the read information on the number of output times is set in the output number counter provided in the main-side RAM 65 (step S1103). The output number counter is a counter for specifying the number of output times of the type identification signal by the main-side CPU 63.

[0306] In the present embodiment, when the management-side CPU 112 recognizes the types of signals input to the first buffer 122a to the twelfth buffer 122l, the type identification signal is output the same number of times as the number of prize balls set for the entrance corresponding to the type of that signal. The management-side CPU 112 stores information corresponding to the number of times the type identification signal is received for each of the first buffer 122a to the twelfth buffer 122l in the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. That is, the types of signals input to the first buffer 122a to the twelfth buffer 122l are grasped as the number of prize balls set for the entrance corresponding to the type of that signal.

[0307] In step S1103, when the value of the recognition output counter is any of "12", "11", and "10", "10" corresponding to the number of prize balls of the general winning opening 31 is set in the output number counter. When the value of the recognition output counter is "9", "15" corresponding to the number of prize balls of the special electric winning device 32 is set in the output number counter. When the value of the recognition output counter is "8", "1" corresponding to the number of prize balls of the first operating port 33 is set in the output number counter. When the value of the recognition output counter is "7", "1" corresponding to the number of prize balls of the second operating port 34 is set in the output number counter. When the value of the recognition output counter is "6", since the game balls are not paid out even if game balls enter the out port 24a corresponding to the out port 24a, "0" is set in the output number counter. When the value of the recognition output counter is any of "5" to "1", since there is no corresponding entrance and it is blank, "0" is set in the output number counter.

[0308] After that, the output process of the start trigger signal is executed (step S1104). In this output process, the output of the start trigger signal is started by setting the output state of the first signal input to the first buffer 122a to the HI level. The period for maintaining the first signal at the HI level is set to a period sufficient for the management-side CPU 112 to recognize the output state of the first signal.

[0309] After that, on the condition that the value of the output count counter in the main-side RAM 65 is not "0" (step S1105: YES), that is, on the condition that a value of 1 or more is set in the output count counter in step S1103, the process proceeds to step S1106. In step S1106, the output process of the type identification signal is executed. In this output process, the output of the type identification signal is started by setting the output state of the second signal input to the second buffer 122b to the HI level. The period for maintaining the second signal at the HI level is set to a period sufficient for the management-side CPU 112 to recognize the output state of the second signal.

[0310] After that, the value of the output count counter in the main-side RAM 65 is decremented by 1 (step S1107), and it is determined whether the value of the output count counter after the decrement by 1 is "0" (step S1108). If the value of the output count counter is 1 or more (step S1108: NO), the process returns to step S1106.

[0311] When an affirmative determination is made in step S1105 or when an affirmative determination is made in step S1108, the output process of the end trigger signal is executed (step S1109). In this output process, the output of the end trigger signal is started by setting the output state of the third signal input to the third buffer 122c to the HI level. The period for maintaining the third signal at the HI level is set to a period sufficient for the management-side CPU 112 to recognize the output state of the third signal.

[0312] Thereafter, the value of the recognition output counter of the main-side RAM 65 is decremented by 1 (step S1110), and it is determined whether the value of the recognition output counter after the decrement by 1 is "0" (step S1111). If the value of the recognition output counter is 1 or more (step S1111: NO), the process returns to step S1103, and the process for recognizing the type of signal corresponding to the value of the recognition output counter after the decrement by 1 is executed.

[0313] On the other hand, if the value of the recognition output counter is "0" (step S1111: YES), the output process of the identification end signal is executed (step S1112). In the output process, the output state of each of the third signal input to the third buffer 122c, the signal during the opening / closing execution mode input to the thirteenth buffer 122m, and the signal during the high-frequency support mode input to the fourteenth buffer 122n is set to the HI level, thereby starting the output of the identification end signal. The period during which these signals are maintained at the HI level is set to a period sufficient for the management-side CPU 112 to recognize the output states of these signals.

[0314] Next, the management process in this embodiment executed by the management-side CPU 112 will be described with reference to the flowchart of FIG. 27. The management process starts when the supply of operating power to the management-side CPU 112 is started in the same manner as in the first embodiment.

[0315] When the reception of the identification start signal from the main CPU 63 is completed (step S1201: YES), the value of the counter to be set in the management-side RAM 114 is cleared to "0" (step S1202). Then, on the condition that the start trigger signal is being received from the main CPU 63 (step S1203: YES), the process proceeds to step S1204. In step S1204, it is determined whether a type identification signal is being received from the main CPU 63. When a type identification signal is being received (step S1204: YES), the value of the reception count counter provided in the management-side RAM 114 is incremented by 1 (step S1205). The reception count counter is a counter for the management-side CPU 112 to identify the number of times the type identification signal has been received from the main CPU 63. Note that the value of the reception count counter is cleared to "0" when an affirmative determination is made in step S1203.

[0316] When a negative determination is made in step S1204, or when the process of step S1205 is executed, it is determined whether an end trigger signal is being received from the main CPU 63 (step S1206). When the end trigger signal is not being received (step S1206: NO), the process returns to step S1204. When the end trigger signal is being received (step S1206: YES), the correspondence relationship setting process is executed (step S1207). In the correspondence relationship setting process, among the first to twelfth correspondence relationship areas 123a to 123l of the correspondence relationship memory 116, the value set in the reception count counter is stored in the correspondence relationship area corresponding to the current value in the counter to be set in the management-side RAM 114. In this case, "10" corresponding to the number of prize balls in the general winning opening 31 is set in the first correspondence relationship area 123a, the second correspondence relationship area 123b, and the third correspondence relationship area 123c, "15" corresponding to the number of prize balls in the special electric winning device 32 is set in the fourth correspondence relationship area 123d, "1" corresponding to the number of prize balls in the first operating opening 33 is set in the fifth correspondence relationship area 123e, and "1" corresponding to the number of prize balls in the second operating opening 34 is set in the sixth correspondence relationship area 123f. Also, "0" is set in the seventh to twelfth correspondence relationship areas 123g to 123l. Then, the value of the counter to be set in the management-side RAM 114 is incremented by 1 (step S1208).

[0317] When a negative determination is made in step S1203 or when the process of step S1208 is executed, it is determined whether the reception of the identification end signal from the host CPU 63 has ended (step S1209). If the reception of the identification end signal has not ended (step S1209: NO), the process returns to step S1203, and the processes after step S1204 are executed on the condition that the start trigger signal is received from the host CPU 63 (step S1203: YES). When the reception of the identification end signal from the host CPU 63 has ended (step S1209: YES), the history setting process of step S1210 and the external output process of step S1211 are repeatedly executed.

[0318] FIG. 28 is a time chart showing a state in which information on the correspondence relationship between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l is stored in the correspondence relationship memory 116. FIG. 28(a) shows a period during which the output state of the first signal is at the HI level, FIG. 28(b) shows a period during which the output state of the second signal is at the HI level, FIG. 28(c) shows a period during which the output state of the third signal is at the HI level, FIG. 28(d) shows a period during which the output state of the signal during the open / close execution mode is at the HI level, FIG. 28(e) shows a period during which the output state of the signal during the high-frequency support mode is at the HI level, FIG. 28(f) shows an execution period of an identification state in which a process for identifying the correspondence relationship between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l is executed, FIG. 28(g) shows a timing at which the value of the reception count counter of the management side RAM 114 is incremented by 1, and FIG. 28(h) shows a timing at which the correspondence relationship setting process (step S1207) is executed by the management side CPU 112.

[0319] When the supply of operating power to the main CPU 63 and the management CPU 112 is started, at the timing of t1, as shown in FIGS. 28(a), 28(d), and 28(e), the output states of the first signal, the signal during the opening / closing execution mode, and the signal during the high-frequency support mode are changed from the LOW level to the HI level. As a result, the output of the identification start signal from the main CPU 63 to the management CPU 112 is started. Thereafter, at the timing of t2, the output states of the first signal, the signal during the opening / closing execution mode, and the signal during the high-frequency support mode are changed from the HI level to the LOW level. As a result, the output of the identification start signal from the main CPU 63 to the management CPU 112 is stopped. At the timing of t2, the management CPU 112 makes an affirmative determination in step S1201 of the management process (FIG. 27), and enters the identification state as shown in FIG. 28(f).

[0320] Thereafter, from the timing of t3 to the timing of t4, the output state of the first signal is maintained at the HI level as shown in FIG. 28(a). As a result, the start trigger signal is output to the management CPU 112. Then, from the timing of t5 to the timing of t7, the output state of the second signal is maintained at the HI level as shown in FIG. 28(b). As a result, the type identification signal is output once to the management CPU 112. In this case, at the timing of t6, as shown in FIG. 28(g), the value of the reception count counter of the management-side RAM 114 is incremented by 1.

[0321] Thereafter, from the timing of t8 to the timing of t10, the output state of the third signal is maintained at the HI level as shown in FIG. 28(c). As a result, the end trigger signal is output to the management CPU 112. In this case, at the timing of t9, as shown in FIG. 28(h), the management CPU 112 executes the correspondence setting process. Since the value of the reception count counter is "1" at the timing when the correspondence setting process is executed, the information "1" is stored as correspondence information in the correspondence area 123a to 123l of the current setting target in the correspondence memory 116.

[0322] Thereafter, as shown in FIG. 28(a), the output state of the first signal is maintained at the HI level from the timing of t11 to the timing of t12. As a result, the start trigger signal is output to the management-side CPU 112. Then, as shown in FIG. 28(b), the output state of the second signal is maintained at the HI level for each of the timings from t13 to t15, from t16 to t18, from t19 to t21, and from t22 to t24. As a result, the type identification signals are each output once to the management-side CPU 112. In this case, at each of the timings of t14, t17, t20, and t23, as shown in FIG. 28(g), the value of the reception count counter in the management-side RAM 114 is incremented by 1.

[0323] Thereafter, as shown in FIG. 28(c), the output state of the third signal is maintained at the HI level from the timing of t25 to the timing of t27. As a result, the end trigger signal is output to the management-side CPU 112. In this case, at the timing of t26, as shown in FIG. 28(h), the correspondence relationship setting process is executed by the management-side CPU 112. Since the value of the reception count counter is "10" at the timing when the correspondence relationship setting process is executed, information "10" is stored as correspondence relationship information in the correspondence relationship areas 123a to 123l of the current setting target in the correspondence relationship memory 116.

[0324] Thereafter, at the timing of t28, as shown in FIGS. 28(c), 28(d), and 28(e), the output states of the third signal, the signal during the opening / closing execution mode, and the signal during the high-frequency support mode are changed from the LOW level to the HI level. Thereby, the output of the identification completion signal from the main CPU 63 to the management CPU 112 is started. Thereafter, at the timing of t29, the output states of the third signal, the signal during the opening / closing execution mode, and the signal during the high-frequency support mode are changed from the HI level to the LOW level. Thereby, the output of the identification completion signal from the main CPU 63 to the management CPU 112 is stopped. At the timing of t29, the management CPU 112 makes an affirmative determination in step S1209 of the management process (FIG. 27), and the identification state is released as shown in FIG. 28(f).

[0325] In addition, in the present embodiment, since the information on the number of prize balls is stored as the correspondence relationship information, the history information stored in the history memory 117 includes the information on the number of prize balls corresponding to the ball entry unit that triggered the storage of the history information as the correspondence relationship information. In such a configuration, when there are multiple types of ball entry units with the same number of prize balls, they cannot be distinguished in the history information. Specifically, since both the first operation port 33 and the second operation port 34 have one prize ball each, the first operation port 33 and the second operation port 34 cannot be distinguished in the history information. In such a situation, the number of prize balls for the first operation port 33 and the second operation port 34 may be made different. Thereby, even in a configuration in which history information as in the second embodiment is stored, it becomes possible to distinguish the first operation port 33 and the second operation port 34 in the history information.

[0326] Also, in the present embodiment, in step S801 of the history setting process, "15" is set in the confirmation target counter of the management-side RAM 114. Thereby, all of the first to fifteenth buffers 122a to 122o become the confirmation targets.

[0327] According to the present embodiment described in detail above, not only the output instruction signal, but also information corresponding to whether it is in the opening / closing execution mode, information corresponding to whether it is in the high-frequency support mode, and information corresponding to whether the front door frame 14 is open can be specified by the management-side CPU 112 without receiving the correspondence information from the main-side CPU 63 which is the signal path corresponding to these information. In this case, only the information corresponding to the detection results of the respective ball entry detection sensors 42a to 48a becomes the information that needs to be recognized by the management-side CPU 112 from the main-side CPU 63 regarding the correspondence between each information and each signal path 118a to 118g. And when making the management-side CPU 112 recognize the correspondence information, the same number of pulse signals as the number of prize balls corresponding to the respective ball entry detection sensors 42a to 48a are output from the main-side CPU 63 to the management-side CPU 112 using the second signal. Thereby, it becomes possible to simplify the configuration regarding the transmission of the correspondence information.

[0328] <Third Embodiment> In this embodiment, the timing when various parameters are calculated using the history information is different from that of the first embodiment described above. Hereinafter, the configuration different from that of the first embodiment will be described. Note that the description of the same configuration as that of the first embodiment will be basically omitted.

[0329] FIG. 29 is a block diagram for explaining the electrical configuration of the management IC 66 in this embodiment. The management IC 66 is provided with a management-side I / F 111, a management-side CPU 112, a management-side ROM 113, a management-side RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117 in the same manner as in the first embodiment described above. These functions are the same as those of the first embodiment.

[0330] In addition to the above, the management IC 66 is provided with a calculation result memory 131. In this embodiment, as will be described in detail later, when a calculation trigger occurs, various parameters are calculated by the management side CPU 112 using the history information stored in the history memory 117 at that time. Then, the calculated various parameters are sequentially stored in the calculation result memory 131. The various parameters stored in the calculation result memory 131 are output to a reading device electrically connected to the reading terminal 102.

[0331] The trigger for calculating various parameters occurs before the timing when a reading device is electrically connected to the reading terminal 102. Thereby, it becomes possible to make the timing for calculating various parameters different from the timing for externally outputting to the reading device, and it becomes possible to disperse the processing load.

[0332] Also, since the calculation result memory 131 for storing the calculation results of various parameters is provided, it becomes possible to collectively store not only the various parameters for one calculation trigger but also the various parameters for a plurality of calculation triggers. Thereby, it becomes possible to shorten the time required to calculate various parameters in each calculation trigger.

[0333] FIG. 30 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0334] The same types of signals as those in the first embodiment are input to the first to tenth buffers 122a to 122j and the sixteenth buffer 122p. Specifically, a first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a, a second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b, a third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c, a fourth signal corresponding to the detection result of the special power detection sensor 45a is input to the fourth buffer 122d, a fifth signal corresponding to the detection result of the first operating port detection sensor 46a is input to the fifth buffer 122e, a sixth signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a seventh signal corresponding to the detection result of the out port detection sensor 48a is input to the seventh buffer 122g, a signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h, a signal corresponding to the high-frequency support mode is input to the ninth buffer 122i, a signal corresponding to the front door frame 14 is input to the tenth buffer 122j, and an output instruction signal is input to the sixteenth buffer 122p.

[0335] In this embodiment, in addition to the above various signals, an operation instruction signal is input to the fifteenth buffer 122o. The operation instruction signal is a signal output from the main CPU 63 to provide a trigger for calculating various parameters to the management-side CPU 112. The input of the operation instruction signal to the fifteenth buffer 122o, similar to the input of the output instruction signal to the sixteenth buffer 122p, is determined at the design stage of the management IC 66. Without receiving an instruction from the main CPU 63, the management-side CPU 112 can identify that the above respective signals corresponding to the fifteenth to sixteenth buffers 122o to 122p are input. On the other hand, what types of signals are input to the first to fourteenth buffers 122a to 122n are not determined at the design stage of the management IC 66, and the types of these signals are identified by the management-side CPU 112 upon receiving an instruction from the main CPU 63. The process for identifying the types of these signals is executed when the supply of operating power to the main CPU 63 and the management-side CPU 112 is started, similar to the first embodiment.

[0336] Next, a processing configuration for causing the management CPU 112 to execute calculations of various parameters in response to the occurrence of a calculation trigger will be described. FIG. 31 is a flowchart showing a power failure information storage process executed by the main CPU 63. The power failure information storage process is executed in step S201 of the timer interrupt process (FIG. 8).

[0337] In the power failure information storage process, when a power failure signal corresponding to the occurrence of a power failure is received from the power failure monitoring board 67 (step S1301: YES), an output process of a calculation instruction signal is executed (step S1302). In the output process, the output state of the calculation instruction signal input to the 15th buffer 122o in the input port 121 of the management I / F 111 is maintained at the HI level for a specific period. This specific period is sufficient for the management CPU 112 to recognize that the output state of the calculation instruction signal is at the HI level. After that, after executing the power failure time process in step S1303, an infinite loop is entered, and the process waits until the supply of operating power to the main CPU 63 is completely stopped. In the power failure time process, a "1" is set in the power failure flag of the main RAM 65, and a checksum is calculated and the calculated checksum is saved.

[0338] FIG. 32 is a flowchart showing a power failure countermeasure process executed by the management CPU 112. The power failure countermeasure process is configured to be executed after the external output process in the management process (FIG. 18). In the management process, after receiving an identification end command from the main CPU 63 (step S606: YES), the history setting process in step S607, the external output process in step S608, and the power failure countermeasure process are repeatedly executed in this order.

[0339] In the power failure response process, when the output state of the operation instruction signal received from the main CPU 63 becomes the HI level (step S1401: YES), in steps S1402 to S1406, similar to steps S1002 to S1006 of the external output process (Fig. 24) in the first embodiment, the number of balls entering each of the output port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is calculated. Also, in step S1407, similar to step S1007 of the external output process (Fig. 24) in the first embodiment, the number of balls entering various ports in the situation where the front door frame 14 is open is calculated. Further, in step S1408, similar to step S1008 of the external output process (Fig. 24) in the first embodiment, various parameters are calculated, and in step S1409, similar to step S1009 of the external output process (Fig. 24) in the first embodiment, the total time is calculated. Then, the information of the calculation result in step S1408 and the information of the calculation result in step S1409 are written into the calculation result memory 131 (step S1410). In this case, when there is already other calculation result information stored in the calculation result memory 131, the writing of the calculation result information is performed so as not to overwrite the already stored calculation result information. Also, the current year, month, day information and time information are read from the RTC 115, and the read year, month, day information and time information are associated with the calculation result information for which the writing is performed this time. Thereby, it becomes possible to specify at what timing the calculation result information for which the writing is performed this time corresponds to.

[0340] After that, in step S1411, in the same manner as step S1011 of the external output process (Fig. 24) in the first embodiment, various ball entry counts during the opening / closing execution mode are calculated. In step S1412, in the same manner as step S1012 of the external output process (Fig. 24) in the first embodiment, various ball entry counts in the situation where the front door frame 14 is open during the opening / closing execution mode are calculated. Also, in step S1413, in the same manner as step S1013 of the external output process (Fig. 24) in the first embodiment, various parameters are calculated. Then, the information of the calculation result in step S1414 is written into the calculation result memory 131 (step S1414). In this case, the writing of the calculation result information is performed so as not to overwrite the information of other calculation results already stored in the calculation result memory 131. Also, the current date, month, year information and time information are read from the RTC 115, and the read date, month, year information and time information are attached to the calculation result information for which the writing is performed this time. Thereby, it becomes possible to specify at what timing the calculation result information for which the writing is performed this time corresponds to.

[0341] Thereafter, in step S1415, in the same manner as step S1015 of the external output process (Fig. 24) in the first embodiment, various ball entry counts during the high-frequency support mode are calculated. In step S1416, in the same manner as step S1016 of the external output process (Fig. 24) in the first embodiment, various ball entry counts in the situation where the front door frame 14 is open during the high-frequency support mode are calculated. Also, in step S1417, in the same manner as step S1017 of the external output process (Fig. 24) in the first embodiment, various parameters are calculated. Then, the information of the calculation result in step S1417 is written into the calculation result memory 131 (step S1418). In this case, the writing of the calculation result information is performed so as not to overwrite the information of other calculation results already stored in the calculation result memory 131. Also, the current date, month, year information and time information are read from the RTC 115, and the read date, month, year information and time information are associated with the calculation result information for which the writing is performed this time. Thereby, it becomes possible to specify at what timing the calculation result information for which the writing is performed this time corresponds. Thereafter, it becomes an infinite loop, and it waits until the supply of the operating power to the management-side CPU 112 is completely stopped.

[0342] Fig. 33 is a flowchart showing the external output process executed by the management-side CPU 112. Note that the external output process is executed in step S608 of the management process (Fig. 18).

[0343] When the output state of the output instruction signal from the master CPU 63 becomes the HI level (step S1501: YES), the output process of the calculation result is executed (step S1502). In this output process, various calculation results stored in the calculation result memory 131 are output to the reading terminal 102. As a result, in the reading device electrically connected to the reading terminal 102, various calculation results stored in the calculation result memory 131 are read. In this case, if only the various calculation results corresponding to the occurrence of one calculation opportunity are stored in the calculation result memory 131, only the various calculation results corresponding to the occurrence of that one calculation opportunity are read by the reading device. If various calculation results corresponding to the occurrence of multiple calculation opportunities are stored in the calculation result memory 131, then the various calculation results corresponding to the occurrence of those multiple calculation opportunities are read by the reading device.

[0344] Thereafter, the output process of the history information is executed (step S1503). In this output process, all the history information stored in the history area 124 of the history memory 117 is sequentially output to the reading terminal 102. As a result, in the reading device electrically connected to the reading terminal 102, various history information stored in the history area 124 is read. By outputting not only various calculation results but also history information in this way, it becomes possible for an operator using the reading device to perform a detailed analysis of the various calculation results.

[0345] Thereafter, a clear process is executed (step S1504). In the clear process, all of the history information storage area 125 of the history memory 117 is cleared to "0", and the pointer area 126 is cleared to "0". As a result, the history area 124 is in an initialized state. Also, in the clear process, all areas of the calculation result memory 131 are cleared to "0". As a result, the calculation result memory 131 is in an initialized state.

[0346] According to the present embodiment described in detail above, the following excellent effects are achieved.

[0347] When the supply of operating power to the main CPU 63 is stopped, various parameters are calculated by the management CPU 112. As a result, it becomes possible to manage various parameters on a per business day basis.

[0348] When it is specified that the supply of operating power to the main CPU 63 is stopped, the output state of the calculation instruction signal is changed to the HI level, and various parameters are calculated by the management CPU 112. As a result, it becomes possible to calculate various parameters by the management CPU 112 based on an instruction from the main CPU 63.

[0349] The various parameters calculated by the management CPU 112 are sequentially written into the calculation result memory 131. As a result, it becomes possible to accumulate various parameters in the management IC 66, and when reading various parameters by a reading device, it becomes possible to read out the various parameters of a plurality of business days collectively.

[0350] When various parameters are written into the calculation result memory 131, information that enables identification of the timing when the various parameters were calculated is written into the calculation result memory 131 in association with the respective various parameters. As a result, it becomes possible to analyze various parameter information while grasping the timing when the various parameters were calculated.

[0351] Note that when a calculation trigger occurs and the calculation result of various parameters with respect to the trigger is written into the calculation result memory 131, the history memory 117 may be configured to be cleared to "0". As a result, it becomes less likely that an event will occur in which new history information becomes a write target to the history memory 117 in a situation where the maximum number of history information that can be stored is already stored in the history memory 117.

[0352] Further, the information of the object to be externally output to the reading device may be only the information of various parameters stored in the operation result memory 131, and the history information stored in the history memory 117 may not be externally output. This makes it possible to suppress the amount of information to be externally output.

[0353] <Fourth Embodiment> In this embodiment, the processing configuration of the power failure countermeasure processing executed by the management side CPU 112 is different from that of the third embodiment described above. Hereinafter, the configuration different from that of the third embodiment will be described. Note that the description of the same configuration as that of the third embodiment described above will be basically omitted.

[0354] FIG. 34 is a flowchart showing the power failure countermeasure processing executed by the management side CPU 112 in this embodiment.

[0355] When the output state of the operation instruction signal received from the main side CPU 63 becomes the HI level (step S1601: YES), various arithmetic processes are executed (step S1602). In the various arithmetic processes, the processes of step S1402 to step S1409, step S1411 to step S1413, and step S1415 to step S1417 of the power failure countermeasure processing (FIG. 32) in the third embodiment are executed.

[0356] Thereafter, it is determined whether or not a predetermined parameter among the various parameters calculated in step S1602 is within a reference range (step S1603). Specifically, · Seventh parameter: Ratio of (K3 × "number of prize balls for winning in special electric winning device 32" + K5 × "number of prize balls for winning in second operation port 34") / total number of game balls paid out (K2 × "number of prize balls for winning in general winning port 31" + K3 × "number of prize balls for winning in special electric winning device 32" + K4 × "number of prize balls for winning in first operation port 33" + K5 × "number of prize balls for winning in second operation port 34") · Eighth parameter: Ratio of K3 × "number of prize balls for winning in special electric winning device 32" / total number of payout game balls (K2 × "number of prize balls for winning in general winning opening 31" + K3 × "number of prize balls for winning in special electric winning device 32" + K4 × "number of prize balls for winning in first operating opening 33" + K5 × "number of prize balls for winning in second operating opening 34") These two parameters are set as parameters to be determined whether they are within the reference range. And when the value of the seventh parameter is 0.7 or less and the value of the eighth parameter is 0.6 or less, an affirmative determination is made in step S1603 assuming that the predetermined parameter is within the reference range.

[0357] Note that the predetermined parameter is not limited to the seventh parameter and the eighth parameter, and instead of or in addition to these, other parameters may be set as the predetermined parameter. For example, · Second parameter: Ratio of total number of game balls K2 entering general winning opening 31 / total number of game balls discharged from game area PA (K1 + K2 + K3 + K4 + K5) It may be configured to be set as a predetermined parameter. In this case, for example, when the value of the second parameter is 0.1 or more and 0.2 or less, it may be configured to be determined that the predetermined parameter is within the reference range. Also, it may be configured that only the predetermined parameter to be determined in step S1603 is calculated in the various arithmetic processes of step S1602.

[0358] When the specified parameters are not within the reference range (step S1603: NO), the various parameters calculated in step S1602 are written to the calculation result memory 131 (step S1604). In this case, if information on other calculation results is already stored in the calculation result memory 131, the information on the calculation results is written so as not to overwrite the already stored information on the calculation results. Also, the current date, month, year information, and time information are read from the RTC 115, and the read date, month, year information and time information are associated with the information on the calculation results for which the writing is performed this time. As a result, it becomes possible to identify at what timing the information on the calculation results for which the writing is performed this time corresponds to.

[0359] On the other hand, when the specified parameters are within the reference range (step S1603: YES), the process of step S1604 is not executed. As a result, only the various parameters in the case where the specified parameters are not within the reference range are written to the calculation result memory 131. Therefore, it becomes possible to suppress the storage capacity required for the calculation result memory 131 while leaving the history in the calculation result memory 131 when an abnormal situation occurs.

[0360] When an affirmative determination is made in step S1603 or when the process of step S1604 is executed, a clear process for the history memory 117 is executed (step S1605). In the clear process, all of the history information storage areas 125 of the history memory 117 are cleared to "0", and the pointer area 126 is cleared to "0". As a result, the history area 124 is in an initialized state. After the process of step S1605 is executed, an infinite loop occurs, and the process waits until the supply of operating power to the management side CPU 112 is completely stopped.

[0361] According to the embodiment described in detail above, it is determined whether the content of each calculated parameter is included in the reference range, and only the various parameters determined not to be included in the reference range are written into the calculation result memory 131. As a result, it is possible to suppress the amount of various parameters to be stored in the calculation result memory 131, and it is possible to suppress the necessary storage capacity in the calculation result memory 131.

[0362] <Fifth Embodiment> In this embodiment, the content of the calculation trigger for causing the management side CPU 112 to execute the calculation of various parameters is different from that of the third embodiment described above. Hereinafter, the configuration different from that of the third embodiment will be described. Note that the description of the same configuration as that of the third embodiment will be basically omitted.

[0363] FIG. 35(a) is a flowchart showing the trigger specifying process executed by the main side CPU 63. The trigger specifying process is executed as a process when an affirmative determinatio...

Claims

【Claim 1】 Predetermined storage execution means for storing predetermined information in the predetermined storage means by executing a predetermined storage process so that when a predetermined event occurs as a result of a game, storage of information corresponding thereto is executed in the predetermined storage means; Information calculation means for calculating mode information corresponding to the result of a game in a predetermined period by using the predetermined information each time a predetermined calculation trigger occurs; Result storage execution means for sequentially storing the mode information obtained by the calculation by the information calculation means in a calculation result storage means; comprising The result storage execution means includes means for causing the mode information to be stored in the calculation result storage means to be the mode information to be stored among the mode information obtained by the calculation by the information calculation means; The mode information that is not the storage target among the mode information obtained by the calculation by the information calculation means is not configured to be stored in the calculation result storage means; This gaming machine Predetermined control means capable of executing a predetermined process including a predetermined progress process for advancing the game and the predetermined storage process; Means for generating a specific advantageous period when a specific trigger occurs; Means for causing the predetermined information in the predetermined storage means to be erased after the calculation of the mode information by the information calculation means is completed; Notification means capable of notifying the content corresponding to the mode information stored in the calculation result storage means; comprising In one process cycle of the predetermined process, the predetermined storage process is executed after the predetermined progress process is executed; The information calculation means calculates the mode information by using the predetermined information in the specific advantageous period as the mode information corresponding to the result of the game in the predetermined period. A gaming machine characterized by this.

Images