Display device

Abstract

To propose a semiconductor device having a highly reliable thin-film transistor excellent in electrical properties, and also to propose a method for manufacturing the semiconductor device without variation.SOLUTION: A display device includes a thin-film transistor of a reverse stagger type (a bottom gate structure) using an oxide semiconductor film containing In, Ga and Zn as a semiconductor layer, having a buffer layer between a semiconductor layer, and a source electrode layer and a drain electrode layer. An ohmic contact is formed through intentionally disposing the buffer layer containing In, Ga and Zn having a higher carrier concentration than that of the semiconductor layer between the source electrode layer and the drain electrode layer, and the semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) using an oxide semiconductor film in a channel formation region, and a method for manufacturing the same. For example, it relates to an electronic device equipped with an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element as a component.

[0002] In this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and all electro-optical devices, semiconductor circuits, and electronic devices are semiconductor devices.

Background Art

[0003] In recent years, active matrix display devices (liquid crystal display devices, light-emitting display devices, and electrophoretic display devices) provided with switching elements composed of thin film transistors (TFTs) for each display pixel arranged in a matrix have been actively developed. An active matrix display device has a switching element provided for each pixel (or one dot), and is advantageous because it can be driven at a low voltage when the pixel density is increased compared to the simple matrix method.

[0004] In addition, techniques for manufacturing thin film transistors (TFTs) using an oxide semiconductor film in a channel formation region and applying them to electronic devices and optical devices have attracted attention. For example, TFTs using ZnO as an oxide semiconductor film, and TFTs using InGaO3(ZnO) are mentioned. Techniques for forming TFTs formed using these oxide semiconductor films on a light-transmissive substrate and using them for switching elements of image display devices and the like are disclosed in Patent Document 1, Patent Document 2, etc. m ​​​​​​​​It is disclosed.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] For thin film transistors using an oxide semiconductor film in the channel formation region, high operating speed, relatively simple manufacturing processes, and sufficient reliability are required. When forming a thin film transistor, a low-resistance metal material is used for the source electrode layer and the drain electrode layer. In particular, when manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. On the other hand, in a thin film transistor structure in which the source electrode layer and the drain electrode layer made of a metal material with a low electrical resistance value are in direct contact with the oxide semiconductor film, there is a risk that the contact resistance will increase. One of the factors causing the increase in contact resistance is considered to be the formation of a Schottky junction at the contact surface between the source electrode layer and the drain electrode layer and the oxide semiconductor film.

[0007] In addition, a capacitance is formed at the portion where the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) deteriorate, which may prevent the high-speed operation of the thin film transistor. When manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. When manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. When forming a thin film transistor, a low-resistance metal material is used for the source electrode layer and the drain electrode layer. In particular, when manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. On the other hand, in a thin film transistor structure in which the source electrode layer and the drain electrode layer made of a metal material with a low electrical resistance value are in direct contact with the oxide semiconductor film, there is a risk that the contact resistance will increase. One of the factors causing the increase in contact resistance is considered to be the formation of a Schottky junction at the contact surface between the source electrode layer and the drain electrode layer and the oxide semiconductor film. One of the factors causing the increase in contact resistance is considered to be the formation of a Schottky junction at the contact surface between the source electrode layer and the drain electrode layer and the oxide semiconductor film.

[0008] In addition, a capacitance is formed at the portion where the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) deteriorate, which may prevent the high-speed operation of the thin film transistor. In addition, a capacitance is formed at the portion where the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) deteriorate, which may prevent the high-speed operation of the thin film transistor. In addition, a capacitance is formed at the portion where the source electrode layer and the drain electrode layer are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) deteriorate, which may prevent the high-speed operation of the thin film transistor.

[0009] One aspect of the present invention is an oxide containing indium (In), gallium (Ga), and zinc (Zn). In a thin film transistor using an oxide semiconductor film, the contact between the source electrode and the oxide semiconductor layer Thin-film transistor with reduced drain resistance and contact resistance between drain electrode and oxide semiconductor layer One of the objectives of the present invention is to provide a stator and a method for manufacturing the same.

[0010] In addition, the operating characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn One of the challenges is to improve the reliability of the system.

[0011] In addition, the electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn In particular, in liquid crystal display devices, it is necessary to reduce the variation in individual If there is a large variation between elements, the display will be uneven due to the variation in the TFT characteristics. There is a risk that this may happen.

[0012] In addition, in a display device having a light-emitting element, the pixel electrodes are arranged so that a constant current flows through them. The on-chip TFT (which supplies current to the driver circuit or the light-emitting element arranged in the pixel) Current (I on If the variation in the brightness of the display screen is large, the brightness of the display screen may vary. As described above, one aspect of the present invention has an object to solve at least one of the above problems. do. [Means for solving the problem]

[0013] One embodiment of the present invention is a semiconductor layer using an oxide semiconductor layer containing In, Ga, and Zn. An inverted staggered type (both The gist is to include a thin film transistor having a Tom gate structure.

[0014] In this specification, a semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an "IGZO semiconductor layer". A source electrode layer and a drain electrode layer and the IGZO semiconductor layer must have an ohmic contact, and further, it is desirable to reduce the contact resistance as much as possible. Similarly, a drain electrode and the IGZO semiconductor layer require an ohmic contact, and further, it is desirable to reduce the contact resistance as much as possible.

[0015] Therefore, an ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element that imparts an n-type. As the impurity element, for example, magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. This buffer layer functions as an n-layer and can also be called a drain region or a source region.

[0016]

[0017]

[0018] + ​​​​​​​​​​​​​​

[0019] One form of the semiconductor device of the present invention includes a gate electrode, an insulating film covering the gate electrode, and an IGZO semiconductor layer on the gate electrode via a gate insulating film, a channel protection layer in a region overlapping with the channel formation region of the IGZO semiconductor layer, a source electrode layer and a drain electrode layer on the IGZO semiconductor layer and a thin film transistor having a buffer layer formed between the semiconductor layer and the source electrode layer and the drain electrode layer, and the carrier concentration of the buffer layer is higher than that of the IGZO semiconductor layer and the IGZO semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer. In the above configuration, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. continue.

[0020] oxide semiconductor film (IGZO film) containing In, Ga, and Zn has the characteristic that the hole mobility increases as the carrier concentration increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 29. In one aspect of the present invention, the carrier concentration range of the IGZO film suitable as the channel of the semiconductor layer (channel concentration range 1) is less than 1×10 atoms / cm - layer and functions as.

[0021] (more preferably 1×10 or more), and the carrier concentration range of the IGZO film suitable as the buffer layer (buffer layer concentration range 2) is 1×10 atoms / cm or more (1×10 17 atoms / cm 3 less (more preferably 1×10 11 atoms / cm 3 or more), and the carrier concentration range of the IGZO film suitable as the buffer layer (buffer layer concentration range 2) is 1×10 18 atoms / cm 3 or more (1×10 22 at oms / cm 3 is preferably as follows. The carrier concentration of the IGZO film is used as a semiconductor layer In the case of, it is the value at room temperature without applying source, drain, and gate voltages.

[0022] If the carrier concentration range of the IGZO film for the channel exceeds the above range (channel concentration range 1) there is a risk of becoming normally-on as a thin film transistor.

[0023] Note that the carrier concentration and hole mobility of the IGZO film can be obtained by Hall effect measurement. As an example of a Hall effect measuring instrument, the resistivity / hole measurement system ResiTest8 310 (manufactured by Toyo Technica) can be mentioned. The resistivity / hole measurement system Resi Test8310 can perform AC (alternating current) Hall measurement in which the direction and magnitude of the magnetic field are changed at a constant period, and only the Hall electromotive force appearing in the sample is detected synchronously. It is possible to detect the Hall electromotive force even for a material with a small mobility and a high resistivity. For materials with small mobility and high resistivity, the Hall electromotive force can be detected.

[0024] In the above configuration, it is preferable that the source electrode layer and the drain electrode layer contain titanium. For example using a multilayer film in which a titanium film, an aluminum film, and a titanium film are laminated has low resistance and it is difficult for hillocks to occur in the aluminum film.

[0025] Since the structure of the thin film transistor according to one aspect of the present invention is a structure provided with a channel protection layer, the region on the side opposite to the surface in contact with the gate insulating film of the IGZO semiconductor layer, the so-called back channel, can be protected from damage during the process (film reduction due to plasma or etching agent during etching, oxidation, etc.) and the reliability of the semiconductor device can be improved.

[0026] One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, and the gate electrode form a gate insulating film on the layer, form an IGZO semiconductor layer on the gate insulating film, and form a channel protection layer in a region overlapping the channel formation region on the IGZO semiconductor layer layer, form a pair of buffer layers having an n-type conductivity type on the IGZO semiconductor layer, form a source electrode layer and a drain electrode layer on the buffer layer, and the pair of buffer layers having an n-type conductivity type are formed using an oxide semiconductor layer containing In, Ga, and Z n, and the carrier concentration of the buffer layer is higher than the carrier concentration of the IGZO semiconductor layer and the IGZO semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. In addition, continuously forming the gate insulating film, the semiconductor film, and the channel protection layer without exposing them to the atmosphere not only improves productivity but also forms a laminated interface free from contamination by atmospheric components such as water vapor, impurity elements floating in the atmosphere, and dust. Therefore, variations in thin film transistor characteristics can be reduced.

[0027] In other words, continuously forming the gate insulating film, the oxide semiconductor film containing In, Ga, and Zn serving as the semiconductor film, and the insulating film serving as the channel protection layer without exposing them to the atmosphere not only improves productivity but also forms a laminated interface free from contamination by atmospheric components such as water vapor, impurity elements floating in the atmosphere, and dust. Therefore, variations in thin film transistor characteristics can be reduced. In this specification, continuous film formation means that during a series of processes from the first film formation process performed by sputtering to the second

[0028] film formation process performed by sputtering, the atmosphere in which the substrate to be processed is placed is a contaminated atmosphere such as air. film formation process, not only the productivity is improved, but also a laminated interface free from contamination by atmospheric components such as water vapor, impurity elements floating in the atmosphere, and dust can be formed. Therefore, variations in thin film transistor characteristics can be reduced. film formation process, not only the productivity is improved, but also a laminated interface free from contamination by atmospheric components such as water vapor, impurity elements floating in the atmosphere, and dust can be formed. Therefore, variations in thin film transistor characteristics can be reduced.

[0029] In this specification, continuous film formation means that during a series of processes from the first film formation process performed by sputtering to the second film formation process performed by sputtering, the atmosphere in which the substrate to be processed is placed is a contaminated atmosphere such as air. It means that it is always controlled in a vacuum or an inert gas atmosphere (nitrogen atmosphere or rare gas atmosphere) without being exposed to the atmosphere. By performing continuous film formation, it is possible to avoid reattachment of moisture or the like to the cleaned substrate to be processed and perform film formation. Performing a series of processes from the first film formation step to the second film formation step within the same chamber is considered to be within the scope of continuous film formation in this specification. Also, when performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere and the second film formation is performed, which is also considered to be within the scope of continuous film formation in this specification.

[0030] Moreover, even if there are a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc. between the first film formation step and the second film formation step, it is considered to be within the scope of continuous film formation in this specification. However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as referred to in this specification.

[0031] In addition, the gate insulating film, semiconductor layer, and channel protection layer are formed in an oxygen atmosphere (or 90% or more oxygen, 10% or less rare gas (such as argon)), so that it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side. Also, the buffer layer having an n-type conductivity type is preferably formed in a rare gas (such as argon) atmosphere. When performing a series of processes from the first film formation step to the second film formation step in different chambers, after completing the first film formation step, the substrate is transported between the chambers without being exposed to the atmosphere and the second film formation is performed, which is also considered to be within the scope of continuous film formation in this specification. Moreover, even if there are a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc. between the first film formation step and the second film formation step, it is considered to be within the scope of continuous film formation in this specification.

[0032] However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as referred to in this specification. In addition, the gate insulating film, semiconductor layer, and channel protection layer are formed in an oxygen atmosphere (or 90% or more oxygen, 10% or less rare gas (such as argon)), so that it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side. Also, the buffer layer having an n-type conductivity type is preferably formed in a rare gas (such as argon) atmosphere. Moreover, even if there are a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc. between the first film formation step and the second film formation step, it is considered to be within the scope of continuous film formation in this specification.

[0033] However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as referred to in this specification. In addition, the gate insulating film, semiconductor layer, and channel protection layer are formed in an oxygen atmosphere (or 90% or more oxygen, 10% or less rare gas (such as argon)), so that it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side. Also, the buffer layer having an n-type conductivity type is preferably formed in a rare gas (such as argon) atmosphere. Moreover, even if there are a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc. between the first film formation step and the second film formation step, it is considered to be within the scope of continuous film formation in this specification.

[0034] In addition, the gate insulating film, semiconductor layer, and channel protection layer are formed in an oxygen atmosphere (or 90% or more oxygen, 10% or less rare gas (such as argon)), so that it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side. Also, the buffer layer having an n-type conductivity type is preferably formed in a rare gas (such as argon) atmosphere. Moreover, even if there are a substrate transfer step, an alignment step, a slow cooling step, or a step of heating or cooling the substrate to the temperature required for the second step, etc. between the first film formation step and the second film formation step, it is considered to be within the scope of continuous film formation in this specification. However, if a process using a liquid such as a cleaning process, wet etching, or resist formation is between the first film formation step and the second film formation step, it is not considered to be within the scope of continuous film formation as referred to in this specification. In addition, the gate insulating film, semiconductor layer, and channel protection layer are formed in an oxygen atmosphere (or 90% or more oxygen, 10% or less rare gas (such as argon)), so that it is possible to reduce a decrease in reliability due to deterioration and a shift of thin film transistor characteristics to the normal-on side. Also, the buffer layer having an n-type conductivity type is preferably formed in a rare gas (such as argon) atmosphere. Yes.

[0035] One embodiment of the method for manufacturing a semiconductor device of the present invention is to form a gate electrode layer on a substrate, and the gate electrode form a gate insulating film on the layer, form an IGZO semiconductor layer on the gate insulating film, and form a channel protection layer in a region overlapping the channel formation region on the IGZO semiconductor layer. form a pair of buffer layers having an n-type conductivity type on the IGZO semiconductor layer, form a source electrode layer and a drain electrode layer on the buffer layer. The pair of buffer layers having an n-type conductivity type are formed using an oxide semiconductor layer containing In, Ga, and Zn n, and the carrier concentration of the buffer layer is higher than the carrier concentration of the IGZO semiconductor layer. The IGZO semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. The gate insulating film, the semiconductor layer, and the channel protection layer are formed continuously without being exposed to the air.

[0036] One aspect of the semiconductor device of the present invention is a thin film transistor including a gate electrode, a gate insulating film covering the gate electrode, a semiconductor layer on the gate electrode through the gate insulating film, a channel protection layer in a region overlapping the channel formation region of the semiconductor layer, a source electrode layer and a drain electrode layer on the semiconductor layer, and a buffer layer formed between the semiconductor layer and the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are made of an oxide semiconductor containing indium, gallium, and zinc

[0037] Also, the semiconductor device is one in which the buffer layer contains an n-type impurity.

[0038] Also, the carrier concentration of the semiconductor layer is 1×10 17atoms / cm 3 is less than, and the buffer layer has a carrier concentration of 1×10 18 atoms / cm 3 or more, which is a semiconductor device.

[0039] Also, a semiconductor device having a second buffer layer with a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer is provided between the semiconductor layer and the buffer layer. is a semiconductor device.

[0040] Also, a semiconductor device in which the source electrode layer and the drain electrode layer contain titanium.

[0041] Another aspect of the disclosed invention is to form a gate electrode layer on a substrate, form a gate insulating film on the gate electrode layer, form a semiconductor layer on the gate insulating film, form a channel protection layer in a region overlapping the channel formation region on the semiconductor layer, form a pair of buffer layers having an n-type conductivity type on the semiconductor layer, form a source electrode layer and a drain electrode layer on the buffer layer, and the semiconductor layer and the buffer layer having an n type conductivity type are formed using an oxide semiconductor layer containing In, Ga, and Zn, and the carrier concentration of the buffer layer is higher than that of the semiconductor layer, and a method of manufacturing a semiconductor device in which the semiconductor layer and the source electrode layer and the drain electrode layer are electrically connected through the buffer layer. type conductivity type buffer layer is formed using an oxide semiconductor layer containing In, Ga, and Zn, and the carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer and the source electrode layer and the drain electrode layer are electrically connected through the buffer layer. is a method of manufacturing a semiconductor device.

[0042] Also, form a gate electrode layer on a substrate, form a gate insulating film on the gate electrode layer, form a semiconductor layer on the gate insulating film, form a channel protection layer in a region overlapping the channel formation region on the semiconductor layer, form a buffer layer having an n-type conductivity type on the semiconductor layer, form a source electrode layer and a drain electrode layer on the buffer layer, and the semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium, gallium ium, and zinc, and the carrier concentration of the buffer layer is semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium, gallium ium, and zinc, and the carrier concentration of the buffer layer is semiconductor Higher than the carrier concentration of the layer, the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through a buffer layer, and a method for manufacturing a semiconductor device in which a gate insulating film, a semiconductor layer, and a channel protection layer are continuously formed without being exposed to the atmosphere. It is a method for manufacturing a semiconductor device.

[0043] Also, a method for manufacturing a semiconductor device in which a gate insulating film, a semiconductor layer, and a channel protection layer are formed by a sputtering method. It is a method for manufacturing a semiconductor device.

[0044] Also, a method for manufacturing a semiconductor device in which a gate insulating film, a semiconductor layer, and a channel protection layer are formed in an oxygen atmosphere. It is a method for manufacturing a semiconductor device.

[0045] Also, a method for manufacturing a semiconductor device in which a buffer layer is formed in a rare gas atmosphere.

[0046] Also, the carrier concentration of the semiconductor layer is 1×10 17 atoms / cm 3 less than, and the carrier concentration of the buffer layer is 1×10 18 atoms / cm 3 or more. There is a method for manufacturing a semiconductor device. It is.

[0047] Also, a method for manufacturing a semiconductor device in which a buffer layer is formed containing magnesium, aluminum, or titanium. It is a method for manufacturing a semiconductor device.

Effect of the Invention

[0048] According to one aspect of the present invention, a thin film transistor with low photocurrent, small parasitic capacitance, and high on / off ratio can be obtained, and a thin film transistor with good dynamic characteristics (f characteristics) can be manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. manufactured. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided. provided.

Brief Description of the Drawings

[0049]

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Embodiments for Carrying Out the Invention

[0050] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are commonly used for the same parts or parts having the same functions in different drawings, and the repeated description thereof will be omitted.

[0051] (Embodiment 1)(Embodiment 1) In this embodiment, a thin-film transistor and its manufacturing process will be described with reference to FIGS. 1 and 2.

[0052] ​FIG. 1 shows a thin film transistor with a bottom gate structure according to the present embodiment. FIG. 1(A) is a plan view, and FIG. 1(B) is a cross-sectional view taken along the line A1-A2 in FIG. 1(A). The thin film transistor shown in FIG. 1 has a gate electrode 101 formed on a substrate 100, a gate insulating film 102 formed on the gate electrode 1 01, a semiconductor layer 103 made of an amorphous oxide semiconductor that functions as a channel formation region formed on the gate electrode 101 via the gate insulating film 102 , a channel protection layer 106 formed in a region overlapping the channel formation region of the semiconductor layer 103 made of an amorphous oxide semiconductor, buffer layers 104a and 104b formed on the semiconductor layer 103 made of an amorphous oxide semiconductor, and a source electrode layer and a drain electrode layer (105a and 105b) formed in contact with the buffer layers 104a and 104b . . . .

[0053] An oxide semiconductor containing In, Ga, and Zn is used as the semiconductor layer 103, and a buffer layer 104a, 104b having a higher carrier concentration than the semiconductor layer 103 is intentionally provided between the source electrode layer and the drain electrode layer (105a, 105b) and the semiconductor layer 103 to form an ohmic contact. . . .

[0054] The buffer layers 104a, 104b are formed of an oxide semiconductor containing In, Ga, and Zn having an n-type conductivity type. Further, an impurity element for imparting an n-type to the buffer layer may be included. . . As the impurity element, for example, magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, etc. can be used. Magnesium, aluminum, titanium, etc. may be included in the buffer layer. . . and has an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer 103 can be maintained within an optimal range by heat treatment after film formation

[0055] The buffer layers 104a and 104b function as an n + layer and can also be called the drain region or the source region

[0056] The manufacturing method of the thin film transistor shown in FIG. 1 will be described with reference to FIG. 2. First, a gate electrode 101, a gate insulating film 102, a semiconductor film 133, and a channel protection layer 106 are formed on a substrate 100 (see FIG. 2(A)). (see FIG. 2(A)).

[0057] The substrate 100 can be an alkali-free glass substrate manufactured by a fusion method or a float method, such as barium borosilicate glass, aluminoborosilicate glass, or aluminum nosilicate glass, a ceramic substrate, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process, etc. Further, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless steel alloy may be applied. When the substrate 100 is mother glass, the size of the substrate is the first generation (320 mm × 400 mm), the second generation (400 mm × 500 mm), the third generation (55 0 mm × 650 mm), the fourth generation (680 mm × 880 mm, or 730 mm × 920 mm), the fifth generation (1000 mm × 1200 mm or 1100 mm × 1250 mm), the sixth generation 1500 mm × 1800 mm), the seventh generation (1900 mm × 2200 mm), the eighth generation (2160 mm × 2460 mm), the ninth generation (2400 mm × 2800 mm, 24 50 mm × 3050 mm), the tenth generation (2950 mm × 3400 mm), etc. can be used (see FIG. 2(A)). (see FIG. 2(A)). 8 generations (2160 mm × 2460 mm), the ninth generation (2400 mm × 2800 mm, 24 50 mm × 3050 mm), the tenth generation (2950 mm × 3400 mm), etc. can be used (see FIG. 2(A)).

[0058] ​​ An insulating film may also be formed as an underlayer film on the substrate 100. As the underlayer film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxynitride film may be formed by using a CVD method, a sputtering method, or the like, either as a single layer or as a laminate. An insulating film may also be formed as an underlayer film on the substrate 100. As the underlayer film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxynitride film may be formed by using a CVD method, a sputtering method, or the like, either as a single layer or as a laminate. An insulating film may also be formed as an underlayer film on the substrate 100. As the underlayer film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon oxynitride film may be formed by using a CVD method, a sputtering method, or the like, either as a single layer or as a laminate.

[0059] The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, etc. are applicable. A preferred example of the gate electrode is formed by aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high melting point metals such as titanium, molybdenum, and chromium are applicable. The barrier metal is preferably provided to prevent hillock formation and oxidation of aluminum. The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, etc. are applicable. A preferred example of the gate electrode is formed by aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high melting point metals such as titanium, molybdenum, and chromium are applicable. The barrier metal is preferably provided to prevent hillock formation and oxidation of aluminum. The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, etc. are applicable. A preferred example of the gate electrode is formed by aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high melting point metals such as titanium, molybdenum, and chromium are applicable. The barrier metal is preferably provided to prevent hillock formation and oxidation of aluminum. The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, etc. are applicable. A preferred example of the gate electrode is formed by aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high melting point metals such as titanium, molybdenum, and chromium are applicable. The barrier metal is preferably provided to prevent hillock formation and oxidation of aluminum. The gate electrode 101 is formed of a metal material. As the metal material, aluminum, chromium, titanium, tantalum, molybdenum, copper, etc. are applicable. A preferred example of the gate electrode is formed by aluminum or a laminated structure of aluminum and a barrier metal. As the barrier metal, high melting point metals such as titanium, molybdenum, and chromium are applicable. The barrier metal is preferably provided to prevent hillock formation and oxidation of aluminum.

[0060] The gate electrode is formed with a thickness of 50 nm or more and 300 nm or less. By setting the thickness of the gate electrode to 300 nm or less, it is possible to prevent step breakage of the semiconductor film and wiring formed later. Also, by setting the thickness of the gate electrode to 150 nm or more, it is possible to reduce the resistance of the gate electrode and enable large area formation. The gate electrode is formed with a thickness of 50 nm or more and 300 nm or less. By setting the thickness of the gate electrode to 300 nm or less, it is possible to prevent step breakage of the semiconductor film and wiring formed later. Also, by setting the thickness of the gate electrode to 150 nm or more, it is possible to reduce the resistance of the gate electrode and enable large area formation. The gate electrode is formed with a thickness of 50 nm or more and 300 nm or less. By setting the thickness of the gate electrode to 300 nm or less, it is possible to prevent step breakage of the semiconductor film and wiring formed later. Also, by setting the thickness of the gate electrode to 150 nm or more, it is possible to reduce the resistance of the gate electrode and enable large area formation. The gate electrode is formed with a thickness of 50 nm or more and 300 nm or less. By setting the thickness of the gate electrode to 300 nm or less, it is possible to prevent step breakage of the semiconductor film and wiring formed later. Also, by setting the thickness of the gate electrode to 150 nm or more, it is possible to reduce the resistance of the gate electrode and enable large area formation.

[0061] Since a semiconductor film and wiring are formed on the gate electrode 101, it is desirable to process the end portion into a tapered shape to prevent step breakage. Also, although not shown, wiring and capacitive wiring connected to the gate electrode can be formed simultaneously in this process. Since a semiconductor film and wiring are formed on the gate electrode 101, it is desirable to process the end portion into a tapered shape to prevent step breakage. Also, although not shown, wiring and capacitive wiring connected to the gate electrode can be formed simultaneously in this process. Since a semiconductor film and wiring are formed on the gate electrode 101, it is desirable to process the end portion into a tapered shape to prevent step breakage. Also, although not shown, wiring and capacitive wiring connected to the gate electrode can be formed simultaneously in this process.

[0062] The gate electrode 101 can be formed by a sputtering method, a CVD method, a plating method, a printing method, or by using a conductive nanopaste such as silver, gold, or copper. Also, the gate electrode can be formed by ejecting and firing by an inkjet method. The gate electrode 101 can be formed by a sputtering method, a CVD method, a plating method, a printing method, or by using a conductive nanopaste such as silver, gold, or copper. Also, the gate electrode can be formed by ejecting and firing by an inkjet method. The gate electrode 101 can be formed by a sputtering method, a CVD method, a plating method, a printing method, or by using a conductive nanopaste such as silver, gold, or copper. Also, the gate electrode can be formed by ejecting and firing by an inkjet method.

[0063] Here, an aluminum film and a molybdenum film are laminated as a conductive film on a substrate as shown in Fig. 2(A) by sputtering to form a film, and using the resist mask formed by using the first photomask in the present embodiment, the conductive film formed on the substrate is etched to form the gate electrode 101.

[0064] In the present embodiment, an example in which a multilayer film in which two insulating films are laminated is used as the gate insulating film 102 is shown. The first gate insulating film 102a and the second gate insulating film 102b can each be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film having a thickness of 50 to 150 nm. Here, a form in which a silicon nitride film or a silicon oxynitride film is formed as the first gate insulating film 102a, and a silicon oxide film or a silicon oxynitride film is formed as the second gate insulating film 102b and laminated is shown. Note that the gate insulating film may not be made into two layers, but may be formed of a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film, or a three-layer gate insulating film may be formed. By forming the first gate insulating film 102a using a silicon nitride film or a silicon oxynitride film, the adhesion between the substrate and the first gate insulating film 102a is increased, and when a glass substrate is used as the substrate, it is possible to prevent impurities from the substrate from diffusing into the oxide semiconductor film, and further, it is possible to prevent oxidation of the gate electrode 101. That is, peeling of the film can be prevented,

[0065] and the electrical characteristics of the thin film transistor formed later can be improved. Also, the first gate insulating film 102a and the second gate insulating film 102b each have a thickness of 50 nm or more ​​​​​​This is preferable because it can cover the unevenness of the gate electrode 101.

[0066] Here, the silicon oxynitride film has a composition with a higher oxygen content than nitrogen and, in terms of the concentration range, contains oxygen in the range of 55 to 65 atomic %, nitrogen in the range of 1 to 20 atomic %, Si in the range of 25 to 35 atomic %, and hydrogen in the range of 0.1 to 10 atomic %. Also, the silicon nitride oxide film has a composition with a higher nitrogen content than oxygen, and, in terms of the concentration range contains oxygen in the range of 15 to 30 atomic %, nitrogen in the range of 20 to 35 atomic %, Si in the range of 25 to 35 atomic %, and hydrogen in the range of 15 to 25 atomic %.

[0067] Further, as the second gate insulating film 102b in contact with the semiconductor layer 103, for example, silicon oxide, aluminum oxide, magnesium oxide, aluminum nitride, yttrium oxide, hafnium oxide can be used.

[0068] The first gate insulating film 102a and the second gate insulating film 102b can each be formed using a CVD method, a sputtering method, or the like. Here, a silicon nitride film is formed as the first gate insulating film 102a by a plasma CVD method.

[0069] In particular, it is desirable that the second gate insulating film 102b in contact with the semiconductor film 133 and the semiconductor film 133 are continuously formed. By continuously forming the film, a laminated interface free from contamination by atmospheric components such as water vapor, impurity elements floating in the air, and dust can be formed, so that the variation in thin film transistor characteristics can be reduced.

[0070] In an active matrix type display device, the electrical properties of the thin film transistors constituting the circuit The characteristics are important, and these electrical characteristics affect the performance of the display device. In particular, for thin film transistors among their electrical characteristics, the threshold voltage (Vth) is important. Even if the field effect mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, it becomes difficult to control as a circuit and. In the case of a thin film transistor with a high threshold voltage value and a large absolute value of the threshold voltage, in a state where the driving voltage is low, the switching function as a thin film transistor cannot be achieved, and there is a risk of becoming a load. Also, if the threshold voltage value is negative, a current flows between the source electrode and the drain electrode even when the gate voltage is 0V, which is likely to become a so-called normally on state.

[0071] In the case of an n-channel type thin film transistor, it is desirable that a channel is formed and a drain current flows only when a positive voltage is applied to the gate voltage. A transistor in which a channel is not formed unless the driving voltage is increased, or a transistor in which a channel is formed and a drain current flows even in a negative voltage state is not suitable as a thin film transistor used in a circuit. Therefore, it is desirable that a channel is formed with a positive threshold voltage as close as possible to 0V for a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn. The threshold voltage of the thin film transistor is considered to be greatly affected by the interface of the semiconductor layer, that is, the interface between the semiconductor layer and the gate insulating film. Therefore, by forming these interfaces in a clean state, the electrical characteristics of the thin film transistor can be improved, and the complication of the manufacturing process can be prevented.

[0072] A thin film transistor having both mass productivity and high performance can be realized.

[0073] ​​​​ In particular, if moisture is present at the interface between the oxide semiconductor layer and the gate insulating film, the electrical conductivity of the thin film transistor may deteriorate. Problems such as deterioration of electrical characteristics, variation in threshold voltage, and tendency to become normally on By successively forming the oxide semiconductor layer and the gate insulating film, it is possible to prevent such hydrogen compounds from being generated. can be eliminated.

[0074] Therefore, the gate insulating film and the oxide semiconductor film can be formed by sputtering without exposure to the air. By continuously forming the films under reduced pressure, the interface is excellent, the leakage current is low, and the current driving capability is high. Thus, a high-power thin film transistor can be realized.

[0075] The gate insulating film and the oxide semiconductor film containing In, Ga, and Zn are grown under an oxygen atmosphere (or It is preferable to form the film using an atmosphere of 90% or more oxygen and 10% or less rare gas (such as argon).

[0076] By using the sputtering method to continuously form films in this way, the productivity is high and the reliability of the thin film interface is high. In addition, the gate insulating film and the semiconductor layer are formed in an oxygen atmosphere, and the Doing so may result in a decrease in reliability due to degradation, or the thin-film transistor may become normally on. This can reduce the risk of injury.

[0077] In addition, the insulating film that will become the channel protection layer 106 is also formed continuously following the formation of the semiconductor film. By forming the films successively, the surface of the semiconductor film that contacts the gate insulating film is opposite to the surface of the semiconductor film that contacts the gate insulating film. The opposite area, the so-called back channel, contains atmospheric components such as water vapor and impurity elements floating in the air. This allows the formation of a lamination interface that is free from contamination by metals or dust, improving the thin-film transistor characteristics. The variation can be reduced.

[0078] As a method of forming a film continuously, a multi-chamber type sputtering device having a plurality of film formation chambers, a sputtering device having a plurality of targets, or a pulse laser deposition (P LD) device may be used.

[0079] When forming silicon oxide as an insulating film, silicon oxide (synthetic quartz) or single crystal silicon is used as a target, and a high-frequency sputtering method or a reactive sputtering method can be used to form a film.

[0080] Here, a multi-chamber type sputtering device equipped with a single crystal silicon target and a target for a semiconductor film is used to form a silicon oxide film as the second gate insulating film 102 in contact with the semiconductor film, and the semiconductor film and the silicon oxide film serving as a channel protection layer are continuously formed without exposing them to the atmosphere. b,

[0081] The semiconductor layer 103 is formed of an amorphous oxide semiconductor film. As the amorphous oxide semiconductor film, a composite oxide of elements selected from indium, gallium, aluminum, zinc, and tin can be used. For example, indium oxide containing zinc oxide (IZO), In, Ga, and an oxide containing Zn (IGZO), or an oxide composed of zinc oxide and tin oxide (ZTO) can be cited as an example.

[0082] In the case of an oxide composed of indium oxide, gallium oxide, and zinc oxide, the degree of freedom of the composition ratio of metal elements is high, and it functions as a semiconductor layer at a wide range of mixing ratios. For example, indium oxide containing 10 wt% of zinc oxide , a material in which indium oxide, gallium oxide, and zinc oxide are mixed in equimolar amounts, or the abundance ratio of metal elements in the film is In:Ga:Zn = 2.2:2.2:1.0 ​​​​Oxides present in a ratio of can be cited as an example.

[0083] The semiconductor film 133 made of an oxide semiconductor used for the semiconductor layer 103 may be formed to have a thickness of 2 nm or more and 200 nm or less, preferably 20 nm or more and 150 nm or less. Also, as the oxygen deficiency in the film increases, the carrier concentration increases and the thin film transistor characteristics are impaired. Therefore, it is made to have a composition that suppresses oxygen deficiency.

[0084] The semiconductor film 133 made of an amorphous oxide semiconductor can be formed by a reactive sputtering method, a pulsed laser deposition method (PLD method), or a sol-gel method. Among the vapor phase methods, the PLD method is suitable in terms of easily controlling the composition of the material system, and the sputtering method is suitable in terms of mass productivity as described above. Here, as an example of the method for forming the semiconductor film 133, a method using an oxide (IGZO) containing In, Ga, and Zn will be described.

[0085] Indium oxide (In2O3), gallium oxide (Ga2O3), and zinc oxide (ZnO) are each mixed in equimolar amounts and sintered to obtain an 8-inch diameter target. Using this target, a substrate is placed at a position 17 0 mm away, and DC (Direct Current ) sputtering is performed at an output of 500 W to form the semiconductor film 133. The pressure in the chamber is 0.4 Pa, and the gas composition ratio is such that Ar / O2 is 10 / 5 sccm, and a film of 50 nm is formed. The oxygen partial pressure during film formation is set higher than the film formation conditions for a transparent conductive film such as indium tin oxide (ITO), and it is desirable to control the oxygen concentration in the film formation atmosphere to suppress oxygen deficiency. Also, it is preferable to use a pulsed DC power supply because dust can be reduced and the film thickness distribution of the semiconductor layer becomes uniform.

[0086] Note that the semiconductor layer 103 may be subjected to plasma treatment. By performing the plasma treatment, the damage caused by the etching of the semiconductor layer 103 can be recovered. The plasma treatment is preferably performed in an atmosphere of O 2, N2O, preferably N2 containing oxygen, He, Ar. Also, it may be performed in an atmosphere in which Cl2 and CF4 are added to the above atmosphere. Note that the plasma treatment is preferably performed without bias.

[0087] In this embodiment, a multi-chamber type sputtering apparatus equipped with a single crystal silicon target together with a target for an oxide semiconductor film is used, and the second gate insulating film 102b formed in the previous process is not exposed to the atmosphere, and a semiconductor film is formed thereon. The formed semiconductor film is not continuously exposed to the atmosphere, and an insulating film that becomes the channel protection layer 106 is formed on the semiconductor film in the next process. The channel protection layer 106 is formed of an insulating film in a region overlapping with the channel formation region of the semiconductor layer 103 as shown in FIG. 2(A). The insulating film functioning as the channel protection layer 106 can be made of an inorganic material ( silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, etc.). Also,

[0088] a photosensitive or non-photosensitive organic material (organic resin material) (polyimide, acrylic, polyamide , polyimide amide, resist, benzocyclobutene, etc.), or a film composed of a plurality of types, or a laminate of these films, etc. can be used. Also, siloxane may be used. The insulating film that becomes the channel protection layer 106 can be formed by a vapor deposition method such as plasma CVD method or thermal CVD method or sputtering method. Also, a coating method such as spin coating method which is a wet method can be used.

[0089] The insulating film that becomes the channel protection layer 106 can be formed by a vapor deposition method such as plasma CVD method or thermal CVD method or sputtering method. Also, a coating method such as spin coating method which is a wet method can be It can be used. Also, it may be selectively formed by a droplet discharge method, a printing method (such as a screen printing or an offset printing method for forming a pattern), or the like.

[0090] Here, a multi-chamber type sputtering apparatus equipped with a single crystal silicon target and a target for an oxide semiconductor film is used to form a silicon oxide film to be a channel protection layer 106 without exposing the semiconductor film 133 made of an oxide semiconductor formed in the previous process to the atmosphere.

[0091] Next, using a resist mask formed using the second photomask in the present embodiment, the silicon oxide film formed on the semiconductor film 133 is selectively etched to form a channel protection layer 106 as shown in Fig. 2(A).

[0092] Next, using a resist mask formed using the third photomask in the present embodiment, the semiconductor film 133 made of an oxide semiconductor formed on the gate insulating film is etched to form a semiconductor layer 103.

[0093] Note that, as a method for etching an oxide (IGZO) film containing In, Ga, and Zn, a wet etching method can be used. Organic acids such as citric acid and oxalic acid can be used as an etchant. For example, an oxide (IGZO) film having a thickness of 50 nm and containing In, Ga, and Zn can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Inc.).

[0094] A pair of buffer layers 104a and 104b formed on the amorphous oxide semiconductor film are formed of an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type.

[0095] ​ In addition, a heterogeneous metal can also be doped into an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type and used. Examples of the dopant include magnesium, aluminum, titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, and the like. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. and the like. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. and the like.

[0096] In one aspect of the present invention, the carrier concentration range (channel concentration range 1) of the semiconductor layer is less than 1× 10 17 atoms / cm 3 (more preferably 1×10 11 atoms / cm 3 or more ), and the carrier concentration range (buffer layer concentration range 2) of the IGZO film suitable as the buffer layer is , 1×10 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 or less). It is preferable to do so. Further, a second buffer layer that functions as an n layer having a higher carrier concentration than the semiconductor layer and a lower carrier concentration than the buffer layer may be provided between the semiconductor layer and the buffer layer. - layer having a higher carrier concentration than the semiconductor layer and a lower carrier concentration than the buffer layer may be provided between the semiconductor layer and the buffer layer. Yes.

[0097] Since the carrier concentration of the buffer layers 104a and 104b is higher than that of the semiconductor layer made of an oxide (I GZO) containing In, Ga, and Zn and is superior in conductivity, the contact resistance is reduced compared to the case where the source electrode layer and the drain electrode layers (105a, 105b) are directly joined to the semiconductor layer 103. In addition, the source electrode layer and the drain electrode layer (105a, 105b) and the semiconductor By sandwiching the buffer layers 104a and 104b at the bonding interface of the dielectric layer 103, the This can reduce the electric field that occurs during

[0098] In order to ensure that the buffer layers 104a and 104b cover the semiconductor layer 103, As shown in FIG. 2B, the buffer layer is patterned so as to overlap a part of the channel protection layer 106. You may do so.

[0099] The buffer layers 104a and 104b are made of In, Ga, and Zn having n-type conductivity. The oxide semiconductor film is preferably formed to a thickness of 2 nm to 100 nm.

[0100] The buffer layers 104a and 104b are made of In, Ga, and Zn having n-type conductivity. The oxide semiconductor film is formed by sputtering or pulsed laser deposition (PLD). It is possible.

[0101] In this embodiment, a resist mask is formed using the fourth photomask. The semiconductor layer 103 and the channel protection layer 106 are formed on the semiconductor layer 103 and have an n-type conductivity. Dry etching or wet etching of an oxide semiconductor film containing In, Ga, and Zn Then, buffer layers 104a and 104b are formed by etching.

[0102] The source electrode layer and the drain electrode layer (105a, 105b) are made of a conductive film, and the gate electrode The same materials as 101 can be used, but in particular the layers in contact with the buffer layers 104a and 104b. The layer is preferably a titanium film. Specific examples of the conductive film include a titanium film alone, or It may be a laminated film of a titanium film and an aluminum film, or a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order. It may be a three-layer structure.

[0103] Here, as shown in Fig. 2(C), a three-layer laminated film composed of a titanium film, an aluminum film, and a titanium film is formed on the buffer layers 104a and 104b and the channel protection layer by a sputtering method. Next, using the resist mask formed using the fifth photomask in the present embodiment, the conductive film formed on the channel protection layer 106 is etched and separated to form the source electrode layer and the drain electrode layers (105a, 105b) as shown in Fig. 2(D). Note that the conductive film having a three-layer structure in which a titanium film, an aluminum film, and a titanium film are stacked in this order can be etched using hydrogen peroxide water or heated hydrochloric acid as an etchant.

[0104] In the present embodiment, since the formation of the buffer layers 104a and 104b and the formation of the source electrode layer and the drain electrode layers (105a, 105b) are performed separately, the overlapping length at the ends of the buffer layers 104a, 104b and the source electrode layer and the drain electrode layers (105a, 105b) can be easily controlled.

[0105] The thin film transistor using the oxide (IGZO) containing In, Ga, and Zn described in the present embodiment for the semiconductor layer 10 3 has its characteristics improved by heat-treating the formed semiconductor layer 103. Specifically, the on-current increases, and the variation in transistor characteristics decreases.

[0106] The heat treatment temperature of the semiconductor layer 103 is preferably in the range of 300°C to 400°C. Here, it is treated at 350°C for one hour. The heat treatment may be performed at any time after the formation of the semiconductor layer 103. Yes. For example, after continuously forming the insulating films that will become the semiconductor layer 103 and the channel protection layer 106 it may be possible, or it may be possible after patterning and forming the channel protection layer 106, or the buffer layer 104a, 104b made of an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type it may be possible after forming the film. Also, it may be possible after forming the conductive films that will become the source electrode layer and the drain electrode layers (105a, 10 5b), or it may be possible after forming the encapsulation film of the thin film transistor, or the heat curing treatment of the planarization film formed on the thin film transistor may be combined with the heating treatment of the semiconductor layer 103. According to the above description, the semiconductor layer 103 made of an amorphous oxide semiconductor shown in FIG. 1, the cha

[0107] nel protection layer 106, the buffer layers 104a, 104b, and the source electrode layer and the drain electrode layer (105a, 105b) are formed. (105a, 105b) are formed.

[0108] The thin film transistor of one aspect of the present invention has a stacked structure of a gate electrode, a gate insulating film, a semiconductor layer (an oxide semiconductor layer containing In, G a, and Zn), a buffer layer, a channel protection layer, a source electrode layer, and a drain electrode layer. By using a buffer layer having a higher carrier concentration than the semiconductor layer, it is possible to keep the film thickness of the semiconductor layer thin and suppress the parasitic capacitance while maintaining the film thickness of the semiconductor layer thin and suppressing the parasitic capacitance. It is possible.

[0109] The structure of the thin film transistor of one aspect of the present invention is a structure in which a channel protection layer 106 is provided Therefore, in the region on the opposite side of the surface of the oxide semiconductor film that contacts the gate insulating film 102b, the so-called back channel can be protected from damage during the process (film loss due to plasma or etching agent during etching, oxidation, etc.). Therefore, the reliability of the thin film transistor can be improved It is possible to...

[0110] Note that the channel protection layer 106 can also be said to be a channel stopper layer because it functions as an etching stopper in the etching process for forming the semiconductor layer 103. It is possible to...

[0111] Also, in this embodiment, on the channel protection layer 106, the ends of the source electrode layer and the drain electrode layer ( 105a, 105b) retreat from the ends of the buffer layers 104a, 104b and are located apart from each other. Therefore, leakage current and short - circuit between the source electrode layer and the drain electrode layer (105a, 105b) can be prevented. It is possible to...

[0112] Thus, by applying one aspect of the present invention, a thin - film transistor with low photocurrent, small parasitic capacitance, and a high on - off ratio can be obtained, and a thin - film transistor with good dynamic characteristics can be fabricated. Therefore, a semiconductor device having a thin - film transistor with high electrical characteristics and high reliability can be provided. It is possible to... It is possible to... It is possible to provide...

[0113] (Embodiment 2) In this embodiment, regarding the structure of a thin - film transistor having an n - type conductivity oxide semiconductor containing In, Ga, and Zn with a structure different from that of the above - described Embodiment 1 in the buffer layer, it will be described with reference to FIG. 3. Also, in this embodiment, the same components as those in Embodiment 1 are denoted by the same reference numerals, and detailed descriptions thereof are omitted. It is possible to...

[0114] Through the same process as in Embodiment 1, the channel protection layer 106 is formed of an insulating film in a region overlapping the channel formation region of the semiconductor layer 103 as shown in FIG. 3(A - 1). Note that in the etching process of the channel protection layer 106, the surface that joins the buffer layer 104 of the semiconductor layer 103... ... It may be etched as shown in Fig. 3(A-2). By etching the surface that joins with the buffer layer 104 of the oxide semiconductor layer, a better join with the buffer layer 104 can be obtained. That is to say, through the same processes as in Embodiment 1, a channel protection layer 106 is formed in a region overlapping with the gate electrode 101 on the semiconductor film 133. In the process of forming the channel protection layer 106, the surface of the semiconductor film 133 may be etched as shown in Fig. 3(A-2).

[0115] The surface of the semiconductor film 133 at the opening of the channel protection layer 106 is etched, and as a result, the surface has an n-type conductivity type which will be the buffer layer to be formed next, and can be joined well with the oxide semiconductor film 134 containing In, Ga, and Zn. In this embodiment, the description will continue based on the form of Fig. 3(A-2). In this embodiment, an oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed as shown in Fig. 3(B). After the oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning. The conductive film 105 is formed in the same manner as the method described in Embodiment 1. Here, as the conductive film 105, a three-layer laminated film is formed by sputtering. For example, a titanium film can be used as the source electrode layer or the drain electrode layer (105a1, 105b1), an aluminum film as (105a2, 105b2), and a titanium film as (105a3, 105b3). It may be etched as shown in Fig. 3(A-2). The surface of the semiconductor film 133 at the opening of the channel protection layer 106 is etched, and as a result, the surface has an n-type conductivity type which will be the buffer layer to be formed next, and can be joined well with the oxide semiconductor film 134 containing In, Ga, and Zn. In this embodiment, the description will continue based on the form of Fig. 3(A-2). The surface of the semiconductor film 133 at the opening of the channel protection layer 106 is etched, and as a result, the surface has an n-type conductivity type which will be the buffer layer to be formed next, and can be joined well with the oxide semiconductor film 134 containing In, Ga, and Zn. In this embodiment, the description will continue based on the form of Fig. 3(A-2). The surface of the semiconductor film 133 at the opening of the channel protection layer 106 is etched, and as a result, the surface has an n-type conductivity type which will be the buffer layer to be formed next, and can be joined well with the oxide semiconductor film 134 containing In, Ga, and Zn. In this embodiment, the description will continue based on the form of Fig. 3(A-2). In this embodiment, an oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed as shown in Fig. 3(B). After the oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning.

[0116] In this embodiment, an oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed as shown in Fig. 3(B). After the oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning. In this embodiment, an oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed as shown in Fig. 3(B). After the oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning. The oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, and then a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning. The oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, and then a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning. The oxide semiconductor film 134 containing In, Ga, and Zn with an n-type conductivity type serving as the buffer layer is formed in the same manner as the method described in Embodiment 1, and then a conductive film 105 that will become the source electrode layer and the drain electrode layers (105a, 105b) is laminated as shown in Fig. 3(C) without patterning.

[0117] The conductive film 105 is formed in the same manner as the method described in Embodiment 1. Here, as the conductive film 105, a three-layer laminated film is formed by sputtering. For example, a titanium film can be used as the source electrode layer or the drain electrode layer (105a1, 105b1), an aluminum film as (105a2, 105b2), and a titanium film as (105a3, 105b3). The conductive film 105 is formed in the same manner as the method described in Embodiment 1. Here, as the conductive film 105, a three-layer laminated film is formed by sputtering. For example, a titanium film can be used as the source electrode layer or the drain electrode layer (105a1, 105b1), an aluminum film as (105a2, 105b2), and a titanium film as (105a3, 105b3). The conductive film 105 is formed in the same manner as the method described in Embodiment 1. Here, as the conductive film 105, a three-layer laminated film is formed by sputtering. For example, a titanium film can be used as the source electrode layer or the drain electrode layer (105a1, 105b1), an aluminum film as (105a2, 105b2), and a titanium film as (105a3, 105b3). The conductive film 105 is formed in the same manner as the method described in Embodiment 1. Here, as the conductive film 105, a three-layer laminated film is formed by sputtering. For example, a titanium film can be used as the source electrode layer or the drain electrode layer (105a1, 105b1), an aluminum film as (105a2, 105b2), and a titanium film as (105a3, 105b3). 。

[0118] In other words, using the conductive film 105 in which titanium is used as the first conductive film, aluminum is used as the second conductive film, and titanium is laminated as the third conductive film, the first conductive layer ( 105a1, 105b1) made of titanium, the second conductive layer (105a2, 105 b2) made of aluminum, and the third conductive layer (105a3, 105b3) made of titanium are laminated to form the source electrode layer and the drain electrode layer (105a, 105b).

[0119] Next, using the resist mask formed using the fourth photomask in the present embodiment, the conductive film 105 is etched.

[0120] First, using the source electrode and the drain electrode (105a1, 105b1) as an etching stopper, the source electrode layer and the drain electrode layer (105a2, 105a3, 105 b2, 105b3) are etched and formed by wet etching. Using the same mask as the wet etching, the source electrode layer or the drain electrode layer (105a1, 1 05b1), the buffer layers 104a, 104b, and the semiconductor layer 103 are etched and formed by dry etching. Therefore, as shown in FIG. 3(D), the source electrode layer 105a1 coincides with the end of the buffer layer 104a, and the drain electrode layer 105b1 coincides with the end of the buffer layer 104b, respectively. The source electrode layer or the drain electrode layer (105a2, 105a3), the source electrode layer or the drain electrode layer (105b2, 105b3) are recessed from the source electrode layer or the drain electrode layer (105a1, 105b1). 05b1), the buffer layers 104a, 104b, and the semiconductor layer 103 are etched and formed by dry etching. Therefore, as shown in FIG. 3(D), the source electrode layer 105a1 coincides with the end of the buffer layer 104a, and the drain electrode layer 105b1 coincides with the end of the buffer layer 104b, respectively. The source electrode layer or the drain electrode layer (105a2, 105a3), the source electrode layer or the drain electrode layer (105b2, 105b3) are recessed from the source electrode layer or the drain electrode layer (105a1, 105b1).

[0121] In other words, first, the titanium film, which is the third conductive film, is etched to form the third conductive layer (10 5a3, 105b3), and then a titanium film, which is a first conductive film, is formed as an etching stopper. The second conductive layer (105a) is then etched away from the aluminum film. 2, 105b2) are formed. Furthermore, the same resist mask as that used in the wet etching is used. The first conductive film was a titanium film and a second conductive film containing In, Ga, and Zn having n-type conductivity. The oxide semiconductor film 134 is dry-etched to form the third conductive layer (105a1, 105b 1) and buffer layers (104a, 104b) are formed. After the formation of the first and drain electrodes (105a, 105b), the first conductive layer (105a1, 105b1) coincides with the ends of the buffer layers (104a, 104b) and the second conductive layer (1 05a2, 105b2) and the third conductive layer (105a1, 105b1) are the first conductive layer The end portion is recessed from (105a1, 105b1). The cross-sectional view at this stage is shown in FIG. As shown in.

[0122] In this manner, the conductive film used for the source electrode layer and the drain electrode layer, the buffer layer, and the semiconductor If the layer has a low selectivity in the etching process, it functions as an etching stopper. To this end, a conductive film having different etching conditions may be stacked and etching steps may be performed a number of times.

[0123] In addition, the formed semiconductor layer 103 is subjected to heat treatment in a manner similar to that in Embodiment Mode 1.

[0124] According to this embodiment, the buffer layers 104a and 104b, the source electrode layer, and the drain electrode layer Resist masks in which the patterns of (105a, 105b) are formed using the same photomask Since it is carried out using [a certain method], the number of photomasks used can be reduced compared to Embodiment 1. As a result , by combining a plurality of steps into one step, the number of steps is reduced, the yield is improved , and the manufacturing time can be shortened.

[0125] (Embodiment 3) In this embodiment, the structure of the thin film transistor provided in a buffer layer having a structure different from that of Embodiment 1 and Embodiment 2 will be described with reference to FIG. 4. Also, in this embodiment , for those that are the same as in Embodiment 1, the same reference numerals are used and detailed descriptions are omitted. After going through the same steps as in Embodiment 2, a channel protection layer 106 is formed on an indium (In), gallium (Ga), and zinc (Zn)-containing oxide (IGZO) semiconductor film 133 that will become the semiconductor layer 103 as shown in FIG. 4(A).

[0126] In this embodiment, here, the semiconductor film 133 is not selectively etched to form the semiconductor layer 103, and an n-type conductive oxide semiconductor film that will become the buffer layers 104a and 104b is formed on the semiconductor film 133 by the same method as in Embodiment 2. Next , using the resist mask formed using the third photomask in this embodiment, the buffer layers 104a and 104b and the semiconductor layer 103 are formed as shown in FIG. 4(B).

[0127] The source electrode layer and the drain electrode layer (105a, 105b) are made of a conductive film and are formed in the same manner as in Embodiment 1. Here, a three-layer laminated film composed of a titanium film, an aluminum film, and a titanium film is formed as a conductive film on the buffer layers 104a and 104b and the channel protection layer 10 6 by sputtering. Next, using the resist formed using the fourth photomask in this embodiment , and the buffer layers 104a and 104b and the semiconductor layer 103 are formed as shown in FIG. 4(B).

[0128] The source electrode layer and the drain electrode layer (105a, 105b) are made of a conductive film and are formed in the same manner as in Embodiment 1. Here, a three-layer laminated film composed of a titanium film, an aluminum film, and a titanium film is formed as a conductive film on the buffer layers 104a and 104b and the channel protection layer 10 6 by sputtering. Next, using the resist formed using the fourth photomask in this embodiment mask​​​ Using a resist mask, etch and remove the conductive film to form a source electrode layer as shown in FIG. 4(D). and drain electrode layers (105a, 105b). FIG. 4(D) is a plan view, and FIG. 4(C) is a cross-sectional view taken along line A1 - A2 in FIG. 4(D).

[0129] Also, the heat treatment of the formed semiconductor layer 103 is performed in the same manner as in Embodiment 1.

[0130] According to this embodiment, since the patterning of the buffer layers 104a, 104b and the semiconductor layer 103 is performed simultaneously, the number of photomasks used can be reduced compared to Embodiment 1. As a result, by combining a plurality of processes into one process, the number of processes can be reduced, the yield can be improved, and the manufacturing time can be shortened.

[0131] (Embodiment 4) In this embodiment, a thin film transistor having a plurality of electrically connected gate electrodes and buffer layers will be described with reference to FIGS. 5 to 7. FIG. 5(A) is a plan view, and FIG. 5( B) is a cross-sectional view taken along line A1 - A2 in FIG. 5(A). FIG. 6(A) is a plan view and FIG. 6(B) is a cross-sectional view taken along line A1 - A2 in FIG. 6(A). FIG. 7(A) is a plan view, and FIG. 7(B) is a cross-sectional view taken along line A1 - A2 in FIG. 7(A). Also in this embodiment, the same components as those in Embodiment 1 are denoted by the same reference numerals, and detailed description thereof is omitted.

[0132] Note that in this embodiment, a structure in which two channel formation regions are connected is taken as an example, but it is not limited to this, and a triple gate structure in which three channel formation regions are connected, etc., is not limited thereto, and other structures such as a triple gate structure in which three channel formation regions are connected ​It is a multi-gate structure (a structure having two or more channel formation regions connected in series). That's okay too.

[0133] In the form in which the two channel formation regions of the thin film transistor of the present embodiment are connected, there are two forms of connecting the channel formation regions only with the buffer layers 104c (Fig. 5), and forms of connecting with the buffer layers 10 4c and the conductive layer 105c (Fig. 6), and three forms of connecting the two channel formation regions with the semiconductor layer 103, the buffer layer 104c, and the conductive layer 105c (Fig. 7). By changing the portion sandwiched between the two first gate electrodes 101a and the second gate electrode 10 1b of the photomask of the corresponding layer, these thin film transistors can be formed in the same manner as in Embodiment 1.

[0134] Such a multi-gate structure is extremely effective in reducing the off-current value.

[0135] (Embodiment 5) In the present embodiment, the structure of the thin film transistor having a buffer layer with a structure different from those of the above Embodiments 1 to 4 will be described with reference to Fig. 8. Note that since the thin film transistor of the present embodiment can be formed in the same manner as described in Embodiment 1 except for the buffer layer, detailed description of parts other than the buffer layer will be omitted.

[0136] The buffer layer of the present embodiment is composed of two layers, a first buffer layer and a second buffer layer. The buffer layers 104a and 104b in contact with the source electrode or the drain electrode are the first buffer layers, and the second buffer layers 114a and 114b are respectively the second buffer layers sandwiched between the first buffer layers 104a and 104b and the semiconductor layer 103.

[0137] ​​​In other words, the buffer layer of the present embodiment is in contact with one of the source electrode or the drain electrode. It includes a first buffer layer 104a that contacts one of the source electrode or the drain electrode, and a first buffer layer 104b that contacts the other of the source electrode or the drain electrode, and a second b uffer layer 114a sandwiched between the first buffer layer 104a and the semiconductor layer 103, and a second b uffer layer 114b sandwiched between the first buffer layer 104b and the semiconductor layer 103.

[0138] Both the first buffer layers 104a and 104b and the second buffer layers 114a and 114b are formed of an oxide semiconductor containing In, Ga, and Zn having an n-type conductivity type. In addition, it is also possible to use a hetero-doped oxide semiconductor containing In, Ga, and Zn having an n-type conductivity type. Examples of dopants include magnesium, aluminum,

[0139] titanium, scandium, yttrium, zirconium, hafnium, boron, thallium, germanium, tin, lead, and the like. Doping can increase the carrier concentration in the buffer layer.

[0140] As an example of the method for forming the buffer layer, a co-sputtering method can also be used, in which a sintered target of an oxide (IGZO) containing In, Ga, and Zn and a target of a compound containing a dopant for imparting an n-type conductivity type are simultaneously sputtered. According to the co-sputtering method, a mixed layer of an oxide (IGZO) containing In, Ga, and Zn and a compound containing a dopant can be formed, and the first buffer layers 104a and 104b and the second buffer layers 114a and 114b can be separately formed.

[0141] ​​​​​The carrier concentrations of the first buffer layers 104a and 104b and the second buffer layers 114a and 114b are higher than those of the semiconductor layer 103 made of an oxide (IGZO) containing In, Ga, and Zn, and are excellent in conductivity. Further, the first buffer layers 104a and 104b are selected to have a composition higher than the carrier concentrations of the second buffer layers 114a and 114b. That is, while the buffer layers 104a and 104b function as n layers, the second buffer layers (buffer layers 114a and 114b) function as n layers. a, 104b + layers, the second buffer layer (buffer layer 114 a, 114b) - functions as an n

[0142] The carrier concentration range (channel concentration range 1) of the semiconductor layer 103 is less than 1×10 17 atoms / cm 3 (more preferably, 1×10 11 atoms / cm 3 or more), and the carrier concentration range (buffer layer concentration range 2) of the IGZO film suitable as the buffer layers 104a and 104b that function as n + layers is preferably 1×10 atoms / cm or more (more preferably, 1×1 18 atoms / cm 3 or more) and 1×1 0 22 atoms / cm 3 or less).

[0143] By providing a gradient such that the carrier concentration increases from the semiconductor layer 103 toward the source electrode layer and the drain electrode layers (105a and 105b), the contact resistance between the semiconductor layer 103 and the source electrode layer and the drain electrode layers (105a and 105b) can be reduced. The carrier concentration increases from the semiconductor layer 103 toward the source electrode layer and the drain electrode layers (105a and 105b), and the contact resistance between the semiconductor layer 103 and the source electrode layer and the drain electrode layers (105a and 105b) can be reduced. and the drain electrode layers (105a, 105b) can be reduced.

[0144] Further, the carrier concentration increases from the semiconductor layer 103 toward the source electrode layer and the drain electrode layers (105a and 105b). By sandwiching a buffer layer with a gradient of increasing carrier concentration at the bonding interface, the electric field concentrated at the bonding interface can be relaxed. The electric field concentrated at the bonding interface can be relaxed.

[0145] A thin-film transistor having a stacked buffer layer according to one aspect of the present invention has a low off-current, and a semiconductor device including such a thin-film transistor can provide high electrical characteristics and high reliability. This can be achieved.

[0146] This embodiment can be implemented in appropriate combination with other embodiments.

[0147] (Embodiment 6) Here, an example of manufacturing an inverted staggered thin-film transistor in which at least the stack of the gate insulating film and the oxide semiconductor film is formed continuously without being exposed to the atmosphere is shown below. Here, the steps up to the step of forming the continuous film are shown, and the subsequent steps may be performed according to any one of Embodiments 1 to 5 to manufacture the thin-film transistor. When forming the continuous film without being exposed to the atmosphere, it is preferable to use a multi-chamber type manufacturing apparatus as shown in FIG. 9. The steps up to the step of forming the continuous film are shown, and the subsequent steps may be performed according to any one of Embodiments 1 to 5 to manufacture the thin-film transistor. This can be achieved.

[0148] When forming the continuous film without being exposed to the atmosphere, it is preferable to use a multi-chamber type manufacturing apparatus as shown in FIG. 9. This can be achieved.

[0149] At the center of the manufacturing apparatus, a transfer chamber 80 equipped with a transfer mechanism for transferring the substrate (typically a transfer robot 81) is provided, and a cassette chamber 82 for setting a cassette case for storing a plurality of substrates to be carried into and out of the transfer chamber is connected to the transfer chamber 80. At the center of the manufacturing apparatus, a transfer chamber 80 equipped with a transfer mechanism for transferring the substrate (typically a transfer robot 81) is provided, and a cassette chamber 82 for setting a cassette case for storing a plurality of substrates to be carried into and out of the transfer chamber is connected to the transfer chamber 80. A cassette chamber 82 for setting a cassette case for storing a plurality of substrates to be carried into and out of the transfer chamber is connected to the transfer chamber 80.

[0150] In addition, a plurality of processing chambers are connected to the transfer chamber via gate valves 84 to 88, respectively. Here, an example of connecting five processing chambers to a transfer chamber 80 having a hexagonal upper surface shape is shown. Note that, an example of connecting five processing chambers to a transfer chamber 80 having a hexagonal upper surface shape is shown. Note that, By changing the upper surface shape of the transfer chamber, the number of process chambers that can be connected can be changed. For example, if it is square, three process chambers can be connected, and if it is octagonal, seven process chambers can be connected.

[0151] Among the five process chambers, at least one process chamber is a sputtering chamber - for performing sputtering. The sputtering chamber is provided with at least a sputtering target, a power application mechanism for sputtering the target, a gas introduction means, a substrate holder for holding a substrate at a predetermined position, etc. Further, in order to make the inside of the sputtering chamber in a reduced pressure state, a pressure control means for controlling the pressure in the chamber is provided in the sputtering chamber.

[0152] There are an RF sputtering method using a high-frequency power source for the sputtering power supply and a DC sputtering method in the sputtering method, and there is also a pulsed DC sputtering method for applying a bias pulse. RF sputtering The method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film .

[0153] There is also a multi-source sputtering apparatus capable of installing a plurality of targets made of different materials. Multi-source sputtering The apparatus can also deposit different material films in the same chamber or discharge a plurality of types of materials simultaneously in the same chamber to form a film.

[0154] There is also a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber and a sputtering apparatus using an ECR sputtering method using plasma generated using microwaves without using glow discharge .

[0155] As the sputtering chamber, the various sputtering methods described above are appropriately used. Also, as a film formation method, during film formation, a target substance and a sputtering gas component are chemically reacted to form a compound thin film by a reactive sputtering method, or a bias sputtering method in which a voltage is also applied to the substrate during film formation is also available.

[0156] Among the five processing chambers, one of the other processing chambers is a heating chamber that performs preheating of the substrate before sputtering, a cooling chamber that cools the substrate after sputtering, or a chamber that performs plasma processing. is used.

[0157] Next, an example of the operation of the manufacturing apparatus will be described.

[0158] A substrate cassette containing a substrate 94 with the film formation surface facing downward is set in the cassette chamber 82, and the cassette chamber is evacuated by the vacuum evacuation means provided in the cassette chamber 82 to a reduced pressure state. Note that in advance, each processing chamber and the inside of the transfer chamber 80 are evacuated to a reduced pressure by the vacuum evacuation means provided therein. By doing so, a clean state can be maintained without the substrate coming into contact with the atmosphere while the substrate is being transferred between the processing chambers.

[0159] Note that the substrate 94 with the film formation surface facing downward has at least a gate electrode provided in advance. For example, an underlying insulating film such as a silicon nitride film or a silicon oxynitride film obtained by plasma CVD may be provided between the substrate and the gate electrode. When using a glass substrate containing an alkali metal as the substrate 94, the underlying insulating film has the effect of suppressing the intrusion of mobile ions such as sodium from the substrate into the semiconductor region above, which may change the electrical characteristics of the TFT.

[0160] Here, a silicon nitride film covering the gate electrode is formed by plasma CVD, and the first layer of gate A substrate with a trench insulating film is used. The silicon nitride film formed by plasma CVD is dense and by using it as the first layer of the gate insulating film, the occurrence of pinholes and the like can be suppressed . Here, an example of a laminated gate insulating film is shown, but it is not particularly limited, and a single layer or three layers or more of lamination may be used.

[0161] Next, the gate valve 83 is opened, and the first substrate 94 is taken out of the cassette by the transfer robot 81 , the gate valve 84 is opened, and it is transferred into the first processing chamber 89, and the gate valve 8 4 is closed. In the first processing chamber 89, the substrate is heated by a heating heater or lamp heating to remove moisture and the like adhering to the substrate 94 . In particular, if moisture is contained in the gate insulating film, the electrical characteristics of the TFT may change, so heating before sputtering film formation is effective. If the moisture has been sufficiently removed at the stage of setting the substrate in the cassette chamber 82, this heat treatment is unnecessary.

[0162] Also, plasma processing means may be provided in the first processing chamber 89 to perform plasma processing on the surface of the first layer of the gate insulating film . Further, heating means may be provided in the cassette chamber 82 to perform heating to remove moisture in the cassette chamber 82 .

[0163] Next, the gate valve 84 is opened, and the substrate is transferred to the transfer chamber 80 by the transfer robot 81 , the gate valve 85 is opened, and it is transferred into the second processing chamber 90, and the gate valve 85 is closed.

[0164] Here, the second processing chamber 90 is a sputtering chamber using the RF magnetron sputtering method. In the second processing chamber 90, a silicon oxide film (SiO A film of x-film (x > 0) is formed. As the second gate insulating film, in addition to the silicon oxide film, aluminum oxide film (Al2O3 film), magnesium oxide film (MgOx film (x > 0)), aluminum nitride film (AlNx film (x > 0)), yttrium oxide film (YOx film (x > 0 )) etc. can be used.

[0165] Also, a small amount of a halogen element, for example, fluorine, chlorine, etc., may be added to the second gate insulating film in the film to fix mobile ions such as sodium. As the method, a gas containing a halogen element is introduced into the chamber and sputtering is performed. However, when introducing a gas containing a halogen element it is necessary to provide a detoxification facility in the exhaust means of the chamber. The concentration of the halogen element to be included in the gate insulating film is preferably in the range where the concentration peak obtained by analysis using SIMS (secondary ion mass spectrometer) is 1 × 10 cm 15 cm -3 or more and 1 × 10 20 cm -3 or less. It is preferable to be within the range.

[0166] When obtaining a SiOx film (x > 0), artificial quartz is used as the target, and a sputtering method using a rare gas, typically argon, or a reactive sputtering method using single crystal silicon as the target and reacting with oxygen gas to obtain a SiOx film (x > 0) can be used. Here, in order to include as much oxygen as possible in the SiOx film (x > 0), artificial quartz is used as the target, and sputtering is performed in an atmosphere of only oxygen, or an atmosphere where oxygen is 90% or more and Ar is 10% or less, and a SiOx film (x > 0) with excess oxygen is formed

[0167] ​​​After forming the SiOx film (x > 0), without exposing it to the atmosphere, open the gate valve 85 and transfer Transfer the substrate into the transfer chamber 80 by the robot 81, open the gate valve 86 and transfer it into the third processing chamber 91, and close the gate valve 86.

[0168] Here, the third processing chamber 91 is a sputtering chamber using the DC magnetron sputtering method. In the third processing chamber 91, a metal oxide layer (IGZO film) is formed as the semiconductor layer. It can be formed in a rare gas atmosphere or an oxygen atmosphere using an oxide semiconductor target containing indium (In), gallium (Ga), and zinc (Zn). Here, in order to include as much oxygen as possible in the IGZO film, an oxide semiconductor containing In, Ga, and Zn is used as the target, and sputtering is performed by the pulsed DC sputtering method in an atmosphere of only oxygen or an atmosphere where oxygen is 90% or more and Ar is 10% or less to form an oxygen-excessive IGZO film.

[0169] In this way, by continuously forming an oxygen-excessive SiOx film (x > 0) and an oxygen-excessive IG ZO film without exposing them to the atmosphere, the interface state between the oxygen-excessive films can be stabilized, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before forming the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, causing variations in the threshold value, deterioration of electrical characteristics, and symptoms such as the TFT becoming a normally-on TFT. Moisture is a hydrogen compound, and by continuously forming the film without exposing it to the atmosphere, the presence of the hydrogen compound at the interface can be eliminated. Therefore, by continuously forming the film, variations in the threshold value can be reduced, deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally-on side can be prevented. prevented. Reduction, preferably elimination of the shift, can be achieved.

[0170] In addition, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed in the sputtering chamber of the second processing chamber 90, and sequential lamination is carried out using a shutter to perform lamination within the same chamber by continuous film formation. The shutter is provided between the target and the substrate. The target for film formation has the shutter opened, and the target for which film formation is not carried out is closed by the shutter. The advantages of lamination within the same chamber include the reduction in the number of chambers to be used, and the prevention of the adhesion of particles, etc. to the substrate during the transfer of the substrate between different chambers.

[0171] Next, without exposing to the atmosphere, the gate valve 86 is opened, and the substrate is transferred to the transfer chamber 80 by the transfer robot 81, the gate valve 87 is opened, and the substrate is transferred into the fourth processing chamber 92, and the gate valve 87 is closed.

[0172] Here, the fourth processing chamber 92 is a sputtering chamber using the RF magnetron sputtering method. In the fourth processing chamber 92, a silicon oxide film ( SiOx film (x > 0)) is formed as an insulating film serving as the channel protection layer. In addition to the silicon oxide film, as the channel protection layer, an aluminum oxide film (Al2O3 film), a magnesium oxide film (MgOx film (x > 0 )), an aluminum nitride film (AlNx film (x > 0)), a yttrium oxide film (YOx film ( x > 0)), etc. can be used.

[0173] In addition, a small amount of a halogen element, for example, fluorine, chlorine, etc. is added to the film of the channel protection layer, and ​​It is also possible to immobilize mobile ions such as tritium. As a method thereof, a gas containing a halogen element is introduced into the chamber to perform sputtering. However, when introducing a gas containing a halogen element, it is necessary to provide a detoxification facility in the exhaust means of the chamber. The concentration of the halogen element contained in the channel protective layer should be in the range where the concentration peak obtained by analysis using SIMS (Secondary Ion Mass Spectrometer) is 1×10 cm or more and 1×10 cm or less. It is preferably within the range. 15 cm -3 or more and 1×10 20 cm -3 or less. It is preferably within the range.

[0174] When obtaining a SiOx film (x>0) as the channel protective layer, artificial quartz is used as the target, and a sputtering method using a rare gas, typically argon, or a reactive sputtering method using single crystal silicon as the target and reacting with oxygen gas to obtain a SiOx film (x>0) can be used. Here, in order to include as much oxygen as possible in the SiOx film (x>0), artificial quartz is used as the target, and sputtering is performed in an atmosphere of only oxygen or an atmosphere where oxygen is 90% or more and Ar is 10% or less to form an oxygen-excess SiO x film (x>0). By continuously forming a film of an oxygen-excess SiOx film (x>0), an oxygen-excess IGZO film, and an oxygen-excess channel protective layer without exposure to the atmosphere in this way, the interface state is more stable because all three layers are oxygen-excess films, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. By continuously forming a film of an oxygen-excess SiOx film (x>0), an oxygen-excess IGZO film, and an oxygen-excess channel protective layer without exposure to the atmosphere in this way, the interface state is more stable because all three layers are oxygen-excess films, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. x film (x>0). % or more and Ar is 10% or less to form an oxygen-excess SiO x film (x>0).

[0175] In this way, by continuously forming films of an oxygen-excess SiOx film (x>0), an oxygen-excess IGZO film, and an oxygen-excess channel protective layer without exposure to the atmosphere, since all three layers are oxygen-excess films, the interface state is more stable, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. In this way, by continuously forming films of an oxygen-excess SiOx film (x>0), an oxygen-excess IGZO film, and an oxygen-excess channel protective layer without exposure to the atmosphere, since all three layers are oxygen-excess films, the interface state is more stable, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. In this way, by continuously forming films of an oxygen-excess SiOx film (x>0), an oxygen-excess IGZO film, and an oxygen-excess channel protective layer without exposure to the atmosphere, since all three layers are oxygen-excess films, the interface state is more stable, and the reliability of the TFT can be improved. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. If the substrate is exposed to the atmosphere before and after the formation of the IGZO film, moisture and the like adhere, which has an adverse effect on the interface state, resulting in variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. variations in threshold values, deterioration of electrical characteristics, and symptoms such as becoming a normally-on TFT. There is a risk of causing. Moisture is a hydrogen compound, and by forming a continuous film without contacting the atmosphere, the presence of the hydrogen compound at the interface of the IGZO film can be eliminated. Therefore, by forming three layers continuously, variations in the threshold value can be reduced, deterioration of electrical characteristics can be prevented, and the shift of the TFT to the normally-on side can be reduced, preferably eliminated. Also, in the sputtering chamber of the second processing chamber 90, both an artificial quartz target and an oxide semiconductor target containing In, Ga, and Zn are installed, and by sequentially laminating them using a shutter to form three layers continuously, lamination can also be performed within the same chamber. The advantages of laminating within the same chamber include reducing the number of chambers used and preventing particles from adhering to the substrate during substrate transfer between different chambers.

[0176] After repeating the above steps to perform film formation processing on the substrates in the cassette case and finishing the processing of multiple substrates, the vacuum in the cassette chamber is released to the atmosphere, and the substrates and the cassette are taken out. Next, in order to pattern the IGZO film, the channel protection layer is selectively etched, and further the IGZO film is selectively etched. It may be formed using dry etching or wet etching, or it may be selectively etched separately in two etchings. At this stage, the surface of the gate insulating film is exposed in the region where the IGZO film has been removed. Then, the channel protection layer is further positioned to overlap the gate electrode, that is, the channel shape of the IGZO film

[0177]

[0178]

[0179] ​​​​​​​​​​Etching is performed while leaving only the overlapping portion with the position that becomes the forming region. The channel protection layer here etching uses conditions where the etching rate is sufficiently different from that of the IGZO film. Channel If there is no sufficient difference in the etching rate during the etching of the protection layer, the surface of the IGZO film is partially etched, and a region with a thinner film thickness is formed compared to the region overlapping with the channel protection layer. In addition, when the channel protection layer is made of the same material as the gate insulating film, the gate insulating film will also be etched by this etching. Therefore, in order to prevent the gate insulating film from being etched, it is preferable to use a material different from that of the gate insulating film for the channel protection layer. In this embodiment, the gate insulating film has two layers. Since the upper layer is a SiOx film (x>0), there is a risk of being removed, but the lower layer is a silicon nitride film and functions as an etching stopper.

[0180] Next, the substrate is set again in the cassette chamber of the multi-chamber type manufacturing apparatus shown in FIG. 9.

[0181] Next, after evacuating the cassette chamber, the substrate is transferred to the transfer chamber 80 and then transferred to the third processing chamber 91. Here, sputtering by the pulsed DC sputtering method is performed in an atmosphere of only a rare gas to form an oxide semiconductor film containing In, Ga, and Zn with an n-type conductivity type serving as a buffer layer. This oxide semiconductor film containing In, Ga, and Zn with an n-type conductivity type has a lower oxygen concentration in the film than the oxygen-excess IGZO film. Also, as the oxide semiconductor film containing In, Ga, and Zn with an n-type conductivity type, it is preferable to have a higher carrier concentration than the oxygen-excess IGZO film. As the target, an oxide semiconductor containing In, Ga, and Zn. is preferably used, and an oxide semiconductor containing In, Ga, and Zn is used as the target. ​​​A target further containing Mg, Al, or Ti may be used for the conductor. Mg, Al, or Ti is a material that is prone to oxidation reaction. When these materials are included in an oxide semiconductor film containing In, Ga, and Z n with an n-type conductivity type, there is an oxygen blocking effect, etc., and the oxygen concentration in the semiconductor layer can be maintained within an optimal range even after heat treatment or the like. The oxide semiconductor film containing In, Ga, and Zn with this n-type conductivity type functions as a source region or a drain region.

[0182] Next, without exposing to the atmosphere, the gate valve 87 is opened and the substrate is transported to the transfer chamber 80 by the transfer robot 81, the gate valve 88 is opened and transported into the fifth processing chamber 93, and the gate valve 88 is closed.

[0183] Here, the fifth processing chamber 93 is a sputtering chamber using the DC magnetron sputtering method -. In the fifth processing chamber 93, a metal multilayer film serving as a source electrode and a drain electrode is formed . Both a titanium target and an aluminum target are installed in the sputtering chamber of the fifth processing chamber 93, and they are sequentially laminated using a shutter and continuously formed in the same chamber . Here, an aluminum film is laminated on the titanium film, and a titanium film is further laminated on the aluminum film.

[0184] In this way, without exposing to the atmosphere, by continuously forming an oxide semiconductor film containing In, Ga, and Zn with an n-type conductivity type and a metal multilayer film, a good interface state can be realized between the oxide semiconductor film containing In, Ga, and Zn with an n-type conductivity type and the metal multilayer film , and the contact resistance can be reduced.

[0185] ​​​ Repeat the above steps to perform a film forming process on the substrate in the cassette case, and finish the processing of multiple substrates. After that, release the vacuum in the cassette chamber to the atmosphere, and take out the substrate and the cassette.

[0186] Next, selectively etch the metal multilayer film to form the source electrode and the drain electrode. Furthermore, perform etching using the source electrode and the drain electrode as a mask, and selectively etch the oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type to form a source region or a drain region. In the etching of the oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type, the channel protection layer functions as an etching stopper.

[0187] An inverted staggered thin film transistor having a channel protection layer can be fabricated by the above steps.

[0188] In addition, in the above steps, an example of forming an oxygen-excess IGZO film and an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type in the same chamber was shown, but it is not particularly limited. They may be formed in separate chambers.

[0189] Here, a manufacturing apparatus of a multi-chamber system was taken as an example for explanation, but a continuous film formation may be performed without exposing to the atmosphere using a manufacturing apparatus of an in-line system in which sputtering chambers are connected in series.

[0190] In addition, the apparatus shown in FIG. 9 has a processing chamber of a so-called face-down method in which the substrate is set with the film formation surface facing downward, but it may be a processing chamber of a vertical placement method in which the substrate is set vertically. The processing chamber of the vertical placement method has an advantage that the footprint is smaller than that of the processing chamber of the face-down method. This is effective when using a large-area substrate that may be bent due to its own weight.

[0191] (Embodiment 7) In this embodiment, an example of fabricating at least a part of a drive circuit and thin-film transistors disposed in a pixel portion on the same substrate will be described below. The thin-film transistors disposed in the pixel portion are formed according to Embodiments 1 to 5.

[0192] Also, since the thin-film transistors shown in Embodiments 1 to 5 are n-channel type TFTs, a part of the drive circuit that can be configured with n-channel type TFTs in the drive circuit is formed on the same substrate as the thin-film transistors in the pixel portion.

[0193] An example of a block diagram of an active matrix liquid crystal display device is shown in Fig. 10(A). The display device shown in Fig. 10(A) has a pixel portion 5301 having a plurality of pixels each provided with a display element on a substrate 5300, a scanning line drive circuit 5302 for selecting each pixel, and a signal line drive circuit 5303 for controlling the input of a video signal to the selected pixel. (A) is connected to the signal line drive circuit 5303 by a plurality of signal lines S1 to Sm (not shown) extending in the column direction from the signal line drive circuit 5303, and is connected to the scanning line drive circuit 5302 by a plurality of scanning lines G1 to Gn (not shown) extending in the row direction from the scanning line drive circuit 5302, and has a plurality of pixels (not shown) arranged in a matrix corresponding to the signal lines S1 to Sm and the scanning lines G1 to Gn. And each pixel is connected to a signal line Sj (any one of the signal lines S1 to Sm) and a scanning line Gi (any one of the scanning lines G1 to Gn).

[0194] ​​​​​​​​​​​​

[0195] Also, the thin film transistors shown in Embodiments 1 to 5 are n-channel type TFTs, and a signal line driving circuit configured by n-channel type TFTs will be described with reference to FIG. 11.

[0196] The signal line driving circuit shown in FIG. 11 includes a driver IC 5601, a switch group 5602_1 to 56 02_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 56 21_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

[0197] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613 and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. For example, the wiring 5621 _J (any one of the wirings 5621_1 to 5621_M) in the Jth column is connected to the signal lines Sj-1, signal line Sj, and signal line S j+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in the switch group 5602 _J. For example, the wiring 5621 _J (any one of the wirings 5621_1 to 5621_M) in the Jth column is connected to the signal lines Sj-1, signal line Sj, and signal line S

[0198] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0199] Note that the driver IC 5601 is preferably formed on a single crystal substrate. Further, the switch groups 5602_1 to 5602_M are preferably formed on the same substrate as the element portions shown in Embodiments 1 to 5. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_M may be connected via an FPC or the like.

[0200] Next, the operation of the signal line driving circuit shown in FIG. 11 will be described with reference to the timing chart of FIG. 12. The timing chart of FIG. 12 shows the timing chart when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Further, the signal line driving circuit in FIG. 11 operates in the same manner as in FIG. 12 even when other rows of scanning lines are selected.

[0201] Note that the timing chart of FIG. 12 shows the case where the wiring 5621_J in the J-th column is connected to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 560 3c.

[0202] Note that the timing chart of FIG. 12 shows the timing when the scanning line Gi in the i-th row is selected, the on / off timing 5703a of the first thin film transistor 5603a, the second thin film transistor ​​​​​​​​​The on / off timing 5703b of the transistor 5603b, the on / off timing 5703c of the third thin film transistor 56 and the signal 5721_J input to the wiring 5621_J in the J column are shown.

[0203] Note that different video signals are input to the wirings 5621_1 to 5621_M during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621 _J during the third sub-selection period T3 is input to the signal line Sj+1. Further, during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, the video signals input to the wiring 5621_ J are respectively denoted as Data_j-1, Data_j, and Data_j+ 1.

[0204] As shown in FIG. 12, during the first sub-selection period T1, the first thin film transistor 5603 a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2 the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. ​​In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 56 03c.

[0205] From the above, the signal line driving circuit in FIG. 11 divides one gate selection period into three, so that a video signal can be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 11 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1 / 3 compared to the number of signal lines. By reducing the number of connections to about 1 / 3, the signal line driving circuit in FIG. 11 can improve reliability, yield, etc. If the thin film transistor arrangement, number, driving method, etc. are not limited as long as one gate selection period is divided into a plurality of sub-selection periods as shown in FIG. 11, and a video signal can be input from one wiring to each of a plurality of signal lines in each of the plurality of sub-selection periods. For example, when inputting a video signal from one wiring to each of three or more signal lines in each of three or more sub-selection periods, additional wiring for controlling the thin film transistors and thin film transistors may be added. However, if one gate selection period is divided into four or more sub-selection periods, one sub-selection period becomes short. Therefore, it is desirable that one gate selection period be divided into two or three sub-selection periods.

[0206]

[0207]

[0208] ​​​​​​​​As another example, as shown in the timing chart of FIG. 13, one selection period can be divided into a precharge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third selection period T3. Further, the timing chart of FIG. 13 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 13, in the precharge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c are turned on. At this time, the precharge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c, respectively. In the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 via the first thin film transistor 5603a. In the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603c. (Note that in the above description, Data_j-1, Data_j, and Data_j+1 represent data input to the wiring 5621_J at different times, and their specific values depend on the input signal of the circuit.) In addition, the scanning line Gi and the signal lines Sj-1, Sj, Sj+1 are part of the circuit structure of the display device. When the thin film transistors are turned on and off at specific timings, the data on the wiring 5621_J can be accurately transmitted to the corresponding signal lines, so as to control the display state of the pixels connected to these signal lines. This operation process realizes the selection and data input of different lines in the display device, which is an important part of the display control process. By precisely controlling the timing of the thin film transistors, the correct data can be transmitted to the appropriate positions to ensure the normal display of the image. Moreover, the precharge voltage Vp plays a role in preparing the signal lines for receiving data. By inputting the precharge voltage Vp during the precharge period Tp, the signal lines can be charged to a suitable voltage level, so that when the data is input later, it can be accurately transmitted and processed. In the display device, this kind of timing control and data transmission mechanism is very crucial. It ensures the synchronization and accuracy of the operation of each component, so that the display device can display high-quality images. For example, in a liquid crystal display device, this mechanism is used to control the voltage applied to the liquid crystal molecules, so as to achieve the purpose of displaying different colors and brightness levels. In the first sub-selection period T1, only the first thin film transistor 5603a is turned on, which enables the data on the wiring 5621_J to be specifically transmitted to the signal line Sj-1, while preventing the data from being transmitted to the signal lines Sj and Sj+1. This selective transmission of data is achieved by the on / off state of the thin film transistors, which is an important means to realize the address selection function in the display device. Similarly, in the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the data on the wiring 5621_J is transmitted to the signal line Sj, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off to prevent data leakage. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the data on the wiring 5621_J is transmitted to the signal line Sj+1, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. This sequential control of the thin film transistors realizes the accurate input of data to different signal lines, which is the key to ensuring the correct display of the image in the display device. During the operation process, the timing of each period and the on / off state of the thin film transistors need to be accurately controlled. This requires precise design and calibration of the circuit to ensure that the data can be transmitted correctly and the display effect meets the requirements. For example, in a large-size display device, the circuit design needs to consider factors such as signal transmission delay and interference to ensure the stability and accuracy of the timing control. In the second sub-selection period T2, when the second thin film transistor 5603b is turned on, the electrical characteristics of the transistor need to meet certain requirements to ensure that the data on the wiring 5621_J can be effectively transmitted to the signal line Sj. This includes parameters such as the on-resistance and off-leakage current of the transistor. If these parameters are not properly controlled, it may lead to data transmission errors or display abnormalities. In the third sub-selection period T3, the third thin film transistor 5603c also needs to work properly to ensure that the data on the wiring 5621_J can be accurately transmitted to the signal line Sj+1. is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603c. 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5 603b are turned off. At this time, Data_j+1 input to the wiring 5621_J passes through the third thin film transistor 5603c and is input to the signal line Sj+1.

[0209] From the above, the signal line driving circuit of FIG. 11 to which the timing chart of FIG. 13 is applied provides a precharge selection period before the subselection period, so that the signal line can be precharged, and the video signal can be written to the pixel at high speed. In FIG. 13, the same components as those in FIG. 12 are denoted by common reference numerals, and detailed descriptions of the same parts or parts having similar functions are omitted.

[0210] Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit includes a shift register and a buffer. In some cases, it may also include a level shifter. In the scanning line driving circuit, a selection signal is generated when a clock signal (CLK) and a start pulse signal (SP ) are input to the shift register. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. The scanning line is connected to the gate electrodes of the transistors of one line of pixels. And since the transistors of one line of pixels must be turned on all at once, a buffer capable of flowing a large current is used.

[0211] A form of the shift register used in a part of the scanning line driving circuit will be described with reference to FIGS. 14 and 15.

[0212] ​​​​Fig. 14 shows the circuit configuration of the shift register. The shift register shown in Fig. 14 is composed of a plurality of flip-flops 5701_i (any one of flip-flops 5701_1 to 5701_n). Also, it operates with the input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal. flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) is composed of. Also, it operates with the input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal. signal, and a reset signal.

[0213] The connection relationship of the shift register in Fig. 14 will be described. In the shift register of Fig. 14, the i-th stage flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in Fig. 15 connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in Fig. 15 connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in Fig. 15 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in Fig. 15 connected to the fifth wiring 5715. flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) is connected to the seventh wiring 5717_i - 1, the second wiring 5502 shown in Fig. 15 is connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in Fig. 15 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in Fig. 15 is connected to the fifth wiring 5715. is connected, the second wiring 5502 shown in Fig. 15 is connected to the seventh wiring 5717_i + 1, the third wiring 5503 shown in Fig. 15 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in Fig. 15 is connected to the fifth wiring 5715. shown in Fig. 15 is connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in Fig. 15 is connected to the fifth wiring 5715. shown in Fig. 15 is connected to the fifth wiring 5715.

[0214] Also, the fourth wiring 5504 shown in Fig. 15 is connected to the second wiring 5712 in the odd-stage flip-flops and to the third wiring 5713 in the even-stage flip-flops, and the fifth wiring 5505 shown in Fig. 15 is connected to the fourth wiring 5714. is connected to the second wiring 5712 in the odd-stage flip-flops and to the third wiring 5713 in the even-stage flip-flops, and the fifth wiring 5505 shown in Fig. 15 is connected to the fourth wiring 5714. is connected to the fourth wiring 5714.

[0215] However, the first wiring 5501 shown in Fig. 15 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in Fig. 15 of the n-th stage flip-flop 5701_n is connected to the sixth wiring 5716. is connected to the first wiring 5711, and the second wiring 5502 shown in Fig. 15 of the n-th stage flip-flop 5701_n is connected to the sixth wiring 5716. is connected to the sixth wiring 5716.

[0216] Note that the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 5716 are respectively referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line. can also be called the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Okay. Further, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the second power supply line, respectively.

[0217] Next, the details of the flip-flop shown in FIG. 14 are shown in FIG. 15. The flip -flop shown in FIG. 15 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film tran sistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Note that the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film tran sistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n-channel type transistors, and are assumed to be in a conductive state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

[0218] Next, the connection configuration of the flip-flop shown in FIG. 14 is shown below.

[0219] A first electrode (either the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and a second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0220] A first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and a second electrode of the second thin film transistor 5572 is connected to the third wiring 5503.

[0221] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the third The second electrode of the thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505 .

[0222] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth The second electrode of the thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0223] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the fifth The second electrode of the thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501 .

[0224] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth The second electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0225] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh The second electrode of the thin film transistor 5577 is connected to the gate electrode of the first thin film transistor 5571 is connected, and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502 The first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506 , the second electrode of the eighth thin film transistor 5578 is connected to the gate electrode of the second thin film transistor 5572, and the gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550 1.

[0226] Note that the connection points of the gate electrode of the first thin film transistor 5571, the gate electrode of the fourth thin film transistor 5574 , the second electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor 5576, and the second electrode of the seventh thin film transistor 5577 are defined as node 5543. Further, the connection points of the gate electrode of the second thin film transistor 5572, the second electrode of the third thin film transistor 5573, the second electrode of the fourth thin film transistor 5574 , the gate electrode of the sixth thin film transistor 5576, and the second electrode of the eighth thin film transistor 5578 are defined as node 5544.

[0227] Note that the first wiring 5501, the second wiring 5502, the third wiring 5503, and the fourth wiring 5 504 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Further, the fifth wiring 5505 may be referred to as the first power supply line, and the sixth wiring 5506 may be referred to as the second power supply line.

[0228] Also, it is possible to fabricate the signal line driving circuit and the scanning line driving circuit only with the n-channel type TFTs shown in Embodiments 1 to 5. Since the n-channel type TFTs shown in Embodiments 1 to 5 have a high mobility of the transistor, the driving frequency of the driving circuit can be increased ​​​​​This becomes possible. Further, the n-channel TFTs shown in Embodiments 1 to 5 have a low parasitic capacitance due to the buffer layer, and thus have high frequency characteristics (referred to as f characteristics). For example, a scanning line driving circuit using the n-channel TFTs shown in Embodiments 1 to 5 can be operated at high speed, so that it is possible to increase the frame frequency or to realize black screen insertion.

[0229] Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or by arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the scanning lines of even rows is arranged on one side, and the scanning line driving circuit for driving the scanning lines of odd rows is arranged on the opposite side. By doing so, it is possible to increase the frame frequency.

[0230] Also, when manufacturing an active matrix light-emitting display device, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of a block diagram of an active matrix light-emitting display device is shown in FIG. 10(B).

[0231] The display device shown in FIG. 10(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit 504 for selecting each pixel, and a signal line driving circuit 5403 for controlling the input of a video signal to the selected pixel.

[0232]

[0232] When the video signal input to the pixel of the display device shown in FIG. 10(B) is in digital format, Pixels become in a light-emitting or non-light-emitting state by switching on and off a transistor. . Therefore, grayscale display can be performed using an area grayscale method or a time grayscale method. The area grayscale method is a driving method for performing grayscale display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal. The time grayscale method is a driving method for performing grayscale display by controlling the period during which a pixel emits light.

[0233] Since the light-emitting element has a higher response speed than a liquid crystal element or the like, it is more suitable for the time grayscale method than the liquid crystal element. Specifically, when performing display by the time grayscale method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel is made to be in a light-emitting or non-light-emitting state during each sub-frame period. By dividing into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light during one frame period can be controlled by the video signal, and grayscale can be displayed.

[0234] Note that, in the light-emitting device shown in FIG. 10(B), when two, i.e., a switching TFT and a current control TFT, are arranged for one pixel, an example is shown in which a signal input to a first scanning line, which is a gate wiring of the switching TFT, is generated by a first scanning line driving circuit 5402, and a signal input to a second scanning line, which is a gate wiring of the current control TFT, is generated by a second scanning line driving circuit 5404. However, the signal input to the first scanning line and the signal input to the second scanning line may be generated by one scanning line driving circuit. Further, for example, depending on the number of transistors included in the switching element, the operation of the switching element may be controlled. The first scanning line used may be provided in plural numbers for each pixel. In this case, all signals input to the plural first scanning lines may be generated by one scanning line driving circuit, or may be generated by plural scanning line driving circuits respectively.

[0235] Also, in a light emitting device, a part of driving circuits that can be configured by n-channel type TFTs among driving circuits can be formed on the same substrate as thin film transistors in a pixel portion. Further, the signal line driving circuit and the scanning line driving circuit can be fabricated only by n-channel type TFTs shown in Embodiment 1 to Embodiment 5. Moreover, the above-described driving circuit is not limited to a liquid crystal display device or a light emitting device, and may be used for an electronic paper that drives electronic ink by using an element electrically connected to a switching element. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape.

[0236] Moreover, the above-described driving circuit is not limited to a liquid crystal display device or a light emitting device, and may be used for an electronic paper that drives electronic ink by using an element electrically connected to a switching element. The electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape. paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape. paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape. paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption than other display devices, and being able to have a thin and light shape.

[0237] Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). Although various forms of electrophoretic displays are conceivable, a microcapsule containing a first particle having a positive charge and a second particle having a negative charge is dispersed in a solvent or a solute in plural numbers, and by applying an electric field to the microcapsule, only the color of the particles that are moved in opposite directions to each other and gathered on one side in the microcapsule is displayed. Note that the first particle or the second particle contains a dye and does not move when there is no electric field. Also, the color of the first particle and the color of the second particle are different (including colorless).

[0238] Thus, an electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. An electrophoresis display does not require a polarizing plate or a counter substrate, which are necessary for liquid crystal display devices, and its thickness and weight are halved.

[0239] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having color filters or dyes.

[0240] Further, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, the active matrix substrate obtained in Embodiment 2 can be used.

[0241] Note that the first particles and the second particles in the microcapsules may be made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, a composite material thereof, or a composite material of these.

[0242] (Embodiment 8) A thin film transistor according to an aspect of the present invention can be manufactured, and a semiconductor device (also referred to as a display device) having a display function can be manufactured by using the thin film transistor in a pixel portion and further in a driving circuit. Also, a part or all of a driving circuit using a thin film transistor according to an aspect of the present invention can be used as a pixel portion. ​​​​​​​It can be integrally formed on the same substrate as the element part to form a system-on-panel.

[0243] The display device includes a display element. As the display element, a liquid crystal element (also referred to as a liquid crystal display element), a light-emitting element (also referred to as a light-emitting display element) can be used. The light-emitting element includes an element whose luminance is controlled by current or voltage in its category. Specifically, it includes inorganic EL (Electr o Luminescence), organic EL, etc. In addition, a display medium whose contrast changes by an electric action, such as electronic ink, can also be applied.

[0244] Further, the display device includes a panel in a state where the display element is sealed, and a module in a state where an IC including a controller is mounted on the panel. Furthermore, one aspect of the present invention relates to an element substrate corresponding to a form before the display element is completed in the process of manufacturing the display device, and the element substrate includes means for supplying current to the display element for each of a plurality of pixels. The element substrate may specifically be in a state where only the pixel electrode of the display element is formed, or may be in a state after forming a conductive film to be a pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0245] Note that the display device in this specification refers to an image display device, a display device, or a light source (including an illumination device). In addition, a module to which a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) is attached, and a module in which a printed wiring board is provided at the tip of the TAB tape or the TCP ール, or a module in which an IC (integrated circuit) is directly mounted on a display element by the COG (Chip On Glass) method, is also included in the display device.

[0246] In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device according to one aspect of the present invention.

[0247] FIGS. 16(A) and (B) show an active matrix type liquid crystal display device to which one aspect of the present invention is applied. FIG. 16(A) is a plan view of the liquid crystal display device, and FIG. 16(B) is a cross-sectional view taken along line V-X in FIG. 16(A). The thin film transistor 201 used in the semiconductor device can be manufactured in the same manner as the thin film transistor shown in Embodiment 4, and is a highly reliable thin film transistor including a buffer layer made of an IGZO semiconductor layer and an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type. In addition, the thin film transistors shown in Embodiments 1 to 3 and Embodiment 5 can also be applied as the thin film transistor 201 of the present embodiment.

[0248] The liquid crystal display device of the present embodiment in FIG. 16(A) includes a source wiring layer 202, a reverse staggered type thin film transistor 201 having a multi-gate structure, a gate wiring layer 203, and a capacitance wiring layer 204.

[0249] Also, in FIG. 16(B), the liquid crystal display device of the present embodiment includes a thin film transistor 201 having a multi-gate structure, an insulating layer 211, an insulating layer 212, an insulating layer 213, an electrode layer 255 used for a display element, an insulating layer 261 functioning as an alignment film, a polarizing plate 268, a substrate 200, an insulating layer 263 functioning as an alignment film, an electrode layer 265 used for a display element, a coloring layer 264 functioning as a color filter, and a substrate 266 provided with a polarizing plate 267, with a liquid crystal layer 2 ​​​​​​​​​​ They sandwich 62 and face each other, and have a liquid crystal display element 260.

[0250] Although FIG. 16 shows an example of a transmissive liquid crystal display device, one aspect of the present invention can also be applied to a reflective liquid crystal display device or a transflective liquid crystal display device.

[0251] Also, in the liquid crystal display device of FIG. 16, a polarizing plate 267 is provided on the outside (viewing side) of the substrate 266, and an example is shown in which a coloring layer 264 and an electrode layer 265 used for the display element are provided in this order on the inside. However, the polarizing plate 267 may be provided inside the substrate 266. Also, the laminated structure of the polarizing plate and the coloring layer is not limited to that shown in FIG. 16 and may be appropriately set according to the materials of the polarizing plate and the coloring layer and the production process conditions. Further, a light-shielding film that functions as a black matrix may be provided.

[0252] The electrode layers 255 and 265 that function as pixel electrode layers are indium oxides containing tungsten oxide, indium zinc oxides containing tungsten oxide, indium oxides containing titanium oxide, indium tin oxides containing titanium oxide, indium tin oxides (hereinafter referred to as ITO .), indium zinc oxides, indium tin oxides added with silicon oxide, etc., and conductive materials having light transmittance can be used.

[0253] Also, as the electrode layers 255 and 265, a conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used to form . The pixel electrode formed using the conductive composition preferably has a sheet resistance of 10,000 Ω / sq or less and a light transmittance of 70% or more at a wavelength of 550 nm . Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0254] ​​​ As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or or a derivative thereof, or a copolymer of two or more of these.

[0255] Through the above steps, a highly reliable liquid crystal display device can be manufactured as a semiconductor device. .

[0256] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0257] (Embodiment 9) In this embodiment, an example of electronic paper will be described as a semiconductor device of one embodiment of the present invention.

[0258] FIG. 17 shows an active matrix type semiconductor device as an example of a semiconductor device to which one embodiment of the present invention is applied. The thin film transistor 581 used in the semiconductor device is It can be fabricated in the same way as the thin-film transistor shown in Example 4, and has an IGZO semiconductor layer and an n-type conductivity. The buffer layer is made of an oxide semiconductor layer containing In, Ga, and Zn. The thin film transistor is a thin film transistor. A thin film transistor can also be applied as the thin film transistor 201 of this embodiment. .

[0259] The electronic paper in FIG. 17 is an example of a display device that uses the twisting ball display method. The spherical display method is an electrode layer that uses spherical particles painted in black and white as display elements. A potential difference is applied between the first electrode layer and the second electrode layer. A method of performing display by controlling the orientation of spherical particles to cause it.

[0260] The thin-film transistor 581 is an inverted staggered thin-film transistor with a multi-gate structure, and the source electrode layer and the drain electrode layer form the first electrode layer 587, and are in contact with and electrically connected to the opening formed in the insulating layer 585. Between the first electrode layer 587 and the second electrode layer 588, there are a black region 590a and a white region 590b, and spherical particles 589 including a cavity 594 filled with liquid around it are provided, and the periphery of the spherical particles 589 is filled with a filler 595 such as resin (see Fig. 17).

[0261] In Fig. 17, an electrode layer containing a translucent conductive polymer is used as the first electrode layer. An inorganic insulating film is provided on the first electrode layer 587a, and the inorganic insulating film functions as a barrier film to prevent the diffusion of ionic impurities from the first electrode layer 587a.

[0262] Also, instead of the twist ball, an electrophoresis element can also be used. A transparent liquid and microcapsules with a diameter of about 10 μm to 200 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. The microcapsules provided between the first electrode layer and the second electrode layer, when an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoresis display element, which is generally called electronic paper. The electrophoresis display element has a higher reflectance than a liquid crystal display element, so an auxiliary light is not required, and also has low power consumption and can recognize the display part even in a dim place. Also 、Even when the display unit is not supplied with power, it is possible to hold the image that has been displayed once Therefore, even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device equipped with a display device) is kept away from the radio wave transmission source, it is possible to save the displayed image.

[0263] By the above steps, a highly reliable electronic paper can be manufactured as a semiconductor device.

[0264] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0265] (Embodiment 10) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device according to one aspect of the present invention. As the display element of the display device, a light-emitting element using electroluminescence is shown here. The light-emitting element using electroluminescence is classified according to whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

[0266] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light-emitting organic compound, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. From such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0267] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element structure.​​​​​​​​ They are classified. The distributed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. It is a device that uses a donor-acceptor recombination type of light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emission mechanism is a localized light emission that utilizes the inner-shell electron transition of metal ions. Here, an organic EL element is used as the light-emitting element for explanation.

[0268] Figures 18(A) and (B) show an active matrix type light-emitting display device as an example of a semiconductor device to which one aspect of the present invention is applied. Figure 18(A) is a plan view of the light-emitting display device, and Figure 18(B) is a cross-sectional view taken along line Y-Z in Figure 18(A). In addition, Figure 19 shows an equivalent circuit of the light-emitting display device shown in Figure 18.

[0269] As the thin-film transistors 301 and 302 used in the semiconductor device, they can be manufactured in the same manner as the thin-film transistors shown in Embodiment 1 and Embodiment 2, and are highly reliable thin-film transistors including an IGZO semiconductor layer and a buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type. Also, the thin-film transistors shown in Embodiments 3 to 5 can also be applied as the thin-film transistors 301 and 302 of the present embodiment.

[0270] The light-emitting display device of the present embodiment shown in Figures 18(A) and 19 includes multi-gate structure thin-film transistors 301, a light-emitting element 303, a capacitive element 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin-film transistors 301 and 302 are n-channel type thin-film transistors.

[0271] Also, in FIG. 18(B), the light-emitting display device of the present embodiment includes a thin-film transistor 302 , an insulating layer 311, an insulating layer 312, an insulating layer 313, a partition 321, and a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323 used for the light-emitting element 303. It has.

[0272] The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, polyamide, or siloxane .

[0273] In the present embodiment, since the thin-film transistor 302 of the pixel is n-type, it is desirable to use a cathode as the first electrode layer 320 which is the pixel electrode layer. Specifically, as the cathode, a material having a small work function, for example, Ca, Al, CaF, MgAg, AlLi, etc. can be used.

[0274] The partition 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular using a photosensitive material, an opening is formed on the first electrode layer 320, and the side wall of the opening is connected It is preferably formed so as to be an inclined surface formed with a continuous curvature.

[0275] The electroluminescent layer 322 may be composed of a single layer or may be configured such that a plurality of layers are stacked.

[0276] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The second electrode layer 323 can be formed of a transparent conductive film using a conductive material having transparency listed as the pixel electrode layer in Embodiment 7. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 32 ​ By overlapping them, the light-emitting element 303 is formed. After that, on the light-emitting element 303 so that the atmosphere (oxygen, hydrogen, moisture, carbon dioxide, etc.) does not enter, the second electrode layer 323 and a protective film may be formed on the partition wall 321. As the protective film, a silicon nitride film, a silicon oxynitride film , a DLC film, etc. can be formed.

[0277] Furthermore, actually, when it is completed up to Fig. 18(B), in order not to be further exposed to the outside air, the airtightness is high, and it is preferable to package (enclose) it with a protective film (laminated film, ultraviolet curable resin film, etc. ) or a cover material with less outgassing.

[0278] Next, the configuration of the light-emitting element will be described with reference to Fig. 20. Here, the case where the driving TFT is of n type will be taken as an example to describe the cross-sectional structure of the pixel. The driving TFTs 7001, 7011, 7021 used in the semiconductor devices of Figs. 20(A), (B), and (C) can be fabricated in the same manner as the thin film transistors shown in Embodiment 1, and are reliable thin film transistors including an IGZO semiconductor layer and a buffer layer made of an oxide semiconductor layer having an n-type conductivity type and containing I n, Ga, and Zn. Also, the thin film transistors shown in Embodiment 2, Embodiment 3, or Embodiment 4 can be applied as the driving TFTs 7001, 7011, 7021. n, Ga, and Zn. Also, the thin film transistors shown in Embodiment 2, Embodiment 3, or Embodiment 4 can be applied as the driving TFTs 7001, 7011, 7021. n, Ga, and Zn. Also, the thin film transistors shown in Embodiment 2, Embodiment 3, or Embodiment 4 can be applied as the driving TFTs 7001, 7011, 7021. For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate are available. The pixel configuration of one aspect of the present invention is

[0279] For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate are available. The pixel configuration of one aspect of the present invention is For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate are available. The pixel configuration of one aspect of the present invention is For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate are available. The pixel configuration of one aspect of the present invention is For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or a light-emitting element having a double-sided emission structure that extracts light from the surface on the substrate side and the surface opposite to the substrate are available. The pixel configuration of one aspect of the present invention is It can be applied to any light-emitting element with an injection structure.

[0280] The light-emitting element with a top emission structure will be described with reference to Fig. 20(A).

[0281] Fig. 20(A) shows a cross-sectional view of a pixel when the driving TFT 7001 is of the n-type and the light emitted from the light-emitting element 7002 leaks to the anode 7005 side. In Fig. 20(A), the cathode 7003 of the light-emitting element 70 02 is electrically connected to the driving TFT 7001, and a light-emitting layer 7004 and an anode 7005 are sequentially laminated on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film with a low work function and capable of reflecting light. For example, C a, Al, CaF, MgAg, AlLi, etc. are desirable. The light-emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are laminated. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially laminated on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films may be used. When it is composed of a plurality of layers, an electron injection layer, an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially laminated on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films may be used. sten, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films may be used. (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide, or other light-transmitting conductive films may be used. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 20(A), the light emitted from the light-emitting element 7002 is indicated by an arrow

[0282] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in Fig. 20(A), the light emitted from the light-emitting element 7002 is indicated by an arrow Inject as shown by the print on the anode 7005 side.

[0283] Next, the light-emitting element with the bottom injection structure will be described with reference to Fig. 20(B). The driving TFT7 011 is of the n-type, and when the light emitted from the light-emitting element 7012 is injected toward the cathode 7013 side, a cross-sectional view of the pixel is shown. In Fig. 20(B), on the transparent conductive film 7017 electrically connected to the driving TFT 7011, the cathode 7013 of the light-emitting element 7012 is formed, and the light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7 015 is transparent, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013, similar to the case of Fig. 20(A), can use various materials as long as they are conductive materials with a small work function. However, its film thickness should be such that it can transmit light (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7 014, similar to Fig. 20(A), may be composed of a single layer or may be configured with multiple layers laminated either way. The anode 7015 does not need to transmit light, but similar to Fig. 20(A), it can be formed using a transparent conductive material. And the shielding film 7016 can use, for example, a metal that reflects light, etc., but is not limited to a metal film. For example, a resin with black pigment added can also be used. The region sandwiched by the cathode 7013 and the anode 7015 and containing the light-emitting layer 7014 corresponds to the light-emitting element 7012.

[0284] In the case of the pixel shown in Fig. 20(B), the light emitted from the light-emitting element 7012 is injected toward the cathode 7013 side as shown by the arrow. ​

[0285] Next, the light-emitting element with a double-sided emission structure will be described with reference to FIG. 20(C). FIG. 20(C) shows that on a light-transmissive conductive film 7027 electrically connected to the driving TFT 7021, the cathode 7023 of the light-emitting element 7022 is formed, and on the cathode 7023, a light-emitting layer 7024, the anode 7025 are sequentially laminated. The cathode 7023 can be made of various materials as long as it is a conductive material with a low work function, similar to the case of FIG. 20(A). However, its film thickness should be such that light can pass through. For example, Al with a film thickness of 20 nm can be used as the cathode 7023. And the light-emitting layer 7024 can be composed of a single layer or a plurality of laminated layers, similar to the case of FIG. 20(A). The anode 70 25 can be formed using a light-transmissive conductive material that transmits light, similar to the case of FIG. 20(A). The portion where the cathode 7023, the light-emitting layer 7024, and the anode 7025 overlap corresponds to the light-emitting element 70 22. In the case of the pixel shown in FIG. 20(C), the light emitted from the light-emitting element 7022 is emitted to both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0286] Here, although an organic EL element is described as the light-emitting element, it is also possible to provide an inorganic E L element as the light-emitting element. In the present embodiment, an example in which a thin film transistor (driving TFT) for controlling the driving of the light-emitting element and

[0287] the light-emitting element are electrically connected is shown, but a configuration in which a current control TFT is connected between the driving TFT and the light-emitting element may also be employed.

[0288]

[0289] Note that the semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 20, and various modifications based on the technical idea of the present invention are possible.

[0290] Through the above steps, a highly reliable light-emitting display device can be manufactured as a semiconductor device.

[0291] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0292] (Embodiment 11) Next, the configuration of a display panel, which is one form of the semiconductor device of the present invention, is shown below. In this embodiment, a liquid crystal display panel (also referred to as a liquid crystal panel), which is one form of a liquid crystal display device having a liquid crystal element as a display element, and a light-emitting display panel ( also referred to as a light-emitting panel), which is one form of a semiconductor device having a light-emitting element as a display element, will be described.

[0293] Next, the appearance and cross-section of a light-emitting display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 21. FIG. 21 is a top view of a panel in which a highly reliable thin-film transistor and a light-emitting element including an IGZO semiconductor layer formed on a first substrate and a buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type are sealed with a sealing material between the first substrate and a second substrate. FIG. 21(B) corresponds to a cross-sectional view taken along the line H-I in FIG. 21(A). FIG. 21 shows a highly reliable thin-film transistor and a light-emitting element including an IGZO semiconductor layer formed on a first substrate and a buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type. The thin-film transistor and the light-emitting element are sealed with a sealing material between the first substrate and a second substrate. FIG. 21(A) is a top view of the panel, and FIG. 21(B) corresponds to a cross-sectional view taken along the line H-I in FIG. 21(A).

[0294] A pixel portion 4502, signal line driver circuits 4503a and 4503b, and scanning line driver circuits 4504a and 4504b provided on a first substrate 4501 are surrounded by a sealing material 4505. ​​​​​​​​In addition, a pixel portion 4502, signal line driver circuits 4503a and 4503b, and A second substrate 4506 is provided on the scanning line driver circuits 4504a and 4504b. The pixel portion 4502, the signal line driver circuits 4503a and 4503b, and the scanning line driver circuit 45 4504a and 4504b are a first substrate 4501, a sealant 4505, and a second substrate 4506. 4507. It is sealed together with the filler material 4507 by

[0295] A pixel portion 4502, a signal line driver circuit 4503a, and a fourth 503b and the scanning line driver circuits 4504a and 4504b each have a plurality of thin film transistors. In FIG. 21B, a thin film transistor 4510 included in a pixel portion 4502 and a signal 45, a thin film transistor 4509 included in a line driver circuit 4503a is illustrated.

[0296] The thin film transistors 4509 and 4510 are I-type transistors having an IGZO semiconductor layer and an n-type conductivity type. A thin film transistor including a buffer layer made of an oxide semiconductor layer containing n, Ga, and Zn. The thin film transistors described in any of Embodiments 1 to 5 can be used. In this embodiment mode, the thin film transistors 4509 and 4510 are n-channel thin film transistors. It is a ninja.

[0297] In addition, 4511 corresponds to a light-emitting element, and a first electrode which is a pixel electrode of the light-emitting element 4511 is The layer 4517 is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the structure of the light-emitting element 4511 is not limited to that shown in this embodiment mode. The structure of the light emitting element 4511 is adjusted according to the direction of the light to be extracted from the light emitting element 4511. The composition can be changed as appropriate.

[0298] Also, various signals and potentials applied to the signal line drive circuits 4503a and 4503b and the scanning line drive circuits 4504a and 4504b , or the pixel section 4502 are supplied from the FPCs 4518a and 4518 b.

[0299] In this embodiment, wiring 4516 that connects to the pixel section 4502, the signal line drive circuits 4503a and 4503 b, or the scanning line drive circuits 4504a and 4504b through contact holes (not shown) provided in the insulating film covering the thin film transistors 4509 and 4510 is formed using the same material as the source electrode layer or the drain electrode layer. Further, a connection terminal 4515 is formed on the wiring 4516 at the end of the substrate 4501 using the same material as the first electrode layer 4517 . The connection terminal 4515 is electrically connected to the terminal of the FPC 4518a via an anisotropic conductive film 4519

[0300] .

[0301] The second substrate 4506 located in the light extraction direction of the light emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0302]

[0302] As the filling material 4507, in addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EV A (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filling material .

[0303] Further, if necessary, a polarizing plate, or a circularly polarizing plate (including an elliptically polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter, etc. may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, an antiglare treatment can be performed to diffuse the reflected light due to surface irregularities and reduce reflections.

[0304] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b may be implemented by drive circuits formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Also, only the signal line drive circuit, or a part thereof, or only the scan line drive circuit, or a part thereof may be separately formed and implemented, and this embodiment is not limited to the configuration of FIG. 21. Next, regarding the appearance and cross-section of the liquid crystal display panel corresponding to one form of the semiconductor device of the present invention,

[0305] it will be described with reference to FIG. 22. FIG. 22 is a top view of the panel in which the IGZO semiconductor layer formed on the first substrate 4001 and the buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type are included, and the highly reliable thin film transistors 4010, 4011, and the liquid crystal element 4013 are sealed with a sealing material 4005 between the second substrate 4006, and FIG. 22(B) corresponds to the cross-sectional view at M-N in FIGS. 22(A1)(A2). The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scan line drive circuit 4004. Also, between the pixel portion 4002 and the scan line drive circuit

[0306] ​​​​A second substrate 4006 is provided on the path 4004. Thus, the pixel portion 4002 and the scanning line driving circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Also, a signal line driving circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film is mounted on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. Note that the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method can be used. FIG. 22(A1)

[0307] is an example of mounting the signal line driving circuit 4003 by the COG method, and FIG. 22(A2) is an example of mounting the signal line driving circuit 4003 by the TAB method. The pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 each have a plurality of thin film transistors. In FIG. 22(B), the thin film

[0308] transistor 4010 included in the pixel portion 4002 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated. The thin film transistors 4010 and 4011 correspond to thin film transistors including an IGZO semiconductor layer and a buffer layer made of an oxide semiconductor layer having an n-type conductivity type, and the thin film transistors shown in Embodiments 1 to 5 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film

[0309] transistors. The thin film transistors 4010 and 4011 correspond to thin film transistors including an IGZO semiconductor layer and a buffer layer made of an oxide semiconductor layer containing In, Ga, and Zn having an n-type conductivity type, and the thin film transistors shown in Embodiments 1 to 5 can be applied. In this embodiment, the thin film transistors 4010 and 4011 are n-channel thin film transistors. transistors.

[0310] In addition, the pixel electrode layer 4030 of the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The overlapping portion of the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are provided with insulating layers 4032 and 4033 that function as alignment films, respectively, and sandwich the liquid crystal layer 4008 via the insulating layers 4032 and 4033.

[0311] As the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless steel), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) plate, a PVF (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0312] Further, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used.

[0313] In addition, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0314] In this embodiment, the connection terminal 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013. The wiring 4016 is formed of the same conductive film as the gate electrode layers of the thin film transistors 4010 and 4011.

[0315] The connection terminal 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0316] Also, in FIG. 22, an example is shown in which the signal line driving circuit 4003 is separately formed and mounted on the first substrate 4001. However, the present embodiment is not limited to this configuration. The scanning line driving circuit may be separately formed and mounted, or a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

[0317] FIG. 23 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by applying one aspect of the present invention.

[0318] FIG. 23 is an example of a liquid crystal display module. The TFT substrate 2600 and the counter substrate 2601 are fixed by the sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display area. The coloring layer 2605 is necessary for performing color display. In the case of the RGB system, coloring layers corresponding to the respective colors of red, green, and blue are provided corresponding to each pixel. On the outside of the TFT substrate 2600 and the counter substrate 2601, polarizing plates 2606, 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is a flexible wiring board. It is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by the wiring substrate 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Also, it may be laminated in a state of having a retardation plate between the polarizing plate and the liquid crystal layer. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. By the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0319] The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc. The liquid crystal display module may use a TN (Twisted Nematic) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an MVA (Multi-domain Vertical Alignment) mode, a PVA (Patterned Vertical Alignment) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optical Compensated Bend) mode, an FLC (Ferroelectric Liquid Crystal) mode, an AFLC (AntiFerroelectric Liquid Crystal) mode, etc.

[0320] By the above steps, a highly reliable display panel can be manufactured as a semiconductor device.

[0321] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. Yes.

[0322] (Embodiment 12) The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, an electronic paper, a digital camera, a digital video The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). Examples of the electronic device include a television device (also referred to as a television or a television receiver), a monitor for a computer, an electronic paper, a digital camera, a digital video camera, etc. Digital cameras, digital photo frames, mobile phones (also referred to as mobile phones and mobile phone devices) , portable game machines, portable information terminals, audio playback devices, large game machines such as pachinko machines, etc. are listed. In particular, as shown in Embodiments 8 to 11, by applying the thin film transistor according to the present invention to a liquid crystal display device, a light emitting device, an electrophoretic display device, etc., it can be used for the display unit of an electronic device. Specific examples are given below.

[0323] A semiconductor device according to one aspect of the present invention can be applied to electronic paper as shown in Embodiment 9. Electronic paper can be used in electronic devices in any field as long as it can display information. For example, using electronic paper, it can be applied to electronic books (e-books), posters, in-vehicle advertisements in vehicles such as trains, displays on various cards such as credit cards, etc. Examples of electronic devices are shown in FIGS. 24 and 25.

[0324] FIG. 24(A) shows a poster 1601 made of electronic paper. When the advertising medium is a paper print, the advertisement is exchanged manually, but by using the electronic paper to which a semiconductor device according to one aspect of the present invention is applied, the advertisement display can be changed in a short time. Also, since a thin film transistor with good electrical characteristics is used, a stable image can be obtained without the display being distorted. Note that the poster may be configured to be able to wirelessly transmit and receive information.

[0325] Also, FIG. 24(B) shows an in-vehicle advertisement 1602 in a vehicle such as a train. When the advertising medium is a paper print, the advertisement is exchanged manually, but by using the electronic paper to which a semiconductor device according to one aspect of the present invention is applied, the advertisement display can be changed in a short time. Also, since a thin film transistor with good electrical characteristics is used, a stable image can be obtained without the display being distorted. Note that the in-vehicle advertisement may be configured to be able to wirelessly transmit and receive information. ​​​​​If an electronic paper applied with a conductor device is used, the advertisement display can be changed in a short time without much manual effort. In addition, since a thin film transistor with good electrical characteristics is used, a stable image can be obtained without the display being distorted. Incidentally, the in-vehicle advertisement may be configured to be able to wirelessly transmit and receive information.

[0326] Also, FIG. 25 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed around the shaft portion 2711. With such a configuration, it becomes possible to perform operations similar to those of a paper book.

[0327] A display portion 2705 is incorporated in the housing 2701, and a display portion 2707 is incorporated in the housing 2703. The display portion 2705 and the display portion 2707 may be configured to display consecutive screens, or may be configured to display different screens. With a configuration of displaying different screens, for example, text can be displayed on the right display portion (display portion 2705 in FIG. 25), and an image can be displayed on the left display portion (display portion 2707 in FIG. 25).

[0328] Also, in FIG. 25, an example in which the housing 2701 is provided with an operation portion and the like is shown. For example, in the housing 2701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. By operating the operation keys 2723, the page can be advanced. Incidentally, the configuration may be such that a key board, a pointing device, or the like is provided on the same surface as the display portion of the housing. Also, external connection terminals (earphone terminals, USB terminals, or an AC adapter and USB) may be provided on the back surface or side surface of the housing. terminals) may be provided. a configuration including terminals connectable to various cables such as a cable, a recording medium insertion part, etc. It may be. Further, the electronic book 2700 may have a configuration with a function as an electronic dictionary. It may be.

[0329] Also, the electronic book 2700 may be configured to be able to transmit and receive information wirelessly. By wireless, it is possible to purchase and download desired book data, etc. from an electronic book server. It is also possible.

[0330] FIG. 26(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. An image can be displayed by the display unit 9603. Also, here, a configuration in which the housing 9601 is supported by a stand 9605 is shown. The display unit 9603 can apply the display devices shown in Embodiments 8 to 11. The operation of the television device 9600 can be performed by an operation switch provided in the housing 9601 or a separate remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control unit 9610, and the image displayed on the display unit 9603 can be operated. Also, the remote control unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control unit 9610. It may be.

[0331] In addition, the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, via the modem, it can be connected to a wired or wireless network. The operation can be performed by a remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control unit 9610, and the image displayed on the display unit 9603 can be operated. Also, the remote control unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control unit 9610. The operation can be performed by a remote control unit 9610. Channel and volume operations can be performed by operation keys 9609 provided in the remote control unit 9610, and the image displayed on the display unit 9603 can be operated. Also, the remote control unit 9610 may be configured to be provided with a display unit 9607 for displaying information output from the remote control unit 9610.

[0332] Note that the television device 9600 has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts, and further, via the modem, it can be connected to a wired or wireless network. The receiver can receive general television broadcasts, and further, via the modem, it can be connected to a wired or wireless network. By connecting to a communication network, one-way (from sender to receiver) or two-way information communication (between the sender and the receiver, or between receivers, etc.) can also be performed.

[0333] FIG. 26(B) shows an example of the digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and for example, by displaying the image data taken with a digital camera or the like, it can function in the same way as a normal photo stand.

[0334] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables, etc.), a recording medium insertion unit, etc. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because it improves the design. For example, by inserting a memory storing the image data taken with a digital camera into the recording medium insertion unit of the digital photo frame, the image data can be captured and the captured image data can be displayed on the display unit 9703.

[0335] Also, the digital photo frame 9700 may be configured to be able to transmit and receive information wirelessly. It can also be configured to capture and display desired image data wirelessly.

[0336] FIG. 27 shows an example of the digital player 2100 which is a portable audio device. The digital player 2100 includes a main body 2130, a display unit 2131, a memory unit 2132 , an operation unit 2133, earphones 2134, a control unit 2137, etc. Note that the earphones ​​​​Instead of 2134, headphones or wireless earphones can be used. Display unit 2131 can apply the display devices shown in Embodiments 8 to 11.

[0337] Also, by operating the operation unit 2133 using the memory unit 2132, video and audio ( music) can be recorded and played back. Note that the display unit 2131 displays white characters on a black background to suppress power consumption. Note that the memory provided in the memory unit 2132 may be configured to be removable.

[0338] FIG. 28 shows an example of the mobile phone 1000. The mobile phone 1000 includes, in addition to the display unit 1002 incorporated in the housing 100 1, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc. The display unit 1002 can apply the display devices shown in Embodiments 8 to 11.

[0339] For the mobile phone 1000 shown in FIG. 28, information can be input by touching the display unit 1002 with a finger or the like. Also, operations such as making a call or sending an email can be performed by touching the display unit 1002 with a finger or the like.

[0340] The screen of the display unit 1002 mainly has three modes. The first is the display mode mainly for displaying images, the second is the input mode mainly for inputting information such as characters. The third is the display + input mode in which the two modes of the display mode and the input mode are mixed. For example, when making a call or creating an email, the display unit 1002 is used for character input

[0341] Set the main character input mode and perform the input operation on the characters displayed on the screen. In this case , it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002 .

[0342] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000 to detect the inclination, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0343] Also, the switching of the screen mode is performed by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0344] Also, in the input mode, the signal detected by the optical sensor of the display unit 1002 is detected, and when there is no input by the touch operation of the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0345] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 10 02, palm prints, fingerprints, etc. can be imaged to perform personal authentication. Also, by using a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light on the display unit, finger veins, palm veins, etc. can also be imaged.

[0346] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

Explanation of symbols

[0347] 80 Conveyor chamber 81 Conveyor robot 82 Cassette chamber 83 Gate valve 84 Gate valve 85 Gate valve 86 Gate valve 87 Gate valve 88 Gate valve 89 Processing chamber 90 Processing chamber 91 Processing chamber 92 Processing chamber 93 Processing chamber 94 Substrate 100 Substrate 101 Gate electrode 101a Gate electrode 101b Gate electrode 102 Gate insulating film 102a Gate insulating film 102b Gate insulating film 103 Semiconductor layer 104 Buffer layer 104a Buffer layer 104b Buffer layer 104c Buffer layer 105 Conductive film 105a, 105b Source electrode layer and drain electrode layer 105a1 Source electrode layer 105b1 Drain electrode layer 105a2 Source electrode layer 105b2 Drain electrode layer 105c Conductive layer 106 Channel protection layer 114a Buffer layer 114b Buffer layer 133 Semiconductor film 134 Oxide semiconductor film 200 Substrate 201 Thin film transistor 202 Source wiring layer 203 Gate wiring layer 204 Capacitance wiring layer 211 Insulating layer 212 Insulating layer 213 Insulating layer 255 Electrode layer 260 Liquid crystal display element 261 Insulating layer 262 Liquid crystal layer 263 Insulating layer 264 Coloring layer 265 Electrode layer 266 Substrate 267 Polarizing plate 268 Polarizing plate 301 Thin film transistor 302 Thin film transistor 303 Light emitting element 304 Capacitance element 305 Source wiring layer 306 Gate wiring layer 307 Power supply line 311 Insulating layer 312 Insulating layer 313 Insulating layer 320 Electrode layer 321 Partition wall 322 Electroluminescent layer 323 Electrode layer 504 Scanning line drive circuit 581 Thin film transistor 585 Insulating layer 587 Electrode layer 587a Electrode layer 588 Electrode layer 589 Spherical particles 590a Black region 590b White region 594 Cavity 595 Filler 1000 Mobile phone 1001 Housing 1002 Display unit 1003 Operation button 1004 External connection port 1005 Speaker 1006 Microphone 1601 Poster 1602 In-vehicle advertisement 2100 Digital player 2130 Main body 2131 Display unit 2132 Memory unit 2133 Operation unit 2134 Earphone 2137 Control unit 2600 TFT substrate 2601 Opposite substrate 2602 Sealant 2603 Pixel part 2604 Display element 2605 Coloring layer 2606 Polarizing plate 2607 Polarizing plate 2608 Wiring circuit part 2609 Flexible wiring board 2610 Cold cathode tube 2611 Reflector 2612 Circuit board 2613 Diffuser 2700 E-book 2701 Housing 2703 Housing 2705 Display unit 2707 Display unit 2711 Shaft part 2721 Power supply 2723 Operation key 2725 Speaker 4001 Substrate 4002 Pixel part 4003 Signal line driving circuit 4004 Scanning line driving circuit 4005 Sealant 4006 Substrate 4008 Liquid crystal layer 4010 Thin film transistor 4011 Thin film transistor 4013 Liquid crystal element 4015 Connection terminal 4016 Wiring 4018 FPC 4019 Anisotropic Conductive Film 4030 Pixel Electrode Layer 4031 Counter Electrode Layer 4032 Insulating Layer 4501 Substrate 4502 Pixel Portion 4503a Signal Line Driving Circuit 4504a Scanning Line Driving Circuit 4505 Sealing Material 4506 Substrate 4507 Filling Material 4509 Thin Film Transistor 4510 Thin Film Transistor 4511 Light Emitting Element 4515 Connection Terminal 4516 Wiring 4517 Electrode Layer 4518a FPC 4519 Anisotropic Conductive Film 5300 Substrate 5301 Pixel Portion 5302 Scanning Line Driving Circuit 5303 Signal Line Driving Circuit 5400 Substrate 5401 Pixel Portion 5402 Scanning Line Driving Circuit 5403 Signal Line Driving Circuit 5404 Scanning Line Driving Circuit 5501 Wiring 5502 Wiring 5503 Wiring 5504 Wiring 5505 Wiring 5506 Wiring 5543 Node 5544 Node 5571 Thin Film Transistor 5572 Thin Film Transistor 5573 Thin Film Transistor 5574 Thin Film Transistor 5575 Thin Film Transistor 5576 Thin Film Transistor 5577 Thin Film Transistor 5578 Thin Film Transistor 5601 Driver IC 5602 Switch Group 5603a Thin Film Transistor 5603b Thin Film Transistor 5603c Thin Film Transistor 5611 Wiring 5612 Wiring 5613 Wiring 5621 Wiring 5701 Flip-Flop 5703a Timing 5703b Timing 5703c Timing 5711 Wiring 5712 Wiring 5713 Wiring 5714 Wiring 5715 Wiring 5716 Wiring 5717 Wiring 5721 Signal 5803a Timing 5803b Timing 5803c Timing 5821 Signal 7001 Driving TFT 7002 Light Emitting Element 7003 Cathode 7004 Light Emitting Layer 7005 Anode 7011 Driving TFT 7012 Light Emitting Element 7013 Cathode 7014 Light Emitting Layer 7015 Anode 7016 Masking Film 7017 Conductive Film 7021 Driving TFT 7022 Light Emitting Element 7023 Cathode 7024 Light Emitting Layer 7025 Anode 7027 Conductive Film 8310 Resistivity / Hole Measurement System ResiTest 9600 Television device 9601 Housing 9603 Display unit 9605 Stand 9607 Display unit 9609 Operation key 9610 Remote control operation unit 9700 Digital photo frame 9701 Housing 9703 Display unit

Claims

1. having a plurality of pixels arranged in a matrix, at least one of the pixels having a first transistor, a second transistor, and a capacitive element, wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor and one of the electrodes of the capacitive element, respectively, and is a display device, a first conductive layer having a first region functioning as the gate electrode of the first transistor and a second region functioning as one of the electrodes of the capacitive element, an oxide semiconductor layer having a region located above the first conductive layer and having a channel formation region of the first transistor, an insulating layer having a region located above the oxide semiconductor layer and having an overlap with the channel formation region, a second conductive layer having a region functioning as the gate electrode of the second transistor and a region functioning as a scanning line, a third conductive layer having a region functioning as one of the source electrode and the drain electrode of the second transistor, and a fourth conductive layer electrically connected to the first transistor and having a region functioning as a pixel electrode, in a plan view of one of the pixels, the region of the second conductive layer functioning as the scanning line extends along a first direction, the width of the second region in the first direction is larger than the width of the first region in the first direction, in a plan view, the third conductive layer has a region arranged side by side with the second region along the first direction, in a plan view, the fourth conductive layer has a region arranged side by side with the channel formation region of the first transistor along the first direction, and is a display device.

2. having a plurality of pixels arranged in a matrix, at least one of the pixels having a first transistor, a second transistor, and a capacitive element, wherein one of the source electrode and the drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor and one of the electrodes of the capacitive element, respectively, and is a display device, a first conductive layer having a first region functioning as the gate electrode of the first transistor and a second region functioning as one of the electrodes of the capacitive element, an oxide semiconductor layer having a region located above the first conductive layer and having a channel formation region of the first transistor, An insulating layer having a region located above the oxide semiconductor layer and overlapping with the channel formation region, A second conductive layer having a region functioning as a gate electrode of the second transistor and a region functioning as a scanning line, A third conductive layer having a region functioning as one of a source electrode and a drain electrode of the second transistor, A fourth conductive layer electrically connected to the first transistor and having a region functioning as a pixel electrode, The third conductive layer has a region in contact with the first conductive layer, In a plan view of the pixel, the region functioning as the scanning line in the second conductive layer extends along a first direction, The width of the second region in the first direction is larger than the width of the first region in the first direction, In a plan view, the third conductive layer has a region arranged side by side with the second region along the first direction, In a plan view, the fourth conductive layer has a region arranged side by side with the channel formation region of the first transistor along the first direction, a display device.

Images