Semiconductor memory device

Abstract

To provide a semiconductor memory device that reduces power consumption.SOLUTION: According to an embodiment, a semiconductor memory device includes a first memory string NS including a first select transistor ST1, first to third memory cells MC, and a second select transistor ST2; a bit line BL; a source line SL; a first select gate line SGD; first to third word lines WL; and a second select gate line SGS. When writing data to the first memory cell, a control unit applies a first voltage VBL to the bit line, applies a second voltage VSS to the source line, applies a third voltage VON to the first select gate line, applies a fourth voltage VON to the second select gate line, applies a program voltage VPGM to the first word line, applies a fifth voltage VSW to the second word line, and applies a sixth voltage VPASS, which is higher than the fifth voltage and lower than the program voltage, to the third word line.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor memory device.

Background Art

[0002] As a semiconductor memory device, a NAND type flash memory is known.

Prior Art Documents

Non-Patent Documents

[0003]

Non-Patent Document 1

Non-Patent Document 2

[0004] In one embodiment of the present invention, a semiconductor memory device capable of reducing power consumption is provided. Means for Solving the Problems

[0005] The semiconductor memory device according to the embodiment includes a first memory string including a first selection transistor, a first memory cell, a second memory cell, a third memory cell, and a second selection transistor, in which each current path is connected in series, a bit line connected to the first selection transistor, a source line connected to the second selection transistor, a first selection gate line connected to the gate of the first selection transistor, a second selection gate line connected to the gate of the second selection transistor, a first word line connected to the gate of the first memory cell, a second word line connected to the gate of the second memory cell, a third word line connected to the gate of the third memory cell, and a control circuit configured to execute a writing operation including a program operation and a program verification operation. In the program operation of the first memory cell, when writing data to the first memory cell, the control circuit applies a first voltage to the bit line BL, applies a second voltage lower than the first voltage to the source line, applies a third voltage higher than the first voltage to the first selection gate line, applies a fourth voltage higher than the first voltage to the second selection gate line, applies a program voltage to the first word line, applies a fifth voltage to the second word line, and applies a sixth voltage higher than the fifth voltage and lower than the program voltage to the third word line.

Brief Description of the Drawings

[0006]

Figure 1

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Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. When distinguishing a plurality of components having a common reference numeral, a suffix is attached to the common reference numeral for distinction. When no distinction is particularly required for a plurality of components, only the common reference numeral is attached to the plurality of components, and no suffix is attached. Here, the suffix is not limited to subscripts and superscripts, and includes, for example, small letters of the alphabet added to the end of the reference numeral, and indexes indicating arrays.

[0008] 1. First Embodiment The semiconductor memory device 1 according to the first embodiment will be described. The semiconductor memory device 1 is a NAND-type flash memory capable of storing data non-volatilely. Note that the semiconductor memory device 1 is not limited to a NAND-type flash memory. The semiconductor memory device 1 may be another non-volatile memory.

[0009] 1.1 Configuration 1.1.1 Overall Configuration of the Semiconductor Memory Device First, an example of the overall configuration of the semiconductor memory device 1 will be described with reference to FIG. 1. FIG. 1 is a block diagram showing the overall configuration of the semiconductor memory device 1. Note that in FIG. 1, a part of the connection of each component is shown by an arrow line, but the connection between components is not limited to this.

[0010] As shown in FIG. 1, the semiconductor memory device 1 is configured to be controllable by an external memory controller 2. For example, the semiconductor memory device 1 transmits and receives signals DQ and timing signals DQS and DQSn to and from the memory controller 2. The signal DQ is, for example, data DAT, an address ADD, or a command CMD. The timing signals DQS and DQSn are timing signals used at the time of input / output of the data DAT. The timing signal DQSn is an inverted signal of the timing signal DQS.

[0011] Further, the semiconductor memory device 1 receives various control signals from the memory controller 2. Then, the semiconductor memory device 1 transmits a ready / busy signal RBn to the memory controller 2. The ready / busy signal RBn is a signal indicating whether the semiconductor memory device 1 is in a state where it cannot receive a command CMD from the memory controller 2 (busy state) or a state where it can (ready state).

[0012] The semiconductor memory device 1 includes an input / output circuit 10, a logic control circuit 11, an address register 12, a command register 13, a sequencer 14, a ready / busy circuit 15, a voltage generation circuit 16, a memory cell array 17, a row decoder 18, a sense amplifier 19, a data register 20, and a column decoder 21.

[0013] The input / output circuit 10 is a circuit that inputs and outputs the signal DQ. The input / output circuit 10 is connected to the memory controller 2. Also, the input / output circuit 10 is connected to the logic control circuit 11, the address register 12, the command register 13, and the data register 20.

[0014] When the input signal DQ is the address ADD, the input / output circuit 10 transmits the address ADD to the address register 12. Also, when the input signal DQ is the command CMD, the input / output circuit 10 transmits the command CMD to the command register 13.

[0015] When the input signal DQ is the data DAT, the input / output circuit 10 receives the input signal DQ based on the timing signals DQS and DQSn. Then, the input / output circuit 10 transmits the data DAT to the data register 20. Also, the input / output circuit 10 outputs the data DAT as the output signal DQ to the memory controller 2 together with the timing signals DQS and DQSn.

[0016] The logic control circuit 11 is a circuit that performs logic control based on control signals. The logic control circuit 11 is connected to the memory controller 2. Also, the logic control circuit 11 is connected to the input / output circuit 10 and the sequencer 14. The logic control circuit 11 receives a plurality of control signals from the memory controller 2. The logic control circuit 11 controls the input / output circuit 10 and the sequencer 14 based on the received control signals.

[0017] The address register 12 is a register that temporarily stores the address ADD. The address register 12 is connected to the input / output circuit 10, the row decoder 18, and the column decoder 21. The address ADD includes the row address RA and the column address CA. The row address RA is an address for selecting the wirings (word lines and selection gate lines) arranged in the row direction in the memory cell array 17. The column address CA is an address for selecting the wirings (bit lines) arranged in the column direction in the memory cell array 17. For example, the row address RA includes the block address and the word line address. The block address is an address for specifying any one of the plurality of blocks BLK included in the memory cell array 17. The word line address is an address for specifying any one of the plurality of word lines connected to the block BLK.

[0018] The address register 12 transfers the row address RA to the row decoder 18. Also, the address register 12 transfers the column address CA to the column decoder 21.

[0019] The command register 13 is a register that temporarily stores the command CMD. The command register 13 is connected to the input / output circuit 10 and the sequencer 14. The command register 13 transfers the command CMD to the sequencer 14.

[0020] The sequencer 14 is a control circuit that controls the semiconductor memory device 1. The sequencer 14 controls the operation of the entire semiconductor memory device 1. For example, the sequencer 14 controls the ready / busy circuit 15, the voltage generation circuit 16, the row decoder 18, the sense amplifier 19, the data register 20, and the column decoder 21. For example, the sequencer 14 executes a write operation, a read operation, an erase operation, etc. based on the command CMD.

[0021] The ready / busy circuit 15 is a circuit that transmits the ready / busy signal RBn to the memory controller 2 based on the control of the sequencer 14.

[0022] The voltage generation circuit 16 generates voltages used for a write operation, a read operation, and an erase operation based on the control of the sequencer 14. The voltage generation circuit 16 supplies the voltages generated to the memory cell array 17, the row decoder 18, the sense amplifier 19, etc. The row decoder 18 and the sense amplifier 19 can apply the voltages supplied from the voltage generation circuit 16 to the memory cell array 17.

[0023] The memory cell array 17 is a collection of a plurality of memory cells (also referred to as "memory cell transistors") arranged in a matrix. The memory cell array 17 includes a plurality of blocks BLK. In the example shown in FIG. 1, the memory cell array 17 includes four blocks BLK0, BLK1, BLK2, and BLK3. Note that the number of blocks BLK in the memory cell array 17 is arbitrary. The block BLK is, for example, a collection of a plurality of memory cells in which data is erased in a batch. That is, the block BLK is a data erasure unit. Details of the configuration of the block BLK will be described later.

[0024] The row decoder 18 is a decoding circuit for the row address RA. Based on the decoding result, the row decoder 18 selects any one of the blocks BLK in the memory cell array 17. The row decoder 18 applies a voltage to the wiring in the row direction (word line and selection gate line) of the selected block BLK.

[0025] The sense amplifier 19 is a circuit that writes and reads data DAT. The sense amplifier 19 is connected to the memory cell array 17 and the data register 20. During a read operation, the sense amplifier 19 reads data DAT from the memory cell array 17. Also, during a write operation, the sense amplifier 19 supplies a voltage based on the write data DAT to the memory cell array 17.

[0026] The data register 20 is a register that temporarily stores data DAT. The data register 20 is connected to the sense amplifier 19 and the column decoder 21. The data register 20 includes a plurality of latch circuits. Each latch circuit temporarily stores write data or read data.

[0027] The column decoder 21 is a circuit that decodes the column address CA. The column decoder 21 receives the column address CA from the address register 12. Based on the decoding result of the column address CA, the column decoder 21 selects a latch circuit in the data register 20.

[0028] 1.1.2 Circuit Configuration of Memory Cell Array Next, with reference to FIG. 2, an example of the circuit configuration of the memory cell array 17 will be described. FIG. 2 is a circuit diagram of the memory cell array 17. FIG. 2 shows an example of the circuit configuration of one block BLK included in the memory cell array 17. Note that other blocks BLK also have the same configuration as FIG. 2.

[0029] Block BLK includes, for example, four string units SU0 to SU3. Note that the number of string units SU included in block BLK is arbitrary. The string unit SU is, for example, a set of a plurality of NAND strings NS that are collectively selected in a write operation or a read operation.

[0030] The string unit SU includes a plurality of NAND strings NS. The NAND string NS includes a set of a plurality of memory cells connected in series. Each of the plurality of NAND strings NS within the string unit SU is connected to any one of bit lines BL0 to BLm (m is an integer of 1 or more).

[0031] The NAND string NS includes a plurality of memory cells MC, a plurality of dummy memory cells DMC, one or more selection transistors ST1, and one or more selection transistors ST2. The number of memory cells MC and dummy memory cells DMC is arbitrary. Note that the dummy memory cells DMC may not be provided. In the example shown in FIG. 2, the NAND string NS includes 14 memory cells MC0 to MC13, 2 dummy memory cells DMC0 and DMC1, 2 selection transistors ST1, and 2 selection transistors ST2.

[0032] The memory cell MC is a memory element that stores data non-volatilely. The dummy memory cell DMC has the same configuration as the memory cell MC, but is used as a dummy and not used for data storage.

[0033] The memory cell MC and the dummy memory cell DMC include a control gate and a charge storage layer. The memory cell MC and the dummy memory cell DMC may be of the MONOS (Metal-Oxide-Nitride-Oxide-Silicon) type using an insulator for the charge storage layer, or of the FG (Floating Gate) type using a conductor for the charge storage layer. Hereinafter, the case where the memory cell MC and the dummy memory cell DMC are of the MONOS type will be described.

[0034] The selection transistors ST1 and ST2 are switching elements. The selection transistors ST1 and ST2 are respectively used for the selection of the string unit SU during various operations. The number of the selection transistors ST1 and ST2 is arbitrary, and there may be one or more of each.

[0035] In the example shown in FIG. 2, in the NAND string NS, in order from the source line SL side, the current paths of two selection transistors ST2, dummy memory cell DMC0, memory cells MC0 to MC13, dummy memory cell DMC1, and two selection transistors ST1 are connected in series. The drain of the selection transistor ST1 located at one end of the NAND string NS is connected to the bit line BL. Also, the source of the selection transistor ST2 located at the other end of the NAND string NS is connected to the source line SL.

[0036] The control gates of the memory cells MC0 to MC13 in the same block BLK are commonly connected to the word lines WL0 to WL13 respectively. More specifically, for example, the block BLK includes four string units SU0 to SU3. And each string unit SU includes a plurality of memory cells MC0 respectively. The control gates of the plurality of memory cells MC0 in the block BLK are commonly connected to one word line WL0. The same applies to the memory cells MC1 to MC13.

[0037] Similar to the memory cell MC, the control gates of the dummy memory cells DMC0 and DMC1 in the same block BLK are commonly connected to the dummy word lines DWL0 and DWL1 respectively.

[0038] The gates of a plurality of selection transistors ST1 within the string unit SU are commonly connected to one selection gate line SGD. More specifically, the gates of a plurality of selection transistors ST1 within the string unit SU0 are commonly connected to the selection gate line SGD0. The gates of a plurality of selection transistors ST1 within the string unit SU1 are commonly connected to the selection gate line SGD1. The gates of a plurality of selection transistors ST1 within the string unit SU2 are commonly connected to the selection gate line SGD2. The gates of a plurality of selection transistors ST1 within the string unit SU3 are commonly connected to the selection gate line SGD3.

[0039] The gates of a plurality of selection transistors ST2 within the block BLK are commonly connected to the selection gate line SGS. Note that, similar to the selection gate line SGD, the selection gate line SGS may be provided for each string unit SU.

[0040] The word lines WL0 to WL13, the dummy word lines DWL0 and DWL1, the selection gate lines SGD0 to SGD3, and the selection gate line SGS are respectively connected to the row decoder 18.

[0041] The bit line BL is commonly connected to one NAND string NS within each string unit SU of each block BLK. Each bit line BL is connected to the sense amplifier 19.

[0042] The source line SL is shared among, for example, a plurality of blocks BLK.

[0043] A set of a plurality of memory cells MC connected to a common word line WL within one string unit SU is denoted as, for example, "cell unit CU". In other words, the cell unit CU is a set of a plurality of memory cells MC that are collectively selected in a write operation or a read operation. A page is a unit of data that is collectively written (or read out) to the cell unit CU. For example, when the memory cell MC stores 1-bit data, the storage capacity of the cell unit CU is 1 page. Note that the cell unit CU may have a storage capacity of two or more pages based on the number of bits of data stored in the memory cell MC.

[0044] 1.1.3 Cross-sectional Structure of Memory Cell Array Next, with reference to FIG. 3, an example of the cross-sectional structure of the memory cell array 17 will be described. FIG. 3 is a cross-sectional view of the memory cell array 17. Note that in the example shown in FIG. 3, a part of the insulating layer is omitted.

[0045] In the following description, the direction perpendicular to the surface of the semiconductor substrate 30 is denoted as the Z direction. The direction intersecting the Z direction and in which the word line WL extends is denoted as the X direction. The direction intersecting the X direction and the Z direction and in which the bit line BL extends is defined as the Y direction.

[0046] As shown in FIG. 3, an insulating layer 31 is provided on the semiconductor substrate 30. The insulating layer 31 includes, for example, silicon oxide (SiO). Note that a circuit such as a row decoder 18 or a sense amplifier 19 may be provided in the region where the insulating layer 31 is formed below the memory cell array 17, that is, between the semiconductor substrate 30 and the semiconductor layer 32. On the insulating layer 31, a semiconductor layer 32 that functions as a source line SL is formed.

[0047] The semiconductor layer 32 includes, for example, three semiconductor layers 32a, 32b, and 32c. The semiconductor layer 32a is provided on the insulating layer 31. The semiconductor layer 32b is provided on the semiconductor layer 32a. The semiconductor layer 32c is provided on the semiconductor layer 32b. The semiconductor layer 32b is formed, for example, by replacing (replacing) a sacrificial layer provided between the semiconductor layer 32a and the semiconductor layer 32c. The semiconductor layers 32a to 32c include, for example, silicon. Further, the semiconductor layers 32a to 32c include, for example, phosphorus (P) as a semiconductor impurity. Note that the structure of the source line SL described above is an example. The structure of the source line SL is not limited to the above-described structure. For example, the source line SL may be formed of a single semiconductor layer 32. Further, for example, the semiconductor layer 32 may be removed and the semiconductor substrate 30 may function as the source line SL.

[0048] Above the semiconductor layer 32, 20 wiring layers 33 are provided spaced apart in the Z direction. The 20 wiring layers 33 function as two selection gate lines SGS, dummy word line DWL0, word lines WL0 to WL13, dummy word line DWL1, and two selection gate lines SGD in order from the semiconductor layer 32 side. The wiring layer 33 extends in the X direction. As the conductive material of the wiring layer 33, for example, a laminated structure of titanium nitride (TiN) / tungsten (W) is used. In this case, titanium nitride is formed so as to cover tungsten. Titanium nitride has a function as a barrier layer for suppressing the oxidation of tungsten or an adhesion layer for improving the adhesion of tungsten, for example, when tungsten is formed by CVD (chemical vapor deposition). Further, the wiring layer 33 may contain a high dielectric constant material such as aluminum oxide (AlO). In this case, the high dielectric constant material is formed so as to cover the conductive material. For example, in each of the wiring layers 33, a high dielectric constant material is provided so as to cover the top and bottom of the wiring layer 33 and the side surface of the memory pillar MP. Titanium nitride is provided so as to be in contact with the high dielectric constant material. Then, tungsten is provided so as to be in contact with titanium nitride and fill the inside of the wiring layer 33. For example, when aluminum oxide is provided as the high dielectric constant material, the memory cell MC is also referred to as a MANOS (Metal - Aluminum - Nitride - Oxide - Silicon) type.

[0049] The wiring layer 33 is separated, for example, for each block BLK by a slit SLT extending in the X direction. The bottom surface of the slit SLT is in contact with the semiconductor layer 32. For example, the inside of the slit SLT is filled with an insulating layer 34. The insulating layer 34 contains, for example, silicon oxide. Note that a conductive material may be provided in the slit SLT so as not to be in contact with the semiconductor layer 32 at the bottom surface of the slit SLT and not to be in contact with the wiring layer 33 at the side surface of the slit.

[0050] The topmost two-layer wiring layer 33 that functions as the selection gate line SGD is further separated in the Y direction for each string unit SU by, for example, a slit SHE extending in the X direction. In the example shown in FIG. 3, one slit SHE is provided between two slits SLT. That is, the example shown in FIG. 3 shows a case where two string units SU are included in one block BLK. Inside the slit SHE, it is embedded by an insulating layer 35. For example, the insulating layer 35 contains silicon oxide.

[0051] In the Y direction, between the two slits SLT, a plurality of memory pillars MP extending in the Z direction are arranged along the X direction. Note that the arrangement of the memory pillars MP between the two slits SLT is arbitrary. For example, the arrangement of the memory pillars MP may be a staggered arrangement of 4 columns, 8 columns, or 16 columns in the X direction. One memory pillar MP corresponds to one NAND string NS. For example, the memory pillar MP has a substantially cylindrical shape extending in the Z direction. The memory pillar MP penetrates through the 20-layer wiring layer 33. The bottom surface of the memory pillar MP reaches the semiconductor layer 32.

[0052] The memory pillar MP includes a block insulating film 36, a charge storage layer 37, a tunnel insulating film 38, a semiconductor layer 39, a core layer 40, and a cap film 41. The block insulating film 36 and the core layer 40 contain, for example, silicon oxide. The tunnel insulating film 38 contains, for example, silicon oxynitride (SiON). Note that the tunnel insulating film 38 may contain silicon oxide. The charge storage layer 37 contains, for example, silicon nitride (SiN). The semiconductor layer 39 and the cap film 41 contain, for example, silicon.

[0053] On a part of the side surface and the bottom surface of the memory pillar MP, a block insulating film 36, a charge storage layer 37, and a tunnel insulating film 38 are laminated in order from the outer periphery. More specifically, in the same layer of the semiconductor layer 32b and in the vicinity thereof, the block insulating film 36, the charge storage layer 37, and the tunnel insulating film 38 on the side surface of the memory pillar MP are removed. A semiconductor layer 39 is provided so as to be in contact with the side surface and the bottom surface of the tunnel insulating film 38 and the semiconductor layer 32b. The semiconductor layer 39 is a region where channels of the memory cell MC, the dummy memory cell DMC, and the selection transistors ST1 and ST2 are formed. Therefore, the semiconductor layer 39 functions as a signal line connecting the current paths of the selection transistor ST2, the dummy memory cell DMC0, the memory cells MC0 to MC13, the dummy memory cell DMC1, and the selection transistor ST1. The inside of the semiconductor layer 39 is filled with a core layer 40. Note that the structure of the memory pillar MP described above is an example. The structure of the memory pillar MP is not limited to the above. For example, a block insulating film 36, a charge storage layer 37, and a tunnel insulating film 38 may be provided on the side surface of the memory pillar MP, and the block insulating film 36, the charge storage layer 37, and the tunnel insulating film 38 on the bottom surface of the memory pillar MP may be removed. In this case, on the bottom surface of the memory pillar MP, the semiconductor layer 39 and the semiconductor layer 32 (source line SL) are in contact with each other.

[0054] At the upper part of the memory pillar MP, a cap film 41 is provided on the upper ends of the semiconductor layer 39 and the core layer 40. The side surface of the cap film 41 is in contact with the tunnel insulating film 38.

[0055] The memory cells MC0 to MC13 are each constituted by a memory pillar MP and 14 wiring layers 33 each functioning as word lines WL0 to WL13. Similarly, the dummy memory cells DMC0 and DMC1 are each constituted by a memory pillar MP and 2 wiring layers 33 each functioning as dummy word lines DWL0 and DWL1. The selection transistor ST1 is constituted by a memory pillar MP and a wiring layer 33 functioning as a selection gate line SGD. The selection transistor ST2 is constituted by a memory pillar MP and a wiring layer 33 functioning as a selection gate line SGS. In the example shown in FIG. 3, two wiring layers 33 each functioning as the selection gate lines SGD and SGS are provided, but one or more layers may be provided.

[0056] On the cap film 41, a conductor 42 functioning as a contact plug CP1 is provided. On the conductor 42, a conductor 43 functioning as a contact plug CP2 is provided. For example, the conductors 42 and 43 have a substantially cylindrical shape extending in the Z direction. The conductors 42 and 43 contain, for example, a metal material such as copper (Cu) or tungsten as the conductive material.

[0057] On the conductor 43, a wiring layer 44 functioning as a bit line BL is provided. The wiring layer 44 extends in the Y direction. The wiring layer 44 contains, for example, copper as the conductive material.

[0058] 1.2 Threshold Voltage Distribution of Memory Cells Next, with reference to FIG. 4, an example of the threshold voltage distribution that the memory cell MC can have will be described. FIG. 4 is a diagram showing the threshold voltage distribution and data assignment in the case where the memory cell MC is a TLC (Triple Level Cell) that can store 3-bit (8-value) data. Note that the number of bits of data that the memory cell MC can store is arbitrary. For example, the memory cell MC may be an SLC (Single Level Cell) that can store 1-bit (2-value) data, or an MLC (Multi Level Cell) that can store 2-bit (4-value) data. Further, the memory cell MC may be a QLC (Quad Level Cell) that can store 4-bit (16-value) data, or a PLC (Penta Level Cell) that can store 5-bit (32-value) data.

[0059] As shown in FIG. 4, when the memory cell MC is a TLC, the threshold voltage of each memory cell MC takes a value included in any of, for example, 8 discrete distributions. Hereinafter, the 8 distributions are denoted as the "Er" state, "A" state, "B" state, "C" state, "D" state, "E" state, "F" state, and "G" state in ascending order of the threshold voltage.

[0060] The "Er" state corresponds to, for example, the data erased state. And the "A" to "G" states correspond to the state where data is written by injecting charge into the charge storage layer 37. In the write operation, let the verify voltages corresponding to each threshold voltage distribution be VA to VG. Then, these voltage values are in the relationship of VA < VB < VC < VD < VE < VF < VG < VREAD. The voltage VREAD is the voltage applied to the non-selected word line WL during the read operation. When the voltage VREAD is applied to the gate of the memory cell MC, the memory cell MC is turned on regardless of the stored data. In the following description, the word line WL selected during the write operation or read operation is denoted as the "selected word line WL", and the non-selected word line WL is denoted as the "non-selected word line WL".

[0061] More specifically, the threshold voltage included in the "Er" state is less than the voltage VA. The threshold voltage included in the "A" state is equal to or greater than the voltage VA and less than the voltage VB. The threshold voltage included in the "B" state is equal to or greater than the voltage VB and less than the voltage VC. The threshold voltage included in the "C" state is equal to or greater than the voltage VC and less than the voltage VD. The threshold voltage included in the "D" state is equal to or greater than the voltage VD and less than the voltage VE. The threshold voltage included in the "E" state is equal to or greater than the voltage VE and less than the voltage VF. The threshold voltage included in the "F" state is equal to or greater than the voltage VF and less than the voltage VG. And the threshold voltage included in the "G" state is equal to or greater than the voltage VG and less than the voltage VREAD.

[0062] Note that the set value of the verification voltage and the set value of the read voltage corresponding to each state may be the same or different.

[0063] Hereinafter, the read operations corresponding to the "A" to "G" states are respectively referred to as AR read operation, BR read operation, CR read operation, DR read operation, ER read operation, FR read operation, and GR read operation. The AR read operation determines whether the threshold voltage of the memory cell MC is less than the voltage VA. The BR read operation determines whether the threshold voltage of the memory cell MC is less than the voltage VB. The CR read operation determines whether the threshold voltage of the memory cell MC is less than the voltage VC. The DR read operation, ER read operation, FR read operation, and GR read operation are the same.

[0064] As described above, each memory cell MC can take eight states by having any one of eight threshold voltage distributions. By assigning these states to "000" to "111" in binary notation, each memory cell MC can hold 3-bit data. Hereinafter, the 3-bit data will be denoted as Lower bit, Middle bit, and Upper bit, respectively. Also, the set of Lower bits written (or read) collectively to the cell unit CU is called the Lower page, the set of Middle bits is called the Middle page, and the set of Upper bits is called the Upper page.

[0065] In the example of FIG. 4, data is assigned to each memory cell MC included in each threshold voltage distribution as follows to "Upper bit / Middle bit / Lower bit". "Er" state: "111" data "A" state: "110" data "B" state: "100" data "C" state: "000" data "D" state: "010" data "E" state: "011" data "F" state: "001" data "G" state: "101" data

[0066] When reading the data assigned in this way, the Lower bit is determined by the AR read operation and the ER read operation. The Middle bit is determined by the BR read operation, the DR read operation, and the FR read operation. The Upper bit is determined by the CR read operation and the GR read operation. That is, the values of the Lower bit, Middle bit, and Upper bit are determined by two, three, and two read operations, respectively. Hereinafter, this data assignment will be referred to as "2-3-2 code". Note that the assignment of data to the "Er" to "G" states is not limited to the 2-3-2 code.

[0067] 1.3 Write operation Next, an example of the writing operation will be described. The writing operation includes a program operation and a program verification operation. The sequencer 14 repeats a combination of a program operation and a program verification operation (hereinafter referred to as a "program loop") to increase the threshold voltage of the memory cell MC to a target level.

[0068] The program operation is an operation of injecting electrons into the charge storage layer 37 of the memory cell MC (hereinafter also referred to as the "selected memory cell MC") selected as the target of the writing operation based on the write data, or prohibiting the injection of electrons into the charge storage layer 37. When electrons are injected into the charge storage layer 37, the threshold voltage of the selected memory cell MC increases. In other words, the program operation is an operation of increasing or maintaining the threshold voltage of the selected memory cell MC based on the write data. Hereinafter, among the selected memory cells MC, the memory cell MC whose threshold voltage is increased is also referred to as the "selected memory cell MC to be programmed". Also, among the selected memory cells MC, the memory cell MC whose threshold voltage is not increased is also referred to as the "selected memory cell MC prohibited from programming".

[0069] In the program operation of the present embodiment, hot carriers are injected into the charge storage layer 37 of the selected memory cell MC to be programmed. Hereinafter, the program operation using hot carrier injection is also referred to as a "program operation assisted by HCI (Hot Carrier Injection)".

[0070] More specifically, at least one memory cell MC that is not selected as an object of the write operation in the same NAND string NS as the selected memory cell MC (hereinafter also referred to as "non-selected memory cell MC") is used to generate hot carriers, that is, high-temperature electrons. The generated electrons are injected into the charge storage layer 37 of the selected memory cell MC. By performing a program operation assisted by HCI, the voltage (program voltage) applied to the selected word line WL can be reduced as compared with a method using Fowler-Nordheim (FN) tunnel current.

[0071] The program verify operation is an operation that reads data from the selected memory cell MC after the program operation and determines whether the threshold voltage of the selected memory cell MC has reached a target level. The selected memory cell MC to be programmed whose threshold voltage has reached the target level is prohibited from being programmed in subsequent program loops.

[0072] 1.3.1 Write Order First, with reference to FIG. 5, an example of the write order of data in the NAND string NS will be described. FIG. 5 is a diagram showing the write order of data in the NAND string NS.

[0073] As shown in FIG. 5, when the write operation is executed, the memory cells MC on the bit line BL side (selected transistor ST1 side) are sequentially selected as the write targets. Note that the memory cells MC on the source line SL side (selected transistor ST2 side) may be sequentially selected as the write targets.

[0074] In the example shown in FIG. 5, the sequencer 14 first selects the word line WL13 and executes a write operation. Next, the sequencer 14 sequentially selects the word lines WL12 to WL1, and finally selects the word line WL0 to execute the write operation corresponding to each word line WL. In other words, the sequencer 14 first selects the memory cell MC13. Then, the sequencer 14 sequentially selects the memory cells MC12 to MC1, and finally selects the memory cell MC0.

[0075] 1.3.2 Program Operation Next, with reference to FIGS. 6 to 9, an example of the program operation will be described. FIG. 6 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC to be programmed, the voltage of each wiring, and the band diagram of the channel during the program operation. FIG. 7 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC prohibited from being programmed, the voltage of each wiring, during the program operation. FIG. 8 is a diagram showing an example of the state of each transistor in the NAND string NS during the program operation. FIG. 9 is a graph showing an example of the relationship between the current Icell flowing through the switch memory cell MC and the voltage VSW of the switch word line WL.

[0076] In the following description, the string unit SU selected as the target of the write operation is referred to as "selected string unit SU". The selected gate line SGD corresponding to the selected string unit SU is referred to as "selected gate line SGD_s". Also, the string unit SU not selected as the target of the write operation is referred to as "non-selected string unit SU". The selected gate line SGD corresponding to the non-selected string unit SU is referred to as "selected gate line SGD_u". The bit line BL corresponding to the selected memory cell MC to be programmed is referred to as "bit line BL_p". Also, the bit line BL corresponding to the selected memory cell MC prohibited from being programmed is referred to as "bit line BL_i".

[0077] As shown in FIGS. 6 and 7, in this embodiment, in the program operation, a switch word line WL (switch WL) is provided separately from the selected word line WL (selected WL) and the non-selected word line WL (non-selected WL). The switch word line WL is a non-selected word line WL connected to a memory cell MC that generates hot carriers. In a memory cell MC corresponding to the switch word line WL (hereinafter, also referred to as "switch memory cell MC"), an electric field (potential difference) is formed between the drain and the source, and by applying an appropriate voltage to the switch word line WL, hot carriers (HC) are generated.

[0078] For example, when the write operation is executed sequentially from the memory cell MC on the bit line BL side, the switch word line WL is selected from the non-selected word lines WL located on the source line SL side from the selected word line WL. The switch word line WL may or may not be adjacent to the selected word line WL. Also, a plurality of adjacent non-selected word lines WL may be selected as the switch word line WL. When the word line WL0 is the selected word line WL, the dummy word line DWL0 arranged on the source line SL side, or at least one of the plurality of selected gate lines SGS can be selected as the switch word line WL.

[0079] As shown in FIG. 6, during the program operation, the sense amplifier 19 applies a voltage VBL to the bit line BL_p. The voltage VBL is a voltage higher than the voltage applied to the source line SL (for example, the ground voltage VSS). The voltage VBL is preferably set to a voltage 1V or more higher than the voltage VSS applied to the source line SL. Thereby, in the switch memory cell MC, a relatively strong electric field for generating hot carriers can be generated in the extending direction of the semiconductor layer 39, that is, the extending direction of the channel. In other words, an electric field can be generated between the drain and the source of the switch memory cell MC. On the other hand, as shown in FIG. 7, in order not to generate hot carriers, the sense amplifier 19 applies the same voltage VSS as the source line SL to the bit line BL_i.

[0080] As shown in FIGS. 6 and 7, a voltage VSS is applied to the source line SL. The row decoder 18 applies a voltage VON to the selected gate line SGD_s and the selected gate line SGS. The voltage VON is a positive voltage that turns on the selection transistors ST1 and ST2. The voltage VON is higher than the voltage VBL. The row decoder 18 applies a voltage VPASS to the non-selected word line WL and the dummy word lines DWL0 and DWL1. The voltage VPASS is a voltage that turns on the memory cell MC and the dummy memory cell DMC regardless of the threshold voltage. The voltage VPASS is higher than the voltage VBL. The voltage VPASS may be the same as or different from the voltage VON. The row decoder 18 applies a voltage VPGM to the selected word line WL. The voltage VPGM is a program voltage for injecting electrons into the charge storage layer of the selected memory cell MC to be programmed. The voltage VPGM is higher than the voltage VPASS. Note that the voltage VPGM can be stepped up each time the program loop is repeated. The row decoder 18 applies a voltage VSW to the switch word line WL. The voltage VSW is lower than the voltage VPASS. Therefore, the relationship among the voltage VPGM, the voltage VPASS, and the voltage VSW is VPGM > VPASS > VSW. For example, the voltage VSW is set to a voltage value equal to or lower than the threshold voltage of the switch memory cell MC. More specifically, the voltage VSW is a voltage that places the switch memory cell MC in a state in the sub-threshold region, which is close to cutoff.

[0081] As shown in FIG. 8, for example, word line WL8 is selected as the select word line WL. As the non-select word lines WL, word lines WL0 to WL6 and WL9 to WL13 are selected. As the switch word line WL, word line WL7 is selected. In this case, the non-select memory cells MC (non-select MC) located closer to the bit line BL side than the select memory cell MC (select MC) have already had data written to them. Therefore, the threshold voltages of memory cells MC9 to MC13 are in any state from “Er” to “G”. The switch memory cells MC (switch MC) and non-select memory cells MC located closer to the source line SL side than the select memory cell MC are in an unwritten state. Therefore, the threshold voltages of memory cells MC0 to MC7 are in the “Er” state (erase state). Note that the switch word line WL is selected from among the non-select word lines WL corresponding to the non-select memory cells MC in the “Er” state.

[0082] The voltages described with reference to FIGS. 6 and 7 are applied to the memory pillar MP. As a result, the select transistors ST1 and ST2, the dummy memory cells DMC0 and DMC1, the non-select memory cells MC, and the select memory cell MC are turned on. Hereinafter, a transistor in the on state is also referred to as an “on cell”.

[0083] Next, returning to FIG. 6, the state of the channel of the memory pillar MP will be described. In the band diagram of the channel in FIG. 6, the vertical axis E indicates the level of electron energy. The horizontal axis indicates the channel position.

[0084] When the above-described voltage is applied to the memory pillar MP corresponding to the program target, the select transistor ST1, the dummy memory cell DMC1, the non-select memory cell MC located closer to the bit line BL side than the select memory cell MC, and the select memory cell MC are in the on state. Therefore, a channel is formed in the semiconductor layer 39 from the end on the bit line BL side to the select word line WL (select memory cell MC). The potential of the channel on the bit line BL side rises to the same voltage VBL as the bit line BL_p.

[0085] Also, the non - selected memory cell MC located on the source line SL side from the selection transistor ST2, the dummy memory cell DMC0, and the switch memory cell MC is set to the on state. Therefore, a channel is formed in the semiconductor layer 39 from the end on the source line SL side to the switch word line WL and the non - selected word line WL (non - selected memory cell MC) adjacent to the source line SL side. The potential of the channel on the source line SL side is the same voltage VSS as the source line SL. In the region of the semiconductor layer 39 corresponding to the switch word line WL, an electric field with a potential difference (VBL - VSS) is generated in the extending direction of the channel. In other words, an electric field with a potential difference (VBL - VSS) is formed between the drain and source of the switch memory cell MC.

[0086] Therefore, as shown in the band diagram of the channel in FIG. 6, in the region corresponding to the switch word line WL (switch memory cell MC), the band (potential) is bent. In this state, the row decoder 18 applies the voltage VSW to the switch word line WL. As a result, electrons on the source line SL side cross the potential barrier shown by the solid line and are injected into the bit line BL side. That is, hot carriers are generated. The electrons injected into the channel on the bit line BL side are injected into the charge storage layer 37 of the selected memory cell MC to be programmed due to the potential difference between the selected word line WL and the channel. When the voltage VSW is not applied to the switch word line WL and the switch memory cell MC is in the cut - off state, the potential barrier from the source line SL side to the bit line BL side is larger than that shown by the solid line as shown by the dashed - dotted line.

[0087] As shown in FIG. 7, when the above - mentioned voltage is applied to the memory pillar MP corresponding to program inhibition, the potential of the channel on the bit line BL side is the same voltage VSS as the bit line BL_i. Therefore, no electric field is formed between the drain and source of the switch memory cell MC. That is, no hot carriers are generated. Therefore, no electrons are injected into the charge storage layer 37 of the selected memory cell MC for which program inhibition is set.

[0088] Next, the optimal range of the voltage VSW for generating hot carriers will be described.

[0089] As shown in FIG. 9, the vertical axis of the graph indicates the current Icell flowing through the memory pillar MP, that is, the current flowing between the drain and source of the switch memory cell MC. The horizontal axis of the graph indicates the voltage applied to the switch word line WL, that is, the voltage applied to the control gate of the switch memory cell MC. The voltage Vth indicates the threshold voltage of the switch memory cell MC. For example, let the voltage at which the current Icell starts to flow be Vg0. In this case, the range from the voltage Vg0 to the voltage Vth is the subthreshold region of the switch memory cell MC. The voltage VSW is set to a voltage higher than the voltage Vg0 and lower than or equal to the voltage Vth. Let the lower limit value of the optimal range of the voltage VSW be the voltage Vg1, and the upper limit value be the voltage Vg2. The voltages Vg0, Vg1, Vg2, and Vth are in the relationship of Vg0 < Vg1 < Vg2 < Vth. When the voltage VSW is lower than the voltage Vg1, the switch memory cell MC is in a relatively strong cutoff state. Therefore, a sufficient current does not flow between the drain and source of the switch memory cell MC. That is, the current Icell does not flow sufficiently. For this reason, hot carriers are not generated. Also, when the voltage VSW is higher than the voltage Vg2, the switch memory cell MC is in a relatively strong on state. Therefore, a channel is formed and hot carriers are not generated.

[0090] Therefore, even if a voltage VSW outside the optimal range is applied to the switch word line WL, the threshold voltage of the selected memory cell MC cannot be efficiently changed.

[0091] 1.3.3 Voltages of Each Wiring During Program Operation Next, with reference to FIG. 10, an example of the voltages of each wiring during program operation will be described. FIG. 10 is a timing chart showing an example of the voltages of each wiring during program operation.

[0092] As shown in FIG. 10, first, at time t0, the row decoder 18 applies a voltage VON to the selection gate line SGD_s and the selection gate line SGS based on the control of the sequencer 14. The selection gate line SGD_s corresponds to the selection string unit SU. Also, the row decoder 18 applies a voltage VPASS to the dummy word line DWL and the non-selection word line WL. As a result, the selection transistor ST2, the selection transistor ST1 of the selection string unit SU, the dummy memory cell DMC, and the non-selection memory cell MC are turned on. The row decoder 18 applies a voltage VSS to the selection gate line SGD_u corresponding to the non-selection string unit SU, the selection word line WL, and the switch word line WL. The selection transistor ST1 of the non-selection string unit SU is turned off. The sense amplifier 19 applies a voltage VSS to the bit lines BL_p and BL_i based on the control of the sequencer 14. A voltage VSS is applied to the source line SL.

[0093] Next, at time t1, the row decoder 18 applies a voltage VPGM to the selection word line WL. As a result, the selection memory cell MC is turned on.

[0094] Next, at time t2, the row decoder 18 applies a voltage VSW to the switch word line WL. In the example shown in FIG. 10, a case where the voltage VSW is lower than the voltage VSS is shown, but the voltage VSW does not have to be a negative voltage.

[0095] Next, at time t3, the sense amplifier 19 applies a voltage VBL to the bit line BL_p. As a result, hot carriers (electrons) are generated in the switch memory cell MC corresponding to the program target. The generated electrons are injected into the charge storage layer 37 of the selection memory cell MC corresponding to the program target. During the period from time t3 to t4, the injection of electrons is executed.

[0096] Next, at time t4, the sense amplifier 19 applies a voltage VSS to the bit line BL_p.

[0097] Next, at time t5, the row decoder 18 applies the voltage VSS to the selection gate lines SGD_s and SGS, the dummy word line DWL, the non-selection word line WL, the selection word line WL, and the switch word line WL. Thereby, the program operation ends.

[0098] In the example shown in FIG. 10, the case where the voltage VPGM is applied to the selection word line WL at time t1, the voltage VSW is applied to the switch word line WL at time t2, and the voltage VBL is applied to the bit line BL_p at time t3 has been described. However, the order in which the voltages are applied to the selection word line WL, the switch word line WL, and the bit line BL_p is not limited to this. For example, the voltage VSW may be applied to the switch word line WL after the voltage VBL is applied to the bit line BL_p.

[0099] 1.4 Effects of the Present Embodiment With the configuration according to the present embodiment, the semiconductor memory device can reduce power consumption. This effect will be described in detail.

[0100] For example, in a NAND type flash memory, as a method of injecting electrons into the charge storage layer, a method of injecting charges into the charge storage layer by FN tunnel current is known. In this case, a high-voltage program voltage is applied to the control gate of the selected memory cell MC. The program voltage does not depend on the size of the memory cell MC. Therefore, due to the breakdown voltage limit between the selection word line WL and the non-selection word line WL, the interval of the word line WL in the Z direction is rate-limited. Also, when the total number of word lines WL connected to one NAND string NS increases, the area (number) of the high-voltage transistor that supplies the program voltage increases, and the chip size increases.

[0101] On the other hand, in the configuration according to the present embodiment, in the program operation, at least one of the non-selected word lines WL can be selected as the switch word line WL. The semiconductor memory device 1 can apply a voltage VSW lower than the program voltage VPGM applied to the selected word line WL and the voltage VPASS applied to the non-selected word line WL to the switch word line WL. The semiconductor memory device 1 can form an electric field between the drain and source of the switch memory cell MC to generate hot carriers (hot electrons). The semiconductor memory device 1 can inject hot electrons into the charge storage layer of the selected memory cell MC. By executing the program operation assisted by HCI, the program voltage VPGM can be reduced compared to the FN tunneling current method. Therefore, the semiconductor memory device 1 can reduce power consumption.

[0102] Furthermore, in the configuration according to the present embodiment, since the semiconductor memory device 1 can reduce the program voltage, the interval between the word lines WL in the Z direction can be decreased. Furthermore, in the configuration according to the present embodiment, an increase in the area of the high-voltage transistor that supplies the program voltage can be suppressed. Therefore, an increase in the chip size can be suppressed.

[0103] 1.5 First Modification of the First Embodiment Next, two examples of the modification of the first embodiment will be shown. Hereinafter, the description will focus on the differences from the first embodiment.

[0104] 1.5.1 First Modification of the First Embodiment First, with reference to FIG. 11, the first modification of the first embodiment will be described. In the first modification, the case where two switch word lines WL are selected will be described. FIG. 11 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC to be programmed and the voltages of the respective wirings during the program operation.

[0105] As shown in FIG. 11, two adjacent non-selected word lines WL may be selected as the switch word line WL. Note that the number of switch word lines WL may be three or more.

[0106] Two memory cells MC corresponding to each of the two switch word lines WL function as one switch memory cell MC. When there are two switch word lines WL, the effective channel length of the switch memory cell MC is longer than the channel length of the switch memory cell MC when there is one switch word line WL. For this reason, the voltage VSW when there are two switch word lines WL is set higher than the voltage VSW when there is one switch word line WL.

[0107] 1.5.2 Second modification of the first embodiment Next, with reference to FIG. 12, a second modification of the first embodiment will be described. In the second modification, a case will be described in which a non-selection word line WL is provided between the selection word line WL and the switch word line WL. FIG. 12 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC to be programmed and the voltages of the respective wirings during the program operation.

[0108] As shown in FIG. 12, there may be a non-selection word line WL between the selection word line WL and the switch word line WL. A voltage VMID may be applied to the non-selection word line WL located between the selection word line WL and the switch word line WL, or it may be in a floating state. The voltage VMID is a voltage higher than the voltage VBL and lower than the voltage VPASS.

[0109] The selection transistor ST1, the dummy memory cell DMC1, the non-selection memory cell MC located on the bit line BL side from the switch memory cell MC, and the selection memory cell MC are in the on state. Therefore, a channel is formed in the semiconductor layer 39 from the end on the bit line BL side to the non-selection word line WL located between the selection word line WL and the switch word line WL. The potential of the channel on the bit line BL side rises to the same voltage VBL as the bit line BL_p. Also, the selection transistor ST2, the dummy memory cell DMC0, and the non-selection memory cell MC located on the source line SL side from the switch memory cell MC are set in the on state. Therefore, a channel is formed in the semiconductor layer 39 from the end on the source line SL side to the non-selection word line WL (non-selection memory cell MC) adjacent to the switch word line WL on the source line SL side. The potential of the channel on the source line SL side is the same voltage VSS as the source line SL. Therefore, similar to the first embodiment, an electric field is formed between the drain and source of the switch memory cell MC. Thereby, hot carriers are generated.

[0110] 1.5.3 Effects according to this modification With the configuration according to the first modification or the second modification, the same effects as those of the first embodiment can be obtained.

[0111] 2. Second Embodiment Next, the second embodiment will be described. In the second embodiment, the case of generating hot carriers using channel boost will be described. Hereinafter, the description will focus on the points different from the first embodiment.

[0112] 2.1 Program operation First, with reference to FIGS. 13 to 15, an example of the program operation in this embodiment will be described. FIG. 13 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC to be programmed, the voltage of each wiring, and the band diagram of the channel during the program operation. FIG. 14 is a diagram showing an example of the relationship between the state of the channel of the memory pillar MP including the selected memory cell MC prohibited from being programmed, the voltage of each wiring, and the band diagram of the channel during the program operation. FIG. 15 is a diagram showing an example of the state of each transistor in the NAND string NS during the program operation.

[0113] As shown in FIGS. 13 and 14, the voltages applied to the bit lines BL_p and BL_i, the source line SL, the select gate line SGS, the select word line WL, the non-select word line WL, and the dummy word line WL are the same as the description using FIGS. 6 and 7 of the first embodiment.

[0114] In this embodiment, the row decoder 18 applies a voltage VSGD to the select gate SGD_s. The voltage VSGD is a voltage higher than the voltage VSS and lower than the voltage VBL. As shown in FIG. 15, in the memory pillar MP (NAND string NS) corresponding to the object to be programmed, since the voltage VBL is applied to the bit line BL_p, the select transistor ST1 is in the cut-off state. Hereinafter, a transistor in the cut-off state will also be referred to as an "off cell". On the other hand, in the memory pillar MP (NAND string NS) corresponding to the program prohibition, since the voltage VSS is applied to the bit line BL_i, the select transistor ST1 is in the on state.

[0115] As shown in FIG. 13, the row decoder 18 first applies a voltage VOFF to the switch word line WL. The voltage VOFF is lower than the voltage VSW. The voltage VOFF is a voltage that turns off the memory cell MC. As a result, in the memory pillar MP corresponding to the program target, the semiconductor layer 39 between the select gate line SGD_s and the switch word line WL is made floating. In this state, the row decoder 18 applies a voltage VPGM to the select word line WL and a voltage VPASS to the non-select word line WL. Then, due to the coupling between the select word line WL and the non-select word line WL and the semiconductor layer 39, the potential of the semiconductor layer 39 rises (hereinafter referred to as "channel boost"). As a result, a channel on the bit line BL side is formed between the select gate line SGD_s and the switch word line WL. Let the boost voltage of the channel at this time be VBST. The voltage VBST is higher than the voltage VSS.

[0116] Also, the potential of the channel on the source line SL side is the same voltage VSS as the source line SL, similar to the first embodiment. Therefore, due to the potential difference between the voltage VBST and the voltage VSS, an electric field is formed between the drain and source of the switch memory cell MC.

[0117] For this reason, as in the band diagram of the channel shown in FIG. 13, the band (potential) is bent in the region corresponding to the switch word line WL (switch memory cell MC).

[0118] In this state, the row decoder 18 applies a voltage VSW to the switch word line WL. As a result, electrons on the source line SL side cross the potential barrier and are injected into the bit line BL side. That is, hot carriers are generated. The electrons injected into the channel on the bit line BL side are injected into the charge storage layer 37 of the selected memory cell MC to be programmed due to the potential difference between the selected word line WL and the channel. When the voltage VSW is not applied to the switch word line WL and the switch memory cell MC is in the cutoff state, the potential barrier from the source line SL side to the bit line BL side is larger than that indicated by the solid line as shown by the dashed-dotted line.

[0119] As shown in FIG. 14, when the above-described voltage is applied to the memory pillar MP including the selected memory cell MC for which programming is prohibited, the selection transistor ST1 is turned on. Therefore, similar to the description using FIG. 7 of the first embodiment, the potential of the channel on the bit line BL side is the same voltage VSS as the bit line BL_i. For this reason, an electric field is not formed between the drain and source of the switch memory cell MC. That is, hot carriers are not generated. Therefore, electrons are not injected into the charge storage layer 37 of the selected memory cell MC for which programming is prohibited.

[0120] 2.2 Voltages of Each Wiring During Program Operation Next, with reference to FIG. 16, an example of the voltage of each wiring during the program operation will be described. FIG. 16 is a timing chart showing an example of the voltage of each wiring during the program operation.

[0121] As shown in FIG. 16, first, at time t0, the sense amplifier 19 applies a voltage VBL to the bit line BL_p. Also, the sense amplifier 19 applies a voltage VSS to the bit line BL_i. The row decoder 18 applies a voltage VSS to the selected gate lines SGD_s and SGD_u, the selected gate line SGS, the dummy word line DWL, the non-selected word line WL, the selected word line WL, and the switch word line WL. A voltage VSS is applied to the source line SL.

[0122] Next, at time t1, the row decoder 18 applies a voltage VSGD to the selected gate line SGD_s. As a result, the selected transistor ST1 corresponding to the program target of the selected string unit SU is turned off. The selected transistor ST1 corresponding to the program prohibition of the selected string unit SU is turned on. Also, the row decoder 18 applies a voltage VON to the selected gate line SGD_u and the selected gate line SGS. As a result, the selected transistor ST2 and the selected transistor ST1 of the non-selected string unit SU are turned on. Further, the row decoder 18 applies a voltage VOFF to the switch word line WL. As a result, the switch memory cell MC is turned off. As a result, in the memory pillar MP corresponding to the program target of the selected string unit SU, the semiconductor layer 39 between the selected gate line SGD_s and the switch word line WL is in a floating state.

[0123] In this state, the row decoder 18 applies a voltage VPASS to the dummy word line DWL and the non-selected word line WL. Also, the row decoder 18 applies a voltage VPGM to the selected word line WL. As a result, the dummy memory cell DMC, the non-selected memory cell MC, and the selected memory cell MC are turned on. In the memory pillar MP corresponding to the program target of the selected string unit SU, a channel boosted to a voltage VBST is formed between the selected gate line SGD_s and the switch word line WL by channel boost.

[0124] Next, at time t2, the row decoder 18 applies a voltage VSW to the switch word line WL. As a result, hot carriers (electrons) are generated in the switch memory cell MC corresponding to the program target. The generated electrons are injected into the charge storage layer 37 of the selected memory cell MC corresponding to the program target. During the period from time t2 to t3, the injection of electrons is executed.

[0125] Next, at time t3, the row decoder 18 applies a voltage VOFF to the switch word line WL.

[0126] Next, at time t4, the row decoder 18 applies a voltage VSS to the selection gate lines SGD_s and SGD_u, the selection gate line SGS, the dummy word line DWL, the non-selection word line WL, the selection word line WL, and the switch word line WL. Also, the sense amplifier 19 applies a voltage VSS to the bit line BL_p. Thereby, the program operation ends.

[0127] 2.3 Effects according to this embodiment With the configuration according to this embodiment, the same effects as those of the first embodiment can be obtained.

[0128] Note that the first modification example or the second modification example of the first embodiment can be applied to this embodiment. That is, a plurality of adjacent switch word lines WL may be selected, or a non-selection word line WL may be provided between the selection word line WL and the switch word line WL.

[0129] 3. Modification examples, etc. The semiconductor memory device according to the above embodiment includes a first selection transistor (ST1), a first memory cell (selected MC), a second memory cell (switch MC), a third memory cell (non-selected MC), and a second selection transistor (ST2) in which each current path is connected in series, a first memory string (NS), a bit line (BL) connected to the first selection transistor, a source line (SL) connected to the second selection transistor, a first selection gate line (SGD_s) connected to the gate of the first selection transistor, a second selection gate line (SGS) connected to the gate of the second selection transistor, a first word line (selected WL) connected to the gate of the first memory cell, a second word line (switch WL) connected to the gate of the second memory cell, a third word line (non-selected WL) connected to the gate of the third memory cell, and a control circuit (14) configured to execute a write operation including a program operation and a program verify operation. In the program operation of the first memory cell, when writing data to the first memory cell, the control circuit applies a first voltage (VBL) to the bit line BL, applies a second voltage (VSS) lower than the first voltage to the source line, applies a third voltage (VON) higher than the first voltage to the first selection gate line, applies a fourth voltage (VON) higher than the first voltage to the second selection gate line, applies a program voltage (VPGM) to the first word line, applies a fifth voltage (VSW) to the second word line, and applies a sixth voltage (VPASS) higher than the fifth voltage and lower than the program voltage to the third word line.

[0130] With the configuration according to the above embodiment, the semiconductor memory device can reduce power consumption.

[0131] Note that various modifications can be applied, not limited to the above-described embodiment.

[0132] For example, in the above embodiment, in the data writing order in the NAND string NS, the case where the memory cells MC on the bit line BL side are sequentially selected has been described, but the memory cells on the source line SL side may be sequentially selected. In this case, the switch word line WL is selected from the non-selection word lines WL located on the bit line BL side from the selection word line WL. Note that, similar to the above embodiment, the order in which voltages are applied to the selection word line WL, the switch word line WL, and the bit line BL_p can be arbitrarily set.

[0133] Furthermore, "connection" in the above embodiment includes a state where, for example, a transistor or a resistor or the like is interposed in between and indirectly connected.

[0134] Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Explanation of Reference Numerals

[0135] 1…Semiconductor memory device, 2…Memory controller, 10…Input / output circuit, 11…Logic control circuit, 12…Address register, 13…Command register, 14…Sequencer, 15…Ready / Busy circuit, 16…Voltage generation circuit, 17…Memory cell array, 18…Row decoder, 19…Sense amplifier, 20…Data register, 21…Column decoder, 30…Semiconductor substrate, 31, 34, 35…Insulating layer, 32, 32a~32c…Semiconductor layer, 33, 44…Wiring layer, 36…Block insulating film, 37…Charge storage layer, 38…Tunnel insulating film, 39…Semiconductor layer, 40…Core layer, 41…Cap film, 42, 43…Conductor, BL, BL0~BLm…Bit line, BLK, BLK0~BLK3…Block, CP1, CP2…Contact plug, DMC, DMC0, DMC1…Dummy memory cell, DWL, DWL0, DWL1…Dummy word line, MC, MC0~MC13…Memory cell, SGD, SGD0~SGD3…Select gate line, ST1, ST2…Select transistor, SU, SU0~SU3…String unit, WL, WL0~WL13…Word line

Claims

1. A first memory string including a first selection transistor, a first memory cell, a second memory cell, a third memory cell, and a second selection transistor, in which each current path is connected in series; A bit line connected to the first selection transistor; A source line connected to the second selection transistor; A first selection gate line connected to the gate of the first selection transistor; A second selection gate line connected to the gate of the second selection transistor; A first word line connected to the gate of the first memory cell; A second word line connected to the gate of the second memory cell; A third word line connected to the gate of the third memory cell; A control circuit configured to execute a write operation including a program operation and a program verification operation; Comprising; In the program operation of the first memory cell, when writing data to the first memory cell, the control circuit Applies a first voltage to the bit line BL; Applies a second voltage lower than the first voltage to the source line; Applies a third voltage higher than the first voltage to the first selection gate line; Applies a fourth voltage higher than the first voltage to the second selection gate line; Applies a program voltage to the first word line; Applies a fifth voltage to the second word line; Applies a sixth voltage higher than the fifth voltage and lower than the program voltage to the third word line. A semiconductor memory device.

2. After the write operation of the first memory cell, the control circuit executes the write operation of the second memory cell, and after the write operation of the second memory cell, the control circuit executes the write operation of the third memory cell. The semiconductor memory device according to Claim 1.

3. In the program operation of the first memory cell, when not writing data to the first memory cell, the control circuit applies the second voltage to the bit line BL. The semiconductor memory device according to Claim 1.

4. The first selection transistor to which the third voltage is applied to the first selection gate line, the second selection transistor to which the fourth voltage is applied to the second selection gate line, the first memory cell to which the program voltage is applied to the first word line, and the third memory cell to which the sixth voltage is applied to the third word line are in an on state. The semiconductor memory device according to Claim 1.

5. A second memory string including a third selection transistor, a fourth memory cell, a fifth memory cell, a sixth memory cell, and a fourth selection transistor, in which each current path is connected in series; A third selection gate line connected to the gate of the third selection transistor further comprising; The third selection transistor is connected to the bit line, The fourth selection transistor is connected to the source line, The gate of the fourth selection transistor is connected to the second selection gate line, The gate of the fourth memory cell is connected to the first word line, The gate of the fifth memory cell is connected to the second word line, The gate of the sixth memory cell is connected to the third word line, In the programming operation of the first memory cell, the control circuit applies the second voltage to the third selection gate line. The semiconductor memory device according to claim 1.

6. The third selection transistor to which the second voltage is applied to the third selection gate line is turned off. The semiconductor memory device according to claim 5.

7. The first voltage is 1 V or more higher than the second voltage. The semiconductor memory device according to claim 1.

8. The fifth voltage is a voltage value equal to or lower than the threshold voltage of the second memory cell. The semiconductor memory device according to claim 1.

9. In the programming operation of the first memory cell, the first voltage is applied to the drain of the second memory cell, the second voltage is applied to the source of the second memory cell, and based on the voltage difference between the first voltage and the second voltage, hot carriers are generated. The semiconductor memory device according to claim 1.

10. further comprising a fifth word line; The first memory string is provided between the first memory cell and the second memory cell, and further includes an eighth memory cell having the fifth word line connected to its gate. In the programming operation of the first memory cell, the control circuit applies the fifth voltage to the fifth word line. The semiconductor memory device according to claim 1.

11. further comprising a sixth word line; The first memory string is provided between the first memory cell and the second memory cell, and further includes a ninth memory cell having the sixth word line connected to its gate. In the programming operation of the first memory cell, the control circuit applies a seventh voltage higher than the first voltage and lower than the sixth voltage to the sixth word line. The semiconductor memory device according to claim 1.

12. A first memory string including a first selection transistor, a first memory cell, a second memory cell, a third memory cell, and a second selection transistor, in which each current path is connected in series; A bit line connected to the first selection transistor; A source line connected to the second selection transistor; A first selection gate line connected to the gate of the first selection transistor; A second selection gate line connected to the gate of the second selection transistor; A first word line connected to the gate of the first memory cell; A second word line connected to the gate of the second memory cell; A third word line connected to the gate of the third memory cell; A control circuit configured to execute a write operation including a program operation and a program verification operation; and in the program operation of the first memory cell, when writing data to the first memory cell, the control circuit applies a first voltage to the bit line BL; applies a second voltage lower than the first voltage to the source line; applies a third voltage higher than the second voltage and lower than the first voltage to the first selection gate line; applies a fourth voltage higher than the first voltage to the second selection gate line; applies a program voltage to the first word line; applies a fifth voltage to the second word line; applies a sixth voltage higher than the fifth voltage and lower than the program voltage to the third word line. A semiconductor memory device.

13. The first selection transistor to which the third voltage is applied to the first selection gate line and the second memory cell to which the fifth voltage is applied to the second word line are in an off state, and the second selection transistor to which the fourth voltage is applied to the second selection gate line, the first memory cell to which the program voltage is applied to the first word line, and the third memory cell to which the sixth voltage is applied to the third word line are in an on state. The semiconductor memory device according to claim 12.

14. In the program operation of the first memory cell, when not writing data to the first memory cell, the control circuit applies the second voltage to the bit line BL. The semiconductor memory device according to claim 12.

15. The first selection transistor to which the first voltage is applied to the current path and the third voltage is applied to the first selection gate line is in an off state. The semiconductor memory device according to claim 14.

16. In the programming operation of the first memory cell, the control circuit applies a seventh voltage that is higher than the fifth voltage and lower than the sixth voltage after applying the fifth voltage to the second word line. The semiconductor memory device according to claim 12.

17. A second memory string including a third selection transistor, a fourth memory cell, a fifth memory cell, a sixth memory cell, and a fourth selection transistor, in which each current path is connected in series; A third selection gate line connected to the gate of the third selection transistor and further comprising: The third selection transistor is connected to the bit line, The fourth selection transistor is connected to the source line, The gate of the fourth selection transistor is connected to the second selection gate line, The gate of the fourth memory cell is connected to the first word line, The gate of the fifth memory cell is connected to the second word line, The gate of the sixth memory cell is connected to the third word line, In the programming operation of the first memory cell, the control circuit applies an eighth voltage that is higher than the first voltage to the third selection gate line. The semiconductor memory device according to claim 12.

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