Semiconductor device and semiconductor module

Abstract

To provide a semiconductor device and a semiconductor module which can reduce turn-on loss while reducing current noise.SOLUTION: A semiconductor device comprises a first gate electrode, a second gate electrode and a third gate electrode which are controlled independently from one another, where a turn-on period of the second gate electrode is shorter than a turn-on period of the first gate electrode and a turn-on period of the third gate electrode is shorter than a turn-on period of the second gate electrode, in a period during which the first gate electrode is turned on and then turned off. A time point at which a third gate voltage of the third gate electrode reaches a third threshold voltage and a starting time point of a third mirror period of the third gate voltage are in a first mirror period of a first gate voltage of the first gate electrode and in a second mirror period of a second gate voltage of the second gate electrode.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device and a semiconductor module.

Background Art

[0002] An IGBT (Insulated Gate Bipolar Transistor) is widely used as a power semiconductor device for controlling high breakdown voltage and large current. As an IGBT used as a switching element, it is desired that the loss during turn-on is low. Therefore, an IGBT with a triple gate structure has been proposed in which the gate electrode is divided into three systems and the third gate electrode is driven only during turn-on to reduce the turn-on loss.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention aim to provide a semiconductor device and a semiconductor module capable of reducing turn-on loss while reducing current noise.

Means for Solving the Problems

[0005] According to an embodiment of the present invention, a semiconductor device includes a first gate electrode, a second gate electrode, and a third gate electrode that are independently controlled from each other. During the period from when the first gate electrode turns on to when it turns off, the on-period of the second gate electrode is shorter than the on-period of the first gate electrode, and the on-period of the third gate electrode is shorter than the on-period of the second gate electrode. The semiconductor device includes the first gate electrode, the second gate electrode, and the third gate electrode. The time point when the third gate voltage of the third gate electrode reaches a third threshold voltage and the start time point of the third mirror period of the third gate voltage are within the first mirror period of the first gate voltage of the first gate electrode and within the second mirror period of the second gate voltage of the second gate electrode.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. The drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the sizes between parts, etc. are not necessarily the same as the actual ones. Even when representing the same part, the dimensions and ratios of each other may be represented differently in the drawings. Also, the same or similar elements are denoted by the same reference numerals.

[0008] [First Embodiment] As shown in FIG. 1, the semiconductor module 1 of the first embodiment includes a first semiconductor device 101, a second semiconductor device 102, and a driving device 50 that drives the first semiconductor device 101 and the second semiconductor device 102.

[0009] The first semiconductor device 101 and the second semiconductor device 102 include, for example, IGBTs and have the same configuration. In this specification, the first semiconductor device 101 and the second semiconductor device 102 may be simply referred to as the semiconductor device 100 without distinction.

[0010] Each of the first semiconductor device 101 and the second semiconductor device 102 has a collector electrode 22, an emitter electrode 21, a first gate electrode MG, a second gate electrode CGp, and a third gate electrode CGs1. The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 are controlled electrically independently of each other.

[0011] The first semiconductor device 101 and the second semiconductor device 102 are connected in series between a voltage source 200 and ground. The collector electrode 22 of the first semiconductor device 101 is connected to the voltage source 200, the emitter electrode 21 of the first semiconductor device 101 is connected to the collector electrode 22 of the second semiconductor device 102, and the emitter electrode 21 of the second semiconductor device 102 is connected to ground. The connection point (neutral point) 300 between the emitter electrode 21 of the first semiconductor device 101 and the collector electrode 22 of the second semiconductor device 102 is connected to a load (not shown).

[0012] A first freewheeling diode 401 is connected in parallel with the first semiconductor device 101 between the voltage source 200 and the neutral point 300. The first freewheeling diode 401 has a forward direction from the neutral point 300 toward the voltage source 200. A second freewheeling diode 402 is connected in parallel with the second semiconductor device 102 between the neutral point 300 and the ground. The second freewheeling diode 402 has a forward direction from the ground toward the neutral point 300. The first freewheeling diode 401 and the second freewheeling diode 402 are, for example, Schottky barrier diodes.

[0013] The drive device 50 is electrically connected to each gate electrode of the first semiconductor device 101 and the second semiconductor device 102, and applies a gate voltage to each gate electrode of the first semiconductor device 101 and the second semiconductor device 102. The gate voltage is, for example, a gate potential based on the emitter potential. The drive device 50 is electrically connected to the first gate electrodes MG of the semiconductor devices 101, 102 via the first gate wiring 81. The drive device 50 is electrically connected to the second gate electrodes CGp of the semiconductor devices 101, 102 via the second gate wiring 82. The drive device 50 is electrically connected to the third gate electrodes CGs1 of the semiconductor devices 101, 102 via the third gate wiring 83.

[0014] The semiconductor module 1 may include a pulse generator 60 and a control device 70. The pulse generator 60 outputs a pulse signal to the drive device 50, and the drive device 50 applies a pulsed gate voltage to each gate electrode of the first semiconductor device 101 and the second semiconductor device 102 according to the pulse signal from the pulse generator 60. The output of the pulse generator 60 is connected to the input of the drive device 50. The control device 70 controls the drive device 50.

[0015] An example of the structure of the semiconductor device 100 (the first semiconductor device 101 and the second semiconductor device 102) will be described with reference to FIG. 2.

[0016] The semiconductor device 100 has, for example, a trench gate structure. The semiconductor device 100 includes an emitter electrode 21, a collector electrode 22, a semiconductor portion 10, a first gate electrode MG, a second gate electrode CGp, a third gate electrode CGs1, a first insulating film 41, a second insulating film 42, and a third insulating film 43. In FIG. 2, in order to clarify the surface of the semiconductor portion 10 covered by the emitter electrode 21, the emitter electrode 21 is represented by a two-dot chain line.

[0017] The emitter electrode 21 and the collector electrode 22 are located apart from each other in the first direction Z. In FIG. 2, the two directions orthogonal to the first direction Z are defined as the second direction X and the third direction Y. The second direction X and the third direction Y are orthogonal to each other.

[0018] The semiconductor portion 10 is provided between the emitter electrode 21 and the collector electrode 22 in the first direction Z. The material of the semiconductor portion 10 is, for example, silicon. The material of the semiconductor portion 10 may be, for example, silicon carbide, gallium nitride, etc.

[0019] The semiconductor portion 10 has a first semiconductor layer 11 of the first conductivity type, a second semiconductor layer 12 of the second conductivity type, a third semiconductor layer 13 of the first conductivity type, and a fourth semiconductor layer 14 of the second conductivity type. In the present embodiment, for example, the first conductivity type is n-type and the second conductivity type is p-type.

[0020] The semiconductor portion 10 has a plurality of mesa portions 30 that are located apart from each other in the second direction X. Each mesa portion 30 extends in the third direction Y. Each mesa portion 30 includes a part of the first semiconductor layer 11, the second semiconductor layer 12, and the third semiconductor layer 13. Also, the mesa portion 30 may include a fifth semiconductor layer 15 described later.

[0021] The first semiconductor layer 11 is, for example, an n-type drift layer in an IGBT. The second semiconductor layer 12 is, for example, a p-type base layer in an IGBT. The second semiconductor layer 12 is located between the first semiconductor layer 11 and the third semiconductor layer 13 in the first direction Z.

[0022] The third semiconductor layer 13 is, for example, an n-type emitter layer in an IGBT. The n-type impurity concentration of the third semiconductor layer 13 is higher than the n-type impurity concentration of the first semiconductor layer 11. The third semiconductor layer 13 is located between the second semiconductor layer 12 and the emitter electrode 21 in the first direction Z and is electrically connected to the emitter electrode 21.

[0023] The fourth semiconductor layer 14 is, for example, a p-type collector layer in an IGBT. The p-type impurity concentration of the fourth semiconductor layer 14 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fourth semiconductor layer 14 is located between the collector electrode 22 and the first semiconductor layer 11 in the first direction Z and is electrically connected to the collector electrode 22.

[0024] The semiconductor part 10 can further include a fifth semiconductor layer 15 of the second conductivity type and a sixth semiconductor layer 16 of the first conductivity type.

[0025] The fifth semiconductor layer 15 is, for example, a p-type base contact layer in an IGBT. The p-type impurity concentration of the fifth semiconductor layer 15 is higher than the p-type impurity concentration of the second semiconductor layer 12. The fifth semiconductor layer 15 is located between the second semiconductor layer 12 and the emitter electrode 21 and is electrically connected to the second semiconductor layer 12 and the emitter electrode 21. For example, on the second semiconductor layer 12 of the mesa part 30, the third semiconductor layer 13 and the fifth semiconductor layer 15 are alternately arranged in the third direction Y.

[0026] The sixth semiconductor layer 16 is, for example, an n-type buffer layer in an IGBT. The n-type impurity concentration of the sixth semiconductor layer 16 is higher than the n-type impurity concentration of the first semiconductor layer 11. The sixth semiconductor layer 16 is located between the fourth semiconductor layer 14 and the first semiconductor layer 11 in the first direction Z.

[0027] The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 are located between the semiconductor part 10 and the emitter electrode 21 in the first direction Z. The first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 are electrically separated from each other. As the material of the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1, for example, polycrystalline silicon can be used.

[0028] The structure shown in FIG. 2 is repeated a plurality of times in the second direction X. That is, a plurality of first gate electrodes MG, a plurality of second gate electrodes CGp, and a plurality of third gate electrodes CGs1 are arranged side by side at intervals in the second direction X. Each of the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 extends in the third direction Y.

[0029] The plurality of first gate electrodes MG are electrically connected to each other, for example, at the ends in the third direction Y. The plurality of second gate electrodes CGp are electrically connected to each other, for example, at the ends in the third direction Y. The plurality of third gate electrodes CGs1 are electrically connected to each other, for example, at the ends in the third direction Y.

[0030] The third gate electrode CGs1 is arranged, for example, between the adjacent first gate electrode MG and the second gate electrode CGp in the second direction X. FIG. 2 shows an example in which, as the order of the gate electrodes in the second direction X, the first gate electrode MG is adjacent to the third gate electrode CGs, the second gate electrode CGp is adjacent to the third gate electrode CGs1, and the first gate electrode MG is not adjacent to the second gate electrode CGp. The ratio and density of each gate electrode are not limited to those shown in FIG. 2.

[0031] The first insulating film 41 is provided between the first gate electrode MG and the semiconductor portion 10. The first gate electrode MG is adjacent to the mesa portion 30 via the first insulating film 41 in the second direction X. The side surface of the first gate electrode MG in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the first insulating film 41. The first insulating film 41 is also provided between the upper end of the first gate electrode MG and the emitter electrode 21.

[0032] The second insulating film 42 is provided between the second gate electrode CGp and the semiconductor portion 10. The second gate electrode CGp is adjacent to the mesa portion 30 via the second insulating film 42 in the second direction X. The side surface of the second gate electrode CGp in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the second insulating film 42. The second insulating film 42 is also provided between the upper end of the second gate electrode CGp and the emitter electrode 21.

[0033] The third insulating film 43 is provided between the third gate electrode CGs1 and the semiconductor portion 10. The third gate electrode CGs1 is adjacent to the mesa portion 30 via the third insulating film 43 in the second direction X. The side surface of the third gate electrode CGs1 in the second direction X faces the first semiconductor layer 11, the second semiconductor layer 12, the third semiconductor layer 13, and the fifth semiconductor layer 15 of the mesa portion 30 via the third insulating film 43. The third insulating film 43 is also provided between the upper end of the third gate electrode CGs1 and the emitter electrode 21.

[0034] The first insulating film 41, the second insulating film 42, and the third insulating film 43 are, for example, a silicon oxide film and a silicon nitride film.

[0035] The first semiconductor device 101 and the second semiconductor device 102 are alternately turned on and off by the driving device 50. During the period when the first semiconductor device 101 is on, the second semiconductor device 102 is turned off, and during the period when the second semiconductor device 102 is on, the first semiconductor device 101 is turned off. Also, in order to prevent the through current from flowing from the voltage source 200 to the ground through the first semiconductor device 101 and the second semiconductor device 102, a dead time is set, which is the period when both the first semiconductor device 101 and the second semiconductor device 102 are off.

[0036] FIG. 3(a) is a timing chart of the first gate voltage V MG of the first gate electrode MG. FIG. 3(b) is a timing chart of the second gate voltage V CGp of the second gate electrode CGp. FIG. 3(c) is a timing chart of the third gate voltage V CGs 1 of the third gate electrode CGs1.

[0037] Let the threshold voltages of the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 be the first threshold voltage, the second threshold voltage, and the third threshold voltage, respectively. For example, the first threshold voltage, the second threshold voltage, and the third threshold voltage are the same and are represented by Vth in FIGS. 3(a) to 3(c). Note that due to manufacturing variations of the semiconductor device, there may be some variations in the first threshold voltage, the second threshold voltage, and the third threshold voltage.

[0038] In each of the semiconductor devices 101 and 102, during the period from when the first gate electrode MG turns on to when it turns off, the on period of the second gate electrode CGp is shorter than the on period of the first gate electrode MG, and the on period of the third gate electrode CGs1 is shorter than the on period of the second gate electrode CGp. At time t1, the rise of the first gate voltage V MG starts, and at time t3 after time t1, the rise of the third gate voltage V CGs 1 starts, and at time t4 after time t3, the third gate voltage V CGsThe fall of 1 starts, and at time t5 after time t4, the fall of the second gate voltage V CGp starts, and at time t6 after time t5, the fall of the first gate voltage V MG starts.

[0039] Each of the semiconductor devices 101 and 102 is turned on and off by the first gate electrode MG. The second gate electrode CGp is turned off prior to the first gate electrode MG when each of the semiconductor devices 101 and 102 is turned off. The third gate electrode CGs1 is turned on only for a short time when each of the semiconductor devices 101 and 102 is turned on.

[0040] When the first gate voltage V MG exceeds the first threshold voltage Vth, a first channel (n-type inversion layer) is induced in the region of the second semiconductor layer 12 facing the first gate electrode MG. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 through the third semiconductor layer 13 and the first channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 through the sixth semiconductor layer 16. This state is referred to as the on state of the first gate electrode MG. The on voltage of the first gate electrode MG can be set to, for example, +15V.

[0041] When the second gate voltage V CGp exceeds the second threshold voltage Vth, a second channel (n-type inversion layer) is induced in the region of the second semiconductor layer 12 facing the second gate electrode CGp. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 through the third semiconductor layer 13 and the second channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 through the sixth semiconductor layer 16. This state is referred to as the on state of the second gate electrode CGp. The on voltage of the second gate electrode CGp can be set to, for example, +15V.

[0042] For example, the turn-on of the first gate electrode MG and the turn-on of the second gate electrode CGp are simultaneous.

[0043] The third gate voltage VCGs When 1 exceeds the third threshold voltage Vth, a third channel (n-type inversion layer) is induced in the region of the second semiconductor layer 12 facing the third gate electrode CGs1. Electrons are injected from the emitter electrode 21 into the first semiconductor layer 11 through the third semiconductor layer 13 and the third channel. Correspondingly, holes are injected from the fourth semiconductor layer 14 into the first semiconductor layer 11 through the sixth semiconductor layer 16. This state is referred to as the on state of the third gate electrode CGs1. The on voltage of the third gate electrode CGs1 can be set to, for example, +15V.

[0044] When each semiconductor device 101, 102 is turned on, by turning on the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1, the amount of electron injection into the first semiconductor layer 11 can be increased in a short time to reduce the turn-on loss. When each semiconductor device 101, 102 is turned on, by turning off the third gate electrode CGs1 (eliminating the third channel) before the first gate electrode MG and the second gate electrode CGp, the saturation current can be kept low and the short-circuit withstand capacity can be ensured.

[0045] The third gate voltage V CGs When 1 becomes lower than the third threshold voltage Vth, the third channel in the region of the second semiconductor layer 12 facing the third gate electrode CGs1 disappears. This state is referred to as the off state of the third gate electrode CGs1. The off voltage of the third gate electrode CGs1 can be set to, for example, 0V.

[0046] The second gate voltage V CGp When it becomes lower than the second threshold voltage Vth, the second channel in the region of the second semiconductor layer 12 facing the second gate electrode CGp disappears. This state is referred to as the off state of the second gate electrode CGp. By turning off the second gate electrode CGp before the first gate electrode MG, the amount of electron injection into the first semiconductor layer 11 can be restricted to reduce the turn-off loss. Also, the second gate voltage V CGpBy setting it to a negative voltage, a fourth channel (p-type inversion layer) and a fifth channel (p-type inversion layer) are induced in the regions of the first semiconductor layer 11 and the third semiconductor layer 13 facing the second gate electrode CGp. Holes are drawn from the first semiconductor layer 11 through the fourth channel, the second semiconductor layer 12, and the fifth channel to the emitter electrode 21. As a result, since the carrier density of the first semiconductor layer 11 decreases, the turn-off loss can be further reduced. The off voltage of the second gate electrode CGp can be set to, for example, -15V.

[0047] After the second gate electrode CGp turns off, when the first gate voltage V MG of the first gate electrode MG becomes lower than the first threshold voltage Vth, the first channel in the region of the second semiconductor layer 12 facing the first gate electrode MG disappears. This state is referred to as the off state of the first gate electrode MG. The off voltage of the first gate electrode MG can be set to, for example, -15V.

[0048] FIG. 4(a) is a timing chart at the time of turn-on of the first gate voltage V MG , the second gate voltage V CGp , and the third gate voltage V CGs 1. The first gate voltage V MG and the second gate voltage V CGp are represented by thin lines, and the third gate voltage V CGs 1 is represented by a thick line.

[0049] FIG. 4(b) is a graph showing the time changes of the current Ic and the voltage Vce at the time of turn-on of the semiconductor device 100. The current Ic represents the current flowing between the collector electrode 22 and the emitter electrode 21. The voltage Vce represents the collector potential with respect to the emitter potential as a reference.

[0050] In FIGS. 4(a) and 4(b), when the first gate voltage V MG and the second gate voltage V CGp exceed the threshold voltage Vth, the current Ic starts to flow. The first gate voltage V MG and the second gate voltage V CGpAfter exceeding the threshold voltage Vth, a first mirror period of the first gate voltage V MG starts at time t7, and a second mirror period of the second gate voltage V CGp starts at time t8. For example, time t7 and time t8 are the same time. The mirror period is a period during which the parasitic capacitance between each gate electrode and the collector electrode is charged and the gate voltage of each gate electrode does not change.

[0051] At the time when the first mirror period and the second mirror period start, the rise of the current Ic is completed. Also, when the first mirror period and the second mirror period start, the voltage Vce starts to fall. At time t 11 , the first mirror period of the first gate voltage V MG , the second mirror period of the second gate voltage V CGp , and the third mirror period of the third gate voltage V CGs 1 end.

[0052] According to this embodiment, at time t9 when the third gate voltage V CGs 1 of the third gate electrode CGs1 reaches the third threshold voltage Vth, and at the start time t CGs of the third mirror period of the third gate voltage V 10 1, it is during the first mirror period of the first gate voltage V MG (between time t7 and time t 11 ), and during the second mirror period of the second gate voltage V CGp (between time t8 and time t 11 ).

[0053] Since the rise of the current Ic is completed at the time when the first mirror period and the second mirror period start, by making the time t9 when the third gate voltage V CGs 1 reaches the third threshold voltage Vth later than the start time t7 of the first mirror period and the start time t8 of the second mirror period, dIc / dt (the change amount of the current Ic with respect to the time at the rise of the current Ic) can be reduced. Thereby, the amplitude width and the maximum value of the ringing of the current Ic at turn-on can be reduced, and the current noise can be reduced.

[0054] As shown in Fig. 4(b), after the third gate voltage V CGs 1 exceeds the third threshold voltage Vth, at time t 10 when the third mirror period of the third gate voltage V CGs 1 starts, dVce / dt (the change amount of the voltage Vce with respect to the time at the falling edge of the voltage Vce) increases. By setting the start time t CGs of the third mirror period of the third gate voltage V 10 during the first mirror period of the first gate voltage V MG (between time t7 and time t 11 ), and during the second mirror period of the second gate voltage V CGp (between time t8 and time t 11 ), the falling edge of the voltage Vce can be accelerated and the turn-on loss can be reduced.

[0055] That is, according to the present embodiment, the turn-on loss can be reduced while reducing the current noise.

[0056] Fig. 5(a) is a graph showing the measurement results of the turn-on loss Eon [mJ] and dIc / dt [kA / μs] when a current Ic of 30 A flows through the IGBT during turn-on. Fig. 5(b) is a graph showing the measurement results of the turn-on loss Eon [mJ] and the maximum value Ic_max [A] of the ringing of the current Ic when a current Ic of 30 A flows through the IGBT during turn-on.

[0057] In the graphs of FIGS. 5(a) and 5(b), the circles indicate the measurement results of an IGBT of a first comparative example having a single gate structure with one system of gate electrodes. The squares indicate the measurement results of an IGBT having a triple gate structure, which is a second comparative example in which three systems of gate electrodes simultaneously reach the threshold voltage at turn-on and the Miller period is started simultaneously. The triangles indicate the measurement results of the IGBT of the above-described embodiment. Each point of the squares has a different period between the start time t1 of the rise of the first gate voltage and the start time t3 of the rise of the third gate voltage, and each point of the triangles also has a different period between the start time t1 of the rise of the first gate voltage and the start time t3 of the rise of the third gate voltage.

[0058] From the results of FIG. 5(a), according to the embodiment, Eon can be made smaller than that of the first comparative example, and Eon equivalent to that of the second comparative example can be obtained while making dIc / dt smaller than that of the second comparative example. From the results of FIG. 5(b), according to the embodiment, Eon can be made smaller than that of the first comparative example, and Eon equivalent to that of the second comparative example can be obtained while making Ic_max smaller than that of the second comparative example.

[0059] FIGS. 6(a) and 6(b) are timing charts of gate voltages at turn-on of a semiconductor device of the same embodiment as FIG. 4(a). In the semiconductor device of FIG. 6(a), the gate time constants of the first gate electrode MG, the second gate electrode CGp, and the third gate electrode CGs1 are the same. In the semiconductor device of FIG. 6(a), the gate time constant of the third gate electrode CGs1 is smaller than the gate time constants of the first gate electrode MG and the second gate electrode CGp. The gate time constant can be adjusted, for example, by the resistance R of the gate wirings 81 to 83 shown in FIG. 1.

[0060] By making the gate time constant of the third gate electrode CGs1 smaller than the gate time constants of the first gate electrode MG and the second gate electrode CGp, compared with the case where the gate time constants of the respective gate electrodes are the same, the first gate voltage VMG At the start time t7 of the first mirror period and the second gate voltage V CGp From the start time t8 of the second mirror period of, the third gate voltage V CGs The period until the start time t of the third mirror period of 1 can be shortened. As a result, the fall of the voltage Vce can be accelerated, and the turn-on loss can be easily reduced. 10

[0061] [Second Embodiment] FIG. 7(a) is a timing chart of the first gate voltage V of the first gate electrode MG in the semiconductor device of the second embodiment. MG FIG. 7(b) is a timing chart of the second gate voltage V of the second gate electrode CGs2 in the semiconductor device of the second embodiment. CGs 2

[0062] The semiconductor device of the second embodiment is different from the semiconductor device of the first embodiment in that it has two systems of gate electrodes. The semiconductor device of the second embodiment includes an IGBT having a double gate structure with a first gate electrode MG and a second gate electrode CGs2 that are electrically independently controlled from each other. The semiconductor device of the second embodiment does not have the second gate electrode CGp among the three systems of gate electrodes of the semiconductor device of the first embodiment.

[0063] The configuration and operation of the second gate electrode CGs2 in the semiconductor device of the second embodiment correspond to the configuration and operation of the third gate electrode CGs1 in the semiconductor device of the first embodiment. The second gate voltage V of the second gate electrode CGs2 in the second embodiment CGs 2 corresponds to the third gate voltage V of the third gate electrode CGs1 in the first embodiment. CGs 1. The second threshold voltage in the second embodiment corresponds to the third threshold voltage in the first embodiment. The second mirror period in the second embodiment corresponds to the third mirror period in the first embodiment.

[0064] Also in the second embodiment, as shown in FIGS. 7(a) and (b), the second gate voltage V of the second gate electrode CGs2​​CGs At time t6 when 2 reaches the second threshold voltage Vth, and at the start time t7 of the second mirror period of the second gate voltage V CGs is during the first mirror period of the first gate voltage V (between time t5 and time t8). MG Thereby, the amplitude width and the maximum value of the ringing of the current Ic at turn-on can be reduced, and the current noise can be reduced. Also, the fall of the voltage Vce can be accelerated, and the turn-on loss can be reduced.

[0065] Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.

[0066]

Description of Reference Numerals

Description of Reference Numerals

[0067] 1... semiconductor module, 10... semiconductor part, 21... emitter electrode, 22... collector electrode, 50... drive device, 60... pulse generator, 70... control device, 100... semiconductor device, 101... first semiconductor device, 102... second semiconductor device, MG... first gate electrode, CGp... second gate electrode, CGs1... third gate electrode, CGs2... second gate electrode

Claims

1. A first gate electrode, a second gate electrode, and a third gate electrode that are independently controlled from each other, wherein during the period from when the first gate electrode turns on to when it turns off, the on-period of the second gate electrode is shorter than the on-period of the first gate electrode, and the on-period of the third gate electrode is shorter than the on-period of the second gate electrode, comprising the first gate electrode, the second gate electrode, and the third gate electrode, A semiconductor device in which the time point at which the third gate voltage of the third gate electrode reaches a third threshold voltage and the start time point of the third mirror period of the third gate voltage are within the first mirror period of the first gate voltage of the first gate electrode and within the second mirror period of the second gate voltage of the second gate electrode.

2. The semiconductor device according to claim 1, wherein the gate time constant of the third gate electrode is smaller than the gate time constants of the first gate electrode and the second gate electrode.

3. A first gate electrode and a second gate electrode that are independently controlled from each other, wherein during the period from when the first gate electrode turns on to when it turns off, the on-period of the second gate electrode is shorter than the on-period of the first gate electrode, comprising the first gate electrode and the second gate electrode, A semiconductor device in which the time point at which the second gate voltage of the second gate electrode reaches a second threshold voltage and the start time point of the second mirror period of the second gate voltage are within the first mirror period of the first gate voltage of the first gate electrode.

4. The semiconductor device according to claim 3, wherein the gate time constant of the second gate electrode is smaller than the gate time constant of the first gate electrode.

5. The semiconductor device according to any one of claims 1 to 4, including an IGBT (Insulated Gate Bipolar Transistor).

6. The semiconductor device according to claim 1, and A drive circuit electrically connected to the first gate electrode, the second gate electrode, and the third gate electrode, A semiconductor module comprising the same.

7. The semiconductor device has a first semiconductor device and a second semiconductor device connected in series between a voltage source and ground, The semiconductor module according to claim 6, wherein each of the first semiconductor device and the second semiconductor device has the first gate electrode, the second gate electrode, and the third gate electrode.

8. The semiconductor device according to claim 3, and A drive circuit electrically connected to the first gate electrode, the second gate electrode, and the third gate electrode; A semiconductor module comprising the same. **Claim 9** The semiconductor device has a first semiconductor device and a second semiconductor device connected in series between a voltage source and ground, The semiconductor module according to claim 8, wherein each of the first semiconductor device and the second semiconductor device has the first gate electrode and the second gate electrode.

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