Method for manufacturing silicon carbide semiconductor device and silicon carbide semiconductor device

Abstract

To provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that are capable of preventing deterioration in channel mobility.SOLUTION: When a MOS gate is formed, the surface of a semiconductor substrate is first subjected to low-temperature plasma etching using a non-oxidizing source gas containing hydrogen gas, rare gas, or halogen gas without heating the semiconductor substrate or while heating the semiconductor substrate to a low temperature of about 400°C or less. Following this low-temperature plasma etching, a gate insulating film is deposited on the surface of the semiconductor substrate by a sputtering method or the like without exposing the semiconductor substrate to an oxygen atmosphere. Next, the interface between the gate insulating film and the semiconductor substrate is nitrided by a heat treatment using NO gas, N2O gas, or N2 gas. This reduces the defect density at the interface between the gate insulating film and the semiconductor substrate, and the excess carbon amount and the excess carbon distribution width resulting from the oxidation of SiC. Thereafter, a gate electrode is formed on the gate insulating film.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device.

Background Art

[0002] Patent Document 1 describes a technique for suppressing a decrease in channel mobility by etching a dopant deposited on the surface of silicon carbide (SiC) and a deposition layer of excess carbon so as not to redeposit them before forming a gate insulating film, thereby planarizing the SiC surface. Patent Document 2 describes a technique for suppressing an increase in channel resistance by etching and planarizing the surface of a SiC substrate by irradiation with atomic hydrogen before forming a gate insulating film. Patent Document 3 describes a technique for reducing the defect density at the interface between a SiO2 film and a SiC substrate (hereinafter referred to as the SiO2 / SiC interface) by etching the surface of the SiC substrate with H2 gas, forming a SiO2 film on the surface of the SiC substrate, and then nitriding the interface. Patent Document 4 describes a technique for reducing excess carbon at the SiO2 / SiC interface by setting the nitrogen amount at the SiO2 / SiC interface within a predetermined range when forming a SiO2 film by thermal oxidation.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Documents 1 and 3 above, since a high-temperature treatment of 1200°C or higher is included, if an insulating layer (SiO2) such as a field oxide film exists on the SiC surface before this high-temperature treatment, the insulating layer will be damaged. In Patent Document 2 above, the surface of the SiC substrate is etched by irradiating atomic hydrogen while heating the SiC substrate at a temperature of 800°C or higher. However, since the insulating layer reacts more easily with atomic hydrogen than SiC, the surface roughness of the insulating layer becomes prominent. For this reason, in Patent Documents 1 to 3 above, there is a risk that the design of the manufacturing process needs to be changed. In Patent Document 4 above, it cannot be said that the excess carbon at the SiO2 / SiC interface is sufficiently reduced.

[0005] An object of this disclosure is to provide a method for manufacturing a silicon carbide semiconductor device and a silicon carbide semiconductor device that can prevent a decrease in channel mobility.

Means for Solving the Problems

[0006] A method for manufacturing a silicon carbide semiconductor device according to an aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device having an insulating gate on a semiconductor substrate made of silicon carbide, and is as follows. A first step is performed in which the surface of the semiconductor substrate is etched with plasma generated using a source gas that does not contain oxygen atoms, without heating the semiconductor substrate or while heating the semiconductor substrate at a temperature of 400°C or lower. After the first step, a second step is performed in which a gate insulating film constituting the insulating gate is deposited on the surface of the semiconductor substrate without exposing the semiconductor substrate to an oxygen atmosphere. A third step is performed in which the interface between the gate insulating film and the semiconductor substrate is nitrided. A fourth step is performed in which a gate electrode constituting the insulating gate is formed to face the surface of the semiconductor substrate with the gate insulating film interposed therebetween.

[0007] A silicon carbide semiconductor device according to one aspect of this disclosure is as follows. A gate insulating film is provided on the surface of a semiconductor substrate made of silicon carbide. A gate electrode is provided on the surface of the semiconductor substrate via the gate insulating film. An insulated gate is formed by the gate insulating film and the gate electrode. Excess carbon present at the interface between the semiconductor substrate and the gate insulating film is distributed within a range of 2 nm or less from the interface between the semiconductor substrate and the gate insulating film to both the semiconductor substrate side and the gate insulating film side, and the ratio of the amount thereof to the amount of carbon in the semiconductor substrate is 0.025 or less.

Effect of the Invention

[0008] According to the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present disclosure, it is possible to prevent a decrease in channel mobility.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] <Outline of the Embodiment of the Present Disclosure> (1) The manufacturing method of a silicon carbide semiconductor device according to one aspect of this disclosure is a method for manufacturing a silicon carbide semiconductor device having an insulating gate on a semiconductor substrate made of silicon carbide, and is as follows. A first step is performed in which the surface of the semiconductor substrate is etched with plasma generated using a source gas that does not contain oxygen atoms, without heating the semiconductor substrate or while heating the semiconductor substrate at a temperature of 400°C or lower. After the first step, a second step is performed in which a gate insulating film constituting the insulating gate is deposited on the surface of the semiconductor substrate without exposing the semiconductor substrate to an oxygen atmosphere. A third step is performed in which the interface between the gate insulating film and the semiconductor substrate is nitrided. A fourth step is performed in which a gate electrode constituting the insulating gate is formed facing the surface of the semiconductor substrate with the gate insulating film interposed therebetween.

[0011] According to the above-described disclosure, oxidation of the surface of the semiconductor substrate can be prevented during the first step. Further, after the first step, a gate insulating film can be deposited on the surface of the semiconductor substrate without re-oxidizing the surface of the semiconductor substrate. For this reason, the interface state density (defect density) at the interface (SiO2 / SiC interface) between the gate insulating film and the semiconductor substrate can be reduced, and a decrease in the channel mobility of the MOSFET can be prevented.

[0012] (2) Further, the manufacturing method of a silicon carbide semiconductor device according to this disclosure is, in the above-described (1), in the first step, the surface of the semiconductor substrate may be exposed to the plasma to dissolve the surface layer of the semiconductor substrate.

[0013] According to the above-described disclosure, in the first step, the defect structure caused by SiC oxidation on the surface of the semiconductor substrate can be surely removed together with the surface layer of the semiconductor substrate.

[0014] (3) Further, the manufacturing method of a silicon carbide semiconductor device according to this disclosure is, in the above-described (1) or (2), in the first step, the source gas containing hydrogen gas may be used.

[0015] According to the above disclosure, during the first step, it is possible to prevent the surface of the semiconductor substrate from being oxidized and to suppress the occurrence of damage to the surface of the semiconductor substrate.

[0016] (4) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above-mentioned (1), in the first step, radicals in the plasma may be collided with the surface of the semiconductor substrate to scrape off the surface layer of the semiconductor substrate.

[0017] According to the above disclosure, in the first step, it is possible to reliably remove the defect structure caused by the oxidation of SiC on the surface of the semiconductor substrate together with the surface layer of the semiconductor substrate.

[0018] (5) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above-mentioned (1) or (4), in the first step, the raw material gas containing a rare gas or a halogen-based gas may be used.

[0019] According to the above disclosure, it is possible to prevent the surface of the semiconductor substrate from being oxidized during the first step.

[0020] (6) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above-mentioned (1), (4) or (5), after the first step and before the second step, a fifth step of heating the semiconductor substrate at a temperature of 800 ° C or higher and 1000 ° C or lower in an atmosphere not containing oxygen may be included.

[0021] According to the above disclosure, it is possible to recover the damage generated on the surface of the semiconductor substrate during the first step.

[0022] (7) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of the above-mentioned (1) to (6), the first step and the second step may be continuously performed in the same chamber.

[0023] According to the above disclosure, there is no risk that the semiconductor substrate is exposed to the atmosphere between the first step and the second step.

[0024] (8) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of (1) to (7) described above, in the second step, the gate insulating film may be deposited by a sputtering method.

[0025] According to the above disclosure, the first step and the second step can be continuously performed in the same chamber using a plasma processing apparatus.

[0026] (9) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of (1) to (7) described above, in the second step, the gate insulating film may be deposited by a plasma-assisted chemical vapor deposition method.

[0027] According to the above disclosure, the first step and the second step can be continuously performed in the same chamber using a plasma processing apparatus.

[0028] (10) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of (1) to (9) described above, in the second step, after the first step, without exposing the semiconductor substrate to an oxygen atmosphere, without heating the semiconductor substrate, or while heating the semiconductor substrate at a temperature of 600°C or lower, a first deposition step of depositing a silicon-containing layer containing no oxygen atoms on the surface of the semiconductor substrate, and a second deposition step of depositing the gate insulating film on the silicon-containing layer may be included.

[0029] According to the above disclosure, since the silicon-containing layer functions as a cap film that prevents oxidation of the surface of the semiconductor substrate, the steps after the first deposition step can be performed in the air.

[0030] (11) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of (1) to (10) described above, the first step and the first deposition step may be continuously performed in the same chamber.

[0031] According to the above disclosure, there is no risk that the semiconductor substrate is exposed to the atmosphere between the first step and the first deposition step.

[0032] (12) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above (10) or (11), in the first deposition step, the silicon-containing layer may be deposited by a reduced-pressure chemical vapor deposition method using a mixed gas of a gas containing silicon and hydrogen gas.

[0033] According to the above disclosure, the first step and the first deposition step can be continuously performed in the same heating furnace using a heat treatment apparatus.

[0034] (13) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above (10) or (11), in the first deposition step, the silicon-containing layer may be deposited by a plasma-assisted chemical vapor deposition method using a mixed gas of a gas containing silicon and hydrogen gas.

[0035] According to the above disclosure, the first step and the second step can be continuously performed in the same chamber using a plasma processing apparatus.

[0036] (14) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in the above (10) or (11), in the first deposition step, the silicon-containing layer may be deposited by a sputtering method using a silicon target.

[0037] According to the above disclosure, the first step and the second step can be continuously performed in the same chamber using a plasma processing apparatus.

[0038] (15) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of the above (10) to (14), in the first deposition step, the silicon-containing layer may be deposited with a thickness of 1 nm or more and 4 nm or less.

[0039] According to the above disclosure, the entire silicon-containing layer can be made into a SiON film during the third step.

[0040] (16) Further, in the method for manufacturing a silicon carbide semiconductor device according to this disclosure, in any one of the above (10) to (15), in the third step, the interface between the gate insulating film and the semiconductor substrate may be oxynitrided by heat treatment in an atmosphere containing nitrogen and oxygen.

[0041] According to the above-described disclosure, the entire silicon-containing layer can be surely made into a SiON film by the third step.

[0042] (17) A silicon carbide semiconductor device according to one aspect of this disclosure is as follows. A gate insulating film is provided on the surface of a semiconductor substrate made of silicon carbide. A gate electrode is provided on the surface of the semiconductor substrate via the gate insulating film. An insulated gate is formed by the gate insulating film and the gate electrode. Excess carbon present at the interface between the semiconductor substrate and the gate insulating film is distributed within a range of 2 nm or less from the interface between the semiconductor substrate and the gate insulating film to both the semiconductor substrate side and the gate insulating film side, and the ratio of the amount to the carbon amount of the semiconductor substrate is 0.025 or less.

[0043] According to the above-described disclosure, the interface state density (defect density) at the interface (SiO2 / SiC interface) between the gate insulating film and the semiconductor substrate can be reduced, and a decrease in the channel mobility of the MOSFET can be prevented.

[0044] <The knowledge underlying the present disclosure> Generally, when silicon carbide (SiC) is used as a semiconductor material, the defect density (interface state density) at the interface between the oxide film (SiO2 film) and the semiconductor is higher than when silicon (Si) is used as the semiconductor material. Therefore, when manufacturing a silicon carbide semiconductor device equipped with a MOS gate (insulated gate composed of metal - oxide film - semiconductor) using SiC as the semiconductor material, after or before forming the SiO2 film that serves as the gate insulating film, by performing heat treatment (nitridation treatment) using nitrogen monoxide (NO) gas, dinitrogen monoxide (N2O) gas, or nitrogen (N2) gas, the interface between the gate insulating film and the SiC part (hereinafter referred to as the SiO2 / SiC interface) is nitrided to reduce the defect density at the SiO2 / SiC interface.

[0045] However, even when nitridation treatment is performed on the SiO2 / SiC interface, it cannot be said that the defect density at the SiO2 / SiC interface has been sufficiently reduced, and there is room for improvement in terms of the decrease in channel mobility μ FE and the variation in gate threshold voltage Vth. For example, Patent Document 3 also describes that when SiC crystals are oxidized even slightly, a large number of crystal defects are generated at the SiO2 / SiC interface. In addition, SiO2 is decomposed into Si and water and evaporated by heat treatment at a high temperature of 1200 °C or higher using H2 gas. Therefore, in Patent Document 3, it is necessary to form an insulating layer (SiO2) such as a field oxide film after etching with H2 gas, and when forming the field oxide film, the surface of the SiC substrate is oxidized, resulting in a lower reduction effect on channel mobility μ FE

[0046] ​Etching treatment at a high temperature of 1200 °C or higher in the above Patent Document 1, and also etching treatment with atomic hydrogen in a state where the SiC substrate is heated at a temperature of 800 °C or higher in the above Patent Document 2 also cause damage to the insulating layer such as the field oxide film on the surface of the SiC substrate, and the insulation performance deteriorates. For this reason, there is a risk that a design change of the manufacturing process is required. In addition, when performing a high-temperature treatment, an expensive (or expensive and low-productivity) semiconductor manufacturing apparatus is required. In the above Patent Document 4, a defect structure due to thermal oxidation of SiC occurs at the SiO2 / SiC interface, and the distribution width of excess carbon diffusing from the SiO2 / SiC interface into the SiC substrate and the SiO2 film respectively becomes wide.

[0047] Therefore, the problems to be solved in the present embodiment include being able to prevent a decrease in the channel mobility μ FE and preferably being easily applicable to the current manufacturing process.

[0048] Hereinafter, with reference to the accompanying drawings, a method for manufacturing a silicon carbide semiconductor device and a preferred embodiment of the silicon carbide semiconductor device according to this disclosure will be described in detail. In this specification and the accompanying drawings, in a layer or region preceded by n or p, it means that electrons or holes are the majority carriers respectively. Also, + and - attached to n and p respectively mean higher impurity concentration and lower impurity concentration than the layer or region to which they are not attached. In the following description of the embodiments and the accompanying drawings, the same components are denoted by the same reference numerals, and duplicate explanations are omitted.

[0049] (Details of Embodiment 1) The manufacturing method of a silicon carbide semiconductor device according to Embodiment 1 for solving the above problems will be described by taking the case of manufacturing (fabricating) a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor: a MOS-type field effect transistor having an insulated gate composed of a three-layer structure of metal - oxide film - semiconductor), that is, a planar gate type MOSFET, as an example. FIG. 1 is a flowchart showing an overview of the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1. FIGS. 2 to 8 are cross-sectional views showing states during the manufacturing of the silicon carbide semiconductor device according to Embodiment 1.

[0050] First, as shown in FIG. 2, a semiconductor substrate (SiC substrate) 9 using silicon carbide (SiC) as a semiconductor material is fabricated. The semiconductor substrate 9 has an n-type epitaxial layer 11 that becomes an n-type drift region 1 and a p-type epitaxial layer 12 that becomes a p-type base region 2 epitaxially grown in this order on the front surface of an n-type starting substrate (not shown). The semiconductor substrate 9 may be obtained by removing the starting substrate by grinding from the back surface side to the position of the product thickness used as a silicon carbide semiconductor device. Alternatively, the starting substrate may be left. The semiconductor substrate 9 has the first main surface on the p-type epitaxial layer 12 side as the front surface and the second main surface on the n-type epitaxial layer 11 side as the back surface. - type drift region 1 and an n - type epitaxial layer 11 and a p-type epitaxial layer 12 that becomes a p-type base region 2 are epitaxially grown in this order. The semiconductor substrate 9 may be obtained by removing the starting substrate by grinding from the back surface side to the position of the product thickness used as a silicon carbide semiconductor device. Alternatively, the starting substrate may be left. The semiconductor substrate 9 has the first main surface on the p-type epitaxial layer 12 side as the front surface and the second main surface on the n-type epitaxial layer 11 side as the back surface. - type epitaxial layer 11 and a p-type epitaxial layer 12 that becomes a p-type base region 2 are epitaxially grown in this order. The semiconductor substrate 9 may be obtained by removing the starting substrate by grinding from the back surface side to the position of the product thickness used as a silicon carbide semiconductor device. Alternatively, the starting substrate may be left. The semiconductor substrate 9 has the first main surface on the p-type epitaxial layer 12 side as the front surface and the second main surface on the n-type epitaxial layer 11 side as the back surface.

[0051] Next, a diffusion region of a predetermined conductivity type (hereinafter referred to as a SiC region) is formed inside the semiconductor substrate 9 by photolithography and ion implantation of impurities of a predetermined conductivity type (step S1). In the process of step S1, for example, by photolithography and ion implantation of n-type impurities such as phosphorus (P) and arsenic (As), an n-type source region 3 and an n-type drain region are selectively formed inside the p-type epitaxial layer 12 in the surface region of the front surface of the semiconductor substrate 9 in the active region. The portion of the p-type epitaxial layer 12 excluding the n-type source region 3 and the n-type drain region 4 becomes the p-type base region 2. + type source region 3 and an n + type drain region are selectively formed inside the p-type epitaxial layer 12 in the surface region of the front surface of the semiconductor substrate 9 in the active region. The portion of the p-type epitaxial layer 12 excluding the n-type source region 3 and the n-type drain region 4 becomes the p-type base region 2. + type source region 3 and an n + type drain region 4 becomes the p-type base region 2.

[0052] n + type source region 3 and n + type drain region 4 are formed separately from each other between the front surface of the semiconductor substrate 9 and the p-type base region 2 so as to be exposed on the front surface of the semiconductor substrate 9. The p-type base region 2 reaches up to the front surface of the semiconductor substrate 9 between the adjacent n + type source region 3 and n + type drain region 4. An n - type semiconductor substrate 9 may be prepared, and in the process of step S1, a p-type base region 2 may be selectively formed inside the semiconductor substrate 9 by ion implantation of p-type impurities. In this case, n - type semiconductor substrate 9, the p-type base region 2, n + type source region 3 and n + type drain region 4 except part becomes n - type drift region 1.

[0053] In the steps up to here, the semiconductor substrate 9 is oxidized by being exposed to the atmosphere, immersed in a cleaning liquid (acidic solution), or exposed to an oxygen (O2) atmosphere during the deposition of a field oxide film (SiO2) or the like. For this reason, a defect structure containing oxygen atoms (O) and carbon atoms (C) due to SiC oxidation occurs on the front surface (SiC surface of the semiconductor substrate) of the semiconductor substrate 9. This defect structure is not removed by general cleaning treatments such as RCA cleaning or hydrofluoric acid (HF) cleaning. Therefore, by plasma treatment using a non-oxidizing gas, the defect structure due to SiC oxidation on the front surface of the semiconductor substrate 9 is etched (low-temperature plasma etching) at a low temperature together with the surface layer of the front surface of the semiconductor substrate 9 to be removed.

[0054] Specifically, as shown in FIG. 3, the semiconductor substrate 9 is inserted into the chamber 20 of the plasma processing apparatus, and the semiconductor substrate 9 is either not heated or heated to a low temperature of about 400° C. or lower. Then, the front surface (SiC surface) of the semiconductor substrate 9 is subjected to low-temperature plasma etching using the plasma 21 generated by using a non-oxidizing source gas containing hydrogen gas (gaseous hydrogen molecules (H2)) (hereinafter referred to as H2 gas) (step S2: first step). The front surface of the semiconductor substrate 9 is cleaned and etched by the active species (radicals and ions) of hydrogen (H) in the plasma 21. The source gas of the plasma 21 does not contain oxygen atoms and carbon atoms. Therefore, the front surface of the semiconductor substrate 9 is not oxidized during the treatment of step S2. Further, during the treatment of step S2, it is possible to prevent the adhesion and redeposition of carbon-based contaminants on the front surface of the semiconductor substrate 9.

[0055] In the treatment of step S2, the front surface of the semiconductor substrate 9 is exposed to the plasma 21, and the surface layer of the front surface of the semiconductor substrate 9 is dissolved together with the defect structure by reaction with the active species of hydrogen in the plasma 21. More specifically, the defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate 9 is removed by reaction with radicals (atoms and molecules having unpaired electrons * ) of hydrogen (H) in the plasma 21 as shown in the following formulas (1) to (5). In the following formulas (1) to (6), (s) represents the solid state and (g) represents the gas state. The defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate 9 is oxygen-based contaminants and carbon-based contaminants generated by the oxidation of the front surface of the semiconductor substrate 9 before the treatment of step S2.

[0056]

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[0057] The oxygen-based contamination (SiOC(s)) on the front surface of the semiconductor substrate 9 reacts with H radicals (2H * (g)) in the plasma 21 and is decomposed into SiC(s) and water (H2O)(g), which becomes water vapor and is discharged from the chamber 20 to the outside (see the above formula (1)). The carbon-based contamination (CH X (s) (X = 1 to 3), carbon double bond (C=C(s))) on the front surface of the semiconductor substrate 9 reacts with H radicals ((4-X)H * , 4H * , 6H * , 8H * (g)) in the plasma 21 and becomes a hydrocarbon-based gas (C n H m (g), where n and m are positive numbers) and is discharged from the chamber 20 to the outside (see the above formulas (2) to (5)).

[0058] Also, together with the defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate 9, the semiconductor substrate 9 itself (SiC(s)) also reacts with H radicals (8H * (g)) in the plasma 21 and is decomposed into silane gas (SiH4(g)) and methane gas (CH4(g)) and is discharged from the chamber 20 to the outside, and is removed to a certain extent (see the above formula (6)). The H radicals generated in the plasma 21 containing H2 gas are highly reactive. Therefore, when the heating temperature of the semiconductor substrate 9 during etching is high, it is difficult to control the etching amount so that damage to the insulating layer (SiO2) on the front surface of the semiconductor substrate 9 and unevenness on the front surface of the semiconductor substrate 9 do not occur.

[0059] Therefore, the heating temperature (substrate temperature) of the semiconductor substrate 9 during the process of step S2 is preferably a relatively low temperature of about 400°C or lower, and more preferably about 200°C or lower as described above. By performing the process of step S2 at a low temperature, even if an insulating layer such as a field oxide film exists on the front surface of the semiconductor substrate 9 during the process of step S2, almost no damage is caused to the insulating layer, so the degree of freedom in the design of the manufacturing process increases. In addition, by performing the process of step S2 at a low temperature, the process of step S2 can be performed using a general plasma processing apparatus, so the cost can be suppressed at a low level.

[0060] Since the source gas of the plasma 21 contains H2 gas, even if the heating temperature (substrate temperature) of the semiconductor substrate 9 during the process of step S2 is lowered, the front surface of the semiconductor substrate 9 can be efficiently etched. The plasma 21 generated in the process of step S2 can use general plasmas such as capacitively coupled plasma (CCP), inductively coupled plasma (ICP), and electron cyclotron resonance (ECR) plasma.

[0061] During the process of step S2, since relatively light H radicals are collided (sputtered) to etch the front surface of the semiconductor substrate 9, the etching amount of the semiconductor substrate 9 itself can be made relatively small. However, if the pressure in the chamber 20 is high during the generation of the plasma 21, the density of active species in the plasma 21 increases, and the reaction between the semiconductor substrate 9 itself and the active species in the plasma 21 is promoted, resulting in unevenness on the front surface of the semiconductor substrate 9 and an increase in the height difference of the unevenness. Therefore, the pressure in the chamber 20 during the generation of the plasma 21 is preferably about 1 Pa to 100 Pa (more preferably about 50 Pa or lower).

[0062] Also, in the process of step S2, the source gas of the plasma 21 does not contain oxygen atoms as described above. Therefore, it is possible to suppress the deposition of surplus carbon (carbon atoms remaining after the bond with Si atoms is broken) on the front surface of the semiconductor substrate 9 due to the bonding between the Si atoms in the semiconductor substrate 9 and the oxygen atoms in the source gas of the plasma 21 during the process of step S2. Since it is preferable that the amount of oxygen in the chamber 20 is as small as possible, after inserting the semiconductor substrate 9 into the chamber 20, the inside of the chamber 20 is evacuated (vacuum evacuation) and depressurized to about 0.05 Pa or less, for example, to reduce the amount of oxygen in the chamber 20, and then the plasma 21 is generated.

[0063] Next, as shown in FIG. 4, without exposing the semiconductor substrate 9 to an oxygen atmosphere continuously with the process of step S2, an oxide film (SiO2) serving as the gate insulating film 5 is deposited on the front surface of the semiconductor substrate 9 (step S3: second step, second deposition step). In the process of step S3, a general SiO2 deposition method such as a sputtering method, a plasma-enhanced chemical vapor deposition (PECVD) method, or a low-pressure (LP) CVD method (thermal CVD method) may be used to deposit the gate insulating film 5 without oxidizing the front surface of the semiconductor substrate 9 (that is, by a method other than thermal oxidation).

[0064] Since the SiC surface after plasma etching (the process of step S2) is easily oxidized, it is preferable to perform the processes of step S2 and step S3 in the same chamber 20. For example, in a general plasma processing apparatus that generates a self-bias Vdc between electrodes to which an RF (Radio Frequency) voltage is applied by an AC power supply, by switching the insertion position of a blocking capacitor (a capacitor that blocks DC components) to switch the electrode on the negative electrode side (the electrode on the semiconductor substrate 9 side or the electrode on the target material side), the processes of step S2 and step S3 can be continuously performed in the same chamber 20.

[0065] For example, when using a CCP type plasma processing apparatus, within the same chamber 20, CCP plasma etching of the SiC surface and film formation of SiO2 by sputtering or PECVD can be continuously processed. When depositing the gate insulating film 5 using the LPCVD method, the conveyance path of the semiconductor substrate 9 from within the chamber 20 where the process of step S2 is performed to the thermal CVD furnace where the process of step S3 is performed may be evacuated or filled with an inert gas. The gate insulating film 5 may also be deposited using the atomic layer deposition (ALD) method.

[0066] Next, as shown in FIG. 5, the front surface of the semiconductor substrate 9 is nitrided by a heat treatment (POA: Post Oxide Anneal) at about 1150°C or higher and 1300°C or lower using nitrogen monoxide (NO) gas, dinitrogen monoxide (N2O) gas, or nitrogen (N2) gas (step S4: third step). By the process of step S4, an interface region (hereinafter referred to as the gate insulating film 6) having a silicon oxynitride (SiON) or silicon nitride (SiN) composition is formed so as to include the interface 16 at the interface (SiO2 / SiC interface) 16 between the gate insulating film 5 and the semiconductor substrate 9, and the defect density of the SiO2 / SiC interface 16 is reduced. In the process of step S4, it is preferable to perform POA using a gas containing oxygen.

[0067] The defect density of the SiO2 / SiC interface 16 is reduced because the generation of excess carbon derived from SiC oxidation at the SiO2 / SiC interface 16 is suppressed. Further, by suppressing the generation of excess carbon derived from SiC oxidation, the amount of excess carbon at the SiO2 / SiC interface 16 is reduced, and the amount of excess carbon diffused from the SiO2 / SiC interface 16 is also reduced. For this reason, the width (excess carbon distribution width) in which excess carbon diffuses in a direction orthogonal to the SiO2 / SiC interface 16 from the SiO2 / SiC interface 46 becomes narrow. The ratio of the amount of excess carbon at the SiO2 / SiC interface 16 to the carbon amount of the semiconductor substrate 9 is at most 0.025 at the SiO2 / SiC interface 16 (that is, 0.025 or less in the vicinity of the SiO2 / SiC interface 16).

[0068] The amount of excess carbon at the SiO2 / SiC interface 16 decreases as it goes from the SiO2 / SiC interface 16 toward the semiconductor substrate 9 side and the gate insulating film 5 side, respectively. The excess carbon at the SiO2 / SiC interface 16 is distributed in a narrow range within 2 nm from the SiO2 / SiC interface 16 toward both the semiconductor substrate 9 side and the gate insulating film 5 side. That is, the distribution width of the excess carbon at the SiO2 / SiC interface 16 is within ±2 nm from the SiO2 / SiC interface 16 to the semiconductor substrate 9 side and the gate insulating film 5 side (defined as the plus side and the minus side from the reference position, respectively) with the reference (=0 nm).

[0069] Next, as shown in FIG. 6, a gate electrode 7 is formed on the surface of the gate insulating film 5 (step S5: fourth step). The gate electrode 7 is formed on the portion of the p-type base region 2 sandwiched between the n + type source region 3 and the n + type drain region 4 through the gate insulating film 5. The gate electrode 7 is, for example, a polysilicon (poly-Si) layer deposited by a general deposition method such as LPCVD. A part of the gate electrode 7 may be extended to a predetermined location (a region excluding the active region (the region where the cells of the MOSFET are arranged)), and a gate polysilicon wiring layer that functions as a gate runner may be formed by the extended portion of the gate electrode 7.

[0070] Next, as shown in FIG. 7, an interlayer insulating film 8 is formed on the entire front surface of the semiconductor substrate 9. Next, contact holes 8a and 8b that penetrate the interlayer insulating film 8, the gate insulating film 5, and the gate insulating film 6 in the depth direction and reach the semiconductor substrate 9 are formed. A contact hole 8c that penetrates the interlayer insulating film 8 in the depth direction is formed. The n + type source region 3 is exposed in the contact hole 8a, and the n + type drain region 4 is exposed in the contact hole 8b. The extended portion (gate polysilicon wiring layer) of the gate electrode 7 is exposed in the contact hole 8c and functions as a gate runner that becomes a connection portion with a gate pad (not shown).

[0071] Next, an aluminum (Al) film or an Al alloy film is formed and patterned on the front surface of the semiconductor substrate 9 to form a source electrode 13, a drain electrode 14, a gate metal wiring layer 15, and a gate pad (not shown) as surface electrodes (step S6). The source electrode 13 is electrically connected to the n + type source region 3 through an ohmic electrode (not shown) and a barrier metal (not shown) in the contact hole 8a. The drain electrode 14 is electrically connected to the n + type drain region 4 through an ohmic electrode (not shown) and a barrier metal (not shown) in the contact hole 8b.

[0072] The ohmic electrode is, for example, a nickel silicide (Ni X Si Y , where X and Y are positive numbers) film, and makes an ohmic contact with the front surface of the semiconductor substrate 9. The barrier metal is, for example, a titanium (Ti) film, and has a function of preventing atomic diffusion and mutual reaction between regions or metals facing each other with the barrier metal interposed therebetween. The gate polysilicon wiring layer is formed on the front surface of the semiconductor substrate 9 through a field oxide film (not shown). The gate metal wiring layer 15 is formed on the gate polysilicon wiring layer (the extending portion of the gate electrode 7) in the contact hole 8c and functions as a gate runner.

[0073] The field oxide film is disposed over the entire region excluding the active region (the region where the cells of the MOSFET are arranged) between the front surface of the semiconductor substrate 9 and the interlayer insulating film 8. Since the low-temperature plasma etching treatment in step S2 is performed at a low temperature as described above, even if an insulating layer (SiO2) such as a field oxide film exists on the front surface of the semiconductor substrate 9 during the treatment in step S2, almost no damage is caused to the insulating layer. Therefore, the field oxide film can be formed at an arbitrary timing after the treatment in step S1 and before the formation of the interlayer insulating film 8. The interlayer insulating film 8 may also serve as the field oxide film.

[0074] Thereafter, the entire front surface of the semiconductor substrate 9 is covered and protected with a passivation film. Then, the passivation film is partially removed by photolithography and etching to expose portions that will become electrode pads (source pad, drain pad, and gate pad) in different openings of the passivation film, thereby completing the lateral MOSFET 10 shown in FIG. 8. The portion of the source electrode 13 that is exposed in the opening of the passivation film functions as the source pad. The portion of the drain electrode 14 that is exposed in the opening of the passivation film functions as the drain pad.

[0075] Also, in the method for manufacturing a silicon carbide semiconductor device according to the above-described Embodiment 1, instead of the lateral MOSFET 10 (see FIG. 8), a vertical MOSFET having a planar gate structure may be fabricated. In this case, at the time of the process of step S1, on the front surface of the n-type starting substrate that will become the n-type drain region, the epitaxial layers 11 and 12 that will become the n-type drift region 1 and the p-type base region 2 are epitaxially grown, and at the time of the process of step S6, a drain electrode may be formed on the back surface of the n-type starting substrate. The n-type drain region may be formed by ion implantation of n-type impurities into the back surface of the semiconductor substrate 9 before the process of step S6. + type drain region of n + type starting substrate, n - type drift region 1 and p-type base region 2 of each epitaxial layer 11, 12 are epitaxially grown, and at the time of the process of step S6, n + type starting substrate, a drain electrode may be formed on the back surface. The n + type drain region may be formed by ion implantation of n-type impurities into the back surface of the semiconductor substrate 9 before the process of step S6.

[0076] In the method for manufacturing the above-described vertical MOSFET, instead of the planar gate structure, a trench gate structure may be formed. In this case, after the process of step S1, a trench is formed that penetrates the n-type source region 3 and the p-type base region 2 from the front surface of the semiconductor substrate 9 to reach the n-type drift region 1, and low-temperature plasma etching of the process of step S2 is performed on the inner wall of the trench (SiC surface). To form the trench, for example, an oxide film serving as an etching mask is deposited on the front surface of the semiconductor substrate 9, and the portion corresponding to the trench formation region of the oxide film is removed by dry etching to open an aperture. + type source region 3 and p-type base region 2 to penetrate the n - type drift region 1 to reach the trench, and low-temperature plasma etching of the process of step S2 is performed on the inner wall of the trench (SiC surface). To form the trench, for example, an oxide film serving as an etching mask is deposited on the front surface of the semiconductor substrate 9, and the portion corresponding to the trench formation region of the oxide film is removed by dry etching to open an aperture.

[0077] Using the remaining portion of this oxide film as a mask, trenches are formed by dry etching using a mixed gas containing sulfur hexafluoride (SF6) gas, oxygen (O2) gas, and argon (Ar) gas, for example, by an ICP etching apparatus. Then, all of the oxide film used as an etching mask is removed, for example, by hydrofluoric acid. Heat treatment may be performed to control the trench shape. Thereafter, in the process of step S3, a gate insulating film is deposited along the inner wall of the trench using, for example, the LPCVD method. After the process of step S4, in the process of step S5, a gate electrode may be embedded on the gate insulating film inside the trench.

[0078] As described above, according to Embodiment 1, a defect structure caused by SiC oxidation on the front surface (SiC surface) of the semiconductor substrate is removed by low-temperature plasma etching using a non-oxidizing source gas containing H2 gas. Since the source gas of the plasma does not contain oxygen atoms, oxidation of the front surface of the semiconductor substrate can be prevented during low-temperature plasma etching. In addition, since the front surface of the semiconductor substrate is plasma-etched at a low temperature, a general plasma processing apparatus can be used, and the cost can be suppressed at a low level. Further, even if an insulating layer such as a field oxide film is present on the front surface of the semiconductor substrate during low-temperature plasma etching, almost no damage is caused to the insulating layer.

[0079] Further, according to Embodiment 1, after the low-temperature plasma etching treatment of the front surface of the semiconductor substrate, a gate insulating film (SiO2) is deposited on the front surface of the semiconductor substrate without exposing the semiconductor substrate to an oxygen atmosphere. As a result, after removing the defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate, the gate insulating film can be deposited on the front surface of the semiconductor substrate without re-oxidizing the front surface of the semiconductor substrate. Therefore, the interface state density (defect density) at the interface (SiO2 / SiC interface) between the gate insulating film and the semiconductor substrate can be reduced, and a decrease in the channel mobility of the MOSFET can be prevented. Further, by forming the gate insulating film in this way, generation of excess carbon derived from the oxidation of SiC at the interface between the gate insulating film and the semiconductor substrate can be suppressed, and the amount of excess carbon and the excess carbon distribution width at the SiO2 / SiC interface are reduced.

[0080] Further, when chemically dry etching or plasma etching a defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate or a damaged layer due to ion implantation using, for example, a gas containing CF4 and oxygen, a carbon-based polymer (polymer) containing fluorine is generated and adheres to the front surface of the semiconductor substrate. This carbon-based polymer containing fluorine causes a decrease in the reliability of the gate insulating film. According to Embodiment 1, since the source gas used during the low-temperature plasma etching of the front surface of the semiconductor substrate does not contain carbon atoms, a decrease in the reliability of the gate insulating film can be prevented.

[0081] (Details of Embodiment 2) The manufacturing method of a silicon carbide semiconductor device according to Embodiment 2 for solving the above problems will be described below. FIG. 9 is a flowchart showing an outline of the manufacturing method of a silicon carbide semiconductor device according to Embodiment 2. The structure of the silicon carbide semiconductor device manufactured by the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2 is the same as that of Embodiment 1 (for example, the horizontal MOSFET 10 in FIG. 8). The difference between the manufacturing method of the silicon carbide semiconductor device according to Embodiment 2 and the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 (see FIG. 1) is that a low-temperature plasma etching process (the process in step S12) is performed using a non-oxidizing source gas containing a rare gas.

[0082] Specifically, in Embodiment 2, similar to the process in step S1 of Embodiment 1, a semiconductor substrate 9 is fabricated, and a SiC region is formed inside the semiconductor substrate 9 (step S11, FIG. 2). Next, the front surface of the semiconductor substrate 9 is subjected to low-temperature plasma etching using a non-oxidizing gas containing a rare gas (step S12, FIG. 3). In the process of step S12, the active species of the rare gas in the plasma 21 are made to collide with the front surface of the semiconductor substrate 9, and the surface layer of the front surface of the semiconductor substrate 9 is scraped off atom by atom together with the defect structure. Other conditions are the same as the process in step S2 of Embodiment 1 except that the source gas of the plasma 21 contains a rare gas such as argon (Ar), neon (Ne), or krypton (Kr) instead of H2 gas.

[0083] The low-temperature plasma etching process in step S12 is a sputter etching that blows off the defect structure and the surface atoms of the front surface of the semiconductor substrate 9 by sputtering with rare gas ions (ionizing and colliding with a rare gas). Therefore, it is advisable to appropriately adjust the discharge power (RF power) for generating the plasma 21 and the bias voltage (RF voltage) applied to the semiconductor substrate 9 to avoid excessive ion collision on the front surface of the semiconductor substrate 9. By using a rare gas that is chemically stable and difficult to react with other atoms, re-oxidation of the front surface of the semiconductor substrate 9 during the low-temperature plasma etching process in step S12 can be suppressed.

[0084] Also, the damage generated on the front surface of the semiconductor substrate 9 due to ion collision during the process of step S12 may be recovered by heating the semiconductor substrate 9 in an oxygen-free atmosphere (step S13: fifth step). The oxygen-free atmosphere means a state where the inside of the chamber 20 of the plasma processing apparatus is evacuated to a vacuum, or a state where the inside of the chamber 20 is filled with an inert gas atmosphere or an inert gas atmosphere containing hydrogen gas. The heat treatment in step S13 is preferably performed at a temperature of 800°C or higher at which, for example, a damage recovery effect on the SiC surface can be obtained, and at a temperature of about 1000°C or lower at which deposition of graphene (excess carbon) due to Si sublimation does not occur.

[0085] The low-temperature plasma etching process of step S12 may be performed using a non-oxidizing source gas containing a mixed gas of a rare gas and H2 gas, or may be performed using a non-oxidizing source gas containing a halogen-based gas such as nitrogen trifluoride (NF3) gas or chlorine trifluoride (ClF3) gas instead of the rare gas. Further, the process of step S12 may be chemical etching using a halogen-based gas containing no oxygen atoms and carbon atoms as an etching gas, performed with the heating temperature of the semiconductor substrate 9 being about 400°C or lower instead of plasma etching. By using a halogen-based gas, the rate of the low-temperature plasma etching process of step S12 is increased. Even when a halogen-based gas is used, the low-temperature plasma etching process of step S12 becomes sputter etching in which the halogen-based gas is ionized and collided with the front surface of the semiconductor substrate 9.

[0086] Thereafter, in the same manner as in Embodiment 1, deposition of the gate insulating film 5 (step S14, FIG. 4), nitridation of the SiO2 / SiC interface 16 (step S15, FIG. 5), formation of the gate electrode 7 (step S16, FIG. 6), and formation of the surface electrodes 13 to 15 (step S17, FIGS. 7 and 8) are performed in this order, and a MOSFET similar to that in Embodiment 1 is completed. The processes of steps S14 to S17 are the same as the processes of steps S3 to S6 in Embodiment 1, respectively. The processes from step S12 to step S14 are preferably performed without exposing the semiconductor substrate 9 to an oxygen atmosphere, and more preferably continuously performed in the same chamber 20.

[0087] As described above, according to Embodiment 2, before depositing the gate insulating film, by performing a low-temperature plasma etching process using a non-oxidizing source gas containing a rare gas or a halogen-based gas to remove the defect structure caused by the oxidation of SiC on the front surface of the semiconductor substrate, the same effects as those in Embodiment 1 can be obtained.

[0088] (Details of Embodiment 3) Hereinafter, a method for manufacturing a silicon carbide semiconductor device according to Embodiment 3 for solving the above problems will be described. FIG. 10 is a flowchart showing an outline of the method for manufacturing a silicon carbide semiconductor device according to Embodiment 3. FIGS. 11 to 16 are cross-sectional views showing the states during the manufacture of the silicon carbide semiconductor device according to Embodiment 3. The difference between the method for manufacturing a silicon carbide semiconductor device according to Embodiment 3 and the method for manufacturing a silicon carbide semiconductor device according to Embodiment 1 is that after the low-temperature plasma etching process and before depositing the gate insulating film, a silicon (Si) layer or a silicon-containing layer (hereinafter collectively referred to as the Si-containing layer 31) is formed on the front surface of the semiconductor substrate 9 (the process of step S23).

[0089] Specifically, in Embodiment 3, similar to the process of Step S1 in Embodiment 1, a semiconductor substrate 9 is fabricated, and an SiC region is formed inside the semiconductor substrate 9 (Step S21, Figure 2). Next, similar to the process of Step S2 in Embodiment 1, a defect structure caused by SiC oxidation on the front surface of the semiconductor substrate 9 is removed by low-temperature plasma etching using a source gas containing H2 gas (Step S22, Figure 3). Next, as shown in Figure 11, without exposing the semiconductor substrate 9 to an oxygen atmosphere continuously following the process of Step S22, an Si-containing layer 31 that does not contain oxygen atoms is deposited on the front surface of the semiconductor substrate 9 (Step S23: First deposition step).

[0090] In the process of Step S23, the semiconductor substrate 9 is not heated or is heated to a low temperature of about 600°C or lower, and a general deposition method such as the LPCVD method, PECVD method, or sputtering method (by a method other than thermal oxidation) is used to deposit the Si-containing layer 31. For example, in the LPCVD method, a mixed gas of silane (SiH4) gas and H2 gas is used as the film-forming gas, the pressure in the furnace is set to about 20 Pa or more and 500 Pa or less, and the heating temperature of the semiconductor substrate 9 is set to about 400°C or more and less than 600°C, whereby an amorphous silicon (a-Si:H) film, a microcrystalline Si film, or a mixed film thereof is formed as the Si-containing layer 31.

[0091] In the PECVD method, a mixed gas of SiH4 gas and H2 gas is used as the plasma source gas, the discharge pressure is set to about 20 Pa or more and 100 Pa or less, and the heating temperature of the semiconductor substrate 9 is set to about 200°C or more and 400°C or less, whereby an a-Si:H film is formed as the Si-containing layer 31. In the sputtering method, a silicon target is used, the furnace is filled with an inert gas such as Ar gas, the pressure in the furnace is set to about 0.5 Pa or more and 10 Pa or less, and the semiconductor substrate 9 is not heated or the heating temperature of the semiconductor substrate 9 is set to 600°C or lower, whereby an a-Si:H film or a microcrystalline Si film can be formed as the Si-containing layer 31.

[0092] When depositing the Si-containing layer 31 using the LPCVD method or the PECVD method, by adding nitrogen (N2) gas or ammonia (NH3) gas to the film-forming gas, a silicon nitride (SiN X , where X is a positive number) film may be formed. When depositing the Si-containing layer 31 using the LPCVD method, by setting the heating temperature of the semiconductor substrate 9 to about 500°C, for example, a relatively thin Si-containing layer 31 can be formed. By forming the Si-containing layer 31 using the PECVD method or the sputtering method, the thickness control of the Si-containing layer 31 is easy, and a Si-containing layer 31 thinner than other deposition methods can be easily formed.

[0093] Also, when depositing the Si-containing layer 31 using the LPCVD method, the process of step S22 is performed in a heating furnace (thermal CVD furnace), and then, by switching the conditions in the heating furnace (supply gas, pressure in the furnace, heating temperature of the semiconductor substrate 9, etc.) to the processing conditions of step S23, the processes of steps S22 and S23 can be continuously performed in the same heating furnace. When depositing the Si-containing layer 31 using the PECVD method or the sputtering method, by switching the conditions in the chamber 20 where the process of step S22 is performed to the processing conditions of step S23, the processes of steps S22 and S23 can be continuously performed in the same chamber 20.

[0094] The Si-containing layer 31 functions as a cap film for preventing oxidation of the front surface of the semiconductor substrate 9. Therefore, re-oxidation of the front surface of the semiconductor substrate 9 during the process of step S23 can be suppressed. The thickness of the Si-containing layer 31 is preferably in the range of, for example, 1 nm or more and 4 nm or less. Thereby, the entire Si-containing layer 31 can be easily made into a SiO2 film or a SiON film during the process of step S25 performed later. When the thickness of the Si-containing layer 31 exceeds the above upper limit value (for example, about 5 nm), the process of step S25 may be performed under conditions where the entire Si-containing layer 31 is completely oxynitrided.

[0095] Also, by heating the semiconductor substrate 9 during the process of step S23 at a low temperature of about 600°C or lower, since Si is difficult to crystallize, the Si-containing layer 31 can be deposited on the front surface of the semiconductor substrate 9 with a substantially uniform thickness. Substantially uniform thickness means the same thickness within a range including the allowable error due to manufacturing process variations. Since the front surface of the semiconductor substrate 9 is uniformly covered with the Si-containing layer 31, the front surface of the semiconductor substrate 9 does not oxidize even when exposed to the atmosphere. Therefore, subsequent processing can be performed with the semiconductor substrate 9 exposed to the atmosphere.

[0096] Next, as shown in FIG. 12, a gate insulating film 32 is formed on the Si-containing layer 31 (step S24). The conditions for depositing the gate insulating film 32 in the process of step S24 are the same as the conditions for depositing the gate insulating film 5 in the process of step S3 of Embodiment 1. Next, as shown in FIG. 13, the Si-containing layer 31 is oxynitrided by a heat treatment (POA: Post Oxide Anneal) of 1150°C or higher and 1300°C or lower using NO gas or N2O gas (step S25). The process of step S25 also serves as a nitridation treatment of the interface (SiO2 / SiC interface 36) between the gate insulating film 32 and the semiconductor substrate 9.

[0097] In the process of step S25, it is often preferable to perform POA using a gas containing oxygen, and the entire Si-containing layer 31 becomes an oxide film (SiO2 film or SiON film) that functions as a gate insulating film (interface region having a SiO2 or SiON composition) 33. During the process of step S25, since the front surface of the semiconductor substrate 9 is covered by the Si-containing layer 31, the process of step S25 may be performed in an environment where the semiconductor substrate 9 is exposed to an oxygen atmosphere (for example, under atmospheric pressure). Thereafter, similar to the processes of steps S5 and S6 of Embodiment 1, the formation of the gate electrode 7 (step S26, FIG. 14) and the formation of the surface electrodes 13 to 15 (step S27, FIGS. 15 and 16) are performed in this order.

[0098] The contact holes 8d and 8e penetrate the interlayer insulating film 8 and the gate insulating films 32 and 33 in the depth direction and reach the semiconductor substrate 9. n +The p-type source region 3 is exposed to the contact hole 8d, and the n + -type drain region 4 is exposed to the contact hole 8e. The source electrode 13 and the drain electrode 14 are electrically connected to the p-type source region 3 and the n + -type drain region 4 at the contact holes 8d and 8e, respectively, in the same manner as in the first embodiment. The configuration of the gate metal wiring layer 15 and the contact hole 8c is the same as in the first embodiment. Thus, the MOSFET 30 shown in FIG. 16 is completed. + The structure of the lateral MOSFET 30 shown in FIG. 16 is the same as that of the lateral MOSFET 10 in FIG. 8. In the method for manufacturing a silicon carbide semiconductor device according to the third embodiment described above, instead of the lateral MOSFET 30, a vertical MOSFET having a planar gate structure or a vertical MOSFET having a trench gate structure may be fabricated in the same manner as in the first embodiment. The method for manufacturing a silicon carbide semiconductor device according to the second embodiment (see FIG. 9) may be applied to the method for manufacturing a silicon carbide semiconductor device according to the third embodiment, and the low-temperature plasma etching in step S22 may be performed using a non-oxidizing source gas containing a rare gas or a halogen-based gas.

[0099] In the method for manufacturing a silicon carbide semiconductor device according to the third embodiment, the low-temperature plasma etching process in step S22 may be performed without exposing the semiconductor substrate 9 to an oxygen atmosphere, and may be performed in a state where the semiconductor substrate 9 is heated to a high temperature of about 1300°C or higher and 1600°C or lower using a non-oxidizing source gas containing H2 gas. Further, the low-temperature plasma etching process in step S22 may be performed in any pressure atmosphere of a reduced-pressure atmosphere, an atmospheric pressure atmosphere, and a high-pressure atmosphere, and specifically, for example, in a pressure atmosphere of about 67 Pa or higher and 4000 Pa or lower.

[0100]

[0101] ​As described above, according to Embodiment 3, after removing the defect structure caused by the oxidation of the front surface of the semiconductor substrate by low-temperature plasma etching using a non-oxidizing source gas, without exposing the semiconductor substrate to an oxygen atmosphere, a Si-containing layer that does not contain oxygen atoms is deposited on the front surface of the semiconductor substrate. Since the front surface of the semiconductor substrate is covered with the Si-containing layer, the front surface of the semiconductor substrate is not oxidized even when it is exposed to an oxygen atmosphere in subsequent processing. Therefore, the same effects as those of Embodiment 1 can be obtained.

[0102] (Verification Example 1) The relationship between the heating temperature of the semiconductor substrate 9 and the defect density of the SiO2 / SiC interfaces 16 and 36 during the processing (low-temperature plasma etching) of steps S2 and S12 in FIGS. 1 and 9 was verified. FIG. 17 is a cross-sectional view showing the structure of a general MOS capacitor. According to the manufacturing method of the silicon carbide semiconductor device according to Embodiments 1 and 2 described above (see FIGS. 1 and 9), an MOS capacitor 40 (hereinafter referred to as Examples 1 to 4 and Comparative Example 1) was fabricated on an n-type SiC substrate (semiconductor substrate) 41 shown in FIG. 17. The SiC substrate 41 is a 4H-SiC (tetragonal periodic hexagonal crystal of silicon carbide) substrate. The front surface of the SiC substrate 41 is a (0001) surface having an off-angle of about 4 degrees in the <11-20> direction, a so-called Si surface. The thickness of the SiC substrate 41 is 5 μm.

[0103] A SiON film 43, a SiO2 film 42, and an Al electrode layer 44 are formed in this order on the front surface of the SiC substrate 41, and an Al electrode layer 45 is formed on the back surface of the SiC substrate 41. In Examples 1 to 4 and Comparative Example 1, the SiC substrate 41, the SiO2 film 42, the SiON film 43, and the Al electrode layer 44 respectively correspond to the semiconductor substrate 9, the gate insulating film 5, the gate insulating film 6, and the gate electrode 7 (gate pad) of the lateral MOSFET 10 shown in FIG. 8. In Examples 1 to 4 and Comparative Example 1, before the formation of the SiO2 film 42 (corresponding to the processing of steps S3 and S14), the front surface of the SiC substrate 41 was subjected to low-temperature plasma etching under different conditions (corresponding to the processing of steps S2 and S12).

[0104] FIG. 18 is a chart showing the surface treatment conditions of the SiC substrate before forming the gate insulating film (SiO2 film 42) in Examples 1 to 4 and Comparative Example 1. In FIG. 18, in the low-temperature plasma etching treatment (SiC substrate surface treatment) of the front surface of the SiC substrate 41, the non-oxidizing source gas (introduced gas: H2 gas or Ar gas) introduced into the chamber 20 of the plasma apparatus when generating the plasma 21, the discharge pressure and discharge power for generating the plasma 21, the heating temperature (substrate heating) of the SiC substrate 41, and the treatment time of the low-temperature plasma etching are shown. The low-temperature plasma etching treatment of the front surface of the SiC substrate 41 in Examples 1 to 4 and Comparative Example 1 was performed using a CCP type plasma processing apparatus.

[0105] In both Examples 1 to 4 and Comparative Example 1, after the low-temperature plasma etching treatment (corresponding to steps S2 and S12 in FIGS. 1 and 9) of the front surface of the SiC substrate 41 in the chamber 20, the SiO2 film 42, which is the gate insulating film, was formed by a sputtering method using an SiO2 target in the same chamber 20 (corresponding to steps S3 and S14 in FIGS. 1 and 9). The thickness of the SiO2 film 42 was set to 50 nm. In both Examples 1 to 4 and Comparative Example 1, the SiON film 43 was formed by POA at a temperature of 1250° C. for 60 minutes using a mixed gas of 90% N2 gas and 10% NO gas (corresponding to steps S4 and S15 in FIGS. 1 and 9).

[0106] In both Examples 1 to 4 and Comparative Example 1, the Al electrode layers 44 and 45 were vapor-deposited in a vacuum atmosphere while the SiC substrate 41 was heated. The thickness of the Al electrode layers 44 and 45 is 100 nm or less. The Al electrode layer 44, which is the gate electrode, has a circular planar shape with a diameter of 200 μm. Examples 1 to 3 correspond to Embodiment 1, and Example 4 corresponds to Embodiment 2. Comparative Example 1 is different from Examples 2 and 3 in that the heating temperature of the SiC substrate 41 was set to a high temperature of 500° C. Comparative Example 2 is the same as Examples 1 to 4 except that it was fabricated by a general gate process (that is, the low-temperature plasma etching treatment of the front surface of the SiC substrate 41 was not performed).

[0107] The results of calculating the interface state density of the SiO2 / SiC interface (the interface between the SiO2 film 42 and the SiC substrate 41) 46 in the above-described Examples 1 to 4 and Comparative Examples 1 and 2 are shown in FIG. 19. FIG. 19 is a chart showing the results of measuring the interface state density of the SiO2 / SiC interface 46 in Examples 1 to 4 and Comparative Examples 1 and 2. The SiC substrate surface treatment conditions in FIG. 19 are the same as those in FIG. 18. The interface state density of the SiO2 / SiC interface 46 in FIG. 19 was calculated by the High-Low C-V method using the high-frequency C-V (capacitance-voltage) characteristics at 1 MHz and the low-frequency C-V characteristics at 100 Hz based on the measured values in Examples 1 to 4 and Comparative Examples 1 and 2.

[0108] As shown in FIG. 19, in Examples 1 to 4, the interface state density (defect density) of the SiO2 / SiC interface 46 was lower than that in Comparative Example 2. Comparative Example 2 was fabricated by a general gate process, and the interface state density of its SiO2 / SiC interface 46 was about 4×10 11 ~1×10 12 . On the other hand, in Comparative Example 1, the interface state density of the SiO2 / SiC interface 46 increased compared to Comparative Example 2. The reason is presumably that the high heating temperature of the SiC substrate 41 accelerated the low-temperature plasma etching process on the front surface of the SiC substrate 41, increasing the damage to the front surface of the SiC substrate 41 and the surface roughness of the front surface of the SiC substrate 41.

[0109] The results of calculating the field-effect mobility of the horizontal MOSFET 10 (see FIG. 8: hereinafter referred to as Examples 5 to 7 and Comparative Example 3) simulated based on the interface state density of the SiO2 / SiC interface 46 obtained in FIG. 19 are shown in FIG. 21. FIG. 20 is a chart showing the SiC substrate surface treatment conditions (low-temperature plasma etching treatment conditions on the front surface of the semiconductor substrate) before forming the gate insulating film in Examples 5 to 7 and Comparative Example 3. FIG. 21 is a chart showing the results of calculating the field-effect mobility in Examples 5 to 7 and Comparative Example 3. The SiC substrate surface treatment conditions in FIGS. 20 and 21 are the same as those in FIG. 18. Examples 5 to 7 each include an MO gate formed under the same conditions as those in the above-described Examples 1, 2, and 4.

[0110] In Examples 5 to 7, the semiconductor substrate 9 has an n - -type drift region 1 formed by epitaxially growing an n - -type epitaxial layer 11 and a p-type epitaxial layer 12 that becomes a p-type base region 2. The 4H-SiC substrate is the starting substrate for the epitaxial growth of the epitaxial layers 11 and 12. The front surface of the 4H-SiC substrate is a (0001) plane having an off-angle of about 4 degrees in the <11-20> direction, a so-called Si plane. The dopant of the epitaxial layer 11 is nitrogen (N). The dopant and acceptor concentration N A of the p-type epitaxial layer 12 are aluminum (Al) and 1×10 16 / cm 3 , respectively.

[0111] The n + -type source region 3 and the n + -type drain region 4 are SiC regions formed by ion implantation of phosphorus (P). The gate electrode 7 is a polysilicon layer deposited using the LPCVD method. The ohmic electrode is a Ni X Si Y (X, Y are positive numbers) film. The barrier metal is a Ti film. The source electrode 13, the drain electrode 14, the gate metal wiring layer 15, and the gate pad are Al films. Comparative Example 3 has an MO gate formed under the same conditions as Comparative Example 2 described above and is fabricated by a general gate process (without performing low-temperature plasma etching treatment on the front surface of the SiC substrate 41 (without SiC substrate surface plasma etching treatment)), and the other conditions are the same as those in Examples 5 to 7.

[0112] As shown in FIG. 21, in any of Examples 5 to 7, the field-effect mobility was increased by approximately 20% or more compared to Comparative Example 3. It was confirmed that the decrease in the interface state density of the SiO2 / SiC interface 46 (see FIG. 19) greatly contributed to the improvement of the field-effect mobility. Since Examples 5 to 7 are the lateral MOSFETs 10 corresponding to Examples 1, 2, and 4 in which the interface state density of the SiO2 / SiC interface 46 decreased, it is presumed that the field-effect mobility of the lateral MOSFET 10 corresponding to Example 3 also increases compared to Comparative Example 3. Therefore, it was confirmed that the heating temperature of the semiconductor substrate 9 during the low-temperature plasma etching process in Steps S2 and S12 of FIGS. 1 and 9 is preferably 400° C. or lower.

[0113] (Verification Example 2) The relationship between the process of Step S23 in FIG. 10 (deposition of the Si-containing layer 31 serving as a cap film, see FIG. 11) and the defect density of the SiO2 / SiC interface 46 was verified. According to the method for manufacturing a silicon carbide semiconductor device according to Embodiment 3 described above (see FIG. 10), the MOS capacitor 40 shown in FIG. 17 (hereinafter referred to as Examples 8 and 9 and Comparative Examples 4 to 6 and 10) was fabricated. In Examples 8 and 9, the SiC substrate 41, the SiO2 film 42, the SiON film 43, and the Al electrode layer 44 correspond to the semiconductor substrate 9, the gate insulating film 32, the gate insulating film 33, and the gate electrode 7 (gate pad) of the lateral MOSFET 30 shown in FIG. 16, respectively. In Examples 8 and 9 and Comparative Examples 4 to 6 and 10, the conditions of the SiC substrate 41 and the Al electrode layers 44 and 45 are the same as those in Example 1.

[0114] Figure 22 is a chart showing the SiC substrate surface treatment conditions before forming the gate insulating films in Examples 8 and 9 and Comparative Examples 4 to 6 and 10, the formation conditions of the gate insulating films, the results of measuring the interface state density of the SiO2 / SiC interface, and the results of calculating the excess carbon amount and excess carbon distribution width of the SiO2 / SiC interface. The SiC substrate surface treatment conditions before forming the gate insulating film in Figure 22 include the treatment conditions of step S22 (H2 etching, H2 plasma treatment, none) and the treatment conditions of step S23 (forming a Si film by LPCVD method (shown as Si LPCVD), forming a Si film by PECVD method (shown as Si PECVD)). Since Comparative Examples 4 to 6 and 10 did not perform the treatment of step S23, the treatment conditions of step S23 are not described.

[0115] The formation conditions of the gate insulating films (SiO2 film 42 and SiON film 43) in Figure 22 are the conditions (HTO + acid nitridation) corresponding to the treatments of steps S24 and S25. "Thermal oxidation + acid nitridation" in Comparative Example 10 indicates that the gate insulating film was formed by thermal oxidation and acid nitridation (two heat treatments) instead of the treatments of steps S24 and S25. The interface state density of the SiO2 / SiC interface (the interface between the SiO2 film 42 and the SiC substrate 41) 46 in Figure 22 was calculated by the High-Low C-V method using the high-frequency C-V characteristics at 1 MHz and the low-frequency C-V characteristics at 100 Hz based on the measured values of Examples 8 and 9 and Comparative Examples 4 to 6 and 10. The calculation methods for the excess carbon amount and excess carbon distribution width of the SiO2 / SiC interface 46 in Figure 22 will be described later.

[0116] Example 8 corresponds to Embodiment 3. In Example 8, H2 etching (corresponding to the process of step S22) of the front surface (SiC surface) of the SiC substrate 41 was performed using H2 gas, and an Si film by LPCVD was formed as the Si-containing layer 31 on the front surface of the SiC substrate 41 (corresponding to the process of step S23). After forming a high-temperature oxide film (High Temperature Oxide layer: HTO) by LPCVD as the SiO2 film 42 on the Si-containing layer 31 (corresponding to the process of step S24), the Si film was oxynitrided to form an SiON film 43 (corresponding to the process of step S25). In Example 8, the H2 etching of the SiC surface, and the film formation of the Si film by LPCVD were performed without exposure to the atmosphere (that is, without exposure to an oxygen atmosphere).

[0117] For the H2 etching of the SiC surface in Example 8, the pressure of the H2 gas was 700 Pa, the heating temperature of the SiC substrate 41 was 1450 °C, and the treatment time was 5 minutes. The film formation conditions of the Si film by LPCVD in Example 8 were as follows: a mixed gas of 20 sccm of SiH4 gas and 80 sccm of Ar gas was used as the film formation gas, the pressure in the furnace was 200 Pa, the heating temperature of the SiC substrate 41 was 550 °C, and the thickness of the Si film was 3 nm. The film formation conditions of the HTO by LPCVD in Example 8 were as follows: a mixed gas of SiH4 gas and O2 gas was used as the film formation gas, the pressure in the furnace was 0.2 Pa, the heating temperature of the SiC substrate 41 was 600 °C, and the thickness of the HTO was 50 nm. The oxynitriding (thermal oxidation in an oxynitriding atmosphere) of the Si film in Example 8 was performed at a temperature of 1250 °C for 60 minutes at atmospheric pressure using a mixed gas of 90% N2 gas and 10% NO gas.

[0118] Example 9 corresponds to Embodiment 3. In Example 9, H2 gas is made into plasma and H2 plasma treatment (corresponding to the treatment in step S22) of the front surface (SiC surface) of the SiC substrate 41 is performed. A Si film by PECVD method is formed as the Si-containing layer 31 on the front surface of the SiC substrate 41 (corresponding to the treatment in step S23). After forming HTO by LPCVD method as the SiO2 film 42 on the Si-containing layer 31 (corresponding to the treatment in step S24), the Si film is oxynitrided to form a SiON film 43 (corresponding to the treatment in step S25). In Example 9, the H2 plasma treatment of the SiC surface, the film formation of the Si film by PECVD method, and the processes were continuously performed in the same chamber 20 without opening to the atmosphere (that is, without exposing to an oxygen atmosphere).

[0119] In the H2 plasma treatment of the SiC surface in Example 9, H2 gas was used as the source gas of the plasma 21 (see FIG. 3), the discharge pressure was 5 Pa, the discharge power was 0.3 W / cm 2 2, the heating temperature of the SiC substrate 41 was 80 °C, and the treatment time was 3 minutes. The film formation conditions of the Si film by PECVD method in Example 9 were as follows: a mixed gas of 50 sccm of SiH4 gas and 95 sccm of H2 gas was used as the source gas of the plasma, the discharge pressure was 20 Pa, the discharge power was 0.05 W / cm 2 2, the heating temperature of the SiC substrate 41 was 250 °C, the treatment time was 3 minutes, and the thickness of the Si film was 3 nm. The film formation conditions of HTO by LPCVD method and the oxynitriding conditions of the Si film in Example 9 were the same as those in Example 8.

[0120] Comparative Example 4 is a MOS capacitor fabricated by a general gate process (i.e., without performing etching of the front surface of the SiC substrate 41 and deposition of the Si film serving as the cap film before deposition of the SiO2 film 42). In Comparative Example 4, after forming HTO by the LPCVD method as the SiO2 film 42 on the front surface of the SiC substrate 41, the SiO2 / SiC interface (the interface between the SiO2 film 42 and the SiC substrate 41) 46 was oxynitrided to form the SiON film 43. The film deposition conditions of the HTO by the LPCVD method in Comparative Example 4 are the same as those in Example 8. The oxynitridation of the SiO2 / SiC interface 46 in Comparative Example 4 was performed at a temperature of 1250 °C for 60 minutes at atmospheric pressure using a mixed gas of 90% N2 gas and 10% NO gas.

[0121] Comparative Example 5 is a MOS capacitor fabricated by adding the H2 etching of the SiC surface in Example 8 before the formation of HTO which is the SiO2 film 42 in the fabrication method of Comparative Example 4. Comparative Example 6 is a MOS capacitor fabricated by adding the H2 plasma treatment of the SiC surface in Example 9 before the formation of HTO which is the SiO2 film 42 in the fabrication method of Comparative Example 4. Comparative Example 10 is a MOS capacitor in which the SiO2 film 42 was formed by thermal oxidation (the first heat treatment) at a temperature of 1200 °C for 150 minutes in an oxygen atmosphere at atmospheric pressure, and the SiON film 43 was formed by oxynitridation (the second heat treatment) at a temperature of 1300 °C for 120 minutes at atmospheric pressure using a mixed gas of 90% N2 gas and 10% NO gas. The two heat treatments in Comparative Example 10 correspond to the method for forming the gate insulating film (thermal oxide film) in Patent Document 4 mentioned above.

[0122] As shown in Fig. 22, in Examples 8 and 9, the interface state density (defect density) of the SiO2 / SiC interface 46 was lower than that of Comparative Examples 4 to 6 and 10, and was below the lower limit value (detection limit) of the detection accuracy by the High-Low C-V method. Therefore, for Example 1 and Comparative Example 10, the excess carbon amount and the excess carbon distribution width of the SiO2 / SiC interface 46 were calculated. As described above, in all of Examples 1 to 4, 8, and 9, the interface state density of the SiO2 / SiC interface 46 is lower than that of Comparative Examples 1, 2, 4 to 6, and 10 (see Figs. 19 and 22). For this reason, it is presumed that the relationship between the interface state density of the SiO2 / SiC interface 46 and the excess carbon of the SiO2 / SiC interface 46 in Example 1 is applicable to all of Examples 2 to 9 and Examples 10 and 11 described later.

[0123] First, the method for calculating the excess carbon amount and the excess carbon distribution width of the SiO2 / SiC interface 46 will be described. Fig. 25 is a characteristic diagram showing the distribution of the area intensity ratio of the spectrum of excess carbon to the SiC component surface for Example 1 and Comparative Example 10. Fig. 26A is an explanatory diagram schematically showing the measurement points of the EELS measurement in the vicinity of the SiO2 / SiC interface of the sample piece. Fig. 26B is an electron loss energy intensity distribution diagram showing the spectrum of the SiC component (solid line) and the spectrum of the excess carbon (broken line) at each measurement point in Fig. 26A, respectively. Fig. 26C is a distribution diagram of the area intensity ratio of the spectrum of the excess carbon in Fig. 26B to the SiC component. What is obtained by calculating the area intensity ratio of the excess carbon to the SiC component in Fig. 26C for Example 1 and Comparative Example 10 corresponds to Fig. 25.

[0124] The horizontal axis in FIGS. 25 and 26C is the depth from the SiO2 / SiC interface 46 toward the SiC substrate 41 side (SiC side) and the SiO2 film 42 side (SiO2 side), and the vertical axis is the ratio of the spectral integrated intensity of excess carbon to the SiC component area (arbitrary unit (a.u.: arbitrary unit)). The horizontal axis in FIG. 26B is the electron loss energy [eV], and the vertical axis is the intensity (a.u) representing the magnitude of the electron occupancy probability. The integrated intensity (hatched portion in FIG. 26C) of the ratio (relative intensity: hereinafter referred to as the integrated intensity of the ratio of the SiC component area) of the spectral integrated intensity (peak intensity of peak P2) of the excess carbon spectrum 72 at each measurement point 61-1 to 61-9 to the spectral integrated intensity (peak intensity of peak P1) of the SiC component spectrum 71 at the measurement point 61-1 of the test piece 60 is defined as the amount of excess carbon at the SiO2 / SiC interface 46.

[0125] The spectra 71 of the SiC component and the spectra 72 of the excess carbon are the loss energy intensity distributions separated (extracted) from the loss energy intensity distribution (not shown) of electrons obtained by EELS (Electron Energy Loss Spectroscopy) measurement in the vicinity of the SiO2 / SiC interface 46. The EELS measurement is a method of measuring the energy lost by electrons due to interaction with atoms when the electrons pass through the sample piece (here, the test piece on which the MOS capacitor of FIG. 17 is fabricated) 60. By the EELS measurement, the spectra of the signal intensity of the antibonding σ orbital (σ * ) and the spectra of the signal intensity of the antibonding π orbital (π * ) can be obtained at each measurement point 61-1 to 61-9 of the test piece 60.

[0126] The SiC at the SiO2 / SiC interface 46 is the SiC that constitutes the SiC substrate 41, and is a compound of σ bonds formed by sp 3 hybrid orbitals in which silicon (Si) atoms and carbon (C) atoms are bonded one-to-one (covalent bond with a relatively large electron occupancy probability (intensity)). Therefore, by the EELS measurement, as the spectrum 71 of the SiC component, the sp 3A spectrum of σ-bonded carbon (hereinafter referred to as σ-bonded C) by hybrid orbitals can be obtained. The peak intensity of peak P1 of the spectrum 71 of the SiC component (σ-bonded C) is maximum at the measurement point 61-1 inside the SiC substrate 41, and becomes smaller as the measurement points 61-2 to 61-9 are farther from the measurement point 61-1 toward the SiO2 film 42 side.

[0127] Excess carbon is a compound formed only by π-bonds (covalent bonds with relatively low electron probability of existence) by sp 2 hybrid orbitals or sp hybrid orbitals, and specifically, for example, graphite. The spectrum 72 of excess carbon (π-bonded C) appears in the loss energy range (for example, about 280 eV to 285 eV) less than the loss energy of electrons at the peak position (the position where the peak intensity is obtained) of peak P1 of the spectrum 71 of the SiC component (see Fig. 26B). The loss energy of electrons at the peak position of peak P2 of the spectrum 72 of excess carbon is, for example, about 284 eV. The peak intensity of peak P2 of the spectrum 72 of excess carbon is lower than the peak intensity of peak P1 of the spectrum 71 of the SiC component.

[0128] To calculate the amount of excess carbon at the SiO2 / SiC interface 46, first, as shown in Fig. 26A, first, a thin plate-shaped test piece 60 of a predetermined thickness obtained by cutting the SiC substrate 41 so that the plane orthogonal to the SiO2 / SiC interface 46 becomes the main plane is prepared in the portion including the SiC substrate 41 and the SiO2 film 42. An electron beam is irradiated onto each of the predetermined measurement points 61-1 to 61-9 in the transmission electron microscope from a direction orthogonal to the main plane of the test piece 60, and the energy lost by the interaction between the electrons and the atoms in the test piece 60 is measured. As a result, an electron loss energy intensity distribution is obtained at each of the measurement points 61-1 to 61-9 of the test piece 60. At this time, it is preferable that the measurement points 61-1 to 61-9 are located at positions that do not include the damage generated during the production of the test piece 60.

[0129] Each measurement point 61-1 to 61-9 of the test piece 60 is set from the SiC substrate 41 to the SiO2 film 42 on a straight line (hereinafter referred to as the measurement line) 60a that is parallel to the main surface of the test piece 60 and intersects the SiO2 / SiC interface 46. The number of measurement points of the test piece 60 (here, 9) can be appropriately set according to the conditions of the test piece 60. Here, the measurement points 61-1 to 61-9 are arranged in order from the deepest measurement point 61-1 inside the SiC substrate 41 toward the SiO2 film 42 side. The measurement line 60a of the test piece 60 may be 90 degrees with respect to the SiO2 / SiC interface 46, but preferably has a predetermined inclination angle θ other than 90 degrees. Thereby, carbon contamination due to EELS measurement at other measurement points 61-1 to 61-9 can be suppressed.

[0130] The inclination angle θ of the measurement line 60a of the test piece 60 can be variously changed, and for example, it may be about 30 degrees. The spot diameter (diameter) r of the electron beam irradiated to each measurement point 61-1 to 61-9 of the test piece 60 and the interval w3 between adjacent measurement points 61-1 to 61-9 can be variously changed, and for example, they may be about 0.2 nm and about 0.4 nm, respectively. However, it is preferable to make the spot diameter r smaller than the measurement interval w3 because the measurement locations do not overlap. At the distances D1 and D2 between the most distant measurement points 61-1 and 61-9 of the test piece 60, the distance along the measurement line 60a (hereinafter referred to as the first analysis distance) D1 and the distance in the direction orthogonal to the SiO2 / SiC interface 46 (hereinafter referred to as the second analysis distance) D2 can be appropriately set.

[0131] The spectra 71 and 72, separated from the loss energy intensity distributions measured at each measurement point 61-1 to 61-9 of these test pieces 60, are shown in Fig. 26B. The 1 to 9 at the end of the symbols of the spectra 71-1 to 71-9 and 72-1 to 72-9 respectively mean that they were detected at the measurement points 61-1 to 61-9. As shown in Fig. 26B, the peak intensity of the peak P1 of the spectrum 71 (71-1 to 71-9) of the SiC component is the largest at the measurement point 61-1 which is the farthest from the SiO2 / SiC interface 46 toward the SiC substrate 41 side, and becomes smaller as it goes toward the SiO2 film 42 side from the measurement point 61-1, and is the smallest at the measurement point 61-9 which is the farthest from the SiO2 / SiC interface 46 toward the SiO2 film 42 side.

[0132] The peak intensity of the peak P2 of the spectrum 72 of the excess carbon is the largest at the measurement point 61-5 on the SiO2 / SiC interface 46, and becomes smaller at the measurement points 61-4 to 61-1 and 61-6 to 61-9 which are separated from the SiO2 / SiC interface 46 toward the SiC substrate 41 side and the SiO2 film 42 side respectively. Therefore, as shown in Fig. 26C, the distribution of the SiC component area intensity ratios (= area intensity of the spectrum 72 of the excess carbon / area intensity of the spectrum 71 of the SiC component) 62-1 to 62-9 of the spectra 72-1 to 72-9 of the excess carbon at each measurement point 61-1 to 61-9 forms a mountain shape that is the highest on the SiO2 / SiC interface 46 (SiC component area intensity ratio 62-5) and becomes lower as it moves away from the SiO2 / SiC interface 64.

[0133] The deep part of the test piece 60 going further into the SiC substrate 41 from the measurement point 61-1 (the left part from the SiC component area intensity ratio 62-1 in Fig. 26C) and the deep part going further into the SiO2 film 42 from the measurement point 61-9 (the right part from the SiC component area intensity ratio 62-9 in Fig. 26C) become the detection limit of the excess carbon in the EELS measurement (that is, the SiC component area intensity ratio = 0). By integrating the SiC component area intensity ratios 62-1 to 62-9 of the spectra 72-1 to 72-9 of the excess carbon at all the measurement points 61-1 to 61-9 of the test piece 60, the integrated intensity of the SiC component area intensity ratio of the spectrum 72 of the excess carbon (the hatched part in Fig. 26C) is calculated.

[0134] The integrated intensity of the ratio of the spectrum 72 of this excess carbon to the SiC component area intensity is the amount of excess carbon at the SiO2 / SiC interface 46. The spectrum 71 of the SiC component at the measurement point 61-1 farthest from the SiO2 / SiC interface 46 can be regarded as the electron loss energy intensity distribution of the SiC component of the SiC bulk (SiC substrate 41). Therefore, the area intensity of the spectrum 71 of the SiC component at the measurement point 61-1 was used as the carbon amount (reference value) of the SiC substrate 41. The integrated intensity of the ratio (ratio to the SiC component area intensity) of the area intensity of the spectrum 72 of the excess carbon at each measurement point 61-1 to 61-9 to the area intensity of the spectrum 71 of the SiC component at the measurement point 61-1 (carbon amount of the SiC substrate 41) is the amount of excess carbon at the SiO2 / SiC interface 46.

[0135] Regarding Example 1 and Comparative Example 10, the results of calculating the amount of excess carbon at the SiO2 / SiC interface 46 as described above are shown in FIG. 25. As shown in FIG. 25, in Example 1, compared with Comparative Example 10, the height in the vertical axis direction (amount of excess carbon at each measurement point) of the distribution 51 of the ratio of the spectrum 72 of the excess carbon to the SiC component area intensity became smaller overall. In addition to this, in Example 1, compared with Comparative Example 10, the maximum width in the horizontal axis direction (excess carbon distribution width w1) of the distribution 51 of the ratio of the spectrum 72 of the excess carbon to the SiC component area intensity became narrower. As a result, it was confirmed that in Example 1, compared with Comparative Example 10, the amount of excess carbon at the SiO2 / SiC interface 46 (integrated intensity of the ratio of the spectrum 72 of the excess carbon to the SiC component area intensity (hatched portion)) was significantly reduced.

[0136] Specifically, as shown in FIG. 22, the surplus carbon distribution width w2 of Comparative Example 10 (the maximum width in the horizontal axis direction of the ratio distribution 52 of the spectrum 72 of surplus carbon to the SiC component area intensity with respect to the SiC component area intensity) was within ±4.25 nm from the SiO2 / SiC interface 46 (assuming the reference position = 0 nm) to the SiC substrate 41 side and the SiO2 film 42 side (defined as the plus side and the minus side from the reference position, respectively). The ratio of the amount of surplus carbon at the SiO2 / SiC interface 46 of Comparative Example 10 to the amount of carbon in the SiC substrate 41 was at most 0.1 (at measurement point 61-5). On the other hand, the surplus carbon distribution width w1 of Example 1 was within ±2 nm from the SiO2 / SiC interface 46 to the SiC substrate 41 side and the SiO2 film 42 side. The ratio of the amount of surplus carbon at the SiO2 / SiC interface 46 of Example 1 to the amount of carbon in the SiC substrate 41 was at most 0.025, and it was confirmed that the amount of surplus carbon could be made closer to zero than in Comparative Example 10.

[0137] In Example 1, compared with Comparative Example 10, the size (height in the vertical axis direction, width in the horizontal axis direction) of the ratio distribution 51 of the spectrum 72 of surplus carbon to the SiC component area intensity was overall smaller, so that the amount of surplus carbon at the SiO2 / SiC interface 46 was reduced. As a result, the amount of surplus carbon diffused from the SiO2 / SiC interface 46 was also reduced, and it is presumed that the surplus carbon distribution width (diffusion width of surplus carbon in the direction orthogonal to the SiO2 / SiC interface 46) w1 of the SiO2 / SiC interface 46 in Example 1 became about half of the surplus carbon distribution width w2 of the SiO2 / SiC interface 46 in Comparative Example 10. Thus, in Example 1, compared with Comparative Example 10, the integrated intensity of the ratio of the spectrum 72 of surplus carbon to the SiC component area intensity became smaller in both the vertical axis direction and the horizontal axis direction.

[0138] Therefore, by applying the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 as in Example 1, it was confirmed that the interface state density, the excess carbon amount, and the excess carbon distribution width of the SiO2 / SiC interface 46 were reduced compared to Comparative Example 10 (Figs. 19, 22, 25). For Examples 2 and 3 that applied the manufacturing method of the silicon carbide semiconductor device according to Embodiment 1 as in Example 1, and for Examples 4, 8, and 9 that applied the manufacturing method of the silicon carbide semiconductor device according to Embodiments 2 and 3, since the interface state density of the SiO2 / SiC interface 46 was reduced compared to Comparative Example 10 (see Figs. 19 and 22), it is presumed that the excess carbon amount and the excess carbon distribution width of the SiO2 / SiC interface 46 were reduced compared to Comparative Example 10 in accordance with the reduction in the interface state density of the SiO2 / SiC interface 46.

[0139] Fig. 24 shows the results of calculating the field-effect mobility and the gate threshold voltage Vth of the lateral MOSFET 30 (see Fig. 16: hereinafter referred to as Examples 10 and 11 and Comparative Examples 7 to 9) simulated based on the interface state density of the SiO2 / SiC interface 46 obtained in Fig. 22. Fig. 23 is a chart showing the SiC substrate surface treatment conditions before forming the gate insulating film for Examples 10 and 11 and Comparative Examples 7 to 9. Fig. 24 is a chart showing the results of calculating the field-effect mobility and the gate threshold voltage for Examples 10 and 11 and Comparative Examples 7 to 9. The SiC substrate surface treatment conditions in Figs. 23 and 24 are the same as the SiC substrate surface treatment conditions in Fig. 22.

[0140] Examples 10 and 11 and Comparative Examples 7 to 9 each include an MO gate formed under the same conditions as Examples 8 and 9 and Comparative Examples 4 to 6 described above. In Examples 10 and 11 and Comparative Examples 7 to 9, the semiconductor substrate 9 (4H-SiC substrate as the starting substrate, n - -type drift region 1, n - -type epitaxial layer 11, p-type base region 2, p-type epitaxial layer 12), n + -type source region 3, n + -type drain region 4, gate electrode 7, ohmic electrode, barrier metal, source electrode 13, drain electrode 14, gate metal wiring layer 15, and gate pad are configured in the same manner as in Example 5.

[0141] As shown in FIG. 24, in any of Examples 10 and 11, the field-effect mobility was significantly increased compared to Comparative Examples 7 to 9. Also, in any of Examples 10 and 11, the gate threshold voltage Vth was reduced compared to Comparative Examples 7 to 9. The reduction in the interface state density of the SiO2 / SiC interface 46 (see FIG. 22) greatly contributed to the improvement of the field-effect mobility, and it was confirmed that the gate threshold voltage Vth could be reduced by increasing the field-effect mobility.

[0142] As described above, the present disclosure is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present disclosure. In each embodiment, the first conductivity type is an n-type and the second conductivity type is a p-type, but the present disclosure also holds true when the first conductivity type is a p-type and the second conductivity type is an n-type.

Industrial Applicability

[0143] As described above, the method for manufacturing a silicon carbide semiconductor device and the silicon carbide semiconductor device according to the present disclosure are useful for power semiconductor devices used in power conversion devices, power supply devices such as various industrial machines, and the like.

Explanation of Reference Numerals

[0144] 1 n - -type drift region 2 p-type base region 3 n + -type source region 4 n + -type drain region 5, 6, 32, 33 Gate insulating film 7 Gate electrode 8 Interlayer insulating film 8a to 8e Contact hole 9 Semiconductor substrate 11, 12 Epitaxial layer 13 to 15 Surface electrode 16, 36 SiO2 / SiC interface 20 Chamber 21 Plasma 31 Si-containing layer

Claims

1. A method for manufacturing a silicon carbide semiconductor device having an insulating gate on a semiconductor substrate made of silicon carbide, comprising: a first step of etching the surface of the semiconductor substrate with plasma generated using a source gas not containing oxygen atoms, without heating the semiconductor substrate or while heating the semiconductor substrate at a temperature of 400°C or lower; a second step of depositing a gate insulating film constituting the insulating gate on the surface of the semiconductor substrate without exposing the semiconductor substrate to an oxygen atmosphere after the first step; a third step of nitriding the interface between the gate insulating film and the semiconductor substrate; a fourth step of forming a gate electrode constituting the insulating gate opposite to the surface of the semiconductor substrate with the gate insulating film interposed therebetween; A method for manufacturing a silicon carbide semiconductor device, characterized by including the above steps.

2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the first step, the surface of the semiconductor substrate is exposed to the plasma to dissolve the surface layer of the semiconductor substrate.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 2, wherein in the first step, the source gas containing hydrogen gas is used.

4. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the first step, radicals in the plasma are collided with the surface of the semiconductor substrate to scrape off the surface layer of the semiconductor substrate.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 1 or 4, wherein in the first step, the source gas containing a noble gas or a halogen-based gas is used.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further including a fifth step of heating the semiconductor substrate at a temperature of 800°C or higher and 1000°C or lower in an atmosphere not containing oxygen after the first step and before the second step.

7. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first step and the second step are continuously performed in the same chamber.

8. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein in the second step, the gate insulating film is deposited by a sputtering method.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein in the second step, the gate insulating film is deposited by a plasma-assisted chemical vapor deposition method.

10. The second step is After the first step, without exposing the semiconductor substrate to an oxygen atmosphere, either without heating the semiconductor substrate or while heating the semiconductor substrate at a temperature of 600°C or lower, a first deposition step of depositing a silicon-containing layer that does not contain oxygen atoms on the surface of the semiconductor substrate; A second deposition step of depositing the gate insulating film on the silicon-containing layer, the method for manufacturing a silicon carbide semiconductor device according to claim 1, characterized by including the above.

11. The method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized in that the first step and the first deposition step are continuously performed in the same chamber.

12. In the first deposition step, the silicon-containing layer is deposited by a reduced-pressure chemical vapor deposition method using a mixed gas of a gas containing silicon and hydrogen gas, the method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized by this.

13. In the first deposition step, the silicon-containing layer is deposited by a plasma-assisted chemical vapor deposition method using a mixed gas of a gas containing silicon and hydrogen gas, the method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized by this.

14. In the first deposition step, the silicon-containing layer is deposited by a sputtering method using a silicon target, the method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized by this.

15. In the first deposition step, the silicon-containing layer is deposited with a thickness of 1 nm or more and 4 nm or less, the method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized by this.

16. In the third step, the interface between the gate insulating film and the semiconductor substrate is oxynitrided by heat treatment in an atmosphere containing nitrogen and oxygen, the method for manufacturing a silicon carbide semiconductor device according to claim 10, characterized by this.

17. A gate insulating film provided on the surface of a semiconductor substrate made of silicon carbide, A gate electrode provided on the surface of the semiconductor substrate via the gate insulating film, comprising an insulated gate composed of the above, The excess carbon present at the interface between the semiconductor substrate and the gate insulating film, Is distributed within a range of 2 nm or less from the interface between the semiconductor substrate and the gate insulating film to both the semiconductor substrate side and the gate insulating film side, and A silicon carbide semiconductor device characterized in that the ratio of the amount to the carbon amount of the semiconductor substrate is 0.025 or less.

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