Semiconductor device

Abstract

To provide a semiconductor device with a novel structure, having good characteristics.SOLUTION: A semiconductor device includes: an oxide semiconductor layer; a source electrode and a drain electrode electrically connected with the oxide semiconductor layer; a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode; and a gate electrode on the gate insulating layer. The source electrode and the drain electrode includes lateral faces having oxidation regions which are oxidized. In addition, it is preferred that the oxidation regions of the source electrode and the drain electrode are formed by plasma processing using high-frequency power of 300 MHz or more and 300 GHz or less and mixed gas of oxygen and argon.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technical field of the invention relates to a semiconductor device and a method for manufacturing the same. Here, the semiconductor device refers to elements and devices in general that function by utilizing semiconductor characteristics.

Background Art

[0002] Metal oxides exist in various forms and are used in a variety of applications. Indium oxide is a well-known material and is used as a material for transparent electrodes required for liquid crystal display devices and the like.

[0003] Some metal oxides exhibit semiconductor characteristics. Examples of metal oxides that exhibit semiconductor characteristics include tungsten oxide, tin oxide, indium oxide, zinc oxide, etc. Thin-film transistors using such metal oxides in the channel formation region are already known (see, for example, Patent Documents 1 to 4, Non-Patent Document 1, etc.).

[0004] By the way, multi-component oxides are also known for metal oxides. For example, InGaO3(ZnO) (m: natural number) having a homologous phase is known as a multi-component oxide semiconductor containing In, Ga, and Zn (see, for example, Non-Patent Documents 2 to 4, etc.). m

[0005] And it has been confirmed that oxide semiconductors composed of In-Ga-Zn-based oxides as described above are also applicable to the channel formation region of thin-film transistors (see, for example, Patent Document 5, Non-Patent Documents 5 and 6, etc.).

Prior Art Documents

Patent Documents

[0006] ​​​​​​​​​ [Patent Document 1] Japanese Patent Application Laid-Open No. 60-198861 [Patent Document 2] Japanese Patent Application Laid-Open No. 8-264794 [Patent Document 3] Japanese Patent Application Laid-Open No. 11-505377 [Patent Document 4] Japanese Patent Application Laid-Open No. 2000-150900 [Patent Document 5] Japanese Patent Application Laid-Open No. 2004-103957 [Non-Patent Document]

[0007] [Non-Patent Document 1] M. W. Prins, K. O. Grosse-Holz, G. Muller, J. F. M. Cillessen, J. B. Giesbers, R. P. Weening, and R. M. Wolf, "A ferroelectric transparent thin-film transistor", Appl. Phys. Lett., 17 June 1996, Vol.68 p.3650-3652 [Non-Patent Document 2] M. Nakamura, N. Kimizuka, and T. Mohri, "The Phase Relations in the In2O3-Ga2ZnO4-ZnO System at 1350℃", J. Solid State Chem., 1991, Vol.93, p.298-315 [Non-Patent Document 3] N. Kimizuka, M. Isobe, and M. Nakamura, "Syntheses and Single-Crystal Data of Homologous Compounds, In2O3(ZnO)m (m = 3, 4, and 5), InGaO3(ZnO)3, and Ga2O3(ZnO)m (m = 7, 8, 9, and 16) in the In2O3-ZnGa2O4-ZnO System", J. Solid State Chem., 1995, Vol.116, p.170-178 [Non-Patent Document 4] Shinsuke Nakamura, Noboru Kimizuka, Hisahiko Mouri, Mitsumasa Isobe, "Synthesis and Crystal Structure of Homologous Phases, InFeO3(ZnO)m (m: natural number) and Its Isomorphic Compounds", Solid State Physics, 1993, Vol.28, No.5, p.317-327 [Non-Patent Document 5] K. Nomura, H. Ohta, K. Ueda, T. Kamiya, M. Hirano, and H. Hosono, "Thin-film transistor fabricated in single-crystalline transparent oxide semiconductor", SCIENCE, 2003, Vol.300, p.1269-1272 [Non-Patent Document 6] K. Nomura, H. Ohta, A. Takagi, T. Kamiya, M. Hirano, and H. Hosono, "Room-temperature fabrication of transparent flexible thin-film transistors using amorphous oxide semiconductors", NATURE, 2004, Vol.432 p.488-492 [Summary of the Invention] [Problems to be Solved by the Invention]

[0008] By the way, the transistors using the current oxide semiconductors have sufficient characteristics for practical use It is difficult to say that it is superior in various characteristics of transistors such as S value, on-off ratio, and reliability. Better ones are required.

[0009] Therefore, one aspect of the disclosed invention aims to provide a semiconductor device with a new structure having good characteristics. This is one of the objectives.

[0010] Or, one of the objectives is to provide a method for manufacturing a semiconductor device with a new structure.

Means for Solving the Problem

[0011] A transistor using an oxide semiconductor, which is one aspect of the invention, exhibits excellent characteristics in terms of S value, on-off ratio, reliability, etc. due to the oxidation of the side surfaces of the source electrode or the drain electrode. Specifically, for example, it can be configured as follows. Specifically, for example, it can be configured as follows.

[0012] One aspect of the present invention has an oxide semiconductor layer, a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer, a gate insulating layer that covers the oxide semiconductor layer, the source electrode and the drain electrode, and a gate electrode on the gate insulating layer. The source electrode and the drain electrode have an oxidized region on their side surfaces. The oxidized region is formed together with the supply of oxygen to the oxide semiconductor layer. And a gate electrode on the gate insulating layer. The source electrode and the drain electrode have an oxidized region on their side surfaces. The oxidized region is formed together with the supply of oxygen to the oxide semiconductor layer. In the above, the oxidized regions of the source electrode and the drain electrode are preferably formed by plasma treatment using high-frequency power of 300 MHz or more and 300 GHz or less, and a mixed gas of oxygen and argon. It is also desirable to have a protective insulating layer on the source electrode and the drain electrode, the planar shape of which is substantially the same as that of the source electrode and the drain electrode. The oxidized region is formed together with the supply of oxygen to the oxide semiconductor layer.

[0013] In the above, the oxidized regions of the source electrode and the drain electrode are preferably formed by plasma treatment using high-frequency power of 300 MHz or more and 300 GHz or less, and a mixed gas of oxygen and argon. It is also desirable to have a protective insulating layer on the source electrode and the drain electrode, the planar shape of which is substantially the same as that of the source electrode and the drain electrode. It is also desirable to have a protective insulating layer on the source electrode and the drain electrode, the planar shape of which is substantially the same as that of the source electrode and the drain electrode. It is also desirable to have a protective insulating layer on the source electrode and the drain electrode, the planar shape of which is substantially the same as that of the source electrode and the drain electrode. Note that the expression "substantially the same" is used in the sense that it does not require strict identity, and includes a range where it can be regarded as the same. For example, differences in the case of being formed by one etching process are allowed.

[0014] Also, in the above, the hydrogen concentration of the oxide semiconductor layer is preferably 5×10 19 / cm 3 or less. Also, the off-current is preferably 1×10 A or less. -13

[0015] One aspect of the present invention is a method of manufacturing a semiconductor device, including forming an oxide semiconductor layer on a substrate, forming a source electrode and a drain electrode that are electrically connected to the oxide semiconductor layer, oxidizing the side surfaces of the source electrode and the drain electrode, and then forming a gate insulating layer that covers the oxide semiconductor layer, the source electrode, and the drain electrode, and forming a gate electrode on the gate insulating layer. Note that when oxidizing the side surfaces of the source electrode and the drain electrode, oxygen is supplied to the oxide semiconductor layer.

[0016] In the above, the oxidation of the side surfaces of the source electrode and the drain electrode is preferably performed by plasma processing using high-frequency power of 300 MHz or more and 300 GHz or less, and a mixed gas of oxygen and argon.

[0017] Also, in the above, it is desirable to form a protective insulating layer having a planar shape substantially the same as that of the source electrode and the drain electrode on the source electrode and the drain electrode.

[0018] Also, in the above, the hydrogen concentration of the oxide semiconductor layer is made 5×10 19 / cm 3 or less. Thus, it is desirable that the off-current be 1×10 -13 A or less.

[0019] In addition, in this specification and the like, terms such as "above" and "below" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "the first gate electrode on the gate insulating layer", those including other components between the gate insulating layer and the gate electrode are not excluded. Also, the terms "above" and "below" are merely expressions used for convenience of explanation, and except when specifically mentioned, those with their upper and lower reversed are also included.

[0020] In addition, in this specification and the like, the terms "electrode" and "wiring" do not functionally define these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wirings" are integrally formed.

[0021] Also, the functions of "source" and "drain" may be interchanged when different polarities of transistors are adopted or when the direction of current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0022] Note that in this specification and the like, "electrically connected" includes cases where it is connected through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0023] ​For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors , resistance elements, inductors, capacitors, and other elements having various functions .

Advantages of the Invention

[0024] In one aspect of the disclosed invention, by supplying oxygen to the oxide semiconductor layer, the characteristics of transistors using the oxide semiconductor are further improved. Here, the oxygen supply process appears in such a form that the side surfaces of the source electrode or the drain electrode are oxidized in a transistor using an oxide semiconductor . Further, due to the oxidation of the side surfaces of the source electrode or the drain electrode, it is possible to prevent a short circuit between the gate electrode and the source electrode or the drain electrode that may occur due to thinning of the gate insulating layer or coverage failure .

[0025] . In this way, by supplying oxygen to the oxide semiconductor layer, a semiconductor device having a new structure with excellent characteristics can be realized .

[0026] .

Brief Description of the Drawings

[0027]

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Embodiments for Carrying Out the Invention

[0028] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not to be construed as limited to the description of the embodiments shown below.

[0029] In addition, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like. Also, the positions, sizes, ranges, etc. of the respective components shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like.

[0030] Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0031] (Embodiment 1) In this embodiment, the configuration and manufacturing method of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 3.

[0032] <Configuration of Semiconductor Device> FIG. 1 is a cross-sectional view showing a transistor 150 which is an example of the configuration of a semiconductor device. Note that the transistor 150 will be described as an n-type transistor, but a p-type transistor may be employed.

[0033] The transistor 150 has an oxide semiconductor layer 104a provided on a substrate 100 with an insulating layer 102 interposed therebetween, a source electrode or drain electrode 106a electrically connected to the oxide semiconductor layer 104a, a source electrode or drain electrode 106b, a gate insulating layer 112 covering the source electrode or drain electrode 106a and the source electrode or drain electrode 106b, and a gate electrode 114 on the gate insulating layer 112 (see FIG. 1).

[0034] Also, an interlayer insulating layer 116 and an interlayer insulating layer 118 are provided on the transistor 150.

[0035] ​Here, the source electrode or drain electrode 106a and the source electrode or drain electrode 106 b each have an oxidized region 110 on their side surfaces. By having the oxidized region 110 it is possible to prevent a short circuit between the gate electrode and the source electrode or drain electrode, which may occur due to thinning of the gate insulating layer or coverage defects.

[0036] Also, the oxide semiconductor layer 104a is preferably one in which impurities such as hydrogen are sufficiently removed and oxygen is supplied to achieve high purity. Specifically, the hydrogen concentration in the oxide semiconductor layer 1 04a is 5×10 / cm 19 or less, desirably 5×10 3 / cm 18 or less, 3 and more desirably 5×10 / cm 17 or less. Note that in the oxide semiconductor layer 104a in which the hydrogen concentration is sufficiently reduced and oxygen is supplied to achieve high purity, the carrier concentration is sufficiently small compared to that in a general silicon wafer (a silicon wafer doped with trace amounts of impurity elements such as phosphorus and boron) (on the order of 1×10 / cm ). That is, the oxide semiconductor layer 104a has a carrier concentration value (for example, less than 1×10 14 / cm 3 , desirably, 1×10 / cm 12 or less, more desirably 1×10 3 / cm 11 or less). 3 By using an i-type or substantially i-type oxide semiconductor in this way, a transistor 150 with extremely excellent off-current characteristics can be obtained. For example, when the drain voltage V d is +1V or +10V and the gate voltage Vg is in the range from -5V to -20V , the off-current is 1×10 / A or less, -13It is A or less. Note that the hydrogen concentration in the above-described oxide semiconductor layer 104a is measured by secondary ion mass spectrometry (SIMS).

[0037] Note that the oxide semiconductor constituting the oxide semiconductor layer is not particularly limited as long as it has a non-single crystal structure. For example, an amorphous structure, a microcrystalline (such as microcrystal, nanocrystal) structure, a polycrystalline structure, a structure in which microcrystals or polycrystals are included in an amorphous material, a structure in which microcrystals or polycrystals are formed on the surface of an amorphous structure, etc., can be applied.

[0038] <Method for manufacturing a semiconductor device> Next, a method for manufacturing the transistor 150 will be described with reference to FIGS. 2 and 3.

[0039] First, an insulating layer 102 is formed on the substrate 100. Then, an oxide semiconductor layer 104 is formed on the insulating layer 102 (see FIG. 2(A)).

[0040] The substrate 100 may be a substrate having an insulating surface. For example, a glass substrate can be used. The glass substrate is preferably a non-alkali glass substrate. Examples of the non-alkali glass substrate include glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass. In addition, as the substrate 100, an insulating substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate, a semiconductor substrate made of a semiconductor material such as silicon whose surface is coated with an insulating material, or a conductive substrate made of a conductor such as metal or stainless steel whose surface is coated with an insulating material can be used. Also, a plastic substrate can be used as long as it can withstand the heat treatment in the manufacturing process. ​

[0041] The insulating layer 102 functions as a base and can be formed using a CVD method, a sputtering method, or the like. Also, the insulating layer 102 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, etc. Note that the insulating layer 102 may have a single-layer structure or a laminated structure. The thickness of the insulating layer 102 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less. Here, since the insulating layer 102 is not an essential component, it is also possible to adopt a configuration in which the insulating layer 102 is not provided. When hydrogen, water, or the like is contained in the insulating layer 102, intrusion of hydrogen into the oxide semiconductor layer, extraction of oxygen in the oxide semiconductor layer by water, etc. may occur, and the characteristics of the transistor may deteriorate. Therefore, it is desirable to form the insulating layer 102 so as to contain as little hydrogen and water as possible. For example, when using a sputtering method or the like, it is desirable to form the insulating layer 102 in a state where residual moisture in the processing chamber has been removed. Also, in order to remove residual moisture in the processing chamber, it is desirable to use an adsorption-type vacuum pump such as a cryopump, an ion pump, or a titanium sublimation pump. It is also possible to use a turbo pump with a cold trap added. Since the processing chamber evacuated using a cryopump or the like has sufficiently removed hydrogen, water, etc., the concentration of impurities contained in the insulating layer 102 can be reduced. Also, when forming the insulating layer 102, impurities such as hydrogen and water should be at a concentration of about ppm (desirable

[0042]

[0043]

[0044] ​ Alternatively, it is desirable to use a high-purity gas reduced to a concentration of about ppb.

[0045] As the oxide semiconductor layer 104, In-Sn-Ga-Zn-O which is a quaternary metal oxide, or In-Ga-Zn-O, In-Sn-Zn-O, In-Al- Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O which are ternary metal oxides, or binary metal oxides such as In-Zn-O, Sn-Zn-O, Al-Zn-O, Zn-Mg- O, Sn-Mg-O, In-Mg-O, or oxides using In-O, Sn-O, Zn-O, etc. can be applied as the oxide semiconductor layer. Further, SiO2 may be included in the above oxide semiconductor layer.

[0046] Further, as the oxide semiconductor layer 104, a thin film containing a material represented by InMO3(ZnO) m (m>0) can be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, G a and Mn, Ga and Co, etc. can be applied. Among the materials represented by InMO3(ZnO )(m>0), those containing Ga as M are called In-Ga-Zn -O oxide semiconductors, and their thin films may be called In-Ga-Zn-O oxide semiconductor films (In-Ga -Zn-O amorphous films), etc. m (m>0) -O oxide semiconductor film (In-Ga -Zn-O amorphous film), etc.

[0047] In this embodiment, an amorphous oxide semiconductor layer is formed by sputtering using a target for forming an In-Ga-Zn-O-based oxide semiconductor as the oxide semiconductor layer 104. By adding silicon to the amorphous oxide semiconductor layer, its crystallization can be suppressed. ​ Therefore, for example, a target containing 2% by weight or more and 10% by weight or less of SiO2 may be used to form the oxide semiconductor layer 104.

[0048] As a target for forming the oxide semiconductor layer 104 by sputtering, for example , a target of a metal oxide mainly composed of zinc oxide can be used. Also, an oxide semiconductor film-forming target containing In, Ga, and Zn (as a composition ratio, In2O3:G a2O3:ZnO = 1:1:1 [mol ratio], or In:Ga:Zn = 1:1:0. 5 [atom ratio]) etc. can also be used. Also, as an oxide semiconductor film-forming target containing In, Ga, and Zn, a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom ratio], or a target having a composition ratio of In:Ga:Zn = 1:1:2 [atom ratio] etc. may be used . The filling rate of the oxide semiconductor film-forming target is 90% or more and 100% or less, preferably 95% or more (for example, 99.9%). By using an oxide semiconductor film-forming target with a high filling rate, a dense oxide semiconductor layer 104 is formed.

[0049] The film formation atmosphere of the oxide semiconductor layer 104 is preferably a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a rare gas (typically argon) and oxygen . Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of about ppm ( preferably about ppb concentration). .

[0050] When forming the oxide semiconductor layer 104, the substrate is held in a processing chamber maintained in a reduced pressure state, Heat the substrate temperature to 100 °C or higher and 600 °C or lower, preferably 200 °C or higher and 400 °C or lower. Then introduce a sputtering gas from which hydrogen and water have been removed while removing residual moisture in the processing chamber and form an oxide semiconductor layer 104 using a metal oxide as a target. By forming the oxide semiconductor layer 104 while heating the substrate, the impurity concentration contained in the oxide semiconductor layer 104 can be reduced. Also, damage due to sputtering is reduced. To remove residual moisture in the processing chamber, it is preferable to use an adsorption type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Alternatively, a turbo pump with a cold trap added may be used. The processing chamber evacuated using a cryopump has had hydrogen, water, etc. removed, and the impurity concentration in the oxide semiconductor layer 104 can be reduced. As the film formation conditions for the oxide semiconductor layer 104, for example, conditions such as a distance between the substrate and the target of 100 mm, a pressure of 0.6 Pa, a DC power of 0.5 kW, and an atmosphere of oxygen (oxygen flow rate ratio 100%) atmosphere can be applied. Note that when using a pulsed DC power

[0051] source, it is preferable because powdery substances (also called particles, dust) generated during film formation can be reduced and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer 104 is 2 nm or more and 200 nm or less, preferably 5 nm or more and 30 nm or less. However, since the appropriate thickness varies depending on the oxide semiconductor material applied, the application, etc., the thickness may be selected according to the material used, the application, etc.

[0052] Note that before forming the oxide semiconductor layer 104 by sputtering, introduce argon gas Performing reverse sputtering to generate plasma and removing deposits on the surface of the insulating layer 102 is preferred. Here, reverse sputtering means that in normal sputtering, ions are collided with the sputtering target, whereas, conversely, it refers to a method of modifying the surface by colliding ions with the processing surface. As a method of colliding ions with the processing surface, there is a method of applying a high-frequency voltage to the processing surface side in an argon atmosphere to generate plasma near the substrate. Note that an atmosphere of nitrogen, helium, oxygen, etc. may be applied instead of the argon atmosphere.

[0053] Next, the oxide semiconductor layer 104 is processed by a method such as etching using a mask to form island-shaped oxide semiconductor layers 104a (see FIG. 2(B)).

[0054] For etching the oxide semiconductor layer 104, either dry etching or wet etching may be used. Of course, both can also be used in combination. The etching conditions (etching gas, etching solution, etching time, temperature, etc.) are appropriately set according to the material so that the oxide semiconductor layer 104 can be etched into a desired shape.

[0055] As dry etching, a parallel plate type RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) etching method, etc. can be used. Also in this case, the etching conditions (the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the temperature of the electrode on the substrate side, etc.) need to be appropriately set.

[0056] Etching gases that can be used for dry etching include, for example, gases containing chlorine ( chlorine-based gases such as chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4) , carbon tetrachloride (CCl4), etc. Also, gases containing fluorine (fluorine-based gases such as carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), gases obtained by adding noble gases such as helium ( He) or argon (Ar) to these gases, etc. may also be used.

[0057] Examples of etching liquids that can be used for wet etching include a mixed solution of phosphoric acid, acetic acid, and nitric acid, an ammonia-hydrogen peroxide mixture (31 wt% hydrogen peroxide solution: 28 wt% ammonia water: water = 5:2:2), etc. Also, an etching liquid such as ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used.

[0058] Thereafter, it is desirable to perform a first heat treatment on the oxide semiconductor layer 104a. By this first heat treatment, water (including hydroxyl groups) and hydrogen in the oxide semiconductor layer 104a can be removed. The temperature of the first heat treatment is 300°C or higher and 750°C or lower, preferably 400 °C or higher and 700°C or lower. For example, the substrate 100 is introduced into an electric furnace using a resistance heating element or the like, and the oxide semiconductor layer 104a is heat-treated at 450°C for 1 hour in a nitrogen atmosphere. During this time, the oxide semiconductor layer 104a is not exposed to the atmosphere, and it is ensured that water and hydrogen do not mix in.

[0059] The heat treatment apparatus is not limited to an electric furnace, and heat conduction from a medium such as a heated gas, or heat radiation It may also be a device for heating an object to be processed. For example, GRTA (Gas Rap id Thermal Anneal) device, LRTA (Lamp Rapid The rmal Anneal) device and other RTA (Rapid Thermal Anneal ) devices can be used. The LRTA device is a device that heats an object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps , xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps . The GRTA device is a device that performs heat treatment using high-temperature gas. As the gas, noble gases such as argon , or inert gases such as nitrogen that do not react with the object to be processed by heat treatment are used.

[0060] For example, as the first heat treatment, the substrate is put into an inert gas atmosphere heated to a high temperature of 650 °C or more and 700 °C or less, heated for several minutes, and then the substrate is taken out from the inert gas atmosphere. GRT A treatment may be performed. Using the GRTA treatment enables high-temperature heat treatment in a short time. Also , since it is a short-time heat treatment, it can be applied even under temperature conditions exceeding the heat-resistant temperature of the substrate . For example, when using a glass substrate, shrinkage of the substrate becomes a problem at temperatures exceeding the heat-resistant temperature (strain point), but this is not a problem in the case of short-time heat treatment. During the treatment , the inert gas may be switched to a gas containing oxygen. This is because by performing the first heat treatment in an atmosphere containing oxygen, defects caused by oxygen deficiency can be reduced . .

[0061] Note that as the inert gas atmosphere, nitrogen or noble gases (helium, neon, argon, etc An atmosphere containing as the main component, preferably an atmosphere containing no water, hydrogen, etc. For example, the purity of nitrogen, helium, neon, argon and other rare gases introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0062] Depending on the conditions of the first heat treatment or the material constituting the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become microcrystalline or polycrystalline. For example, it may become an oxide semiconductor layer of microcrystals with a crystallization rate of 90% or more, or 80% or more. Also, depending on the conditions of the first heat treatment or the material constituting the oxide semiconductor layer, it may become an amorphous oxide semiconductor layer containing no crystal components.

[0063] In addition, there may be an oxide semiconductor layer in which microcrystals (particle size 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) are mixed in an amorphous oxide semiconductor (for example, the surface of the oxide semiconductor layer). In this way, by mixing and arranging microcrystals in the amorphous state, it is also possible to change the electrical characteristics of the oxide semiconductor layer.

[0064] For example, when forming an oxide semiconductor layer using a target for forming an In-Ga-Zn-O-based oxide semiconductor film, the electrical characteristics of the oxide semiconductor layer can be changed by forming a microcrystalline region in which crystal grains of In2Ga2ZnO7 having electrical anisotropy are oriented. The above microcrystalline region is preferably a region in which the c-axis of the In2Ga2ZnO7 crystal is oriented in a direction perpendicular to the surface of the oxide semiconductor layer. By orienting the crystal grains in this way, ​​​​​​By forming the set region, the conductivity in the direction parallel to the surface of the oxide semiconductor layer can be improved, and the insulating property in the direction perpendicular to the surface of the oxide semiconductor layer can be improved. Further, such a microcrystalline region has a function of suppressing the intrusion of impurities such as water and hydrogen into the oxide semiconductor layer.

[0065] Note that the oxide semiconductor layer having the above-described microcrystalline region can be formed by surface heating of the oxide semiconductor layer by GRTA treatment. Further, by using a sputtering target in which the Zn content is smaller than the content of In or Ga, it can be more preferably formed.

[0066] The first heat treatment for the oxide semiconductor layer can also be performed on the oxide semiconductor layer 104 before being processed into the island-shaped oxide semiconductor layer 104a. In that case, after the first heat treatment, the substrate 100 is taken out from the heating device, and a photolithography process is performed.

[0067] Note that the first heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. The dehydration treatment and the dehydrogenation treatment can be performed at timings such as after forming a source electrode or a drain electrode on the oxide semiconductor layer 104a after forming the oxide semiconductor layer, and then forming a gate insulating layer on the source electrode or the drain electrode. Further, such dehydration treatment and dehydrogenation treatment may be performed not only once but also a plurality of times.

[0068] Next, after forming the conductive layer 106 so as to be in contact with the oxide semiconductor layer 104a, an insulating layer 108 is formed on the conductive layer 106 (see FIG. 2(C)). Note that the insulating layer 108 is an essential component. ​​​​​​​​​​​Although it is not, it is effective for selectively oxidizing the side surfaces of the source electrode or drain electrode to be formed later. It is effective for

[0069] The conductive layer 106 can be formed using a PVD method such as sputtering, or a CVD method such as plasma CVD. Also, the conductive layer 106 can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components. It may also be formed using a material containing any one or more of manganese, magnesium, zirconium, beryllium, and thorium. Further, a material containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium in aluminum may be used.

[0070] Also, the conductive layer 106 may be formed by depositing a conductive metal oxide. As the conductive metal oxide, indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO ), indium tin oxide alloy (In2O3 - SnO2, sometimes abbreviated as ITO ), indium zinc oxide alloy (In2O3 - ZnO), or a material obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0071] The conductive layer 106 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Here, a three-layer structure of a titanium film, an aluminum film, and a titanium film will be applied.

[0072] Note that an oxide conductive layer may be formed between the oxide semiconductor layer 104a and the conductive layer 106. The oxide conductive layer and the conductive layer 106 can be formed continuously (continuous film formation). By providing such an oxide conductive layer, the resistance of the source region or the drain region can be reduced, so that high-speed operation of the transistor can be realized.

[0073] The insulating layer 108 can be formed using a CVD method, a sputtering method, or the like. Also, the insulating layer 108 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, and the like. Note that the insulating layer 108 may have a single-layer structure or a stacked structure. The thickness of the insulating layer 108 is not particularly limited, but can be, for example, 10 nm or more and 500 nm or less.

[0074] Next, the conductive layer 106 and the insulating layer 108 are selectively etched to form a source electrode or a drain electrode 106a, a source electrode or a drain electrode 106b, an insulating layer 108a, and an insulating layer 108b. Then, an oxidation treatment is performed to supply oxygen to the oxide semiconductor layer 104a. By this oxidation treatment, an oxidation region 110 is formed in a part of the source electrode or the drain electrode 106a and the source electrode or the drain electrode 106b (see FIG. 2(D)). Also, as shown by the dotted line, a region where oxygen is supplied is formed in the oxide semiconductor layer 104a. Note that the range of the region where the oxygen is supplied varies depending on the material constituting the oxide semiconductor layer 104a, the conditions of the oxidation treatment, and the like. For example, it is also possible to supply oxygen to the lower interface of the oxide semiconductor layer 104a.

[0075] ​​​​​​​​​​ For the exposure during mask formation used for etching, it is preferable to use ultraviolet light, KrF laser light, or ArF laser light. In particular, when performing exposure with a channel length (L) of less than 25 nm, , it is preferable to perform the exposure for mask formation using extreme ultraviolet light with a wavelength as extremely short as several nm or more and several tens of nm or less. Exposure using extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length ( L) of the transistor to be formed later to be 10 nm or more and 1000 nm or less. By reducing the channel length ( L) in such a manner, the operating speed can be improved. Also, since the off-current of the transistor using the above oxide semiconductor is small, an increase in power consumption due to miniaturization can be suppressed. During the etching of the conductive layer 106, appropriate adjustment is made to each material and etching condition so that the oxide semiconductor layer 104a is not removed. Depending on the material and etching condition, in this process, a part of the oxide semiconductor layer 104a may be etched, resulting in an oxide semiconductor layer having groove portions ( recessed portions).

[0076] Also, in order to reduce the number of masks used and the number of processes, a resist mask is formed by a multi-tone mask which is an exposure mask with transmitted light having a plurality of intensities, and the etching process is performed using this. The resist mask formed using a multi-tone mask has a shape (step shape) with a plurality of thicknesses, and since the shape can be further deformed by ashing, it can be used for a plurality of etching processes. That is, with one multi-tone mask, fewer processes can be achieved.

[0077] Also, in order to reduce the number of masks used and the number of processes, a resist mask is formed by a multi-tone mask which is an exposure mask with transmitted light having a plurality of intensities, and the etching process is performed using this. The resist mask formed using a multi-tone mask has a shape (step shape) with a plurality of thicknesses, and since the shape can be further deformed by ashing, it can be used for a plurality of etching processes. That is, with one multi-tone mask, fewer processes can be achieved. That is, with one multi-tone mask, fewer It is possible to form resist masks corresponding to at least two different patterns. This reduces the number of exposure masks and the corresponding photolithography steps. This allows for simplification of the process.

[0078] The oxidation process uses oxygen excited by microwaves (300 MHz to 300 GHz). It is preferable to use an oxidation treatment using plasma (plasma oxidation treatment). By exciting the plasma with the oxygen, a high-density plasma is realized, and the plasma is applied to the oxide semiconductor layer 104a. This is because the damage caused by the above can be sufficiently reduced.

[0079] More specifically, for example, the frequency is 300 MHz or more and 300 GHz or less (typically 2. 45GHz), pressure is 50 Pa to 5000 Pa (typically 500 Pa), and substrate temperature is The temperature is set to 200°C or higher and 400°C or lower (typically 300°C), and a mixed gas of oxygen and argon is used. The above-mentioned processing can be carried out using a gas.

[0080] By the oxidation treatment, oxygen is supplied to the oxide semiconductor layer 104a. While sufficiently reducing damage to the oxide semiconductor layer 104a, the localized levels caused by oxygen vacancies can be eliminated. In other words, the characteristics of the oxide semiconductor layer 104a can be further improved. can be done.

[0081] In addition, while sufficiently reducing damage to the oxide semiconductor layer 104a, If there is a method that can supply oxygen to a, it can be used for plasma oxidation treatment using microwaves. There is no need to be limited to this. For example, a method such as heat treatment in an atmosphere containing oxygen may be used. It is also possible.

[0082] In addition, in combination with the above oxidation treatment, a treatment for removing water, hydrogen, etc. from the oxide semiconductor layer 104a may be performed. For example, plasma treatment using a gas such as nitrogen or argon can be performed. This is possible.

[0083] Note that due to the above oxidation treatment, an oxide region 110 is formed in a part of the source electrode or drain electrode 106a and the source electrode or drain electrode 106b (particularly, the part corresponding to its side surface). This oxide region 110 is particularly effective when the transistor 150 is miniaturized (for example, when the channel length is less than 1000 nm). As the transistor is miniaturized, it is required to reduce the thickness of the gate insulating layer. However, by having the oxide region 110, it is possible to prevent a short circuit between the gate electrode and the source electrode or drain electrode that may occur due to thinning of the gate insulating layer or coverage failure etc. Note that the oxide region 110 is sufficiently effective if it has a thickness of 5 nm or more (preferably 10 nm or more).

[0084]

[0085] In addition, the above oxidation treatment is also effective from the viewpoint of improving the film quality of the exposed insulating layer 102.

[0085] Note that the insulating layers 108a and 108b are important in that they play a role in preventing oxidation of the upper part of the source electrode or drain electrode 106a and the source electrode or drain electrode 106 b. This is because it is extremely difficult to perform the above plasma treatment while leaving the mask used during etching.

[0086] Note that in FIG. 2(D), the conductive layer 106 and the insulating layer 108 shown in FIG. 2(C) are selectively etched. Etch to form the source electrode or drain electrode 106a, the source electrode or drain electrode 106b, the insulating layer 108a, and the insulating layer 108b all at once is illustrated, but one aspect of the invention disclosed is not limited to this.

[0087] For example, only the region of the conductive layer 106 and the insulating layer 108 that overlaps with the oxide semiconductor layer 104a is selectively etched to form an opening reaching the channel formation region of the transistor, and then the plasma treatment is performed on this region to supply oxygen to the oxide semiconductor layer 104a and oxidize the exposed portion of the conductive layer 106. After that, by etching again the source electrode or drain electrode 106a, the source electrode or drain electrode 106b, the insulating layer 108a, and the insulating layer 108b may be completed. When such a process is adopted it has the advantage that the oxidation treatment can be applied only to the target portion, so that other portions are not adversely affected by the oxidation treatment.

[0088] Next, without exposing to the atmosphere, a gate insulating layer 112 in contact with a part of the oxide semiconductor layer 104a is formed (see Fig. 3(A)). The gate insulating layer 112 can be formed using a CVD method, a sputtering method, or the like. Also, the gate insulating layer 112 is preferably formed to contain silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, hafnium oxide, tantalum oxide, or the like. Note that the gate insulating layer 112 may have a single-layer structure or a laminated structure. The thickness of the gate insulating layer 112 is not particularly limited, but for example, it can be 10 nm or more and 500 nm or less.

[0089] ​​An oxide semiconductor that has been made to be of the i-type or substantially of the i-type by removing impurities, etc. (a highly purified oxide semiconductor) is extremely sensitive to interface states and interface charges. Therefore, high quality is required for the gate insulating layer 112.

[0090] For example, the high-density plasma CVD method using microwaves (e.g., 2.45 GHz) is suitable in that it can form a high-quality gate insulating layer 112 that is dense and has a high breakdown voltage. By bringing the highly purified oxide semiconductor layer into close contact with the high-quality gate insulating layer, the interface states can be reduced and the interface characteristics can be made good. Of course, if a high-quality insulating layer can be formed as the gate insulating layer 112, other methods such as sputtering or plasma CVD can also be applied. Also, an insulating layer whose film quality and interface characteristics are modified by heat treatment after formation may be applied. In any case what is needed is to provide an insulating layer that has good film quality as the gate insulating layer 112 and can reduce the interface state density with the oxide semiconductor layer and form a good interface.

[0091] By improving the interface characteristics with the gate insulating layer in this way and eliminating impurities in the oxide semiconductor, especially hydrogen, water, etc., it is possible to obtain a stable transistor in which the threshold voltage (Vth) does not fluctuate with respect to the gate bias - thermal stress test (BT test: e.g., 85°C, 2×10 V / cm, 12 hours, etc.). After that, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is

[0092] Thus, while improving the interface characteristics with the gate insulating layer, by eliminating impurities in the oxide semiconductor, especially hydrogen, water, etc., it is possible to obtain a stable transistor in which the threshold voltage (Vth) does not fluctuate with respect to the gate bias - thermal stress test (BT test: e.g., 85°C, 2×10 6 V / cm, 12 hours, etc.). After that, a second heat treatment is performed in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment

[0093] is is 200°C or higher and 400°C or lower, preferably 250°C or higher and 350°C or lower. For example, a heat treatment may be performed at 250°C for 1 hour in a nitrogen atmosphere. When the second heat treatment is performed, the variation in the electrical characteristics of the transistor can be reduced. In this embodiment, although the second heat treatment is performed after the formation of the gate insulating layer 112, the timing of the second heat treatment is not particularly limited as long as it is after the first heat treatment.

[0094] Next, a gate electrode 11 4 is formed in a region overlapping with the oxide semiconductor layer 104a on the gate insulating layer 112 (see FIG. 3(B)). The gate electrode 114 can be formed by forming a conductive layer on the gate insulating layer 112 and then selectively patterning the conductive layer.

[0095] The above conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. In addition, the conductive layer can be formed using an element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described elements as components. A material containing any one or more of manganese, magnesium, zirconium, beryllium, thorium, and thallium may also be used. Further, a material containing one or more elements selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium in aluminum may also be used.

[0096] In addition, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In2O3), tin oxide (SnO2), zinc oxide (ZnO), and ​​​​Indium tin oxide alloy (In2O3—SnO2, sometimes abbreviated as ITO), oxidation indium zinc oxide alloy (In2O3—ZnO), or those containing silicon or silicon oxide can be used.

[0097] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on the aluminum film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. Here, a material containing titanium is used to form the conductive layer and process it into the gate electrode 114.

[0098] Next, an interlayer insulating layer 116 and an interlayer insulating layer 118 are formed on the gate insulating layer 112 and the gate electrode 114 (see FIG. 3(C)). The interlayer insulating layer 116 and the interlayer insulating layer 118 can be formed using a PVD method, a CVD method, or the like. Also, inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, and tantalum oxide can be used to form a film. In this embodiment, the laminated structure of the interlayer insulating layer 116 and the interlayer insulating layer 118 is shown, but one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers. It is desirable to form the interlayer insulating layer 118 so that its surface is flat. By forming the interlayer insulating layer 118 so that its surface is flat, electrodes, wirings, etc. can be preferably formed on the interlayer insulating layer 118.

[0099]

[0100] Through the above steps, the transistor 150 including an oxide semiconductor is completed.

[0101] When the transistor 150 is manufactured by the above method, hydrogen in the oxide semiconductor layer 104a The concentration is 5×10 19 / cm 3 and the off-current of the transistor 150 is 1×1 0 -13 In this way, the hydrogen concentration is sufficiently reduced and oxygen is supplied. By using the oxide semiconductor layer 104a highly purified by In addition, when oxygen is supplied immediately after the hydrogen concentration is reduced, In this case, there is no risk of hydrogen or water being mixed into the oxide semiconductor layer, and therefore the oxide semiconductor layer has extremely good characteristics. Of course, it is advantageous in that an oxide semiconductor layer having good characteristics can be realized. In order to realize an oxide semiconductor layer having the above structure, the hydrogen concentration reduction process and the oxygen supply process can be performed as follows: The processes do not have to be performed consecutively. For example, they may include other processes between them. Moreover, these processes may be carried out simultaneously.

[0102] In this embodiment, in order to supply oxygen to the oxide semiconductor layer 104a, The transistor 150 is further improved in characteristics by subjecting the surface 104a to oxygen plasma treatment. In addition, the region corresponding to the side of the source electrode or drain electrode is oxidized. Therefore, the gate electrode may be damaged due to the thinning of the gate insulating layer. -Short circuits between source electrodes (or drain electrodes) can be prevented.

[0103] Although there have been many studies on the physical properties of oxide semiconductors, most of these studies have focused on the localized does not include the idea of sufficiently reducing the levels themselves. In one aspect of the disclosed invention, highly purified oxide semiconductors are fabricated by removing water and hydrogen that can cause the local levels from the oxide semiconductor. This is based on the idea of sufficiently reducing the local levels themselves and enables the production of extremely excellent industrial products. When removing hydrogen, water, etc., oxygen may be removed at the same time. Therefore, it is preferable to supply oxygen to the unbonded hands of the metal generated by oxygen deficiency and reduce the local levels caused by oxygen defects to further purify (i-type) the oxide semiconductor.

[0104] For example, by forming an oxygen-excessive oxide film in close proximity to the channel formation region and performing heat treatment under temperature conditions of 200 °C or higher and 400 °C or lower, typically about 250 °C, it is possible to supply oxygen from the oxide film and reduce the local levels caused by oxygen defects. During the second heat treatment, the inert gas may be switched to a gas containing oxygen. Subsequently, it is also possible to supply oxygen into the oxide semiconductor through the temperature reduction process in an oxygen atmosphere or an atmosphere in which hydrogen and water have been sufficiently removed. The factors that deteriorate the characteristics of the oxide semiconductor are considered to be due to shallow levels of 0.1 eV or more and 0.2 eV or less below the conduction band caused by excessive hydrogen, deep levels caused by oxygen deficiency, etc. The idea of thoroughly removing hydrogen and sufficiently supplying oxygen to eliminate these defects would be correct. Although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, water and hydrogen are removed. During the second heat treatment, the inert gas may be switched to a gas containing oxygen. After the second heat treatment, it is also possible to supply oxygen into the oxide semiconductor through the temperature reduction process in an oxygen atmosphere or an atmosphere in which hydrogen and water have been sufficiently removed. Subsequently, through the temperature reduction process in an oxygen atmosphere or an atmosphere in which hydrogen and water have been sufficiently removed, it is possible to supply oxygen into the oxide semiconductor. The factors that deteriorate the characteristics of the oxide semiconductor are considered to be due to shallow levels of 0.1 eV or more and 0.2 eV or less below the conduction band caused by excessive hydrogen, deep levels caused by oxygen deficiency, etc.

[0105] To eliminate these defects, the idea of thoroughly removing hydrogen and sufficiently supplying oxygen is correct. Although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, water and hydrogen are removed. To eliminate these defects, the idea of thoroughly removing hydrogen and sufficiently supplying oxygen is correct.

[0106] Although oxide semiconductors are generally of the n-type, in one aspect of the disclosed invention, water and hydrogen Impurities such as are removed, and oxygen, which is a constituent element of the oxide semiconductor, is supplied to achieve i type conversion. In this regard, it can be said that this is not i-type conversion by adding impurities like silicon, but rather it involves a novel technical concept.

[0107] <Conduction mechanism of a transistor using an oxide semiconductor> Here, the conduction mechanism of a transistor using an oxide semiconductor will be described with reference to FIGS. 4 to 7. In the following description, an ideal situation is assumed for ease of understanding, and not all of it necessarily reflects the actual situation. Also, it should be noted that the following description is merely a consideration and does not affect the validity of the invention.

[0108] FIG. 4 is a cross-sectional view of a transistor (thin film transistor) using an oxide semiconductor. An oxide semiconductor layer (OS) is provided via a gate insulating layer (GI) on a gate electrode (GE1), and a source electrode (S) and a drain electrode (D) are provided thereon, and an insulating layer is provided so as to cover the source electrode (S) and the drain electrode (D).

[0109] FIG. 5 shows an energy band diagram (schematic diagram) of the A-A' cross-section in FIG. 4. Also, the black circles (●) in FIG. 5 indicate electrons, and the white circles (○) indicate holes, each having a charge (-q, +q ). After applying a positive voltage (V >0) to the drain electrode, the dashed line indicates the case where no voltage is applied to the gate electrode (V D =0), and the solid line indicates the case where a positive voltage (V >0) is applied to the gate electrode. When no voltage is applied to the gate electrode, due to a high potential barrier, no carriers (electrons) are injected from the electrode into the oxide semiconductor side, indicating an off state where no current flows. G G ​ Well, when a positive voltage is applied to the gate, the potential barrier decreases, and it shows an on state where current flows. State.

[0110] Fig. 6 shows an energy band diagram (schematic diagram) of the cross-section taken along B - B' in Fig. 4. Fig. 6(A) shows a state where a positive voltage (V G > 0) is applied to the gate electrode (GE1), indicating an on state where carriers (electrons) flow between the source electrode and the drain electrode. Also, Fig. 6(B) shows a state where a negative voltage (V G < 0) is applied to the gate electrode (GE1), showing a case where it is in an off state (a state where minority carriers do not flow).

[0111] Fig. 7 shows the relationship between the vacuum level, the work function of the metal (φ M ), and the electron affinity (χ) of the oxide semiconductor. Shown.

[0112] At room temperature, electrons in the metal are degenerate, and the Fermi level is located within the conduction band. On the other hand, conventional oxide semiconductors are n-type, and their Fermi level (E F ) is located away from the intrinsic Fermi level (E i ) at the center of the bandgap and closer to the conduction band. Note that it is known that in oxide semiconductors, a part of hydrogen acts as a donor and is one of the factors for n-type conversion. Yes.

[0113] On the other hand, the oxide semiconductor according to one aspect of the disclosed invention removes hydrogen, which is a factor for n-type conversion, from the oxide semiconductor, and purifies it to a high purity so that elements (impurity elements) other than the main component of the oxide semiconductor are not contained as much as possible, to make it intrinsic (i-type), or to make it as close to intrinsic as possible. That is, instead of adding impurity elements to make it i-type, impurities such as hydrogen and water are removed as much as possible. . By doing so, it is characterized by obtaining a highly purified type-I (intrinsic semiconductor) or approaching it. As a result, the Fermi level (E F ) can be made approximately the same as the intrinsic Fermi level (E i ). This can be achieved.

[0114] The bandgap (E g ) of the oxide semiconductor is 3.15 eV, and the electron affinity (χ) is said to be 4.3 V. The work function of titanium (Ti) that constitutes the source electrode and the drain electrode is substantially equal to the electron affinity (χ) of the oxide semiconductor. In this case, at the metal-oxide semiconductor interface no Schottky-type barrier is formed for electrons.

[0115] At this time, as shown in Fig. 6(A), electrons move near the interface between the gate insulating layer and the highly purified oxide semiconductor (the lowest energy-stable part of the oxide semiconductor).

[0116] Also, as shown in Fig. 6(B), when a negative potential is applied to the gate electrode (GE1), since the number of minority carriers, holes, is substantially zero, the current becomes a value approaching zero infinitely.

[0117] In this way, by highly purifying the oxide semiconductor so that elements other than the main component (impurity elements) are contained as little as possible, it becomes intrinsic (type-I) or substantially intrinsic, and thus the interface characteristics with the gate insulating layer are manifested. Therefore, the gate insulating layer is required to be able to form a good interface with the oxide semiconductor. Specifically, for example, an insulating layer formed by a CVD method using high-density plasma generated at a power frequency in the VHF band to microwave band or an insulating layer formed by a sputtering method is preferably used. method or an insulating layer formed by a sputtering method is preferably used.

[0118] While purifying the oxide semiconductor, the interface between the oxide semiconductor and the gate insulating layer is made good Thereby, for example, when the channel width (W) of the transistor is 1×10 4 μm and the channel length (L) is 3 μm, an off-current of 10 -13 A or less and a subthreshold swing value (S value) of 0.1 V / dec. (gate insulating layer thickness: 100 nm) can be realized. That is, by purifying the oxide semiconductor so that it contains as little as possible elements (impurity elements) other than the main components of the oxide semiconductor, the operation of the transistor can be made good.

[0119] <Hot Carrier Degradation Resistance of Transistor Using Oxide Semiconductor> Next, the hot carrier degradation resistance of a transistor using an oxide semiconductor will be described with reference to FIGS. 8 to

[0120] 10. In the following description, for ease of understanding, an ideal situation is assumed However, not all of them necessarily reflect the actual situation. Also, it should be noted that the following description is only a consideration and nothing more.

[0121] The main causes of hot carrier degradation are channel hot electron injection (CHE injection) and drain avalanche hot carrier injection (DAHC injection). In the following, for simplicity only electrons are considered.

[0122] CHE injection refers to a phenomenon in which electrons having energy higher than the barrier of the gate insulating layer in the semiconductor layer are injected into the gate insulating layer or the like. The imparting of energy to electrons is performed by accelerating the electrons in a low electric field.

[0123] ​​​DAHC injection refers to the phenomenon in which new electrons generated by the collision of electrons accelerated by a high electric field are injected into a gate insulating layer or the like. The difference between DAHC injection and CHE injection lies in whether or not avalanche breakdown due to impact ionization occurs. In DAHC injection, electrons having a kinetic energy equal to or higher than the semiconductor bandgap are required. The difference between DAHC injection and CHE injection is whether or not it is accompanied by avalanche breakdown due to impact ionization. Note that in DAHC injection, electrons having a kinetic energy equal to or higher than the semiconductor bandgap are required.

[0124] Fig. 8 shows the energies required for various hot carrier injections estimated from the band structure of silicon (Si), and Fig. 9 shows the energies required for various hot carrier injections estimated from the band structure of an In-Ga-Zn-O-based oxide semiconductor (IGZO). Also, Fig. 8(A) and Fig. 9(A) represent CHE injection, and Fig. 8(B) and Fig. 9(B) represent DAHC injection. In silicon, degradation due to DAHC injection is more serious than that due to CHE injection. This is because the carriers (e.g., electrons) that are accelerated without collision in silicon are very few, while silicon has a small bandgap and avalanche breakdown is likely to occur. The number of electrons that can cross the barrier of the gate insulating layer due to avalanche breakdown increases and easily exceeds the probability of CHE injection.

[0125] In an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not very different from that in the case of silicon, and its probability is still low. Also, the energy required for DAHC injection is about the same as the energy required for CHE injection due to the width of the bandgap. That is, the probabilities of both CHE injection and DAHC injection are low, and hot carrier injection is less likely to occur compared to silicon.

[0126] In an In-Ga-Zn-O-based oxide semiconductor, the energy required for CHE injection is not very different from that in the case of silicon, and its probability is still low. Also, the energy required for DAHC injection is about the same as the energy required for CHE injection due to the width of the bandgap.

[0127] That is, the probabilities of both CHE injection and DAHC injection are low, and hot carrier injection is less likely to occur compared to silicon. The carrier has high resistance to degradation.

[0128] By the way, the band gap of In-Ga-Zn-O oxide semiconductors is This is about the same as that of silicon carbide (SiC), which is attracting attention. The energy required for various hot carrier injections is shown in Fig. 10(A). FIG. 10(B) shows the DAHC implantation. As for the CHE implantation, In-Ga-Zn- O-based oxide semiconductors have a slightly higher threshold and are therefore advantageous.

[0129] As mentioned above, the In-Ga-Zn-O oxide semiconductor has a higher hot carrier degradation rate than silicon. It can be seen that the resistance to carbonization and source-drain breakdown is very high. It can be said that the breakdown voltage is comparable to that of silicon.

[0130] <Short-channel effect in transistors using oxide semiconductors> Next, regarding the short-channel effect in a transistor including an oxide semiconductor, FIG. 11 and The following description will be given with reference to FIG. 12. In the following description, an ideal situation is assumed for ease of understanding. The following explanations are based on actual conditions and may not necessarily reflect reality. I would like to add that this is merely one consideration.

[0131] The short channel effect becomes evident as transistors become smaller (as the channel length (L)) The short channel effect is a degradation of electrical characteristics caused by the drain effect extending to the source. Specific examples of short channel effects include a decrease in threshold voltage and S value. Increase in leakage current, etc.

[0132] Here, using device simulation, we verified a structure capable of suppressing the short-channel effect. Specifically, four types of models with different carrier concentrations and oxide semiconductor layer thicknesses were prepared to examine the relationship between the channel length (L) and the threshold voltage (Vth). As the model, a transistor with a bottom-gate structure was adopted. The carrier concentration of the oxide semiconductor was set to either 1.7×10 / cm or 1.0×10 -8 / cm 3 and the thickness of the oxide semiconductor layer was set to either 1 μm or 30 nm. An In-Ga-Zn-O-based oxide semiconductor was used as the oxide semiconductor, and a silicon oxynitride film with a thickness of 100 nm was used as the gate insulating layer. 15 / cm 3 The bandgap of the oxide semiconductor was assumed to be 3.15 eV, the electron affinity was assumed to be 4.3 eV, the relative permittivity was assumed to be 15, and the electron mobility was assumed to be 10 cm / Vs. The relative permittivity of the silicon oxynitride film was assumed to be 4.0. For the calculation, the device simulation software "Atlas" manufactured by Silvaco was used. Note that there is no significant difference in the calculation results between the top-gate structure and the bottom-gate structure. The calculation results are shown in FIGS. 11 and 12. FIG. 11 shows the case where the carrier concentration is 1.7×10 / cm 2 and FIG. 12 shows the case where the carrier concentration is 1.0×10 / cm . In FIGS. 11 and 12, with a transistor having a channel length (L) of 10 μm as a reference, the change amount (Δ

[0133] in the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm is shown.

[0134] When the carrier concentration is 1.7×10 -8 / c m 3 and FIG. 12 shows the case where the carrier concentration is 1.0×10 15 / cm 3 . In FIGS. 11 and 12, with a transistor having a channel length (L) of 10 μm as a reference, the change amount (Δ (L) in the threshold voltage (Vth) when the channel length (L) is changed from 10 μm to 1 μm is shown. It shows (Vth). As shown in FIG. 11, when the carrier concentration of the oxide semiconductor is 1.7×1 0 -8 / cm 3 and the thickness of the oxide semiconductor layer is 1 μm, the change amount (ΔVth) of the threshold voltage was -3.6 V. Also, as shown in FIG. 11, the carri er concentration of the oxide semiconductor is 1.7×10 -8 / cm 3 and when the thickness of the oxide semiconductor layer is 30 nm, the change amount (ΔVth) of the threshold voltage was -0.2 V. Also, as shown in FIG. 12, when the carrier concentration of the oxide semiconductor is 1.0×10 15 / cm 3 and the thickness of the oxide semiconductor layer is 1 μm, the change amount (ΔVth) of the threshold voltage was -3.6 V. Also, as shown in FIG. 12, when the carrier concentration of the oxide semiconductor is 1.0×10 15 / cm 3 and the acid when the thickness of the oxide semiconductor layer is 30 nm, the change amount (ΔVth) of the threshold voltage was -0.2 V. The results indicate that in a transistor using an oxide semiconductor, the short-channel effect can be suppressed by reducing the thickness of the oxide semiconductor layer. For example, when the channel length (L) is about 1 μm, even if the oxide semiconductor layer has a sufficiently large carrier concentration, if its thickness is about 30 nm, it can be understood that the short-channel effect can be sufficiently suppressed. The technical idea of the disclosed invention is to make the carrier concentration in the oxide semiconductor layer sufficiently small

[0135] and approach the intrinsic (i-type) as much as possible. Hereinafter, the method for obtaining the carrier concentration <Carrier Concentration> will be described with reference to FIGS. 13 and 14 regarding the actually measured carrier concentration. and try to make it as close to the intrinsic (i-type) as possible. Hereinafter, the method for obtaining the carrier concentration and the actually measured carrier concentration will be described with reference to FIGS. 13 and 14. .

[0136] First, the method for obtaining the carrier concentration will be briefly described. The carrier concentration can be obtained by fabricating a MOS capacitor and evaluating the result (CV characteristics) of the CV measurement of the MOS capacitor. That is possible.

[0137] More specifically, a C-V characteristic is obtained by plotting the relationship between the gate voltage Vg and the capacitance C of the MOS capacitor, and a graph representing the relationship between the gate voltage Vg and (1 / C) is obtained from the C-V characteristic. In the graph, the differential value of (1 / C) in the weak inversion region is obtained, and the magnitude of the carrier concentration N is obtained by substituting the differential value into Equation (1). In Equation (1), e is the elementary charge, ε0 is the permittivity of vacuum, and ε is the relative permittivity of the oxide semiconductor. 2 2 d

[0138]

Equation

[0139] Next, the carrier concentration actually measured using the above method will be described. For the measurement, a sample (MOS capacitor) was used in which a titanium film was formed on a glass substrate with a thickness of 300 nm, a titanium nitride film was formed on the titanium film with a thickness of 100 nm, an oxide semiconductor layer using an In-Ga-Zn-O-based oxide semiconductor was formed on the titanium nitride film with a thickness of 2 μm, and a silver film was formed on the oxide semiconductor layer with a thickness of 300 nm. The oxide semiconductor layer was formed by a sputtering method using a target for forming an oxide semiconductor containing In, Ga, and Zn (In:Ga:Zn = 1:1:0.5 atomic ratio). Also, the formation of the oxide semiconductor layer ​ The atmosphere was a mixed atmosphere of argon and oxygen (flow rate ratio: Ar:O2 = 30 (sccm):1 5 (sccm)).

[0140] Fig. 13 shows the C-V characteristics, and Fig. 14 shows the relationship between Vg and (1 / C) 2 respectively. Fig The carrier concentration obtained using Equation (1) from the differential value of (1 / C) in the weak inversion region of Fig. 14 2 was 6.0×10 / cm 10 / cm 3 .

[0141] In this way, by using an i-type or substantially i-type oxide semiconductor (for example, the carrier concentration is 1×10 12 / cm 3 less than, preferably, 1×10 11 / cm 3 or less), it is possible to obtain a transistor with extremely excellent off-current characteristics.

[0142] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0143] (Embodiment 2) In this embodiment, an example of an electronic device equipped with the semiconductor device obtained in the previous embodiment will be described with reference to Fig. 15. The semiconductor device obtained in the previous embodiment has unprecedented excellent characteristics. Therefore, it is possible to provide an electronic device with a new configuration using the semiconductor device. Note that the semiconductor device according to the previous embodiment will be integrated and mounted on a circuit substrate or the like, and will be mounted inside each electronic device.

[0144] Fig. 15(A) shows a notebook personal computer including the semiconductor device according to the previous embodiment​​​​ It is data and is composed of a main body 301, a housing 302, a display unit 303, a keyboard 304, etc. By applying the semiconductor device according to the disclosed invention to a personal computer, a personal computer with excellent performance can be provided.

[0145] FIG. 15(B) shows a personal digital assistant (PDA) including the semiconductor device according to the previous embodiment. In the main body 311, a display unit 313, an external interface 315, operation buttons 314, etc. are provided. Also, there is a stylus 312 as an accessory for operation. By applying the semiconductor device according to the disclosed invention to a personal digital assistant (PDA), a personal digital assistant (PDA) with excellent performance can be provided.

[0146] FIG. 15(C) shows an example of an electronic paper including the semiconductor device according to the previous embodiment, an electronic book 320. The electronic book 320 is composed of two housings, a housing 321 and a housing 323. The housing 321 and the housing 323 are integrated by a shaft portion 337, and can perform an opening and closing operation around the shaft portion 337. With such a configuration, the electronic book 320 can be used like a paper book.

[0147] A display unit 325 is incorporated in the housing 321, and a display unit 327 is incorporated in the housing 323. The display unit 325 and the display unit 327 may be configured to display a continuous screen or may be configured to display different screens. By configuring to display different screens, for example, a text can be displayed on the right display unit (display unit 325 in FIG. 15(C)), and an image can be displayed on the left display unit (display unit 327 in FIG. 15 (C)).

[0148] Further, FIG. 15(C) shows an example in which the housing 321 is provided with an operation unit or the like. For example, the housing 321 includes a power supply 331, operation keys 333, a speaker 335, and the like. The page can be scrolled by the operation keys 333. In addition, a configuration may be adopted in which a keyboard or a pointing device is provided on the same surface as the display unit of the housing. Further, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, and the like may be provided. Furthermore, the electronic book 320

[0149] may be configured to be capable of wirelessly transmitting and receiving information. With wireless communication, it is also possible to purchase and download desired book data or the like from an electronic book server.

[0150] In addition, the electronic paper can be applied to any field as long as it can display information. For example, in addition to electronic books, it can be applied to posters, in-vehicle advertisements on vehicles such as trains, and displays on various cards such as credit cards. By applying the semiconductor device according to the disclosed invention to the electronic paper, an electronic paper with excellent performance can be provided.

[0151] FIG. 15(D) shows a mobile phone including the semiconductor device according to the previous embodiment. The mobile phone is composed of two housings, namely a housing 340 and a housing 341. The housing 341 includes a display panel 342, a speaker 343, a microphone 344, a 46. It is equipped with a camera lens 347, an external connection terminal 348, etc. Also, the housing 340 is equipped with a solar cell 349 for charging the mobile phone, an external memory slot 350, etc. Also, the antenna is built inside the housing 341.

[0152] The display panel 342 has a touch panel function, and a plurality of operation keys 345 shown by dotted lines are displayed in FIG. 15(D). Note that the mobile phone implements a boost circuit for boosting the voltage output from the solar cell 349 to the voltage required for each circuit. Also, in addition to the above configuration, it can also be configured to incorporate a non-contact IC chip, a small recording device, etc.

[0153] The display direction of the display panel 342 changes appropriately according to the usage form. Also, since the camera lens 347 is provided on the same plane as the display panel 342, a video phone is possible. The speaker 343 and the microphone 344 are not limited to voice calls, and video phone, recording, playback, etc. are possible. Further, the housing 340 and the housing 341 can be slid and changed from the state shown in FIG. 15(D) where they are unfolded to an overlapping state, enabling miniaturization suitable for carrying.

[0154] The external connection terminal 348 can be connected to various cables such as an AC adapter and a USB cable, enabling charging and data communication. Also, a recording medium can be inserted into the external memory slot 350 to support storage and transfer of a larger amount of data. Also, in addition to the above functions, it may be equipped with an infrared communication function, a TV reception function, etc. By applying the semiconductor device according to the disclosed invention to a mobile phone, a mobile phone with excellent​ to cut

[0155] FIG. 15(E) is a digital camera including a semiconductor device according to the previous embodiment. The digital camera includes a main body 361, a display unit (A) 367, an eyepiece 363, an operation switch 364 , a display unit (B) 365, a battery 366, etc. By applying the semiconductor device according to the disclosed invention to the digital camera, a digital camera with excellent performance can be provided .

[0156] FIG. 15(F) is a television device including a semiconductor device according to the previous embodiment. In the television device 370, a display unit 373 is incorporated in a housing 371. The display unit 373 can display an image. Here, a configuration in which the housing 371 is supported by a stand 375 is shown .

[0157] The operation of the television device 370 can be performed by an operation switch provided in the housing 371 or a separate remote control operation unit 380. By operating keys 379 provided in the remote control operation unit 380, channel and volume operations can be performed, and the image displayed on the display unit 373 can be operated . Also, it is preferable to provide a display unit 377 for displaying information output from the remote control operation unit 380 on the remote control operation unit 380 .

[0158] Note that the television device 370 preferably has a configuration including a receiver, a modem, etc. The receiver can receive general television broadcasts. Also, by connecting to a wired or wireless communication network via a modem, one-way (from the sender to the receiver ),... ​​​It is possible to perform unidirectional (e.g., from a sender to a receiver) or bidirectional (between a sender and a receiver, or between receivers) information communication. By applying the semiconductor device according to the disclosed invention to a television device, a television device with excellent performance can be provided.

[0159] The configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

Example

[0160] In this example, the state in which the conductive layer is oxidized was confirmed by high-density plasma treatment according to one aspect of the disclosed invention. This will be described in detail below.

[0161] In this example, plasma was excited from a mixed gas of oxygen and argon under the conditions that the frequency of the power supply was 2.45 GHz and the pressure was 500 Pa, and this was used to process the conductive layer. Also, by setting the processing time to three conditions of 1 minute (60 seconds), 3 minutes (180 seconds), and 10 minutes (600 seconds), the relationship between the processing time and the thickness of the oxidized region was investigated.

[0162] As the conductive layer, a titanium film formed on a glass substrate and an aluminum film formed on a glass substrate were prepared respectively. Also, the plasma treatment was performed with the substrate temperature set to 300°C and 325°C respectively. That is, regarding the four conditions of the titanium film at a substrate temperature of 300°C, the titanium film at a substrate temperature of 325°C, the aluminum film at a substrate temperature of 300°C, and the aluminum film at a substrate temperature of 3 25°C, the relationship between the processing time and the thickness of the oxidized region was investigated.

[0163] The investigation results are shown in Fig. 16. From Fig. 16, it can be seen that titanium oxidizes faster than aluminum. In addition, the oxidation rate of titanium is highly temperature-dependent, whereas that of alumina is not. In aluminum, the oxidation rate is less dependent on temperature. However, it can be said that the demand for electricity tends to saturate in a short period of time.

[0164] For all materials, short circuits between the gate electrode and the source or drain electrodes are suppressed. It is possible to obtain an oxide region of sufficient thickness (5 nm or more) to suppress the

[0165] By applying the oxidation treatment using high-density plasma as shown in this embodiment, Compared to the case of applying oxidation treatment by thermal treatment, damage to the oxide semiconductor layer is reduced. In addition, the localized levels caused by oxygen vacancies can be reduced. The characteristics can be further improved.

[0166] In addition, the oxidation treatment can be carried out on a portion of the source electrode or drain electrode (particularly on the side surface thereof). As a result, an oxide region is formed in the gate electrode and the source or drain electrode. This can prevent short circuits of electrodes.

[0167] As described above, one embodiment of the disclosed invention is to provide a transistor including an oxide semiconductor, It is understood that the present invention is extremely effective in improving other properties of the present invention. [Explanation of symbols]

[0168] 100 Substrates 102 Insulating layer 104 Oxide semiconductor layer 104a Oxide semiconductor layer 106 Conductive layer 106a Source electrode or drain electrode 106b Source electrode or drain electrode 108 Insulating layer 108a Insulating layer 108b Insulating layer 110 Oxidation region 112 Gate insulating layer 114 Gate electrode 116 Interlayer insulating layer 118 Interlayer insulating layer 150 Transistor 301 Main body 302 Housing 303 Display unit 304 Keyboard 311 Main body 312 Stylus 313 Display unit 314 Operation button 315 External interface 320 E-book 321 Housing 323 Housing 325 Display unit 327 Display unit 331 Power supply 333 Operation key 335 Speaker 337 Shaft portion 340 Housing 341 Housing 342 Display panel 343 Speaker 344 Microphone 345 Operation key 346 Pointing device 347 Camera lens 348 External connection terminal 349 Solar cell 350 External memory slot 361 Main body 363 Viewfinder 364 Operation switch 365 Display unit (B) 366 Battery 367 Display unit (A) 370 Television device 371 Housing 373 Display unit 375 Stand 377 Display unit 379 Operation key 380 Remote control operation unit

Claims

1. A semiconductor device having a transistor, The transistor is a gate electrode layer; a gate insulating film; an oxide semiconductor layer having a region overlapping with the gate electrode layer with the gate insulating film interposed therebetween; a first conductive layer having a region in contact with an upper surface of the first region of the oxide semiconductor layer; a second conductive layer having a region in contact with an upper surface of the second region of the oxide semiconductor layer, the oxide semiconductor layer contains In, Ga, and Zn and has a c-axis oriented crystal region; each of the first conductive layer and the second conductive layer comprises copper; In a cross-sectional view of the transistor in a channel length direction, each end of the first conductive layer and the second conductive layer has a tapered shape; The end of each of the first conductive layer and the second conductive layer has an oxide region.

2. A semiconductor device having a transistor, The transistor is a gate electrode layer; a gate insulating film; an oxide semiconductor layer having a region overlapping with the gate electrode layer with the gate insulating film interposed therebetween; a first conductive layer having a region in contact with an upper surface of the first region of the oxide semiconductor layer; a second conductive layer having a region in contact with an upper surface of the second region of the oxide semiconductor layer, the oxide semiconductor layer contains In, Ga, and Zn and has a c-axis oriented crystal region; each of the first conductive layer and the second conductive layer has a laminated structure including a copper film; In a cross-sectional view of the transistor in a channel length direction, each end of the first conductive layer and the second conductive layer has a tapered shape; The end of each of the first conductive layer and the second conductive layer has an oxide region.

3. A semiconductor device having a transistor, The transistor is a gate electrode layer; a gate insulating film; an oxide semiconductor layer having a region overlapping with the gate electrode layer with the gate insulating film interposed therebetween; a first conductive layer having a region in contact with an upper surface of the first region of the oxide semiconductor layer; a second conductive layer having a region in contact with an upper surface of the second region of the oxide semiconductor layer, the oxide semiconductor layer has a third region between the first region and the second region, a thickness of the third region is smaller than a thickness of the first region and a thickness of the second region; the oxide semiconductor layer contains In, Ga, and Zn and has a c-axis oriented crystal region; each of the first conductive layer and the second conductive layer has a laminated structure including a copper film; In a cross-sectional view of the transistor in a channel length direction, each end of the first conductive layer and the second conductive layer has a tapered shape; The end of each of the first conductive layer and the second conductive layer has an oxide region.

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