Systems and methods for degeneracy mitigation in quantum processor

Abstract

To mitigate degeneracy in analog processor operation via use of floppy qubits or domains of floppy qubits, thereby significantly boosting hardware performance on certain problems.SOLUTION: Samples are drawn from an analog processor, and devices comprising the analog processor are evaluated for floppiness. A normalized floppiness metric is calculated, and an offset is added to advance the device in annealing. Degeneracy in a hybrid computing system that comprises a quantum processor is mitigated by determining a magnetic susceptibility of a qubit, and tuning a tunneling rate for the qubit based on a tunneling rate offset determined based on the magnetic susceptibility. Quantum annealing evolution is controlled by causing the evolution to pause for a determined pause duration.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] Field The present disclosure generally relates to quantum processors and related systems, devices, methods, and articles.

Background Art

[0002] Background Quantum Device A quantum device is a structure in which quantum mechanical effects are observable. A quantum device includes a circuit in which current transport is governed by quantum mechanical effects. Such devices include spintronics and superconducting circuits. Both spin and superconductivity are quantum mechanical phenomena. Quantum devices can be used in measuring devices in computing machines and the like.

[0003] Quantum Computing A quantum computer is a system that directly utilizes at least one quantum mechanical phenomenon such as superposition, tunneling, and entanglement to perform operations on data. The elements of a quantum computer are qubits. A quantum computer can provide a speedup for some classes of computational problems such as computational problems by simulating quantum physics.

[0004] Quantum Annealing Quantum annealing is a computational method that can be used to find the low-energy state of a system (usually, preferably, the ground state of the system). Classical simulated annealing Conceptually similar to, this method is based on the fundamental principle that "a natural system tends towards a lower energy state because a lower energy state is more stable." Classical annealing uses classical thermal fluctuations to induce a system to a low-energy state, while quantum annealing can utilize quantum effects such as quantum tunneling as a source of delocalization to reach the energy minimum more precisely and / or rapidly than classical annealing.

[0005] A quantum processor can be designed to perform quantum annealing and / or adiabatic quantum computing. An evolution Hamiltonian proportional to the sum of a first term proportional to the problem Hamiltonian and a second term proportional to the delocalization Hamiltonian is as follows constructed. H E ∝A(t)H P +B(t)H D where H E is the evolution Hamiltonian, H P is the problem Hamiltonian, H D is the delocalization Hamiltonian, and A(t), B(t) are coefficients that control the evolution rate and can typically be within the range [0,1]. In some embodiments, a time-varying envelope function can be placed on the problem Hamiltonian. A suitable delocalization Hamiltonian is given by:

[0006] where N represents the number of qubits,

Num

Num

Num

[0007] A general problem Hamiltonian can include a first component proportional to diagonal single qubit terms and a second component proportional to diagonal multi-qubit terms, and can be of the following form:

Num

[0008] Here, [Number] The terms are examples of "diagonal" terms. The former is a single - qubit term and the latter is a two - qubit term.

[0009] Throughout this specification, the terms "problem Hamiltonian" and "final Hamiltonian" are used interchangeably unless the context otherwise indicates. Some states of a quantum processor are energetically preferred or simply preferred by the problem Hamiltonian. These include the ground state but may also include excited states.

[0010] The Hamiltonians such as H D and H P in the above two equations can each be physically realized in a variety of ways. A specific example is realized by an embodiment of superconducting qubits.

[0011] Superconducting quantum processor for quantum annealing A superconducting quantum processor can be designed for quantum annealing (and / or adiabatic quantum computing: see below) components that can be used to implement this system and method. A superconducting quantum processor can include a plurality of superconducting qubits and at least one coupler that provides tunable [Number] couplings (diagonal couplings) between the qubits.

[0012] A quantum processor may include a plurality of interfaces used to configure and control the state of the quantum processor. Each of the interfaces may be realized by respective inductive coupling structures as part of a programming subsystem and / or an evolution subsystem.

[0013] During operation of the quantum processor, the interface couples a flux signal to each composite Josephson junction of the qubits, thereby tunable term (Δ i term) can be used to implement within the system Hamiltonian. This coupling provides the off-diagonal σ term of the Hamiltonian. These flux signals are examples of "delocalized signals". x

[0014] Similarly, the interface couples a flux signal into each qubit loop of the qubits, thereby h i term can be used to implement within the system Hamiltonian. This coupling provides the diagonal σ . z term in the system Hamiltonian. Further, the inter face couples a flux signal into a coupler, thereby the coupling J ij term can be used to implement within the stem Hamiltonian. This coupling is diagonal

Number

[0015] The quantum processor may include a readout device for reading out the final state of the qubits. Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, and the like.

[0016] Adiabatic quantum computing ​One model of quantum computing is adiabatic quantum computing. Adiabatic quantum computing is suitable for solving, for example, hard optimization problems and the like. Adiabatic quantum computing can be considered a special case of quantum annealing. In adiabatic quantum computing, the system ideally starts and remains in its ground state through adiabatic evolution. Those skilled in the art will understand that quantum annealing systems and methods can generally be implemented on adiabatic quantum computers. Throughout this specification and the appended claims, any reference to quantum annealing is intended to encompass adiabatic quantum computing, unless the context otherwise requires.

[0017] Hybrid computing system including a quantum processor The hybrid computing system can include a digital computer communicatively coupled to an analog computer. In some embodiments, the analog computer is a quantum computer and the digital computer is a classical computer.

[0018] The digital computer can include a digital processor that can be used to perform classical digital processing tasks described in the present systems and methods. The digital computer can include at least one system memory that can be used to store various sets of computer or processor-readable instructions, application programs, and / or data.

[0019] The quantum computer can include a quantum processor that includes programmable elements such as qubits, couplers, and other devices. The qubits are read out via a readout system, and the results can be transmitted to the digital computer. The qubits and couplers can be controlled by a qubit control system and a coupler control system, respectively. In some embodiments, the qubit and coupler control systems are used to implement quantum annealing on the analog computer and can be used to implement it.

[0020] Degeneracy In a quantum mechanical system, an energy level is said to be degenerate if the energy level can correspond to two or more different measurable states. Two or more different states of a quantum mechanical system are said to be degenerate if they can correspond to the same energy level. A quantum binary number known as a qubit is a two-state quantum mechanical system. Two states are said to be degenerate if reversing the qubit from the first state to the second state of the two states does not affect the energy of the system.

[0021] Degeneracy operations in qubits Dickson and Amin (arXiv 1104.2349) describe a method of avoiding perturbative crossings by adding an ancillary qubit (i.e., a constraint ) to the Hamiltonian. Dickson and Amin demonstrated that "a simple adiabatic qubit quantum algorithm based on penalizing the clustering of the minima of the path by tuning the single qubit tunneling energy can be effective in eliminating perturbative crossings that produce a minimum gap."

[0022] Dickson and Amin describe how, if the final ground state is degenerate, the corresponding eigenstates can repel each other and move away from the final state. If the degeneracy in the final ground state can be introduced without significantly affecting the excited state, the ground state energy can move away from the energy of the excited state. Boixo et al. (arXiv 1212.1739) describe a 17-fold degenerate ground state Hamiltonian that can be constructed from a ferromagnetic 4-cycle by imposing an auxiliary constraint on each of the four original qubits.

[0023] SUMMARY OF THE INVENTION MEANS FOR SOLVING THE PROBLEM

[0024] Summary A method for degeneracy reduction in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of devices and operates as a sample generator for providing samples, the method includes transmitting a problem to the quantum processor; until an end determination criterion is satisfied: extracting a plurality of samples by the quantum processor; returning the plurality of samples to the digital processor; initializing a sample counter; until the sample counter reaches a predetermined sample limit: initializing a device counter; until the device counter reaches a first predetermined device limit: determining whether the device indexed by the device counter is floppy; incrementing the device counter, repeating; incrementing the sample counter; initializing the device counter; until the device counter reaches a second predetermined device limit: calculating a normalized floppiness metric of the device indexed by the device counter; adding an offset to advance the device during annealing; incrementing the device counter, and can be summarized as including.

[0025] The method may further include determining whether an end condition is satisfied. Determining whether an end condition is satisfied may include one of completing a predetermined number of iterations, reaching a predetermined upper limit of the allowable calculation time, or determining that the change in energy of the solution of the problem between consecutive iterations is less than a predetermined threshold. Including a quantum processor Degeneracy reduction in a hybrid computing system can include reducing degeneracy in a hybrid computing system including a superconducting quantum processor. Determining whether a device indexed by a device counter is floppy can include determining whether a superconducting qubit indexed by the device counter is floppy. Determining whether a superconducting qubit indexed by the device counter is floppy can include determining that "the change in the energy of the solution to the problem is less than a predetermined threshold when the state of the superconducting qubit is inverted". Determining whether a superconducting qubit indexed by the device counter is floppy can include determining the prevalence of the net zero bias from neighboring devices. Calculating the normalized floppiness metric of a device indexed by a device counter can include summing the number of times the device is determined to be floppy and dividing this by a predetermined sample limit. The first predetermined device limit can be the same as the second predetermined device limit. Drawing a plurality of samples by a quantum processor can include drawing at least 1000 samples by the quantum processor. Determining whether a device indexed by a device counter is floppy can include determining whether a region of the qubit indexed by the device counter is floppy. The region of the qubit includes a plurality of coupled qubits. Sending a problem to a quantum processor can include sending a difficult problem to the quantum processor.

[0026] A hybrid computing system includes at least one quantum processor including a plurality of devices and a readout subsystem; at least one digital processor-based device communicatively coupled to the at least one quantum processor; and at least one non-transitory computer-readable storage medium storing processor-executable instructions for reducing degeneracy, the at least one non-transitory computer-readable storage medium, when executed, causing the at least one processor-based device to: send a problem to the quantum processor; until an end determination criterion is satisfied, draw a plurality of samples by the quantum processor; return the plurality of samples to the digital processor via the readout system; initialize a sample counter; until the sample counter reaches a predetermined sample limit: initialize a device counter; until the device counter reaches a first predetermined device limit: determine whether the device indexed by the device counter is floppy; and increment the device counter, and repeat; increment the sample counter; initialize the device counter; until the device counter reaches a second predetermined device limit: calculate a normalized floppiness metric of the device indexed by the device counter; add an offset to advance the device during annealing; and increment the device counter, and may be summarized as such.

[0027] The quantum processor can be a superconducting quantum processor, the plurality of devices can include a plurality of superconducting qubits, the quantum processor further includes a plurality of coupling devices, and each coupling device can provide a controllable transmission coupling between each pair of superconducting qubits within the plurality of superconducting qubits. At least one processor device can determine whether a superconducting qubit indexed by a device counter is floppy based at least in part on "whether the change in the energy of the solution to the problem is less than a predetermined threshold when the state of the superconducting qubit is inverted". At least one processor device can determine whether a superconducting qubit indexed by a device counter is floppy based at least in part on the spread of the zero net bias from neighboring devices. The normalized floppiness metric can be the number of times the device is determined to be floppy divided by a predetermined sample limit. The first predetermined device limit can be the same as the second predetermined device limit. The plurality of samples can include at least 1000 samples. End The determination criterion can include at least one of completing a predetermined number of repetitions, reaching a predetermined upper limit of the allowable calculation time, or determining that the change in the energy of the solution to the problem between consecutive repetitions is less than a predetermined threshold. The device can be a region of qubits including a plurality of coupled qubits, and to determine whether a device indexed by a device counter is floppy, at least one processor can determine whether the region of qubits indexed by the device counter is floppy. The problem can be a difficult problem.

[0028] A method for degeneracy reduction in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicably coupled to each other, the quantum processor includes a plurality of qubits, and operates as a sample generator for providing samples. The method may be summarized as including: receiving, by the quantum processor, a computational problem; generating, by the quantum processor, one or more samples based on the problem; determining, for each of one or more qubits of the plurality of qubits, a susceptibility based on the one or more samples; determining, for at least one qubit of the one or more qubits, a tunneling speed offset based on the susceptibility of the one or more qubits; and tuning, based on the tunneling speed offset, the tunneling speed of the at least one qubit.

[0029] The method may further include determining, based on a target susceptibility, a subset of the plurality of qubits to be tuned, wherein the susceptibility of each qubit in the subset differs from the target susceptibility by more than a threshold amount; and wherein at least one qubit is included in the subset. Determining the susceptibility of each of the one or more qubits may include measuring the respective magnetization response of each of the one or more qubits to a magnetic flux bias. Determining the susceptibility of each of the one or more qubits may include, for each of the one or more qubits: generating one or more estimates of the qubit based on the one or more samples; refining the one or more estimates of the qubit; and determining the susceptibility of the qubit based on the one or more estimates of the qubit.

[0030] Refining one or more estimations of qubits may include generating an initial estimation and repeatedly generating another estimation based on at least one of the initial estimation and one or more previously generated estimations. Repeatedly generating another estimation may include generating another estimation based on a mean field model. Each another estimation may include an estimation of at least one of the current of the qubit and the magnetic flux of the qubit, and generating another estimation based on the mean field model may include generating at least one estimation based on the expected value of the current of an isolated qubit based on the magnetic flux of the qubit.

[0031] Determining the magnetic susceptibility of each of one or more qubits among a plurality of qubits may include determining the derivative of the magnetic flux-current relationship of each of the one or more qubits based on at least one of the one or more estimations. Determining the tunneling speed offset of at least one qubit may include, for each of the at least one qubit: determining a target tunneling speed at which an isolated qubit model predicts a predicted magnetic susceptibility corresponding to the magnetic susceptibility of the qubit; and determining the tunneling speed offset based on the target tunneling speed.

[0032] Determining the target tunneling speed may include determining a sample target tunneling speed for each sample and determining the target tunneling speed based on a measure of the sample target tunneling speed. Determining the target tunneling speed based on a measure of the sample target tunneling speed may include determining the average value of the sample target tunneling speed.

[0033] For each of at least one qubit, the tunneling speed offset can be determined based on the difference between the target tunneling speed of the qubit and a measure of a plurality of target tunneling speeds. The measure of the plurality of target tunneling speeds can be the median of the plurality of target tunneling speeds. For each of at least one qubit, determining the target tunneling speed can include reducing the magnitude of the target tunneling speed to less than that predicted by an isolated qubit model.

[0034] A method of operating a digital processor to tune the annealing speed of at least one qubit of a quantum processor can be summarized as including encoding a problem, which includes receiving an encoding that includes one or more qubits; modifying the encoding by representing one of the one or more qubits as a logical qubit, thereby generating a modified encoding of the problem, where the logical qubit includes a plurality of internal qubits of the quantum processor coupled by internal couplings, and the logical qubit has a reduced effective tunneling speed compared to the tunneling speed of the qubit before modification; and causing the problem to be computed by the quantum processor based on the modified encoding. The method can include selecting at least one of the number of internal qubits and the internal coupling strength of the logical qubits such that the effective tunneling speed approximates the target tunneling speed. The qubit can include an initial logical qubit. The method can further include selecting a topology in which the logical qubit affects the effective tunneling speed. Selecting this topology can include selecting this topology from a plurality of topologies based on a minimum internal coupling strength associated with each of the plurality of topologies.

[0035] This method may include modifying the effective tunneling speed of a logical qubit by determining a tunneling speed offset based on the characteristics of the logical qubit, and modifying the effective tunneling speed of the logical qubit by applying the tunneling speed offset to an annealing schedule. The logical qubit may have a chain topology, and the characteristics of the logical qubit may include the chain length. Determining the tunneling speed offset may include determining a scaling factor and scaling an offset value by the scaling factor. The offset value may be based on the following formula: 2^(k - 1) / (k - 1) Here, k is the length of the chain topology of the logical qubit. The encoding may include a multiplication circuit that embeds a factorization problem.

[0036] The characteristics may include the position of the logical qubit in the graph relative to one or more other qubits. The graph may include an embedding graph. Determining the tunneling speed offset may include determining the distance between the logical qubit and the origin and / or the distance between the logical qubit and the edge of the graph, and determining the tunneling speed offset based on this distance. The tunneling speed offset may be determined based on a gradient defined for at least a portion of the graph. The gradient may include a radial gradient having a first region close to the origin, and the annealing schedule is advanced relative to the annealing schedule in a second region. The second region is farther from the origin compared to the first region.

[0037] The effective tunneling speed of a logical qubit may be determined based on an annealing sub - schedule specific to the logical qubit and an annealing schedule defined over a plurality of qubits. At least one of the plurality of qubits is not included in the logical qubit.

[0038] Selecting a topology from a plurality of topologies based on the minimum internal coupling strength may include selecting a topology based on the correspondence between the minimum internal coupling strength and the number of internal qubits that couple to qubits outside the logical qubit.

[0039] A method for operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicably coupled to each other, the quantum processor includes a plurality of qubits, the method comprising: receiving, by the digital processor via a user interface, a pause start and a pause duration as inputs; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, including starting the quantum annealing evolution; pausing, when the pause start is reached, the quantum annealing evolution for the pause duration; and completing the quantum annealing evolution; and reading, by the hybrid computing system, states of the plurality of qubits, which may be summarized as including.

[0040] Receiving the pause start may include receiving a measure of progress through the quantum annealing evolution. Receiving the pause start and the pause duration may include receiving the pause start and the pause duration via an application programming interface. Controlling, by the digital processor, the quantum annealing evolution performed by the quantum processor may include controlling, by the digital processor, the quantum annealing evolution performed by a plurality of superconducting flux qubits.

[0041] Pausing the quantum annealing evolution for the pause duration may include selecting a subset of qubits, pausing the quantum annealing evolution with respect to one or more qubits not within the subset of qubits, and reverse annealing the subset of qubits while the one or more qubits are paused. The method may include forward annealing the subset of qubits after reverse annealing the subset of qubits and before completing the quantum annealing evolution.

[0042] A method of operating a digital processor to reduce degeneracy in a hybrid computing system including a quantum processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, and the method is operated as a sample generator for providing a sample, the method includes: transmitting a problem for calculation to the quantum processor; receiving one or more samples generated by the quantum processor based on the problem; determining a magnetic susceptibility for each of one or more qubits of the plurality of qubits based on the one or more samples; determining a tunneling speed offset for at least one qubit of the one or more qubits based on the magnetic susceptibility of the one or more qubits; and tuning the tunneling speed of the at least one qubit based on the tunneling speed offset, and can be summarized as including the above.

[0043] A method of operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer including a plurality of qubits includes: encoding a computational problem by the digital processor within a first subset of the plurality of qubits; weakly coupling a second subset having no common part with the first subset of the plurality of qubits to the first subset; determining a magnetic resonance tunneling (MRT) peak width by the qubits of the second subset; and adjusting an annealing schedule of the physical quantum annealer at least partially based on the MRT peak width, and can be summarized as including the above. Encoding a computational problem by the digital processor within a first subset of the plurality of qubits may include encoding the computational problem by the digital processor within a first plurality of superconducting qubits, and weakly coupling a second subset of the plurality of qubits to the first subset may include weakly coupling a second plurality of superconducting qubits.

[0044]

[0045] ​A method of operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer may be summarized as including: collecting one or more energy statistics by parallel tempering by the physical quantum annealer; evaluating an expected result by the digital processor; and determining, by the digital processor, a preferred annealing speed and a preferred annealing trajectory based at least in part on the one or more energy statistics and the expected result.

[0046] The method may further include repeatedly determining, by the digital processor, a preferred annealing speed and a preferred annealing trajectory based at least in part on the one or more energy statistics and the expected result until a change in the preferred annealing speed and the preferred annealing trajectory between iterations is less than a predetermined threshold.

[0047] Determining the preferred annealing speed may include inverting a cumulative distribution. Determining the preferred annealing trajectory may include performing local search. Collecting one or more energy statistics by parallel tempering by the physical quantum annealer may include collecting one or more energy statistics by parallel tempering by a superconducting quantum processor.

[0048] A method of operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor includes transmitting a computational problem to the quantum processor by the digital processor; generating one or more samples by the quantum processor; collecting the one or more samples by the digital processor; determining by the digital processor whether a qubit is floppy with respect to a sample; increasing by the digital processor a count of floppy qubits upon determining that the qubit is floppy with respect to the sample; calculating by the digital processor a metric based at least in part on the count of floppy qubits; defining by the digital processor an auxiliary qubit within the quantum processor; and coupling by the digital processor the auxiliary qubit to at least one of the floppy qubits within the quantum processor.

[0049] Transmitting a computational problem to the quantum processor may include transmitting the computational problem to a superconducting quantum processor. Transmitting the computational problem to a superconducting quantum processor may include transmitting the computational problem to a physical quantum annealer. Determining by the digital processor whether a qubit is floppy with respect to a sample may include determining by the digital processor whether a superconducting qubit is floppy. Calculating by the digital processor a metric based at least in part on the count of floppy qubits may include calculating a normalized floppiness metric that describes a portion of one or more samples for which the qubit is floppy. Coupling by the digital processor the auxiliary qubit to at least one of the floppy qubits within the quantum processor may include selecting a strength of coupling between the floppy qubit and the auxiliary qubit to adjust a tunneling amplitude of the floppy qubit.

[0050] A method of operating a hybrid computing system including a digital processor communicatively coupled to a quantum processor including a plurality of qubits includes receiving a first bias value of a first qubit of the plurality of qubits; coupling an auxiliary qubit to the first qubit; determining whether a modulus of the first bias value is less than or equal to a predetermined threshold; and if it is determined that the modulus of the first bias value is less than or equal to the predetermined threshold: providing the auxiliary qubit with a second bias value that is a negative bias value and whose modulus is greater than the modulus of the first bias value; setting a strength of the coupling between the first qubit and the auxiliary qubit to be approximately equal to the first bias value; setting a zero bias to the first qubit. It can be summarized as including the above steps.

[0051] Receiving a first bias value of a first qubit among the plurality of qubits may include receiving a bias value of a superconducting qubit. Coupling an auxiliary qubit to the first qubit may include coupling a superconducting qubit to the first qubit. Determining whether a modulus of the first bias value is less than or equal to a predetermined threshold may include determining whether the modulus of the first bias value is less than or equal to 1.

[0052] A method of operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits, the method comprising: receiving an annealing schedule by the digital processor; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, the controlling including starting the quantum annealing evolution, performing the quantum annealing evolution at least partially based on the annealing schedule, and completing the quantum annealing evolution; and reading out, by the hybrid computing system, states of the plurality of qubits, the receiving of the annealing schedule by the digital processor including receiving, for each qubit of the plurality of qubits, at least one of respective tunneling speeds or respective persistent currents as a univalent function of time.

[0053] Receiving an annealing schedule by a digital processor may include receiving a first annealing schedule for qubits of a first subset of a plurality of qubits, and receiving the first annealing schedule may include, for each qubit of the qubits of the first subset, receiving at least one of a first tunneling speed or a first persistent current as a univalent function of time, and receiving a second annealing schedule for qubits of a second subset of the plurality of qubits, and receiving the second annealing schedule may include, for each qubit of the qubits of the second subset, receiving at least one of a second tunneling speed or a second persistent current as a univalent function of time, and performing quantum evolution based at least in part on the annealing schedule may include performing quantum evolution of the qubits of the first subset based at least in part on the first annealing schedule and performing quantum evolution of the qubits of the second subset based at least in part on the second annealing schedule. In some embodiments, each of the qubits of the first and second subsets may include respective first and second logical qubits.

[0054] Receiving an annealing schedule by a digital processor may include receiving a vector as a univalent function of time. Receiving an annealing schedule by a digital processor may include receiving transverse and longitudinal energy scales as a univalent function of time. Receiving an annealing schedule by a digital processor may include receiving a piecewise linear annealing schedule.

[0055] A method of operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits and a plurality of coupling devices, and each of the plurality of coupling devices selectively communicatively couples a pair of qubits. The method includes receiving an annealing schedule by the digital processor; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, including starting the quantum annealing evolution, performing the quantum annealing evolution based at least in part on the annealing schedule, and completing the quantum annealing evolution. And control; reading out the states of a plurality of qubits by the hybrid computing system, wherein receiving an annealing schedule by the digital processor includes receiving, for each qubit of the plurality of qubits, a respective local bias as a univariate function of time and receiving, for each coupling device of the plurality of coupling devices, a respective coupling strength as a univariate function of time. The reading out can be summarized as including this.

[0056] A method of selecting an annealing schedule for a problem in a hybrid computing system including a quantum processor and a digital processor. The quantum processor and the digital processor are communicatively coupled to each other. The quantum processor includes a plurality of qubits. The method can be summarized as including generating one or more annealing schedules; receiving an input annealing schedule and selecting an annealing schedule from the one or more annealing schedules based on an objective function that provides a measure of at least one characteristic of the input annealing schedule; transmitting the problem to the quantum processor by the digital processor; and executing the problem in the quantum processor according to the annealing schedule.

[0057] This method may include selecting an objective function from a set of one or more objective functions. Generating one or more annealing schedules may include performing an optimization algorithm based on the objective function. The optimization algorithm may include parallel tempering. The objective function may measure at least one of a model generated by applying parallel tempering to a problem modified by an input annealing schedule and a chain linking the models. The objective function may include calculating at most a threshold number of parallel tempering iterations. The threshold number may be less than the number of iterations for solving the problem.

[0058] The optimization algorithm may include Bayesian optimization. The objective function may measure the ground state distribution of the problem according to an input annealing schedule. The objective function may provide at least one of a measure of similarity between ground state distributions and characteristics of one or more outliers of the ground state distribution. The objective function may measure the entropy of the ground state distribution, the distance of the ground state distribution from a uniform distribution by a distance metric, the Gini coefficient of the ground state distribution, and / or the ratio of the maximum probability to the minimum probability of the ground state distribution.

[0059] Selecting an annealing schedule from one or more annealing schedules may include determining that the annealing schedule provides an optimal result compared to one or more annealing schedules. Generating one or more annealing schedules may include generating a plurality of annealing schedules, selecting a tentative annealing schedule based on the objective function, and generating one or more annealing schedules based on the tentative annealing schedule.

[0060] A method for reducing sample bias in a hybrid computing system including an analog processor and a digital processor, wherein the analog processor and the digital processor are communicatively coupled to each other and the analog processor includes a plurality of qubits, the method comprising: transmitting a computational problem to the analog processor by the digital processor; generating, by the analog processor, a first set of one or more samples; collecting, by the digital processor, the first set of one or more samples; identifying, based on the first set of one or more samples, one or more valleys, each valley including a set of equal-energy samples; selecting one valley of the one or more valleys based on valley selection criteria; for each qubit within a valley: determining a degeneracy metric of the qubit; determining an annealing schedule of the qubit based on the degeneracy metric; and collecting, by the analog processor, a second set of one or more samples based on the annealing schedule of the qubits within the valley.

[0061] Identifying one or more valleys may include determining that a plurality of qubits are related by a series of equal-energy qubit flips. Identifying one or more valleys may include determining the membership of a plurality of qubits based on an equal-energy Hamming distance metric. Selecting one valley from the one or more valleys may include selecting, based on the number of samples of one or more samples within a valley, a valley having at least as many samples as each of the other valleys of the one or more valleys. The degeneracy metric may include a normalized floppiness metric. Determining the degeneracy metric of a qubit may include determining the normalized floppiness metric of the qubit based on the number of times the qubit was floppy within the samples of the valley.

[0062] Determining an annealing schedule for a qubit based on a degeneracy metric may include determining that an annealing offset is proportional to the degeneracy metric. Determining an annealing schedule for a qubit based on a degeneracy metric may include advancing the qubit to the start of an anneal. Advancing the qubit to the start of an anneal may include delaying at least one other qubit such that after the qubit completes its anneal, at least one other qubit starts to anneal. Determining an annealing schedule for a qubit based on a degeneracy metric may include delaying the qubit until the end of an anneal. At least one qubit of a valley may include a region of qubits.

[0063] The method of claim 101 may include identifying one or more other valleys, each including a set of equal energy samples, based on a second set of one or more samples; selecting another valley of the one or more other valleys based on a valley selection criterion; and for each qubit in the another valley: determining another degeneracy metric for the qubit; determining another annealing schedule for the qubit based on the degeneracy metric; and collecting, by an analog processor, a third set of one or more samples based on the another annealing schedule for the qubit in the another valley.

[0064] Determining an annealing schedule for a qubit based on a degeneracy metric may include generating a plurality of annealing schedules and selecting one annealing schedule from the plurality of annealing schedules based on one or more selection criteria. Generating a plurality of annealing schedules may include generating a first annealing schedule and generating a plurality of scaled annealing schedules based on a plurality of scaling factors.

[0065] A method for controllably simulating noise in an annealing schedule used in a hybrid computing system, the hybrid computing system including an analog processor and a digital processor, the analog processor and the digital processor communicatively coupled to each other, the method comprising: receiving an input annealing schedule at the digital processor; generating pseudo-noise; modifying the input annealing schedule based on the pseudo-noise to generate an output annealing schedule; and providing the output annealing schedule to the analog processor, may be summarized as including.

[0066] Generating pseudo-noise may include pseudo-randomly generating one or more modifications to be applied to the input annealing schedule. Generating pseudo-noise may include generating one or more annealing pauses and one or more annealing ramps. The one or more annealing pauses and ramps may be ordered as alternating pairs of pauses and ramps.

[0067] Generating pseudo-noise may include adding one or more modifications to the pseudo-noise based on one or more constraints. The one or more constraints may include requiring that the output annealing schedule deviate from the input annealing schedule by no more than a threshold amount. The threshold amount may vary over time and may be based on the time-dependent amplitude of the input annealing schedule. The threshold amount may be a predetermined constant. Adding one or more modifications may include, for each modification, pseudo-randomly determining at least one of the amplitude of the modification and the duration of the modification according to one or more constraints.

[0068] Brief Description of the Drawings In the accompanying drawings, the same reference numerals identify similar elements or acts. The dimensions and relative positions of the elements in the accompanying drawings are not necessarily drawn to scale. For example, the shapes and angles of various elements are not necessarily drawn to scale, and some of these elements are arbitrarily enlarged and arranged to improve the readability of the drawings. Further, a particular shape of a drawn element is not necessarily intended to convey any information regarding the actual shape of the particular element, and is selected for ease of recognition in the accompanying drawings.

Brief Description of the Drawings

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Figure 20

Figure 21

Figure 22

Best Mode for Carrying Out the Invention

[0070] General Comments In the following description, some specific details are included for a complete understanding of various disclosed embodiments. However, those skilled in the art will recognize that the embodiments can be practiced without one or more of these specific details, or with other methods, components, materials, etc. In other instances, well-known structures related to quantum processors, such as quantum devices, couplers, and control systems including microprocessors and drive circuits, have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments of the present method. Throughout this specification and the appended claims, the terms "element" and "group of elements" are used to include, without limitation, all such structures, systems, and devices related to quantum processors, and the programmable parameters associated therewith.

[0071] Unless the context requires otherwise, throughout the following specification and the claims, the term "comprising" and its variations are to be construed in an open, inclusive sense, i.e., as "including, but not limited to."

[0072] References throughout this specification to "one embodiment," "an embodiment," "another embodiment," "an example," "an example," "another example," etc., mean that a particular reference feature, structure, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "in another embodiment," etc., at various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments, examples, or implementations.

[0073] As used in this specification and the appended claims, it should be noted that the singular forms of articles and indefinite articles include plural referents unless the context clearly dictates otherwise. Thus, for example, a reference to a problem-solving system that includes a "quantum processor" includes a single quantum processor or two or more quantum processors. It should also be noted that the term "or" is generally used in the sense of "and / or" unless the context clearly dictates otherwise.

[0074] The subtitles described in this specification are for convenience only and do not interpret the scope or meaning of the embodiments.

[0075] Tunneling Speed and Degeneracy At least some quantum processors utilize the tunneling behavior of qubits to find low-energy states of problems encoded on the processor. The tunneling behavior can be described for each qubit via a single qubit tunneling splitting parameter, denoted by Δ i (also referred to as the "tunneling speed" or "annealing speed" of the qubit). The tunneling speed Δ i typically decreases over the course of annealing and reaches a low value at which the qubit is highly resistant to changing its state during the course of evolution and thus ceases to interact with the problem. This behavior is called "freezing," and the frozen qubits can be considered effectively fixed for the remainder of the evolution.

[0076] Various qubits can freeze at various times, and individual qubits can exhibit various tunneling behaviors in various problems. Typically, qubits with a slow tunneling speed Δ i freeze earlier in evolution than qubits with a relatively fast tunneling speed Δ i ​​Freeze. If various qubits in the same problem have various tunneling speeds, the same problem tends to exhibit degeneracy-related behavior that reduces the optimality of the generated solutions. Such behavior may include, for example, small-gap avoided level crossings and / or Landau-Zener transitions.

[0077] The techniques described in this application are methods that can reduce degeneracy by tuning the tunneling speed either directly or indirectly. Such methods can, in favorable circumstances, significantly enhance the hardware performance for problems vulnerable to degeneracy and / or improve the hardware performance for a larger set of general problems.

[0078] Impact of Degeneracy on Hardware Performance In low-precision problem sets, experiments have shown a strong dependence of hardware performance on the qubit-level parity (i.e., the number of active couplers per qubit). In particular, for large-population low-precision problem sets, even at the C2 scale, the performance data can exhibit "fat tails." The phrase "fat tails" refers to A particularly difficult subset of low-precision problem sets. Fat tails can include problem instances that generate low-energy solutions at a low speed and / or problems that cannot generate low-energy solutions.

[0079] The behavior of problem sets in fat tails appears to be strongly related to degeneracy. Specifically, problems with a low-degeneracy ground state and a highly degenerate first excited state appear to be at least partially responsible for the fat tails.

[0080] One approach is to reduce the problem energy scale of difficult problems. For C2 and C4 Regarding scale problems, by reducing the energy scale of the applied J by a factor of 2× to 5×, the hardware performance for difficult problems can be improved.

[0081] Unfortunately, reducing the problem energy scale of a difficult problem can have adverse effects. For example, reducing the energy scale can increase the effect of analog control errors, some of which do not scale down with the problem scale. Reducing the energy scale can also increase the effective temperature of the bath to which the qubits are coupled. Such effects can reduce the hardware performance at a certain processor scale. Further, reducing the energy scale can reduce the desired quantum behavior.

[0082] At least some embodiments of the techniques described in this application provide a technique that can significantly enhance the hardware performance for fat-tail problems and can also improve the hardware performance for a more general set of problem sets.

[0083] Reduction of degeneracy via "floppy qubits" A "floppy qubit" is a qubit whose state can be reversed without any change in energy. Similarly, a floppy region is a set of a plurality of coupled qubits that can all be reversed simultaneously or at the same time without a change in energy. In the following specification, the term "floppy qubit" includes floppy qubits or floppy regions unless the context indicates otherwise.

[0084] For some problem instances, such as "fat tail" problem instances, there can be large equal-energy clusters of excited states that differ from each other by only a few qubit flips (e.g., 1-qubit flip or 2-qubit flip). Qubits responsible for the movement around such equal-energy clusters are called "floppy" qubits. The techniques described in this application use a local major bias digital-to-analog converter (DAC) to advance (or retard) floppy qubits relative to the rest of the working graph during quantum annealing. In one embodiment, the local major bias DAC can bias a qubit compound-compound Josephson junction (CCJJ) main loop.

[0085] Figures 1A and 1B are flowcharts showing an exemplary method 100 of operation of a hybrid computing system including a quantum processor for reducing degeneracy by the present system, device, article, and method. Figure 1A is a flowchart showing a first portion 100a of the exemplary method 100, and Figure 1B is a flowchart showing a second portion 100b of the exemplary method 100. Control of the method 100 can move from the first portion 100a to the second portion 100b and vice versa.

[0086] The operation method 100 shown by Figures 1A and 1B includes a plurality of acts. One or more of these acts can be performed by (or via) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers including both digital processors and analog processors. For the purposes of the description of Figures 1A and 1B, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The first portion 100a and the second portion 100b of the method 100 are exemplary, and those skilled in the art will recognize that alternative embodiments may omit some acts and / or include additional acts.

[0087] Referring first to FIG. 1A, the first part 100a of method 100 starts at 105, for example, in response to a problem submission or in response to a call by another routine. At 110, the hybrid computer sends the problem to the hardware. For the purposes of this example, the hardware is a quantum processor communicatively coupled to a digital computer. At 115, the hybrid computer collects a number of samples. In some embodiments, the number of samples N is about 1000. In other embodiments, the number of samples N is 10. In acts 120 - 145 (including 120 and 145), the hybrid computer records for each of the N samples which of the M qubits in the quantum processor are floppy. At 120, the hybrid computer initializes a sample index, and at 125, the hybrid computer initializes a qubit index.

[0088] At 130, the hybrid computer determines whether a qubit or region of qubits is floppy (i.e., whether the state of the qubit or region of qubits can be inverted without changing energy). In response to determining at 130 that a qubit or region of qubits is floppy ("yes"), control in the first part 100a proceeds to 135, where the floppy qubit or region of floppy qubits is recorded. In response to determining at 130 that a qubit or region of qubits is not floppy ("no"), control in the first part 100a proceeds to 140.

[0089]

[0090] ​At 140, the hybrid computer determines whether there is another qubit or region of qubits to check for floppiness. In response to determining at 140 that there is another qubit (``yes''), control in the first portion 100a returns to 130. The loop from 130 to 145 is repeated until there are no longer qubits or regions of qubits to check for floppiness.

[0091] This process can repeat while there are additional qubits or regions of qubits for which to check floppiness. In response to determining at 140 that there are no longer qubits or regions of qubits for which to check floppiness (``no''), control in the first portion 100a moves to 145, where the hybrid computer checks whether there is another sample. In response to determining at 145 that there is another sample (``yes''), control in the first portion 100a returns to 125. The loop from 125 to 145 is repeated until there are no longer samples.

[0092] In response to determining at 145 that there are no longer samples (``no''), control of method 100 proceeds to the second portion 100b of FIG. 1B.

[0093] At 150, the hybrid computer initializes a qubit index. At 155, the hybrid computer calculates a normalized floppiness metric for the current qubit or current region of qubits. An exemplary definition of the normalized floppiness metric μ i for the i-th qubit is as follows: [Number] where n i is the number of samples for which the i-th qubit or region of qubits was floppy is a number, and N is the total number of samples. Other suitable definitions of the normalized floppiness metric can be utilized. In some embodiments, the floppiness metric can be unnormalized.

[0094] At 160, the hybrid computer advances the current qubit or region of qubits during quantum annealing based on the normalized floppiness metric. Advancing a qubit (or region of qubits) can be done in any of several ways, as described in more detail elsewhere in this specification. As an example, in some embodiments, advancing a qubit or region of qubits includes adding an offset proportional to the normalized floppiness metric to the main loop (anneal) DAC. If it is a region of qubits, the offset is applied to all member qubits of the region of qubits. In an exemplary embodiment where the qubit is a flux qubit, the offset is μ i × equal to 2.5mΦ0.

[0095] At 165, the hybrid computer determines whether there is another qubit or region of qubits to which the offset should be applied. In response to determining that there is another qubit or region of qubits at 165 (“yes”), the control in the second portion 100b returns to 155. The loop from 155 to 165 is repeated until there is no longer a qubit or region of qubits to which the offset should be applied.

[0096] In response to determining that there are no longer qubits or regions of qubits at 165 ( "no"), the control of the second portion 100b moves to 170. At 170, the hybrid computer determines whether an end determination criterion has been satisfied. The end determination criterion can be a single criterion or a combination of two or more criteria. Exemplary criteria can include thresholds based on sample diversity, sample energy, degree or rate of convergence, and the number of unique ground states or first excited states. Exemplary criteria can also include thresholds based on computation time and number of repetitions.

[0097] In response to determining that the end determination criterion has been satisfied ( "yes") at 170, method 100 ends at 175. In response to determining that the end determination criterion has not been satisfied ( "no") at 170, the control of method 100 returns to 115 of the first portion 100a of FIG. 1A.

[0098] In some embodiments, the hybrid computer progresses only a subset of the floppy qubits. Generally, qubits or regions of qubits become floppy in a certain percentage of the samples drawn, rarely become floppy in any sample, or rarely become floppy in all samples. The floppiness metric (described above) can be used to determine which qubits or regions of qubits are floppy and which qubits should be progressed. In some embodiments, qubits or regions of qubits that exceed a threshold regarding the floppiness metric can be progressed. In other embodiments, other criteria themselves may be used, or used in combination with the floppiness metric, to determine which qubits or regions of qubits should be progressed.

[0099] In some embodiments, the hybrid computer may employ an iterative approach in which qubits or regions of qubits are advanced and repeated within a small subset. In some embodiments, the hybrid computer may choose to advance only the most floppy qubits or regions of qubits in each iteration. In other embodiments, the hybrid computer may execute a suitable combination of the foregoing embodiments to advance qubits or regions of qubits. The benefit of advancing and repeating a small number of qubits or regions of qubits is that the method may reduce overcorrection.

[0100] In some embodiments, the offset applied to each qubit or each region of qubits may be the same. In other embodiments, the offset applied to various qubits or various regions of qubits may vary from qubit to qubit. For example, the hybrid computer may choose to apply a large offset to one qubit or one region of qubits rather than to another qubit or another region of qubits. region may vary from qubit to qubit. For example, the hybrid computer may choose to apply a large offset to one qubit or one region of qubits rather than to another qubit or another region of qubits.

[0101] Reduction of degeneracy via magnetic susceptibility In some embodiments, the qubits are quantities based on the magnetic susceptibility (represented by χ and sometimes simply referred to as "susceptibility" herein) of the qubits It can be advanced or delayed during sub-annealing. The magnetic susceptibility χ is a characteristic of some types of qubits (including flux qubits) that describes the degree of magnetization of a qubit in response to an applied magnetic field. This response can vary in various situations (e.g., depending on the strength and topology of its coupling to other qubits and the flux bias of other qubits). Thus, the magnetic susceptibility χ of a qubit can be different for different problems. In some embodiments, the magnetic susceptibility χ of one or more qubits of a particular problem is measured and / or inferred, and at least one of the one or more qubits is advanced or delayed based on its magnetic susceptibility χ. For convenience, references in this disclosure to "determining" the magnetic susceptibility include measuring the magnetic susceptibility and / or inferring the magnetic susceptibility.

[0102] The inventors have determined through experiments that the magnetic susceptibility χ of a qubit is inversely i correlated with the tunneling speed Δ of that qubit. That is, qubits that freeze earlier during evolution (i.e., qubits that reach a low Δ i quickly) tend to have a high magnetic susceptibility χ, and qubits that freeze later during evolution (i.e., qubits that reach a low Δ slowly) tend to have a relatively low magnetic susceptibility χ. i slowly) tend to have a relatively low magnetic susceptibility χ. bit) tend to have a relatively low magnetic susceptibility χ.

[0103] FIG. 2 is an exemplary method for tuning the tunneling speed Δ i of one or more qubits It is a flowchart showing 200. The method 200 shown in FIG. 2 includes a plurality of actions. One or more of these actions can be performed by (or via) one or more circuits including, for example, one or more processors (such as digital processors), analog processors such as quantum processors, or hybrid computers including both digital processors and analog processors. For the purpose of the description of FIG. 2, it is assumed that the actions are performed by a hybrid computer including a quantum processor. The method 200 is exemplary. Those skilled in the art will recognize that alternative embodiments may omit some actions and / or include additional actions.

[0104] In 202, the problem is received by the hybrid computer and encoded on the quantum processor. In 204, the hybrid computer collects one or more samples based on the encoded problem. The hybrid computer can collect any number of samples depending on the requirements of various other actions of method 200 (e.g., depending on the number of samples required to determine the magnetic susceptibility of one or more qubits in 206). For example, in some embodiments, the number of samples collected is 1. As another example, in other embodiments, the number of samples collected is 1000.

[0105] In 206, the magnetic susceptibility χ of one or more qubits is determined by the hybrid computer. Various techniques can be taken to determine the magnetic susceptibility χ for each qubit. For example, the magnetic susceptibility χ of each qubit can be measured by directly measuring the magnetization response of each qubit to the magnetic flux bias. As another example, the magnetic susceptibility χ of each qubit can be inferred based on numerical methods applied to one or more samples (and / or other data). Some techniques for determining the respective magnetic susceptibility χ of one or more qubits are discussed in more detail below, but those skilled in the art will understand that other techniques can be alternatively or additionally utilized.

[0106] In some embodiments, the magnetic susceptibility χ is measured directly. This can be done in situ, for example, by instructing a quantum processor to perform a first set of evolutions of the problem while varying the flux bias Φ of one or more qubits X and then performing a second set of evolutions of the problem where the flux bias is varied . Next, the resulting difference in the magnetization response of one or more qubits between the first and second sets can be measured to determine the magnetic susceptibility χ of each of the one or more qubits. For example, the magnetic susceptibility χ can be proportional to the change in the persistent current I X with respect to the change in the flux bias Φ P between the evolutions of the first and second sets. Here, each of the evolutions of the first and second sets includes a plurality of evolutions, thereby providing a plurality of sample measurement results, and the average value (or other estimator) of the persistent current I P and / or the flux bias Φ X can be used. For example, the magnetic susceptibility χ of a qubit can be determined based on the following equation : where is the average value of all the persistent current measurements of the qubit in the evolution of the first set, is the average value of all the persistent current measurements of the qubit in the evolution of the second set, is the flux bias applied to the qubit in the evolution of the first set, is the flux bias applied to the qubit in the evolution of the second set.

[0107] The flux bias Φ of the qubit​​​​​X Modifying X corrects problems during computation, so evolving or modifying fewer qubits is likely to provide results that more accurately describe the original problem. In some embodiments, only the flux bias Φ of a single qubit is changed in each set of evolutions, and thus multiple sets of evolutions (and thus more time) are required to determine the magnetic susceptibility χ of multiple qubits. In some embodiments, a group of flux biases {Φ} of multiple qubits is changed in a given evolution, thereby reducing the number of sets of evolutions required (however, in some cases, losing accuracy compared to single qubit measurements). In some embodiments, a global flux bias Φ is uniformly applied to all qubits of the processor in a second set of evolutions. Modifying X corrects problems during computation, so evolving or modifying fewer qubits is likely to provide results that more accurately describe the original problem. In some embodiments, only the flux bias Φ of a single qubit is changed in each set of evolutions, and thus multiple sets of evolutions (and thus more time) are required to determine the magnetic susceptibility χ of multiple qubits. In some embodiments, a group of flux biases {Φ} of multiple qubits is changed in a given evolution, thereby reducing the number of sets of evolutions required (however, in some cases, losing accuracy compared to single qubit measurements). In some embodiments, a global flux bias Φ is uniformly applied to all qubits of the processor in a second set of evolutions. X In some embodiments, only the flux bias Φ of a single qubit is changed in each set of evolutions, and thus multiple sets of evolutions (and thus more time) are required to determine the magnetic susceptibility χ of multiple qubits. In some embodiments, a group of flux biases {Φ} of multiple qubits is changed in a given evolution, thereby reducing the number of sets of evolutions required (however, in some cases, losing accuracy compared to single qubit measurements). In some embodiments, a global flux bias Φ is uniformly applied to all qubits of the processor in a second set of evolutions. X} is changed in a given evolution, thereby reducing the number of sets of evolutions required (however, in some cases, losing accuracy compared to single qubit measurements). In some embodiments, a global flux bias Φ is uniformly applied to all qubits of the processor in a second set of evolutions. In some embodiments, a global flux bias Φ is uniformly applied to all qubits of the processor in a second set of evolutions.

[0108] The first and second sets of evolutions may be performed in any order or optionally interleaved (e.g., the second set of evolutions occurs during the first set of evolutions and / or vice versa). In some embodiments, each of the first and / or second sets of evolutions includes a single evolution. In some embodiments, each of the first and / or second sets of evolutions includes multiple evolutions. The first and second sets of evolutions may include a different number of evolutions.

[0109] In some embodiments, the magnetic susceptibility χ is inferred, for example, via post - processing techniques. For example, in some embodiments, the magnetic susceptibility χ of one or more qubits is inferred via a mean field method (e.g., via some embodiments of the magnetic susceptibility estimation method of FIG. 5). .

[0110] In 208, a subset D of one or more qubits is optionally identified for tuning. Such a subset D, for example, has a threshold amount T with respect to a target magnetic susceptibility χ T from the target magnetic susceptibility χ It may include each of one or more qubits having different magnetic susceptibilities χ across. That is, qubit X having magnetic susceptibility χ may be included in subset D if the following inequality is satisfied. |χ - χ T | > T

[0111] In some embodiments, the target magnetic susceptibility χ T is based on the magnetic susceptibilities χ of one or more qubits . For example, the target magnetic susceptibility χ T may be determined to be the average value, median value, or most frequent value of the magnetic susceptibilities χ of one or more qubits. T may be a predetermined and / or user-provided value. Alternatively or in addition, T may be determined based on the magnetic susceptibilities χ of one or more qubits and / or the target magnetic susceptibility χ T . For example, T may be a certain percentage of the target magnetic susceptibility χ T (e.g., 0.1χ T , 0.5χ T , 1.0χ T or any other suitable value).

[0112] As another example, subset D may be determined by identifying N qubits having the most extreme magnetic susceptibility χ (e.g., N qubits for which |χ - χ T | is maximized, where N is a positive integer).

[0113] In some embodiments, only the qubits to be advanced are included in subset D. In some embodiments, only the qubits to be retarded are included in subset D.

[0114] At 210, a Δ tuning offset ω is determined for each qubit in D. This offset can be determined in various ways and may depend at least in part on the approach taken at 212 to tune Δ i for each qubit. In some embodiments, the qubits are tuned to have approximately equivalent tunneling speeds Δ i and then ​As a result, the qubits are almost simultaneously frozen (such qubits are said to be "synchronized"). In some embodiments, the Δ tuning offset ω of a particular qubit X is based on the normalized difference between the susceptibility χ of qubit X and a threshold susceptibility χ T and is determined. For example, the Δ tuning offset ω can be determined according to the following formula.

Equation

[0115] In 212, the tunneling speed Δ for each qubit in subset D i is tuned according to the associated Δ tuning offset ω of the qubit. As discussed elsewhere in this specification, for example, by correcting the DAC offset for the compound - compound Josephson junctions (CCJJs) of the qubit, by forming logical qubits, etc., there are various ways to tune Δ . In some embodiments, the tunneling speed Δ for each qubit in subset D is scaled in proportion to the Δ tuning offset ω. i For example, an offset ω = 0.2 can correspond to an increase of about 20% in the Δ of the qubit (thus slowing down the annealing speed of the qubit and delaying freezing), while an offset ω = 0.1 can correspond to an increase of about 10% in the Δ i of the qubit (thus accelerating the annealing speed of the qubit and accelerating freezing). For example, each qubit in subset D can be given a new Δ i by the following formula: That is, an offset ω = 0.2 can correspond to an increase of about 20% in the Δ of the qubit (thus slowing down the annealing speed of the qubit and delaying freezing), while an offset ω = 0.1 can correspond to an increase of about 10% in the Δ of the qubit (thus accelerating the annealing i speed of the qubit and accelerating freezing). For example, each qubit in subset D can be given a new Δ by the following formula: For the new Δ i given by: Δ new =(1 + ω)Δ old Here, Δ oldis the Δ of the qubit prior to Δ tuning i and Δ new is the Δ tuning of the qubit after i it.

[0116] Figure 3 shows a chart depicting an exemplary Δ tuning scenario. The vertical axis corresponds to the instantaneous tunneling speed Δ of a given qubit. The horizontal axis corresponds to time, and in particular, to the progress in the evolution (represented in s). Line 302 corresponds to the tunneling speed of an exemplary qubit (not shown), and point 304 represents the initial tunneling speed Δ i of the qubit. Line 31 0 corresponds to a scenario where the evolution of the exemplary qubit is delayed by applying an offset 312 (which can be represented, for example, by a positive number), resulting in an initial tunneling speed Δ i at point 314. Line 320 corresponds to a scenario where the evolution of the exemplary qubit is advanced by applying an offset 322 (for example , which can be represented by a negative number), resulting in an initial tunneling speed Δ i at point 324. In the scenario of line 310, the evolution of the qubit freezes later than it could have originally frozen (i.e., in the pre-Δ tuning scenario corresponding to line 302). In the scenario of line 320, the evolution of the qubit freezes earlier than it could have originally frozen.

[0117] Returning to Figure 2, at 214, the hybrid computer performs the calculation of the problem (which may have been modified by the Δ tuning operation of 212) and determines the solution.

[0118] Estimation of magnetic susceptibility In some embodiments, the susceptibility of a qubit is inferred by using a model for inferring one or more characteristics of the qubit and estimating the susceptibility of the qubit based on those characteristics. Such an estimation of susceptibility can be used, for example, in 206 of method 200. As will be discussed in more detail below, models that can be used in such an estimation include, but are not limited to, mean field models.

[0119] FIG. 5 is a flowchart illustrating an exemplary susceptibility determination method 500. At 502, a sample

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[0120] At 504, an initial estimate or speculation regarding one or more characteristics of a qubit is generated based on a sample

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[0121] ​ At 505, the initial estimate is refined to generate a refined estimate by circuitry. For example,

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[0122] In some embodiments, the estimation can be refined by utilizing an explicit relationship between the magnetic flux Φ applied to a superconducting quantum processor and the induced current I flowing within the device. For example, for at least some superconducting quantum processors, the equilibrium state of the processor can be the following set of coupled equations: For example, for at least some superconducting quantum processors, the equilibrium state of the processor can be the following set of coupled equations:

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[0123] In some embodiments,

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[0124] In some embodiments,

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[0125] In some embodiments,

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[0126] In some embodiments,

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[0127] Based on the above, the inventors made the following judgment. In such an embodiment, the expected value of the permanent current of the isolated qubit (<I p ) can be determined based on the following formula: [Number] Here, k B is the Boltzmann constant. Therefore, the estimation [Number] The element I i can be generated by the circuit system by calculating according to the following formula: [Number] Here, Φ i is [Number] The i-th element of.

[0128] In some embodiments, the temperature T is modeled with the restriction that it is close to zero. This can be achieved, for example, by omitting the tanh term from the above equation. The temperature may be considered separately (e.g., via subsequent adjustment steps), or may not be considered at all.

[0129] In some embodiments,

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[0130] The magnetic susceptibility

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[0131] In 506, the inferred problem magnetic susceptibility

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[0132] In some embodiments, the inferred problem magnetic susceptibility

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[0133] The inferred problem susceptibility of a specific qubit

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[0134] To understand the above relationship, it may be helpful to consider one possible differentiation. Refined estimation

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[0135] In some embodiments, method 500 may output the inferred susceptibilities generated as described above, and method 500 may end. In some embodiments, method 500 may repeat acts 502-506 to generate multiple inferred susceptibilities for each qubit by the circuitry. The multiple inferences may be combined by the circuitry to generate a combined inference

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[0136] At 508, the target tunneling speed for each qubit j

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[0137] Since the magnetic susceptibility can vary according to the magnetic flux / current (a related property as pointed out above), the isolated qubit model can also be based on the magnetic flux and / or current. For example, the value of Δ j can be determined according to the following equation: where Φ

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[0138] Tunneling speed

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[0139] Optionally, at 510, acts 502 - 508 are (e.g., based on another sample received from hardware) the tunneling speed

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[0140] Tunneling speed

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[0141] iAdjustment (e.g., Δ tuning -ning offset) is based on one or more target tunneling speeds

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[0142] In some embodiments, the Δ tuning offset ω j is determined based on the statistical characteristics of multiple target tunneling speeds

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[0143] is used (i.e., an offset having a reduced magnitude compared to the above). In some situations, such a reduction can help compensate for the non-linearity and dispersion effects encountered when adjusting Δ j For example when adjusting Δ j such a reduction can help compensate for the non-linearity and dispersion effects encountered when adjusting Δ. For example the offset ω j is determined as described above and can then be reduced by a constant factor (e.g., ω jcan be halved), can be exponentially reduced and / or can be reduced in other ways. It can be reduced.

[0144] Optionally, method 500 can repeatedly iterate acts 502-514 at 51 j based on the offset ω generated at 514. In some embodiments, after the quantum bit tunneling speed is adjusted based on the offset ω, another hardware sample is received. In some embodiments, another hardware sample is not necessarily received at 502. Instead (or additionally), a modified sample can be generated based on a model that relates the previously received hardware sample at 502, the offset ω, j the change in the tunneling speed Δ, and the change in the sample. j Thus, subsequent iterations of method 500 executed by the circuit based on the offset ω may be fully based on, partially based on, or not at all based on another hardware sample. j Another iteration may include further homogenization at 514, thereby refining the offset ω over multiple iterations.

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[0145] Another repetition may include further homogenization at 514, thereby refining the offset ω over multiple repetitions. j At 518, the offset ω is output by the circuit. Such output can, for example, adjust the tunneling speed Δ of one or more quantum bits based on the offset ω as described elsewhere in this specification, return the offset ω in software,

[0146] or transmit the offset ω via a communication link. j For example, as described elsewhere in this specification, adjust the tunneling speed Δ of one or more quantum bits based on the offset ω, return the offset ω in software, or transmit the offset ω via a communication link. j Adjust the tunneling speed Δ of one or more quantum bits based on the offset ω, return the offset ω in software, j or transmit the offset ω via a communication link. j Return the offset ω in software, or transmit the offset ω via a communication link.j Transmitting, offset ω j Displaying to the user, and / or otherwise offset ω j Providing to hardware and / or software Interface, may include.

[0147] Reduction of degeneracy through in-evolution measurement In some embodiments, the state of the qubit is measured during evolution prior to completion. Such measurements can provide information regarding the time-dependent quantum annealing dynamics characteristics over the course of evolution (e.g., approximate freezing time, correlation of the state as a function of time, and / or other information). Such information can be used to manipulate the annealing process (e.g.,) via Δ tuning. In some embodiments, the flux detector is used to measure the expected value of one or more qubits one or more times during evolution, and the measurement result of the flux detector is Used to tune one or more Δ of one or more qubits. i

[0148] FIG. 4 is an exemplary method for tuning the tunneling speed Δ of one or more qubits i 400 is a flowchart showing. The method 400 shown in FIG. 4 includes a plurality of acts. One or more of these acts can be performed by (or via) one or more circuits including, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers including both digital and analog processors. For the purpose of the description of FIG. 4, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 400 is exemplary, and those skilled in the art will recognize that alternative embodiments may omit some acts and / or include additional acts.

[0149] ​At 402, the problem is received by a hybrid computer and encoded on a quantum processor. At 404, the hybrid computer couples a flux detector to a qubit (referred to herein as a "problem qubit"). The problem qubit can be an individual hardware qubit or a logical qubit comprising a plurality of hardware qubits. Method 400 can include any number of flux detectors and problem qubits. Although the present disclosure generally refers to "problem qubits" and "flux detectors", it is understood that multiple flux detectors and problem qubits can be measured and / or tuned together and / or sequentially according to method 400.

[0150] The flux detector can be any quantum flux parameter that can be annealed separately from the problem qubit. For example, the flux detector can include a qubit adjacent to the problem qubit (i.e., sharing a coupler). As another example, the flux detector can be a calibration device provided by the processor and configured to measure the problem qubit. The strength J of the coupling between the flux detector and the problem qubit can be problem-dependent. Generally, the coupling strength J should be strong enough to reliably replicate the qubit state to the flux detector, but weak enough not to disturb the dynamic characteristics of the problem qubit. Determining the appropriate strength will depend in part on the coupling of the problem qubit to other qubits.

[0151] At 406, the quantum processor initiates an evolution that includes annealing the problem qubit and the flux detector. In some embodiments, the problem qubit and the flux detector initiate annealing substantially simultaneously. In some embodiments, the flux detector initiates annealing after the problem qubit has initiated annealing.

[0152] At 408, the flux detector is annealed more rapidly compared to the problem qubit. This can be done, for example, via any suitable method described herein or, alternatively, via a known method (current or future method) such that the flux detector has a low tunneling rate Δ i to have which can be accomplished by configuring it so. Thus, the flux detector completes its annealing process before the evolution is complete and, in some cases, before the problem qubit freezes. By the end of the annealing of the flux detector, the expected value of the state of the problem qubit over the course of the annealing of the flux detector is replicated to the flux detector.

[0153] At 410, the state of the flux detector is read out. In some embodiments, the state of the flux detector is stored in a buffer and multiple states are read out together.

[0154] At 412, the hybrid computer determines whether another measurement of the problem qubit should be made. In some embodiments, the hybrid computer continues to measure the problem qubit until the evolution is complete. In some embodiments, the hybrid computer makes a predetermined number of measurements and then ceases to make such measurements. In some embodiments, the hybrid computer ceases to measure the problem qubit after determining that the problem qubit has frozen (e.g., based on measurement information read from the flux detector). In some embodiments, the hybrid computer ceases to measure various problem qubits at various times.

[0155] If the hybrid computer determines that another measurement should be made, method 400 returns to 408. The hybrid computer may optionally incorporate delays at 412 and / or 408 such that a predetermined amount of time elapses between measurements. The hybrid computer may return to 408 one or more times over the course of the evolution to obtain measurement results of the problem qubit at various times during the evolution.

[0156] If the hybrid computer determines that further measurements of the problem qubits should no longer be made during this evolution, the hybrid computer continues to proceed to 414. At 414, the quantum processor completes the evolution.

[0157] At 416, the information read from the flux detector at 410 is processed to determine (at least approximately) information regarding the behavior of the problem qubits during evolution. For example, the estimated freezing time of a problem qubit can be determined by observing the estimated time at which the expected value of the qubit's state stops changing (and / or, in some embodiments, stops changing beyond a threshold amount) between measurements. As another example, avoided level crossings can be identified based on changes in the state expectation value between measurements.

[0158] At 418, a Δ tuning offset ω is determined for the problem qubits based at least in part on the information determined at 416. For example, based on the estimated freezing times determined at 416, the evolution of the problem qubits can be advanced or retarded (e.g., as described elsewhere herein) to approximately synchronize those freezing times. Alternatively or in addition, the tunneling rate Δ i can be modified, for example, to reduce the occurrence of avoided level crossings by retarding the problem qubits. In some embodiments, the global annealing rate of the processor can be retarded to reduce the occurrence of avoided level crossings (e.g., problem qubits that experience avoided level crossings do not freeze prior to their synchronous freezing times).

[0159] Acts 420 and 422 generally correspond to 212 and 214 in FIG. 2, respectively. At 420, the problem qubits are tuned according to the Δ tuning offset ω determined at 418. At 422, the hybrid computer performs the calculation of the problem (which may have been modified by the Δ tuning operation of 420) and determines a solution.

[0160] Logical qubit strategy As pointed out elsewhere in this specification, at least some techniques for modifying the qubit-by-qubit annealing schedule Δ i can modify the problem so that it can be effectively computed. For example, modifying the persistent current of a flux qubit will change the annealing schedule Δ i of the qubit, but will also generally modify the flux of the qubit, and in this way change the problem to be solved.

[0161] In some embodiments, Δ tuning (e.g., at 160 and / or 212) can be performed by changing the encoding of the problem so that the problem is effectively solved (although the problem can be represented in different ways by the processor). For a flux qubit-based system, such embodiments may be said to provide orthogonal control between the persistent current (and / or other parameters defining the problem) and the tunneling rate Δ i

[0162] In some embodiments, orthogonal control between the persistent current and the tunneling rate Δ i is provided by encoding the problem in an intermediate form that employs "logical" qubits. A logical qubit includes a plurality of qubits (referred to herein as "internal" qubits) that are coupled to behave effectively as a single qubit. A logical qubit represents a single variable of the problem. Techniques for forming logical qubits (e.g., as qubit chains) are described, for example, in U.S. Patent Nos. 7,984,012, 8,244,662, and 8,174,305.

[0163] Each internal qubit within a logical qubit has its own associated qubit parameters such as the tunneling rate Δ i and the persistent current. The logical qubit itself has an effective tunneling rate Δ ​​eff and an effective permanent current I eff and may have "effective" qubit parameters such as. The effective qubit parameters of a logical qubit are determined by the qubit parameters of the internal qubits, the number of internal qubits in the logical qubit, the coupling J i between the internal qubits (referred to herein as the "internal coupling strength"), the internal topology of the logical qubit (i.e., the topology of the internal qubits and the couplings between the internal qubits), and the strength and arrangement of the couplings between the internal qubits and qubits that do not exist within the logical qubit. Thus, these parameters of the logical qubit can be selected to obtain a desired (or "target") effective tunneling rate Δ eff .

[0164] For example, the effective tunneling rate Δ of a logical qubit having a chain topology with N superconducting qubits and N - 1 couplings J i is as follows (where each individual qubit has a tunneling rate of Δ and the processor operates in the perturbation regime where Δ ≪ J): eff ( i )

Equation

Equation

[0165] Logical qubits with various topologies can exhibit various behaviors. For example, the effective tunneling rate Δ effAlso (or alternatively), by increasing the number of internal couplers and / or the strength of the internal coupling J i it can be suppressed. Importantly this can be done such that the Δ of the logical qubit eff is suppressed without necessarily modifying the Δ of any of the internal qubits i (i.e., it can be tuned to advance the annealing), thereby providing control of the Δ eff (not only the permanent current I of the internal qubit P ) that is orthogonal to the control of the permanent current I eff of the internal qubit.

[0166] Thus, in some embodiments, the Δ tuning of a particular qubit is done by modifying the problem representation on the processor such that the qubit is represented as a logical qubit. Next, the per-qubit annealing schedule Δ eff of the logical qubit can be advanced in proportion to the number of qubits, the strength of the couplings, and the topology of the logical qubit.

[0167] In some embodiments, the qubit being tuned may already be represented as a logical qubit, and the Δ tuning of the logical qubit may include modifying the number of qubits, the strength of the couplings, and / or eff the topology of the logical qubit to delay the per-qubit annealing schedule Δ of the logical qubit.

[0168] In some embodiments, the topology of the logical qubit is determined based on the connectivity to external qubits (i.e., qubits outside the logical qubit). For example, if only a single internal qubit is coupled to one or more external qubits, any coupling strength J i can be provided for internal coupling (i.e., the coupler can be provided with the full range of its coupling strength J i , typically either zero or up to a certain maximum coupling strength). However, if multiple internal qubits are coupled to an external qubit, a problem-dependent minimum internal coupling strength J must be maintained to prevent the logical qubit from "breaking" (i.e., to prevent the internal qubits from taking on various values). min will exist. In some embodiments, the topology of the logical qubit is selected such that only one internal qubit is coupled to one or more external qubits. This topology may be preferentially selected over other topologies (where multiple internal qubits are coupled to one or more external qubits).

[0169] Depending on the problem and / or processor topology, the minimum internal coupling strength J of the logical qubit min can be reduced by selecting a particular topology of the logical qubit. For example, a topology that reduces the number of internal qubits coupled to the external qubit can be selected.

[0170] Ancillary qubit strategy In one approach, results can be obtained using a C2 graph configured to form a 32-qubit 4-regular graph. The hybrid computer can send 1BOP (1 bit of precision) problems with zero local qubit bias to the hardware. The 1BOP problems have a coupling strength J = ±1. Some couplers can also be disabled by making them "inoperable". Generally such problems are easy, but the hybrid computer can, for example, first generate 17,000 instances with two ground states and over 400 first excited states, and then find 100 hard instances by taking 100 instances with the lowest hardware probability of success (usually less than 5%). By using the structure of C2 embedded in a larger graph, ancillary qubits can be attached to each of the 32 qubits.

[0171] The hybrid computer may apply an iterative method to realize this approach. First, the hybrid computer may derive a number of samples (e.g., 1,000 samples) by using hardware. Then, the hybrid computer may apply auxiliary constraints to qubits that are rarely floppy within the number of samples and that do not yet have an auxiliary qubit attached. The auxiliary constraint may be to point away from the current average spin (or magnetization). The hybrid computer may repeat this process, and the chance of success may change between iterations. Other variations of this approach may be used, such as adding a local bias to the qubits instead of an auxiliary constraint.

[0172] A method for eliminating perturbative crossings may be based on adding ancillary qubits to increase the degeneracy of the global minimum compared to the degeneracy of the competing minima (see, for example, U.S. Patent Application Publication No. 2015 / 0032994).

[0173] Advancing qubits during quantum annealing Another approach is to advance some of the qubits relative to other qubits during quantum annealing. The energy spectrum is modified by using local CCJJ (Compound-Compound Josephson Junction) DACs (Digital-to-Analog Converters) to obtain a constant current density over the entire C2 ensemble. This may cause degradation of the persistent current balance over the entire C2 ensemble, but the primary main effect may be to modify the transverse magnetic fields of some of the qubits during quantum annealing.

[0174] Example comparison results of degeneracy reduction Degeneracy reduction is related to area freezing. Area freezing is usually correlated to degeneracy reduction, although the relationship is generally not one-to-one.

[0175] 6-10 are plots illustrating comparative results of exemplary implementations of degeneracy mitigation in a quantum processor according to the present systems, devices, articles and methods. The methodology used to generate FIGS. 6-10 was as follows: 1. Program a difficult C2 problem instance. 2. Extract 1000 samples from the hardware. 3. For a given sample, for each qubit, calculate the net bias from its neighboring qubits as follows:

Equation

[0176] Figures 6 to 10 were generated using the method described above (actions 1 to 7) and a specific variant of the method described below with reference to Figures 6 to 10.

[0177] Figure 6 is a histogram of the probability of finding the ground state of a selected difficult problem instance. The problem was executed using a variant of the method described above with 10 samples in action 2 instead of 1000 samples. The problem was executed without local CCJJ DAC adjustment. This is the baseline case (i.e., no degeneracy reduction). The median is approximately 0.04.

[0178] Figure 7 shows the effect of degeneracy reduction. Even with only 10 samples, the chance of finding the ground state is significantly increased as a result of degeneracy reduction compared to the baseline case. The median of Figure 7 is approximately 0.49.

[0179] FIG. 8 is a histogram of the probability of finding the ground state of a selected difficult problem instance. The problem was run using the method described above with 1000 samples. FIG. 8 shows the effect of using more samples in degeneracy reduction. The chance of finding the ground state is increased compared to the 10-sample case of FIG. 7. The median of FIG. 8 is about 0.66.

[0180] FIG. 9 is a histogram of the probability of finding the ground state of a selected difficult problem instance. The problem was run using a variant of the method described above that advances 5 random qubits rather than qubits with a maximum spread of b i =0. The results are similar to the baseline case, indicating that "random degeneracy reduction may have little or no favorable impact on the chance of finding the ground state." The results reinforce the importance of selecting qubits according to criteria such as those described in the method above. The median of FIG. 9 is about 0.03. FIG. 10 is a histogram of the probability of finding the ground state of a selected difficult problem instance. The problem was run using the method described above but retarding the qubits by performing an inverse CCJJ DAC adjustment instead of advancing the qubits. The results of this example show an adverse effect on the chance of finding the ground state compared to the baseline case without degeneracy reduction. The results show the importance of advancing the qubits rather than retarding them. The median of FIG. 10 is about 0.001.

[0181] In some embodiments, another suitable metric may be used to determine floppiness, such as a metric that may be used with a non-zero bias value. For example, instead of summing the bias values, the method may determine for a given qubit whether the energy of a given state changes when the state of the qubit is inverted. If the method determines that the energy of the given state does not change, the qubit may be counted as a floppy qubit.

[0182] ​​

[0183] This technique enhances performance by algorithmically (and iteratively) modifying the annealing trajectory. Although it has been theoretically proposed to use a set of initial samples to guide the modification to the annealing trajectory, this technique is considered to be the first practical embodiment. Additionally, the present system and method can be implemented to improve sampling diversity (e.g., diversity of ground state and / or excited state samples).

[0184] The benefit of this technique is that it can make the hardware sample probability distribution closer to the Boltzmann distribution (which may be desirable for sampling).

[0185] This technique is not limited to the floppiness metric. For example, one or more "frozen" regions of qubits (regions where qubits are locked into the same configuration over many samples) can be identified, and then other metrics can be used to slow down the regions during quantum annealing.

[0186] Intermediate annealing pause It may be beneficial to implement a pause in the annealing schedule.

[0187] FIG. 11A shows a chart 1100a showing an exemplary annealing scenario without a pause within the annealing schedule. The horizontal axis 1110 corresponds to time. The vertical axis 1112 corresponds to the persistent current i P corresponding thereto. The tunneling speed Δ i of the qubit can be tuned according to the associated Δ tuning offset ω of the qubit. As discussed elsewhere in this specification, Δ i can be tuned by changing the persistent current of the qubit. The line 1115 shows the temporal variation of the persistent current over the duration of the annealing. In the example shown, the persistent current changes linearly with time.

[0188] FIG. 11B shows a chart 1100b that depicts an exemplary annealing scenario having a pause within the annealing schedule. The horizontal axis 1120 corresponds to time. The vertical axis 1122 corresponds to the permanent current i P .

[0189] Lines 1125, 1130, 1135 show the variation of the permanent current over time during the annealing duration. Line 1125 shows the increase in the permanent current until the start of the pause. Line 1130 shows the pause. The start of the pause begins at s P during the progress of the evolution. For example, if the start of the pause is at the midpoint of the annealing , then s P = 0.5. The start of the pause at s P corresponds to time t1. The pause ends at time t2 after the pause duration of t P . Line 1135 shows the increase in the permanent current from the end of the pause until the end of the annealing.

[0190] In some embodiments, the annealing schedule has a single pause. In other embodiments, the annealing schedule has two or more pauses.

[0191] In some embodiments, the user may define the start s P of the pause and the duration t of the pause via a user interface. The user interface can be a graphical user interface, a remote interface, and / or an application programming interface. For example, to implement a 100 μs pause at the midpoint of the annealing, the user may define s P = 0.5 and t = 100 μs. P P

[0192] ​​​During the test, the applicant observed an improvement in the performance of quantum annealing resulting from implementing pauses within the annealing schedule. For example, in the case of a quantum processor including 16 qubits, an improvement in performance of approximately 30 times can be achieved in a 10 μs annealing schedule by incorporating a 100 μs pause at a suitable stage of the annealing during a total annealing time of 110 μs. The same improvement without a pause would require an annealing time of approximately 1000 μs.

[0193] Fast and / or slow annealing The annealing time can be adjusted. In some embodiments of the systems and methods described herein, a user may specify a desired annealing time. The annealing time may be provided via a user interface (e.g., an application programming interface) (API). The annealing time may be faster or slower than a pre-adjusted annealing time.

[0194] Intermediate annealing ramp In some embodiments of the systems and methods described herein, the annealing schedule may include an intermediate annealing ramp. A standard annealing (e.g., a linear increase in a permanent current) may be interrupted by a sudden acceleration of the annealing by a steep increase in the permanent current at some point during the evolution.

[0195] FIG. 11C shows a chart 1100c showing an exemplary annealing scenario having an intermediate annealing ramp 1150 within the annealing schedule. The horizontal axis 1140 corresponds to time. The vertical axis 1142 corresponds to the permanent current i P corresponding thereto. The annealing schedule begins with a standard an nealing 1145, followed by an intermediate annealing ramp 1150.

[0196] In some embodiments, the parameters defining the intermediate annealing ramp may be provided via a user interface (e.g., an API).

[0197] Annealing schedule operation In some embodiments of the systems and methods described herein, the annealing schedule may include a suitable combination of one or more intermediate annealing pauses and / or one or more intermediate annealing ramps.

[0198] FIG. 11D shows a chart 1100d depicting an exemplary annealing scenario having an annealing schedule operation that includes an intermediate annealing pause and an intermediate annealing ramp within the annealing schedule. The horizontal axis 1160 corresponds to time. The vertical axis 1162 corresponds to the permanent current i P corresponding thereto.

[0199] The annealing schedule begins with a standard anneal 1165, followed by a first intermediate annealing ramp 1170. The annealing schedule proceeds with a first intermediate annealing pause 1175 and then a second intermediate annealing ramp 1180 (this time in the opposite direction, a sharp decrease in the permanent current). After ramp 1180, a second intermediate annealing pause 1185 and a third ramp 1190 follow.

[0200] In some embodiments, the annealing schedule operation may be provided via a user interface (e.g., an API). The parameters defining the annealing schedule operation may be, for example, the start and duration of each segment of the schedule. The start of the first intermediate annealing ramp 1170 may be defined by a measure of the progress of the evolution. The timing of the other ramps and pauses may be defined, for example, by the duration.

[0201] FIGS. 11A - 11D each show, for convenience, the permanent current i on the vertical axis P shown. In other parts of this specification As described somewhere, in at least some situations, it is possible to change the tunneling speed of one or more qubits to be orthogonal to the fluctuations of the persistent current. Thus, it is understood that the intermediate annealing pauses, intermediate annealing ramps, and rapid annealing operations in the annealing schedules described herein can be implemented by any suitable technique (or combination of techniques) for changing the tunneling speed.

[0202] Generalized annealing schedule FIG. 11D shows a chart 1100d showing an exemplary annealing scenario having an annealing schedule operation that includes an intermediate annealing pause and an intermediate annealing ramp within the annealing schedule. FIG. 11D shows an exemplary annealing schedule, but one of ordinary skill in the art will recognize that other annealing schedules may be used to achieve the desired evolution.

[0203] The annealing schedule can be expressed using a suitable one-to-one function of time. The function may be linear or non-linear. The function may be injective or non-injective. The function can be expressed as a series of segments each having a suitable one-to-one function of time that are the same or different.

[0204] Piecewise linear annealing schedule The piecewise linear annealing schedule is an example of an annealing schedule. The piecewise linear annealing schedule includes one or more segments each of which is a linear function of time. FIG. 11D is an example of a piecewise linear annealing schedule. In the example of FIG. 11D, the persistent current i p is a linear function of time or the progress through the evolution s It varies in piecewise linear segments that are linear as a function. For example, the first linear segment is ramp 1165. The schedule has five other linear segments 1170, 1175, 1180, 1185, 1190 respectively. Those skilled in the art will recognize that any suitable sequence of linear segments can be combined to generate an annealing schedule.

[0205] Annealing schedule manipulation by using programmable parameters As described above, a quantum processor can be designed to perform quantum annealing and / or adiabatic quantum computing. An evolution Hamiltonian proportional to the sum of a first term proportional to the problem Hamiltonian and a second term proportional to the delocalization Hamiltonian can be constructed as follows. H E ∝A(t)H P +B(t)H D

[0206] In some embodiments, a time-varying envelope function can be placed on the problem Hamiltonian. A suitable delocalization Hamiltonian is given by:

Number

Number

Number

[0207] A general problem Hamiltonian can include a first component proportional to diagonal single qubit terms and a second component proportional to diagonal multi-qubit terms, and can be in the following form: [Number] Here, N represents the number of qubits, [Number] is the Pauli z matrix of the i-th qubit, h i and J ij are the dimensionless local fields of the qubits and the couplings between the qubits. ε is the characteristic energy scale of H P .

[0208] During the operation of the quantum processor, the interface couples the flux signals into each of the composite Josephson junctions of the qubits, thereby making it possible to be used to realize the tunable terms (Δ i terms) in the system Hamiltonian. This coupling provides the off-diagonal σ terms of the Hamiltonian, and these flux signals are examples of "delocalized signals". x

[0209] Similarly, the interface couples the flux signals into each of the qubit loops of the qubits, thereby making it possible to be used to realize the h i terms in the system Hamiltonian . This coupling provides the diagonal σ z terms in the system Hamiltonian. Further, the inter face couples the flux signals into the coupler, thereby making it possible to be used to realize the J ij terms in the system Hamiltonian. This coupling provides the diagonal [Number] terms in the system Hamiltonian.

[0210] In one approach to quantum annealing, the system has programmable parameters h i and J ijcan be manipulated. For example, the system can provide the delay separately, in combination with each other, or in combination with a transverse magnetic field on a programmable parameter and can be provided on the programmable parameter

[0211] At the end of annealing, when the transverse magnetic field becomes zero, the programmable parameters h i , J ij reach their final values. In the method described here, the envelope functions A(t), B(t) are effectively absorbed within the Hamiltonian and its associated parameters Δ i , h i , J ij The system can be flexible with respect to the annealing schedule (e.g., h i , J ij is fixed and Δ i can be evolved). Other schemes can produce similar results. In some cases, one approach to operating the annealing schedule can produce better results than another approach.

[0212] In one exemplary embodiment, the envelope function A(t) is fixed for each qubit, the bias value h i is fixed, the coupling J ij can be set to zero, and the envelope function B(t) can be changed for each J for performing annealing. The per-qubit values of A ij , B i , B i , B ij can be used to advance or delay the evolution of each qubit q i . can be used to advance or delay the evolution of each qubit q

[0213] In another example, A i , B i can be the same for all qubits, and B ij advances the coupling J ij at the center of the graph and the couplings J ijcan be used to gradually delay. The related technique is described elsewhere in this application and is called an annealing schedule operation based on the position of qubits in the graph. More generally, B ij can be used to gradually advance or delay the coupling J starting from a selected position in the graph or processor topology. ij

[0214] In another example, both the B i term and the B ij term can be manipulated to achieve a similar effect.

[0215] In another exemplary implementation of quantum annealing, the system can advance or delay clusters, regions, and / or chains of qubits by advancing or delaying a set of couplings J ij with respect to other couplings in the graph.

[0216] FIG. 11E shows a chart 1100e showing an exemplary annealing scenario in which the local bias h of a qubit is changed during evolution.

[0217] The horizontal axis 1191 corresponds to time. The vertical axis 1192 corresponds to the qubit bias h. The value of the qubit bias h over time is represented by line 1193.

[0218] FIG. 11F shows a chart showing an exemplary annealing scenario in which the coupling strength J of a coupling device between a pair of qubits is changed during evolution.

[0219] The horizontal axis 1194 corresponds to time. The vertical axis 1195 corresponds to the coupling strength J. The value of the coupling strength J over time is represented by line 1196.

[0220] Annealing schedule operation of logical qubits ​In some embodiments of the systems and methods described herein, an annealing schedule for a logical qubit that includes a plurality of hardware qubits is determined based on characteristics of the logical qubit. The logical qubit has an effective tunneling speed (Δ eff ) that depends on various characteristics of the logical qubit (including (partially) the number of constituent qubits, internal and external couplings, etc.). As observed elsewhere in this specification, one strategy is to manipulate these characteristics to obtain a desired Δ eff or an approximation thereof.

[0221] In some embodiments, the Δ eff of a logical qubit is manipulated based on one or more characteristics of the logical qubit (which may or may not include modifying the characteristics themselves). For example, in embodiments having a logical qubit with a chain topology (described elsewhere in this specification), a chain that is significantly shorter than another chain is likely to have a smaller Δ eff than the longer chain. Thus, a potentially useful heuristic for the dynamic characteristics of a logical qubit is the length of the chain (i.e., the number of constituent qubits). In at least some situations, the Δ of a chain can be modified based on the length of the chain (regardless of whether any other characteristics of the chain are considered). eff

[0222] As described elsewhere in this specification, the modification of Δ eff can be accomplished via one or more strategies. For example, Δ can be increased by extending the chain (thus slowing it down during annealing) eff or decreased by shortening the chain (thus speeding it up during annealing). Alternatively or in addition, the Δ of a chain can be modified by adjusting the coupling strengths between its constituent qubits eff (without considering any other characteristics of the chain). It can be modified by modifying the magnetic flux bias and / or coupling strength of the toroid and / or coupler, by modifying the DAC parameters (such as CCJJ DAC), or by any other available strategy.

[0223] In some embodiments, with respect to problems embedded using representations that include multiple variable-length chains, the respective Δ of each chain eff values can be synchronized by modifying their annealing schedules as described herein. In some embodiments, tuning occurs by synchronizing the Δ of the chains at a particular energy level. The inventors have discovered through experiments that this modification strategy can produce impressive results in some situations. For example, a 100-fold increase in the solution speed was observed in some instances of factoring a 2n-bit semiprime into distinct n-bit primes (compared to attempting to solve the same problem without modifying the annealing schedule). eff

[0224] Example of an annealing schedule operation for a logical qubit An example of such an experiment is shown as method 1900 in FIG. 19. At 1905, a factoring problem (e.g., finding the solution (a, b) to a × b = 35) is generated. At 1910, an embedding for a multiplication circuit that encodes the problem is generated (e.g., as described in U.S. Patent No. 8,700,689). Optionally, at 1915, one or more scaling factors are selected. For example, multiple scaling factors within the range [0, 1] (such as a set of factors {0, 0.1, 0.2,... 1}) can be selected. More or fewer scaling factors can be selected.

[0225] In 1920, an annealing schedule offset strategy is generated based on one or more scaling factors. Any suitable offset may be selected. Different offsets may be assigned to chains of different lengths to synchronize their dynamic characteristics on a particular energy scale. In at least the exemplary experiments, the CCJJ offset was selected based on the following formula.

Number

Number

[0226] In 1925, the quantum processor executes the problem and generates a sample solution. 1925 may be repeated with the same and / or different scaling factors (e.g., each scaling factor may have a plurality of corresponding executions). Optionally, method 1900 may return to 1915 to generate additional scaling factors. Alternatively (or in addition), method 1900 may generate a plurality of scaling factors at 1915 and not necessarily return from 1925 to 1915.

[0227] Optionally, at 1930, the results generated at 1925 may be compared, for example, by applying a performance metric and ranking the scaling factors with respect to that metric. For example, scaling factors with a high success rate and / or short time to reach a solution may be ranked higher than scaling factors with a relatively low success rate and / or long time to reach a solution. One or more of the top-ranked scaling factors are stored and may be called later for use in similar problems.

[0228] Method 1900 can be performed by other annealing scheduling strategies described herein and can utilize any available annealing offset technique (such as manipulation of logical qubit characteristics, manipulation of programmable parameters, etc.). It is understood that

[0229] Annealing schedule operations based on the position of qubits in the graph In some embodiments of the systems and methods described herein, the annealing schedule for a qubit and / or a set of qubits can be determined based on the position of the qubit and / or a set of qubits relative to one or more other qubits. For example, one or more qubits disposed on or proximate to the outer edge of a qubit graph can be advanced or retarded compared to other qubits within the graph. The graph can be, for example, a working graph of hardware qubits, a virtual graph that emulates a particular working graph of hardware qubits (such as described in U.S. Provisional Patent Application No. 62 / 375785), and / or an embedding graph of logical qubits where each logical qubit corresponds to one or more hardware qubits.

[0230] For example, the annealing schedule can be modified according to a defined gradient on the graph. FIG. 18 shows an exemplary illustrative gradient 1800 on a graph 1810 that includes a Chimera structured group 1812 of qubits 1814a, 1814b, etc. (collectively and individually "qubit 1814"). Due to the numerous groups 1812 and qubits 1814 of graph 1800, most of their labels are omitted for clarity of explanation. It is understood that the systems and methods described herein are not limited to Chimera structured graphs and that graph 18 10 is exemplary and non-limiting.

[0231] Gradient 1800 associates a value with each qubit 1814 (visually depicted by the shading intensity corresponding to legend 1820). Qubits 1814 within the first region 1802 are advanced during annealing (e.g., by applying a Δ offset as described elsewhere herein), qubits 1814 within the third region 1806 are retarded during annealing (e.g., by applying a Δ offset having the opposite polarity of the Δ offset applied within the first region), qubits 1814 within the second region 1804 are not advanced or retarded, and / or are advanced or retarded only slightly compared to qubits 1814 within the first and third regions 1802, 1806. In some embodiments, gradient 1800 only advances (or retards) qubits 1814, but various qubits 1814 can be advanced (or retarded) by various amounts, and / or some qubits 1814 may not be advanced (or retarded).

[0232] The inventors have observed that in at least some problems executable on at least some quantum processors, qubits 1814 near the outer edges tend to freeze earlier than other qubits 1814 placed relatively far from the edges of the graph. In some embodiments, a gradient is defined that corresponds to an annealing schedule modification that retards qubits 1814 near the outer edges of graph 1810 and advances qubits 1814 far from the outer edges of graph 1810. Gradient 1800 is a non-limiting example of such a gradient, but it is understood that other gradients having this behavior (e.g., a gradient in which each qubit 1814 has an annealing offset determined by its distance from the outer edge (greater distance corresponding to earlier annealing time)) can be defined.

[0233] Gradient 1800 is an exemplary radial gradient. Each qubit 1814 is associated with an offset value that decreases in proportion to the distance of the qubit 1814 from point 1822. Other gradients are possible. For example, the gradient can be a linear gradient associated with an offset value based on the distance of each qubit 1814 from a line defined across the entire graph 1810 (e.g., based on the distance between the qubit 1814 and an edge of the graph 1810, such as edge 1822). In some embodiments, the gradient extends across the entire graph 1810. In alternative or additional embodiments, the gradient is defined on a portion of the graph 1810.

[0234] One or more gradients can be defined on the graph 1810. When multiple gradients are defined, the multiple gradients may be mutually exclusive and / or may overlap. A qubit 1814 for which multiple gradients are defined can have an annealing schedule defined by a combination of the associated values of the overlapping gradients of the qubit 1814. For example, the annealing schedule of the qubit 1814 can be based on the sum, product, or other function of the overlapping gradient associated values.

[0235] Annealing Schedule Operations within a Logical Qubit In some embodiments of the systems and methods described herein, the annealing schedule of a logical qubit can be manipulated such that the qubits that make up the logical qubit have the same or different annealing schedule offsets. For example, all qubits within a logical qubit can have the same annealing offset, qubits having external couplings can be assigned different offsets than qubits having only internal couplings (and / or can be assigned offsets based on various criteria), and / or qubits having various positions within the graph can be assigned various offsets (and / or can be assigned offsets based on various criteria). This annealing schedule manipulation can be applied in addition to (or be an alternative to) other annealing schedule manipulation strategies described elsewhere herein. The logical qubit level schedule may sometimes be referred to as a "sub-schedule" to distinguish it from a broad (e.g., processor-wide) annealing schedule.

[0236] For example, in some embodiments where the broad annealing schedule is directional, the logical qubit can follow a directional annealing sub-schedule that modifies the broad annealing schedule. For example, when an annealing schedule based on a linear gradient across all logical qubits in an embedded graph is given (e.g., such that qubits anneal earlier compared to other qubits when the qubits are present along an axis across the entire embedded graph), the corresponding gradient can be determined within the logical qubit. The constituent qubits of the logical qubit (which can be hardware qubits) can anneal earlier compared to other qubits within the same logical qubit based on the gradient. The logical qubit level gradient can have a different slope than the gradient of the broader annealing schedule (e.g., qubits within a logical qubit can anneal relatively more closely in time compared to other similarly adjacent qubits elsewhere in the graph that are not part of the same logical qubit).

[0237] Selective annealing In some embodiments of the systems and methods described herein, a subset of qubits is annealed while another subset of qubits is not annealed. The subset of qubits can include hardware qubits, logical qubits, and / or any other qubit representation. For example, a subset of qubits can be selected for annealing, an annealing schedule can be assigned to those qubits, and the remaining qubits can be clamped or otherwise prevented from having their dynamical properties changed (e.g., by programming their corresponding CCJJ DAC biases). Such prevention is referred to herein as “resting” the remaining qubits. Next, the selected qubits can be annealed according to their annealing schedule. Next, the remaining qubits can be un-rested (i.e., permitted to resume annealing).

[0238] For example, a subset of qubits can be selected for reverse annealing at some point in the evolution. The remaining qubits can be rested, and the subset can be reverse annealed (e.g., as described in U.S. Patent Application Publication No. 2015 / 363708). Next, the remaining qubits can remain rested while the selected qubits can be forward annealed (which can result in a different resulting state than could have been the case previously), and the remaining qubits can be permitted to anneal when the qubits return to the point within the annealing that they occupied prior to the reverse annealing occurring. Alternatively or in addition, some or all of the remaining qubits can be permitted to anneal after the reverse annealing has completed and before the selected qubits are forward annealed again.

[0239] Intentional De-Tuning of the Annealing Schedule Another embodiment of the disclosed system and method for advancing (or retarding) qubits during annealing identifies constraints and backpropagates them, for example, from the circuit output towards the circuit input across the logic circuit. For example, qubits close to the circuit output can be frozen at an early stage of evolution. This can be achieved by starting to reduce the tunneling amplitude of a subset of qubits earlier than that of another subset of qubits, or by reducing the tunneling amplitude at a faster rate. For example, a time-dependent gradient of the tunneling amplitude can be established across the logic circuit. The gradient of the tunneling amplitude can correspond to an annealing schedule.

[0240] A modified annealing schedule can be generated by intentionally detuning the tunneling amplitude of a selected subset of qubits and the problem Hamiltonian energy scale. In one embodiment, as described elsewhere in this disclosure, the detuning is achieved by adjusting qubit parameters via a DAC within a quantum processor such as a CCJJ DAC.

[0241] Controllably simulating noise within an annealing schedule Analog processors tend to be vulnerable to noise, and significant efforts are generally made in existing systems to reduce the amount and impact of such noise. For example, at least some analog processors are operated in cryogenic environments (e.g., below 1°K) to reduce thermal noise. However, even in such environments, noise can enter. For example, communication lines connecting supercooled analog processors can also be connected to devices in a much warmer (e.g., room temperature) environment, thereby introducing potential paths for noise to affect the analog processor.

[0242] However, in at least some situations, further noise reduction can negatively impact some performance metrics of the analog processor. For example, at least some In the case, the inventors observed that operating an analog processor even at temperatures below normal gives rise to sample diversity and / or the optimization success rate for some problems is reduced compared to the same metric when the same problem is executed at a high temperature (and thus with more noise).

[0243] One potential effect of noise is that it can cause small and random (and / or quasi-random) variations in the annealing schedule. For example, in at least some quantum processors, noise on the annealing control line can cause small and short-lived increases and / or decreases in the persistent current, thereby introducing some jitter in the annealing schedule of the qubits.

[0244] In some embodiments, noise can be controllably simulated by a digital computer by applying short-time ramps and pauses to the annealing schedule executed by an analog computer in relation to the problem. FIG. 22 shows a chart 2200 showing an exemplary annealing scenario in which noise is controllably applied to the anneal. The horizontal axis 2202 corresponds to time. The vertical axis 2204 corresponds to the tunneling speed Δ. As explained elsewhere herein, the tunneling speed can be determined or affected according to one or more of several techniques (such as changing the persistent current i P and the like).

[0245] Line 2210 corresponds to an exemplary input annealing schedule. The input annealing schedule can be, for example, the ideal noise-free annealing schedule for the qubits in the problem. As another example, the input annealing schedule may already include some noise (either intentionally or unintentionally). In the example shown, line 2210 is shown as a dashed line that coincides with a portion 2222 of line 2220 (and is thus partially obscured).

[0246] Line 2220 corresponds to an exemplary output annealing schedule. The output annealing schedule is generated by a digital computer based on an input annealing schedule and a controllable noise addition algorithm. For example, the output annealing schedule corresponding to line 2220 can be determined by applying dithering techniques to input annealing schedule 2210.

[0247] In some embodiments, the output annealing schedule is determined by a digital computer by modifying the input annealing schedule by adding intermediate annealing ramps and pauses. For example, line 2220 includes a portion 2222 that coincides with line 2210 and thus indicates the annealing period when the input annealing schedule and the output annealing schedule are the same. In portion 2224 of line 2220, a ramp is added, deviating line 2220 from line 2210 (in this case, the deviation corresponds to an advance of the output annealing schedule relative to the input annealing schedule). In portion 2226 of line 2220, a pause is added, reducing the deviation of line 2220 from line 2210.

[0248] In the example shown in FIG. 22, the pause in portion 2226 is long enough to cause line 2220 to intersect line 2210 at intersection 2230. The pause ends at intersection 2230, which can cause line 2220 to coincide with line 2210 again (similar to portion 2222), or the pause can continue, causing line 2220 to deviate from line 2210 again (as shown in FIG. 22, for example). Subsequent ramps can cause line 2220 to intersect line 2210 again, as shown by portion 2228 of line 2220, for example. In some embodiments, pauses or ramps can be added that reduce the deviation from the input annealing schedule but end before the input annealing schedule and the output annealing schedule intersect.

[0249] Other modifications are possible. For example, the output annealing schedule may include portions where reverse annealing occurs. As another example, the output annealing schedule may include non-segmented linear modifications. For example, the output annealing schedule may be based on the product of the input annealing schedule and a low amplitude sine curve and / or some other continuous function. As another example, fast and / or slow annealing may be provided respectively instead of (or in addition to) ramps and / or pauses. For example, the output annealing schedule may anneal slowly during a period corresponding to some or all of portion 2226 (this would be graphically shown as portion 2226 having a positive slope less than the slope of line 2210). Thus, lines 2210 and 2220 would intersect at a point in time later than intersection 2230 unless additional modifications are added to bring the intersection of lines 2210 and 2220 forward.

[0250] In some embodiments, modifications to the input annealing schedule (such as pauses and ramps) are added randomly and / or pseudo-randomly by a digital computer. In some embodiments, pauses and ramps (and / or slow annealing and fast annealing) are added as alternating pairs (e.g., first a pause, then a ramp, followed by either a pause-ramp pair or a ramp-pause pair). In some embodiments, the duration and amplitude of the modifications are determined randomly or quasi-randomly.

[0251] In some embodiments, the modifications are added to the output annealing schedule by a digital computer according to one or more constraints. For example, one or both of the duration and amplitude of the modifications may be constrained so that the modification and / or deviation of the output annealing schedule from the input annealing schedule does not exceed a threshold. As an example, each 0.1 millisecond period of annealing may have a modification added randomly (and / or pseudo-randomly), thereby constraining each modification to 0.1 millisecond. Optionally, some periods may not have any modifications.

[0252] As another example, the duration and / or amplitude of one or more modifications may be randomly or pseudo-randomly selected by a digital computer according to the constraint that "each modification must not deviate from the input annealing schedule by more than a threshold amount". For example, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by an amount greater than an amount proportional to the amplitude of the input annealing schedule at the same point in time (e.g., within 1%, 5%, etc.). Alternatively or in addition, the amplitude of the output annealing schedule may be constrained to deviate from the input annealing schedule by an amount greater than a certain amount (e.g., an amount corresponding to 0.1%, 0.5%, 1% of the maximum persistent current, etc.).

[0253] The corrective noise can be added on a per-qubit basis and / or on a multi-qubit basis. For example, an initial set of corrections can be determined and uniformly applied to the annealing schedules of all qubits (and / or all qubits of the problem) on the analog processor. Another set of corrections can be determined and applied individually to each qubit. An intermediate set of corrections can be determined and applied to a group of qubits (e.g., by grouping qubits that receive annealing control signals together on a shared annealing line and uniformly applying the intermediate set of corrections to the group).

[0254] Reduction of sampling bias The techniques of the present disclosure for manipulating annealing schedules are not limited to optimization problems. For example, the techniques of the present disclosure can also be applied to improve the performance of an analog processor (and / or a hybrid computer) during the sampling operation. As will be well known to those skilled in the art, an analog processor can be used to draw samples from a distribution defined by an input problem. As will be well known to those skilled in the art, an analog processor can be used to draw samples from a distribution defined by an input problem.

[0255] A particular problem may be vulnerable to sampling bias where solutions from a particular group are sampled more frequently than others. For example, problems with highly degenerate ground states and / or first-excited states may exhibit strong sampling bias, resulting in valleys with high degeneracy being sampled more frequently than others (perhaps to the extent that "samples from valleys of high degeneracy tend to be dominant over samples from other valleys"). A "valley" is a group of one or more solutions (or samples) that occupy a low-energy region of an energy landscape defined by the Hamiltonian of a problem in which an analog processor (and / or hybrid computer) can transition during annealing without changing the energy. That is, a valley is a low-energy iso-energy cluster of solutions (or samples).

[0256] In some embodiments of the disclosed systems and methods, sampling bias is reduced by modifying the annealing schedule of the problem, thereby enabling samples from other valleys to be obtained with greater frequency.

[0257] A flowchart illustrating an exemplary method 2100 for reducing the sampling bias of an analog processor is shown in FIG. 21. At 2105, a problem is received by a processor (e.g., a digital processor). At 2110, N samples are collected from the analog processor (e.g., as described above with respect to FIG. 1).

[0258] In 2115, N samples are analyzed and one or more valleys are identified. The valleys can be identified by a digital processor, for example, by grouping the samples into clusters based on equal energy qubit flips. For example, two samples can occupy the same valley if there is a series of qubit flips that can be applied to one sample to obtain the other sample without any flip that causes a change in energy (or without causing a change that exceeds a threshold energy). Each qubit flip can include flipping one or more qubits. In some embodiments, only samples that are related to each other by an equal energy qubit flip less than a determined (e.g., predetermined) number are grouped as the identified valleys. Such embodiments are sometimes said to use the equal energy Hamming distance as a metric for valley membership.

[0259] In some embodiments, all valleys are identified by a digital processor in 2115. In some embodiments, only a subset of valleys are identified. For example, valleys having a degeneracy greater than a certain number of degenerate states, valleys for which at least a threshold number of samples have been collected, a subset of valleys including the valley with the largest integer v, valleys having less than a minimum energy, and / or other valleys can be identified.

[0260] In 2120, valley v i is selected by a digital processor from one or more valleys. For example, the valley with the highest probability (i.e., the valley from which the largest number of samples have been drawn) can be selected.

[0261] In 2125, qubit q i is selected from the valley selected by the digital processor. In 2130, the degeneracy metric μ of qubit q i is determined. The degeneracy metric gives a measure of the contribution of qubit q i to the degeneracy of the corresponding valley. For example, the degeneracy me i tric μ of qubit q iis the normalized floppiness as described for act 130 of method 100 and may include a metric (see FIG. 1). For example, the normalized floppiness metric may be determined according to the following formula: μ i =n i / S where n i is the number of times qubit q i was floppy within S samples of valley v i . .

[0262] Acts 2125, 2130 may be performed by a digital processor on a plurality of qubits (e.g., all available qubits, all qubits within the region of interest, etc.), thereby generating a plurality of degeneracy metrics corresponding to the plurality of qubits.

[0263] In 2135, the annealing schedule is determined by a digital processor for each qubit based on its corresponding degeneracy metric. In some embodiments, the annealing schedule includes an annealing offset ω i determined for each qubit q i based on the degeneracy metric μ i . In some embodiments, the offset ω i is proportional to the degeneracy metric μ i . For example, an offset ω i =μ i A may be assigned to each qubit q i . Here, A is a constant annealing offset coefficient (in at least some embodiments, the maximum offset that can be assigned during one iteration of method 2100). The annealing coefficient A may represent either advancing or retarding the qubit during annealing and thus may be positive or negative in at least some embodiments.

[0264] As described elsewhere in this specification, the term "qubit" can refer to a single qubit or a region of qubits (a qubit can be a hardware device, a logical qubit, etc.). Qubit q i When corresponding to a region of qubits, the annealing offset can be applied to each qubit in the same region. For example, each qubit in region q i can receive the same offset ω i . Instead of or in addition to applying an annealing schedule to the qubits in a region, alternative or additional techniques as described elsewhere in this specification can be used.

[0265] In some embodiments, a non-zero annealing offset ω i is assigned only to qubits q i having a corresponding degeneracy metric μ greater than (and / or greater than or equal to) a threshold T i . In some embodiments, Δ is the same for each such qubit q i . i

[0266] In some embodiments, each qubit q i in valley v i is advanced to the start of annealing or delayed until the end of annealing in an annealing schedule. For example, the determined annealing schedule causes qubit q i to end annealing before at least some other qubits start their annealing and / or to start annealing after at least some other qubits have ended their respective annealings. For example, qubit q can be advanced (delayed) before (after) all other qubits. As another example, qubit q i has already not been advanced by method 2100 and qubit q i ​​​It can be advanced (delayed) before (after) other qubits that have been obtained or cannot be delayed. In some embodiments, the selected valley v i One or more other qubits not within The qubits of the selected valley v are delayed so that other qubits can complete their annealing before starting their annealing. i of the quantum bit can be completed.

[0267] Optionally, act 2135 may include determining a plurality of annealing schedules for each quantum bit q i by a digital processor. For example, act 2135 may generate one or more annealing schedules that advance the quantum bit q and one or more annealing schedules that delay the quantum bit q i . Additionally or alternatively, act 2135 may include first determining one or more annealing schedules and then generating a plurality of annealing schedules by applying a set of scaling factors to each of the one or more annealing schedules. For example, the annealing schedule i may be determined as described above, and then the product of the annealing schedule and each scaling factor {α , α2,..., α i}(e.g. {0.1, 0.2,..., 1}) may be determined n . For example, act 2135 may generate an annealing offset ω for the quantum bit q i and further generate a plurality of scaled annealing offsets for the quantum bit q i , {α i ω , α2ω i ,..., α i ω i ,..., α n ω i}.

[0268] Act 2135 may include selecting, by a digital processor, one of a plurality of determined annealing schedules based on one or more selection criteria such as an objective function and / or one or more constraints. For example, the annealing schedule may be selected based on avoiding contradictions, minimizing floppiness, and / or some other decision criteria.

[0269] At 2140, an additional M samples are collected by executing the problem by an analog processor having the determined annealing schedule of Act 2135. Optionally, method 2100 may be repeated by returning to Act 2115 and performing Acts 2115 - 2135 based on the M samples, thereby refining the determined annealing schedule. In such an embodiment, Act 2120 may include selecting valley v i that was not selected during a previous iteration of method 2100. In some embodiments, the same valley v selected in a previous iteration may be used. The repetition may end when an end determination criterion is satisfied. For example, method 2100 may be repeated until the results converge, until the threshold number of iterations ends, until all valleys have been iterated through and end, until no eligible valleys remain (where "eligible valleys" refers to valleys that may be selected in Act 2120), and / or until some other decision criteria are met. i The repetition may end when an end determination criterion is satisfied. For example, method 2100 may be repeated until the results converge, until the threshold number of iterations ends, until all valleys have been iterated through and end, until no eligible valleys remain (where "eligible valleys" refers to valleys that may be selected in Act 2120), and / or until some other decision criteria are met. The repetition may end when an end determination criterion is satisfied. For example, method 2100 may be repeated until the results converge, until the threshold number of iterations ends, until all valleys have been iterated through and end, until no eligible valleys remain (where "eligible valleys" refers to valleys that may be selected in Act 2120), and / or until some other decision criteria are met.

[0270] In 2145, one or more samples generated by method 2100 are returned by at least one of a digital processor and an analog processor. In some embodiments, the M samples collected in the last iteration of method 2100 are returned. In some embodiments, samples collected in multiple iterations are returned. For example, all samples collected by method 2100 can be returned. In some embodiments, a set of annealing schedules determined in one iteration of act 2135 is selected based on an optimality metric (e.g., the objective function of an optimization algorithm), and the M samples generated according to these annealing schedules are returned.

[0271] Detection of Quantum Fluctuations Using a Probe Quantum Bit To determine an improved or optimized annealing schedule, it may be beneficial to measure quantum fluctuations at different times during annealing. Quantum fluctuations tend to increase or peak near a quantum phase transition, and it may be beneficial to slow down the annealing when the quantum fluctuations increase.

[0272] The systems and methods of the present disclosure include techniques in which quantum fluctuations are measured directly via hardware and the results are used to improve or optimize an annealing schedule. In one embodiment, determining an improved or optimized annealing schedule is based on macroscopic resonant tunneling (MRT) noise measurements of quantum fluctuations.

[0273] In one embodiment, the one or more computational problems are encoded in a first subset of the qubits available in the quantum processor. The qubits within the first subset of qubits are known as computational qubits. The second subset of qubits (having no overlap with the qubits of the first subset) includes probe qubits operable to perform MRT noise measurements of quantum fluctuations during annealing. The probe qubits are calculated The computational qubits can be weakly coupled to the probe qubits, and the signals from the computational qubits detected by the probe qubits can be noisy.

[0274] The MRT peak width measurable by each of the probe qubits can depend on the integration of the noise spectrum and can vary according to the quantum fluctuations arising from the computational qubits. As described above, the quantum fluctuations can increase near the phase transition point or near the many-body localization points. The increase in the quantum fluctuations of the computational qubits coupled to the probe qubits can broaden the MRT peaks measurable by the probe qubits.

[0275] The annealing schedule can be adjusted based at least in part on the width of the MRT peaks.

[0276] FIG. 12 is a flowchart showing an exemplary method 1200 of operating a hybrid computer for adjusting a quantum annealing schedule. The method 1200 shown in FIG. 12 includes a plurality of acts. One or more of these acts can be performed by (or via) one or more circuits, such as, for example, one or more processors (e.g., digital processors), analog processors such as quantum processors, or hybrid computers that include both digital processors and analog processors. For the purposes of the description of FIG. 12, it is assumed that the acts are performed by a hybrid computer that includes a quantum processor. The method 1200 describes an exemplary embodiment. One of ordinary skill in the art will recognize that alternative embodiments may omit some of the acts and / or include additional acts.

[0277] At 1205, method 1200 starts. At 1210, the hybrid computer encodes a computational problem in a first subset of qubits within a quantum processor. In one embodiment, the qubits are superconducting flux qubits. At 1220, the hybrid computer allocates a second subset of qubits as probe qubits. The probe qubits can be weakly coupled to the first subset of qubits. At 1230, the hybrid computer measures the MRT peak width. At 1240, the hybrid computer adjusts the annealing schedule based at least in part on one or more measurement results of the MRT peak width. Method 1200 ends at 1245, for example, until it is called again.

[0278] Selection of Annealing Schedule Using Equilibrium Energy Statistics An annealer (such as a physical quantum annealer) can proceed according to an annealing schedule through a series of models between a prepared model and a target model. The prepared model can be, for example, a uniform superposition of states or a uniform distribution over classical states. The target model can be, for example, a distribution regarding the minimum value of an energy function or a Boltzmann distribution at a low system temperature. Physical (or Markov Chain Monte Carlo (MCMC)) dynamical characteristics can modify the state during annealing.

[0279] The purpose of annealing is usually to sample from a final distribution as close as possible to the distribution of the target model. If the target distribution is a Boltzmann distribution described by an energy function E(x) or by an energy operator (classical or quantum), it may be beneficial to select an annealing schedule that improves or maximizes the approximation of the final distribution to the target distribution.

[0280] The annealing schedule thus selected is usually specific to a particular problem. However, there can exist many large-scale problems that share statistical features such that a single schedule can be (practically) sufficiently good for two or more problems. It may be beneficial to determine an improved or optimal schedule for such a group of problems. Alternatively , a set of schedules can be presented to an expert user who can select based on an evaluation. This technique can also be adapted to select a suitable model (a preferred or optimized discrete set of intermediate models for parallel tempering) for the multiple canonical MCMC procedure.

[0281] A thermal annealer can be programmed by a classical Hamiltonian H(x) and a series of inverse temperatures β. The function Γ(t) can be used to describe the time-dependence of β, where Γ(0) = β min is the initial state and Γ(1) = 1 is the target state.

[0282] A quantum annealer can be programmed by a Hamiltonian operator

Number

[0283] The classical Hamiltonian can be defined as follows for either the classical case, the semi-classical case, or the quantum case. H(x) = Γ T Φ(x)

[0284] Φ(x) is a vector when the schedule has two or more components. In the quantum case, the classical Hamiltonian can be constructed by the Trotter slice trick. In the quantum (or semiclassical) case, the first component Φ i (x) is the classical energy statistic, which is conjugate to the energy scale (E) and models the variables that are the diagonal components in the operator expression. The second component Φ2(x) is conjugate to logΔ and is a quantum energy function since it does not exist in the diagonalized operator.

[0285] The equilibrium energy distribution along the path within the trajectory can be evaluated. The distribution can be approximated by a Gaussian distribution and modeled by a mean value and a covariance Σ. The quality of the schedule can be judged by the product of the energy fluctuations along the trajectory and the speed at which the annealer progresses along the trajectory. One approach is to maximize the following objective function subject to the boundary conditions. [Number]

[0286] In the case where Γ(t) is a scalar or a function of one parameter (e.g., the presented classical case), there may exist a simple and straightforward solution to the above equation, for example, using the following equation. [Number]

[0287] In the case where Γ(t) is a vector or a function of two or more parameters (e.g., the presented quantum case), one approach is to perform a local search method to find Γ. Another approach is to try to optimize a weighted combination of functions that satisfy the boundary conditions.

[0288] The Gaussian approximation can be suitable for a wide variety of distributions because the distribution error can accumulate over many steps or the entire iteration, and the central limit theorem applies to the accumulation of errors.

[0289] If the target model has a zero transverse magnetic field (or a large energy scale), the Gaussian approximation may no longer be applicable. Optimization regarding at least a part of the schedule may be possible. When the energy variance becomes close enough to zero, the schedule can be terminated by quenching (i.e., proceeding very rapidly), and the above-described procedure is not required at this stage.

[0290] The energy statistics used for model optimization can be collected, for example, by annealed importance sampling or parallel tempering.

[0291] The energy variance can be used to determine the schedule of thermal annealing (see, for example, Kone and Kofke, 2005). The systems and methods of the present disclosure address the difficult problem of determining the schedule of quantum annealing.

[0292] The energy statistics of a physical quantum annealer can be inferred. In one embodiment, the quantum hardware can be modeled as stoquastic (i.e., a function of the transverse magnetic field, energy scale, and physical temperature). In this case, the equilibrium state characteristics of the hardware can be measured using quantum Monte Carlo methods.

[0293] The hardware dynamic characteristics can affect the degree of success. The systems and methods of the present disclosure are likely to produce beneficial results for many problem classes using the schedule optimized as described above. The degree of success can be measured, for example, by generating two different schedules, predicting the quality of samples of many problems, and determining whether there is a positive correlation with the quality of the output samples. The quality of the output samples can be measured, for example, by using KL divergence, the ground state frequency, or another suitable metric.

[0294] The benefits of the disclosed system and method may include some or all of the following: ● Selection of a suitable Hamiltonian annealing schedule that can be implemented without relying on dynamic insights; ● Selection of an annealing schedule based on inferred equilibrium energy statistics; ● Selection of an annealing schedule for a physical quantum annealer based on input from quantum simulations.

[0295] Figure 13 is a flowchart showing an exemplary method 1300 for adjusting an annealing schedule based on equilibrium energy statistics. At 1305, method 1300 begins. At 1310, the hybrid computer collects energy statistic values by parallel tempering with respect to the classical Hamiltonian, Hamiltonian operator, or classical approximation to the Hamiltonian operator of the problem. The problem can be a problem selected to represent a particular problem or a group of problems.

[0296] At 1320, the hybrid computer evaluates a fixed Γ formula to determine the expected quality of the results of the selected problem or group of problems. At 1330, the hybrid computer determines a preferred or optimized rate (given a fixed trajectory within Γ) by inverting the cumulative distribution function. At 1340, the hybrid computer determines a preferred or optimized trajectory by performing local search. As described above, the local search at 1340 can be replaced by a method that attempts to optimize a weighted combination of functions that satisfy the boundary conditions.

[0297] At 1345, the hybrid computer determines whether to repeat acts 1330 and 1340. If it is determined at 1345 to repeat, method 1300 proceeds to 1330. If it is determined at 1345 not to repeat, method 1300 proceeds to 1350 until, for example, it is called again, and the method ends. The repetition is optional as indicated by the dashed line in Figure 13.

[0298] Selection of Annealing Schedule Based on Objective Function In some embodiments, an annealing schedule for a problem executable by an analog processor is selected by a digital processor based on an objective function. An example of such a selection method 2000 is shown as a flowchart in FIG. 20. At 2005, the problem is received by a digital processor on which an annealing schedule is to be generated.

[0299] At 2010, the objective function is selected by the digital processor. The objective function can be determined (e.g., can be determined in advance (which can be considered a kind of selection in the present disclosure)), can be selected by the user, can be selected according to the characteristics of the problem, can be selected based on another action in the method (e.g., techniques applied at 2015 and / or 2020), and / or can be selected in another way. The objective function can at least partially measure one or more characteristics of the annealing schedule and provide various measures based on these characteristics to various annealing schedules (although various annealing schedules do not necessarily receive the same measure in every instance).

[0300] For example, the objective function can provide a measure of the degree to which "executing the annealing schedule improves, degrades, or otherwise changes the performance of the problem." For example, the objective function can provide a measure of sample quality (if the problem is related to sampling), computational success rate (e.g., if the problem is associated with constraints that can be violated due to the analog nature of the computation), computational efficiency (e.g., time-to-solution metric), and / or some other measure related to the performance of the problem executed according to the candidate annealing schedule.

[0301] In 2015, one or more annealing schedules are generated by a digital processor. For example, a set of candidate annealing schedules can be generated by a user or a remote computing system and received by the digital processor, and / or a set of candidate annealing schedules can be generated according to a series of calculations performed by the digital processor. In some embodiments, the annealing schedule is generated by a computing system by performing an optimization algorithm based on an objective function. An exemplary implementation of a method 2000 using such an optimization algorithm is described in further detail below.

[0302] In 2020, the annealing schedule is selected by a digital processor based on an objective function. For example, in 2020, the annealing schedule can be selected from a set of candidate annealing schedules by determining which of the annealing schedules within the group provides the optimal result (as used in this disclosure, "optimal" is used in the sense of "optimal among the choices considered" and is not necessarily the single most ideal annealing schedule possible). For example, if the objective function provides a measure of time versus solution, an annealing schedule that minimizes the objective function can be selected. In some embodiments, an annealing schedule that maximizes the objective function can be selected. In some embodiments, act 2020 can select an annealing schedule, which is then used in 2015 to generate another annealing schedule, and the other annealing schedule can then result in various annealing schedules being selected.

[0303] In at least some embodiments, generating and selecting an annealing schedule can be performed continuously and / or otherwise by a digital processor via a single act or operation as interleaved or overlapping acts or operations. For example, method 2000 can include performing an optimization algorithm that includes selectively generating and evaluating an annealing schedule repeatedly to generate an optimized annealing schedule. Thus, acts 2015 and 2020 are not necessarily clearly separated in some embodiments. For convenience, acts 2015 and 2020 may sometimes be referred to together as act 2022, whether or not acts 2015 and 2020 are considered separately in a particular embodiment.

[0304] The annealing schedule can be selected for its optimality of that measure compared to other candidate annealing schedules, but does not necessarily have to provide better calculation results than each other candidate annealing schedule (e.g., here the objective function provides a heuristic measure that is not perfectly correlated with the quality of the calculation results). For example, an objective function that is relatively easy to calculate and provides relatively consistent improvement to the calculation results may be more suitable in some situations than an objective function that is relatively expensive to calculate and provides only a small (and / or inconsistent) different improvement.

[0305] In 2025, the optimal annealing schedule (selected in 2020) is returned. Next, the optimal annealing schedule can be used by the analog processor in the process of calculating the problem received in 2005 and / or related problems.

[0306] The inventors have identified, through experiments and theory, several combinations of optimization algorithms and objective functions that (tend to provide annealing schedules that result in improvements to the calculations of their corresponding problems, at least in some situations and for at least some problems). These examples include optimizations for avoiding phase transitions (e.g., via parallel tempering) and Bayesian optimization. Embodiments thereof are described in further detail below.

[0307] In some embodiments, the objective function selected in 2010 measures the ability of an annealing schedule to reduce floppiness during annealing and / or avoid phase transitions. The objective function can measure the ability to avoid phase transitions directly (e.g., by running the problem multiple times with the annealing schedule and determining the frequency of phase transitions) and / or indirectly (e.g., by measuring a characteristic of the annealing schedule that is a proxy ) for that ability to avoid phase transitions during annealing).

[0308] For example, the objective function can describe many models (also called replicas) generated by a parallel tempering algorithm (e.g., a quantum parallel tempering algorithm) in 2022 and / or the chains that link the models. Parallel tempering can be performed on a problem (modified by the described annealing schedule) by a digital processor, thereby generating many models linked by the chains.

[0309] The parallel tempering algorithm is sometimes described as placing models along a path that exists in a two-dimensional space where the dimensions are the energy scale and temperature. Annealing schedules that tend to reduce floppiness and / or avoid phase transitions require, in at least some situations, a particular efficiency between adjacent models for fewer models at the end directions of paths in the higher energy regions of this space. Thus, such annealing schedules can result in a parallel tempering algorithm that produces fewer models overall. Thus, in at least some situations, many Annealing schedules that minimize an objective function that describes the models (and / or chains linking the models) tend to reduce floppiness during annealing and / or avoid phase transitions.

[0310] The objective function based on the placement of models in the parallel tempering algorithm can be calculated relatively efficiently by performing a limited number of iterations (or "sweeps") of the parallel tempering algorithm. It is understood that the parallel tempering algorithm can be used to directly solve problems received in 2005, but this can require many iterations (often hundreds of thousands or millions of iterations). However, finding an efficient placement of models usually requires far fewer iterations (on the order of thousands or tens of thousands of iterations in at least some cases). Thus, a modified (partial) parallel tempering algorithm that terminates after fewer iterations than can be performed to solve the problem can be used.

[0311] In some embodiments, act 2022 includes Bayesian optimization. In some such embodiments, the objective function selected in 2010 provides a measure of the ground state distribution of the problem (corrected by the measured annealing schedule) as performed by a digital processor. Such a measure may correlate with the uniformity of the distribution and / or the characteristics of outliers within the distribution. For example, the objective function may provide an entropy measure of the ground state distribution, a distance of the ground state distribution from a uniform distribution, a Gini coefficient of the ground state distribution, a width of the ground state distribution (e.g., a ratio of the minimum probability to the maximum probability), and / or some other measure of the ground state distribution. In at least some embodiments, the Bayesian optimization algorithm aims to maximize an entropy-based objective function and minimize the other above objective functions.

[0312] Any suitable acquisition function and surrogate model may be used. In some embodiments, the Bayesian optimization algorithm is performed by using an expected improvement acquisition function and a Gaussian process of the surrogate model. Alternative (or additional) acquisition functions include a probability of improvement and a confidence upper bound. Alternative (or additional) surrogate models include linear models, regression trees and random forests, and neural networks. Once suitable objective functions, acquisition functions and surrogate models are selected, Bayesian optimization may be performed to generate and select an optimal annealing schedule.

[0313] Auxiliary qubit delta tuning During quantum annealing, the effect of degeneracy can be reduced and the hardware performance can be improved by advancing or retarding the floppy qubits or the floppy region of the qubits. The reduction can be achieved by using a local CCJJ DAC bias. Advancing or retarding the floppy qubits reduces the tunneling rate Δ q Quantum hardware for reducing In this case, the persistent current can be desynchronized, leading to errors in the qubit bias and coupling terms (h and J respectively). The errors can be corrected once during the quantum annealing process, but advancing or retarding the floppy qubits can introduce time-dependent errors in h and J in the device being mitigated. As a result, the final Hamiltonian can be distorted by the mitigation process.

[0314] The systems and methods of the present disclosure include another approach to mitigation that uses ancillary qubits instead of local CCJJ DAC biases. In this approach, qubits within a quantum processor can have associated ancillary qubits that can be tunably coupled with an intensity J. In one embodiment, the ancillary qubits are dedicated ancillary devices associated with the processor qubits. In another embodiment, the ancillary qubits are processor qubits reserved for use as ancillary qubits rather than being used as computational qubits.

[0315] The floppy qubits or floppy regions can be identified using a small number of samples via the initial Hamiltonian. The ancillary qubits can be coupled to the floppy qubits or regions with a coupling strength J designed to modify the dynamical properties of the floppy qubits or regions. In some cases, the coupling strength J is designed to slow down the dynamical properties of the floppy qubits or regions.

[0316] Coupling the floppy qubits and the ancillary qubits can modify the tunneling amplitude of the floppy qubits as follows:

Equation

[0317] In one embodiment, the auxiliary device is present on a separate annealing line to a floppy qubit. In another embodiment, the CCJJ DAC within the quantum processor can be used to further modify the dynamic characteristics of the auxiliary device by reducing ancilla Δ . Orthogonal control of Δ floppy and |I p | can be achieved in this way by removing or at least reducing the time-dependent errors of h and J.

[0318] FIG. 14 is a flowchart showing an exemplary method 1400 for reducing the effects of degeneracy using an auxiliary qubit. The method 1400 shown in FIG. 14 includes a plurality of acts. One or more of these acts can be performed by (or via) one or more circuits (e.g., one or more processors (e.g., digital processors), and analog processors such as quantum processors, or a hybrid computer including both digital and analog processors). For the purposes of the description of FIG. 14, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 1400 illustrates an exemplary embodiment. Those skilled in the art will recognize that alternative embodiments may omit some acts and / or include additional acts.

[0319] The method 1400 starts at 1405. At 1410, the hybrid computer sends a computational problem to the quantum hardware. At 1415, the hybrid computer collects a set of samples from the quantum hardware. At 1420, the hybrid computer determines whether a qubit (or region of qubits) is floppy within the sample by inverting the qubit state and determining whether it changes the energy of the sample.

[0320] At 1425, the hybrid computer determines whether there is another sample. If the hybrid computer determines at 1425 that there is another sample, method 1400 returns to 1420. If the hybrid computer determines at 1425 that there is no other sample, method 1400 proceeds to 1430.

[0321] At 1430, the hybrid computer generates a "normalized floppiness metric" μ that describes a part of the sample where the qubit is floppy i as follows : μ i = n i / N where n i is the number of times the qubit is floppy, and N is the number of samples used to generate the metric.

[0322] The floppiness metric is an exemplary metric that can be used. In other embodiments, another suitable metric is used. More generally, the disclosed systems and methods can include collecting samples and then processing the samples to determine which qubits and how much to advance (or delay). The processing is not limited to determining floppiness or a floppiness metric. Another suitable processing method can be used to determine which qubits and how much to advance (or delay).

[0323] At 1435, the hybrid computer adds an auxiliary qubit to the floppy qubit and then combines this with the strength J as described above to modify the tunneling amplitude. In one embodiment, an auxiliary qubit is added for each floppy qubit. In another embodiment, an auxiliary qubit is added for each subset of floppy qubits. In one embodiment, Δ floppy ≈ Δ q (1 - μ i ).

[0324] At 1440, the hybrid computer determines whether there are other qubits. If the hybrid computer determines at 1440 that there are other qubits, method 1400 returns to 1420. If the hybrid computer determines at 1440 that there are no other qubits, method 1400 proceeds to 1445.

[0325] At 1445, the hybrid computer determines whether it should collect another set of samples. If the hybrid computer determines at 1445 that it should collect another set of samples, method 1400 returns to 1415. If the hybrid computer determines at 1445 that it should not collect another set of samples, method 1400 proceeds to 1450.

[0326] Correct the h / J mismatch using an auxiliary qubit Quantum annealing may involve evolving a time-dependent Hamiltonian from a simple superposition to a useful classical problem. A drawback of quantum annealing is that "the annealer can be biased towards an undesirable state if the state is unfavorable for the final Hamiltonian but still favorable for an earlier intermediate Hamiltonian during annealing." This can occur, for example, if both the h (qubit bias) term and the J (coupling) term are used. It is possible to give the bias term a relatively higher priority than the coupling term at an early stage during annealing. This can result in a time-dependent h / J mismatch that pushes the annealer towards an undesirable subspace (or valley in the energy landscape). To find the preferred or correct solution, the annealer tunnels from the undesirable subspace to another valley.

[0327] The mismatch is that the coupling terms in the Ising Hamiltonian usually have an expectation value that is early during annealing This can occur because the bias term is weighted by a product of at least two Pauli matrices that have a smaller magnitude early during the anneal. In contrast, the bias term is usually weighted by a single Pauli matrix that has a higher expected magnitude than the coupling term early during the anneal, as follows:

number

[0328] The systems and methods disclosed herein provide techniques for mitigating the above-mentioned h / J mismatch. This method estimates each local bias h i This involves shifting the quantum bit to an auxiliary quantum bit. Q i and the input bias h i = x, the auxiliary qubit q' i can be added, resulting in a large negative balance. Ias (e.g., h' i =-2) is the ancillary qubit q' i The bias can typically be provided to the ancillary qubit q' i The bias on the Then, the qubit q i and the auxiliary qubit q' i The coupling between qubits is set to x and qubit q i The upper bias can be set to 0. If the input bias |x|≦1, If so, this is within the range of acceptable combiner values.

[0329] In one embodiment, if |x|<<1, the qubit and ancillary qubit may be coupled by a coupler having a value of −1, and the bias on x may be adjusted to the ancillary qubit (h′ i =x). In another embodiment, |x|< If it is 1, the state is treated in the same manner as described in the previous paragraph for the general case of |x|.

[0330] If |x|>1, the bias hi Part of it can be shifted to the coupling with the auxiliary qubit q'. i In one embodiment, part of the bias is shifted to the coupling of a single auxiliary qubit. In another embodiment, part of the bias is shifted to two or more auxiliary qubits.

[0331] FIG. 15 is a flowchart showing an exemplary method 1500 for reducing the h / J mismatch using an auxiliary qubit. The method 1500 shown in FIG. 15 includes a plurality of acts. One or more of these acts can be performed by (or via) one or more circuits (e.g., one or more processors (e.g., digital processors), and analog processors such as quantum processors, or a hybrid computer including both digital and analog processors). For the purposes of the description of FIG. 15, it is assumed that the acts are performed by a hybrid computer including a quantum processor. The method 1500 describes an exemplary embodiment. Those skilled in the art will recognize that alternative embodiments may omit some of the acts and / or include additional acts.

[0332] The method 1500 starts at 1505. At 1510, the hybrid computer receives the bias of the qubit. At 1515, the hybrid computer adds an auxiliary qubit. At 1520, the hybrid computer determines whether the bias is 1 or less. If the hybrid computer determines at 1520 that the bias is 1 or less, the method 1500 proceeds to 1525. At 1525, the hybrid computer determines whether the bias is much less than 1. If the hybrid computer determines at 1525 that the bias is much less than 1, the method 1500 proceeds to 1530. At 1530, the hybrid computer couples the qubit and the auxiliary qubit with a coupler of value -1. At 1535, the hybrid computer gives the qubit bias to the auxiliary qubit, and the method 1500 proceeds to 1540.

[0333] If the hybrid computer determines at 1525 that the bias is not much less than 1, method 1500 proceeds to 1545. At 1545, the hybrid computer applies a large negative bias (e.g., -2) to the auxiliary qubit. At 1550, the hybrid computer sets the coupling between the qubit and the auxiliary qubit to the input bias value. At 1555, the hybrid computer sets the bias of the qubit to zero, and method 1500 proceeds to 1540.

[0334] If the hybrid computation determines at 1520 that the bias is greater than 1, method 1500 proceeds to 1560. At 1560, the hybrid computer moves a part of the input bias to the coupling to the auxiliary qubit, and method 1500 proceeds to 1540.

[0335] At 1540, the hybrid computer determines whether there is another qubit for which bias adjustment can be made. If the hybrid computer determines at 1540 that "there is another qubit for which bias adjustment can be made", method 1500 returns to 1510.

[0336] If the hybrid computer determines at 1540 that "there is no other qubit for which bias adjustment can be made", method 1500 returns to and proceeds to 1565. At 1565, method 1500 ends.

[0337] Hybrid computing system including a quantum processor FIG. 16 illustrates an exemplary hybrid computing system 1600 that includes a digital computer 1605 coupled to an analog computer 1651. In some embodiments, the analog computer 1651 is a quantum computer and the digital computer 1605 is a classical computer. The exemplary digital computer 1605 includes a digital processor that can be used to perform classical digital processing tasks described in this system and method. Those skilled in the art will understand that this system and method can be implemented by other digital computer configurations including, but not limited to, a portable device, a multiprocessor system, a microprocessor-based or programmable consumer electronics device, a personal computer (PC), a network PC, a minicomputer, a mainframe computer, etc., when the system and method are properly configured or programmed to form a dedicated machine and / or when communicatively coupled to control an analog computer (e.g., a quantum computer).

[0338] Although the digital computer 1605 will be referred to herein in the singular, this is not intended to limit the application to a single digital computer. This system and method can also be implemented in a distributed computer environment where tasks or a set of processor-readable instructions are performed or executed by a remote processing device linked via a communication network. In a distributed computing environment, computers or processor-readable instructions (sometimes known as program modules), application programs, and / or data can be located in both local and remote storage devices (e.g., non-transitory computer or processor-readable media).

[0339] The digital computer 1605 can include at least one digital processor (such as a central processing unit) 1610, at least one system memory 1620, and at least one system bus 1617 that couples various system components including the system memory 1620 to the digital processor 1610.

[0340] The digital processor(s) 1610 can be, for example, one or more cores (e.g., one or more central processing units (CPUs), graphics processing units) ( GPUs: graphics processing units), digital signal processors (DSPs), application-specific integrated circuits (ASICs), or any logical processing unit having a field-programmable gate array (FPGA). Unless otherwise stated, the structures and operations of the various blocks shown in FIG. 16 are of conventional design. As a result, such blocks are understood by those skilled in the art and need not be described in further detail herein.

[0341] The digital computer 1605 can include a user input / output subsystem 1611. In some embodiments, the user input / output subsystem includes one or more user input / output components such as a display 1612, a mouse 1 613, and / or a keyboard 1614. The system bus 1617 can employ any known bus structure or architecture including a memory bus to a memory controller, a peripheral bus, and a local bus. The system memory 1620 can include non-volatile memory such as read-only memory (ROM), static random access memory (SRAM), flash NAND, and volatile memory such as random access memory (RAM) (not shown). All of these are examples of non-transitory computer or processor-readable media. The basic input / output system (BIOS) 1621, which can form a part of the ROM, includes basic routines that assist in transferring information between elements within the digital computer 1605 during startup periods and the like.

[0342] Digital computer 1605 may also include other non-volatile memories 1615. The non-volatile memory 1615 may adopt various forms including a hard disk drive for reading from and writing to a hard disk, an optical disk drive for reading from and writing to a removable optical disk, and / or a magnetic disk drive for reading from and writing to a magnetic disk. All of these are examples of non-transitory computer or processor-readable media. The optical disk may be a CD-ROM or a DVD, while the magnetic disk may be a magnetic floppy disk or a diskette. The non-volatile memory 1615 may communicate with the digital processor via the system bus 1617 and may include an appropriate interface or controller 1616 coupled to the system bus 1617. The non-volatile memory 1615 may serve as a long-term storage device for computer or processor-readable instructions, data structures, or other data (also called program modules) of the digital computer 1605.

[0343] Although digital computer 1605 has been described as employing a hard disk, an optical disk, and / or a magnetic disk, those skilled in the art will understand that other types of non-volatile computer-readable media such as magnetic cassettes, flash memory cards, flash, ROM, smart cards, etc. may be employed. All of these are another example of non-transitory computer or processor-readable media. Those skilled in the art will understand that some computer architectures combine volatile memory and non-volatile memory. For example, data in volatile memory may be cached to non-volatile memory. Or a solid state disk that employs an integrated circuit to provide non-volatile memory. Some computers place data that is traditionally stored on a disk into memory. Similarly, some media that are traditionally considered volatile may have a non-volatile form (e.g., a non-volatile dual in-line memory module which is a variant of a dual in-line memory module).

[0344] Various sets of computer or processor-readable instructions (also referred to as program modules), application programs, and / or data may be stored within system memory 1620. For example, system memory 1620 may store operating system 1623 and a set of computer or processor-readable server instructions (i.e., server module) 1625. In some embodiments, server module 1625 includes instructions for communicating with remote clients and scheduling the use of resources including resources on digital computer 1605 and analog computer 1651. For example, a web server application and / or web client or browser application to enable digital computer 1605 to exchange data not only with sources but also with other server applications executing on a server computer via the Internet, a corporate intranet, or other network.

[0345] In some embodiments, system memory 1620 may store other sets of computer or processor-readable instructions 1627 such as compute instructions, analog computer interface instructions.

[0346] Although shown as being stored within system memory 1620 in FIG. 16, the modules and other data shown may also be stored elsewhere including within non-volatile memory 1615 or within one or more other non-transitory computer or processor-readable media.

[0347] The analog computer 1651 can be provided in an isolated environment (not shown). For example, if the analog computer 1651 is a quantum computer, the environment shields the internal elements of the quantum computer from heat, magnetic fields, etc. and other external noises (not shown), and / or cools the analog processor to a temperature at which the circuit system of the analog processor exhibits superconductivity (i.e., the critical temperature) or below. In contrast, the digital computer 1605 typically operates at a much higher temperature (e.g., room temperature) at which superconductivity does not occur, and / or the digital computer 1605 can employ materials that do not superconduct even below the critical temperature. The analog computer 1651 includes an analog processor 1640. Examples of the analog processor 1640 include quantum processors such as those described below with reference to FIG. 13.

[0348] The quantum processor includes programmable elements such as qubits, couplers, and other devices. The qubits are read out via a readout system 1660. These results are sent to various sets of computer or processor-readable instructions of the digital computer 1605 including the server module 1625 or other modules 1627, stored in the non-volatile memory 1615, and returned over a network or the like. The qubits are controlled via a qubit control system 1665. The couplers are controlled via a coupler control system 1670. In some embodiments, the qubit control system 1665 and the coupler control system 1670 are used to perform quantum annealing on the analog processor 1640 as described herein.

[0349] In some embodiments, digital computer 1605 may operate within a networking environment using logical connections to at least one client computer system. In some embodiments, digital computer 1605 is coupled via a logical connection to at least one database system. These logical connections may be formed using any means of digital communication via a network such as, for example, a local area network (LAN) or a wide area network (WAN) such as the Internet. The networking environment may include a wired or wireless enterprise-scale computer network, an intranet, an extranet, and / or the Internet. Other embodiments may include other types of communication networks such as remote communication networks, cellular networks, paging networks, and other mobile networks. The information transmitted or received via the logical connection may or may not be encrypted. When used in a LAN networking environment, digital computer 1605 may be connected to the LAN via an adapter or network interface card (NIC) communicatively coupled to system bus 1617. When used within a WAN networking environment, digital computer 1605 may include devices such as an interface and a modem (not shown) or a NIC for establishing communication over the WAN. Non-network communication may additionally or alternatively be employed. In some embodiments, digital computer 1605 may operate within a networking environment using logical connections to at least one client computer system. In some embodiments, digital computer 1605 is coupled via a logical connection to at least one database system. These logical connections may be formed using any means of digital communication via a network such as, for example, a local area network (LAN) or a wide area network (WAN) such as the Internet. The networking environment may include a wired or wireless enterprise-scale computer network, an intranet, an extranet, and / or the Internet. Other embodiments may include other types of communication networks such as remote communication networks, cellular networks, paging networks, and other mobile networks. The information transmitted or received via the logical connection may or may not be encrypted. When used in a LAN networking environment, digital computer 1605 may be connected to the LAN via an adapter or network interface card (NIC) communicatively coupled to system bus 1617. When used within a WAN networking environment, digital computer 1605 may include devices such as an interface and a modem (not shown) or a NIC for establishing communication over the WAN. Non-network communication may additionally or alternatively be employed.

[0350] Exemplary superconducting quantum processor for quantum annealing FIG. 17 is a schematic diagram of a portion of an exemplary superconducting quantum processor 1700 designed for quantum annealing (and / or adiabatic quantum computing) components that may be used to implement the present system and devices. A portion of the superconducting quantum processor 1700 shown in FIG. 17 includes two superconducting qubits 1701, 1702. Qubits 1701, 17 A tunable coupling (diagonal coupling) (i.e., providing a two-local interaction) via a coupler 1710 between qubits 02 is also shown. A part of the quantum processor 1700 shown in FIG. 17 includes only two qubits 1701, 1702 and one coupler 1710, but those skilled in the art will recognize that the quantum processor 1700 may include any number of qubits and any number of couplers that couple information between them.

[0351] A part of the quantum processor 1700 shown in FIG. 17 may be implemented to physically realize quantum annealing and / or adiabatic quantum computing. The quantum processor 1700 includes a plurality of interfaces 1721-1725 used to configure and control the state of the quantum processor 1700. Each of the interfaces 1721-1725 may be realized by its respective inductive coupling structure as shown as part of a programming subsystem and / or an evolution subsystem. Such a programming subsystem and / or an evolution subsystem may be separate from the quantum processor 1700 or may be included locally (i.e., may be on-chip with the quantum processor 1700).

[0352] During operation of the quantum processor 1700, the interfaces 1721, 1724 each couple a magnetic flux signal into the respective composite Josephson junctions 1731, 1732 of the qubits 1701, 1702, thereby tuning the tunable tunneling term (Δ i term) can be used to realize in the system Hamiltonian. This coupling provides the off-diagonal σ x terms of the Hamiltonian, and these magnetic flux signals are examples of "delocalized signals".

[0353] In some embodiments, the tunneling term is selected to make a first part of a qubit on the quantum processor classical compared to a second part of the qubit. For example, qubit 1701 may be a hidden unit in a Boltzmann machine and may have a smaller tunneling term compared to qubit 1702.

[0354] Similarly, interfaces 1722 and 1723 can each be used to apply a magnetic flux signal into respective qubit loops of qubits 1701 and 1702, thereby realizing the hi term in the system Hamiltonian. This coupling provides the diagonal σ z term in the system Hamiltonian. Further, interface 1725 couples a magnetic flux signal into coupler 1710, thereby being used to realize the J ij term in the system Hamiltonian. This coupling provides the diagonal

Number

[0355] In FIG. 17, the respective contributions of interfaces 1721 - 1725 to the evolution Hamiltonian are shown in boxes 1721a - 1725a, respectively. As shown, in the example of FIG. 17, boxes 1721a - 1725a are elements of the time - varying Hamiltonian for quantum annealing and / or adiabatic quantum computing.

[0356] Throughout this specification and the appended claims, the term "quantum processor" is used to generally describe a collection of physical qubits (e.g., qubits 1701, 1702) and couplers (e.g., coupler 1710). The physical qubits 1701, 1702 and coupler 1710 are referred to as "programmable elements" of quantum processor 1700, and their corresponding parameters (e.g., qubit h i value, coupler J ij value) are referred to as "programmable parameters" of the quantum processor. In the context of a quantum processor, the term "programming sub routine" The "system" is used to generally describe the programmable elements of the quantum processor 1700 and other associated control circuitry and / or interfaces (e.g., "programming interfaces" 1722, 1723, 1725) used to apply programmable parameters to instructions.

[0357] As described above, the programming interfaces of the programming subsystem may communicate with other subsystems that may be separate from or locally included on the quantum processor. As will be described in more detail later, the programming subsystem may be configured to receive and execute machine language program instructions of the quantum processor to program the programmable elements according to the program instructions. Similarly, in the context of the quantum processor, the term "evolution subsystem" is used to generally describe the programmable elements of the quantum processor 1700 and other associated control circuitry and / or interfaces (e.g., "evolution interfaces" 1721 and 1724) used to evolve instructions. For example, the evolution subsystem may include interfaces (1721, 1724) to the annealing signal lines and their corresponding qubits (1701, 1702).

[0358] The quantum processor 1700 also includes readout devices 1751, 1752. The readout device 1751 is associated with the qubit 1701, and the readout device 1752 is associated with the qubit 1702. In some embodiments as shown in FIG. 17, each of the readout devices 1751, 1752 includes a DC-SQUID inductively coupled to the corresponding qubit. In the context of the quantum processor 1700, the term "readout subsystem" is generally used to describe generally the readout elements 1751, 1752 used to read the final state of qubits (e.g., qubits 1701 and 1702) in the quantum processor to generate a bit string. The readout subsystem may also include other elements such as routing circuits (e.g., latch elements, shift registers or multiplexer circuits), and / or may be arranged in alternative configurations (e.g., XY-addressable arrays, XYZ-addressable arrays, etc.). Quantum bit readout may also be performed using alternative circuits such as those described in PCT Patent Application International Publication No. 2012064974.

[0359] FIG. 17 shows only two physical qubits 1701, 1702, one coupler 1710, and two readout elements 1751, 1752, but a quantum processor (e.g., processor 1700) may employ any number of qubits, couplers, and / or readout elements, including a large number (e.g., hundreds, thousands, or more) of qubits, couplers, and / or readout elements. The application of the teachings herein to processors having different (e.g., larger) numbers of computer components should be readily apparent to those of ordinary skill in the art.

[0360] Examples of superconducting qubits include superconducting flux qubits, superconducting charge qubits, etc. In a superconducting flux qubit, the Josephson energy is greater than or equal to the charging energy. In a charge qubit, this is reversed. Examples of flux qubits that can be used include an rf-SQUID including a superconducting loop interrupted by one Josephson junction, a persistent current qubit including a superconducting loop interrupted by three Josephson junctions, and the like.

[0361] The qubits and coupling devices within a quantum processor can be arranged within a topology based on an architecture such that a fixed number of qubits can be arranged in a sub-topology of the qubits (hereinafter simply referred to as "sub-topology"). The sub-topology is part of a quantum processor topology that includes qubits and coupling devices. Multiple sub-topologies may be repeated across the area of the quantum processor to generate a certain quantum processor topology or may be tiled (or otherwise directly communicatively coupled to each other).

[0362] In some embodiments, each sub-topology within the topology is identical to each other sub-topology within the same topology. In other embodiments, one or more sub-topologies within the topology include qubits and coupling devices of a different configuration than another sub-topology within the same topology.

[0363] The above description of the illustrated embodiments, including those set forth in the abstract, is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. Specific embodiments and examples have been described herein for illustrative purposes, but various equivalent modifications can be made without departing from the spirit and scope of the present disclosure as will be recognized by those skilled in the art. The teachings described herein for the various embodiments can be applied to other analog processors and are not necessarily limited to the exemplary quantum processors outlined above.

[0364] The various embodiments described above may be combined to provide another embodiment. To the extent not inconsistent with the specific teachings and definitions herein, all of the U.S. patent application publications, U.S. patent applications, U.S. patents, foreign patents, and foreign patent applications referenced herein and / or listed in the Application Data Sheet and commonly assigned to D-Wave Systems Inc., including but not limited to the following patents, are hereby incorporated by reference in their entirety: U.S. Patent No. 7,984,012; U.S. Patent No. 8,244,662; U.S. Patent No. 8,174,305; U.S. Patent No. 8,670,807; U.S. Patent No. 8,700,689; PCT Patent Application Publication No. WO 2012 / 064974; U.S. Patent Application No. 2015 / 0032994; U.S. Provisional Patent Application No. 62 / 247,085, filed October 27, 2015; U.S. Provisional Patent Application No. 62 / 324,210, filed April 18, 2016; U.S. Provisional Patent Application No. 62 / 331,288, filed May 3, 2016; U.S. Provisional Patent Application No. 62 / 399,764, filed September 26, 2016; U.S. Provisional Patent Application No. 62 / 375,785; and U.S. Provisional Patent Application No. 62 / 399,683 (Attorney Docket No. 240105.581P1), filed as a document entitled "System, Method and Device for Sampling from a Sampling Server". Aspects of the embodiments may be modified as necessary to adopt the systems, circuits and concepts of various patents, applications and publications to provide yet another embodiment.

[0365] These and other modifications may be made to the above-described embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed herein, but should be interpreted to include all possible embodiments along with the full scope of equivalents to which such claims are entitled. Accordingly, the claims are not limited by the present disclosure.

Claims

1. A method for degeneracy reduction in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of devices and operates as a sample generator for providing samples, the method comprising: sending a problem to the quantum processor; until an end determination criterion is satisfied: drawing a plurality of samples by the quantum processor; returning the plurality of samples to the digital processor; initializing a sample counter; until the sample counter reaches a predetermined sample limit: initializing a device counter; until the device counter reaches a first predetermined device limit: determining whether the device indexed by the device counter is floppy; repeatedly incrementing the device counter; incrementing the sample counter; initializing the device counter; until the device counter reaches a second predetermined device limit: calculating a normalized floppiness metric of the device indexed by the device counter; adding an offset to advance the device during annealing; incrementing the device counter, the method comprising.

2. The method according to claim 1, further comprising determining whether an end condition is satisfied.

3. Determining whether an end condition is satisfied includes at least one of completing a predetermined number of repetitions, reaching a predetermined upper limit of an allowable calculation time, or determining that a change in energy of a solution to the problem between consecutive repetitions is less than a predetermined threshold, the method according to claim 2.

4. Degeneracy reduction in a hybrid computing system including a quantum processor includes reducing degeneracy in a hybrid computing system including a superconducting quantum processor, the method according to claim 1.

5. Determining whether the device indexed by the device counter is floppy includes determining whether the superconducting qubit indexed by the device counter is floppy, the method of claim 4.

6. Determining whether the superconducting qubit indexed by the device counter is floppy includes determining that the change in energy of the solution to the problem is less than a predetermined threshold when the state of the superconducting qubit is inverted, the method of claim 5.

7. Determining whether the superconducting qubit indexed by the device counter is floppy includes determining the spread of the net zero bias from neighboring devices, the method of claim 5.

8. Normalized floppiness Calculating a ness metric for the device indexed by the device counter includes summing the number of times the device is determined to be floppy and dividing this by the predetermined sample limit, the method of claim 1.

9. The first predetermined device limit is the same as the second predetermined device limit, the method of claim 1.

10. Pulling a plurality of samples by the quantum processor includes pulling at least 1000 samples by the quantum processor, the method of claim 1.

11. Determining whether the device indexed by the device counter is floppy includes determining whether the region of the qubit indexed by the device counter is floppy, the region of the qubit including a plurality of coupled qubits, the method of claim 1.

12. Sending a problem to the quantum processor includes sending a difficult problem to the quantum processor, the method of claim 1.

13. At least one quantum processor including a plurality of devices and a readout subsystem; At least one digital-processor-based device communicatively coupled to the at least one quantum processor; In a hybrid computing system including at least one non-transitory computer-readable storage medium storing processor-executable instructions for reducing degeneracy, the at least one non-transitory computer-readable storage medium, when executed, causes at least one processor-based device to: send the problem to the quantum processor; until an end criterion is satisfied: draw a plurality of samples by the quantum processor; return the plurality of samples to the digital processor via the readout system; initialize a sample counter; until the sample counter reaches a predetermined sample limit: initialize a device counter; until the device counter reaches a first predetermined device limit: determine whether the device indexed by the device counter is floppy; repeatedly increment the device counter; increment the sample counter; initialize the device counter; until the device counter reaches a second predetermined device limit: calculate a normalized floppiness metric of the device indexed by the device counter; add an offset to advance the device during annealing; increment the device counter, a hybrid computing system.

14. The quantum processor is a superconducting quantum processor, the plurality of devices includes a plurality of superconducting qubits, the quantum processor further includes a plurality of coupling devices, and each coupling device provides a controllable transmission coupling between a respective pair of superconducting qubits within the plurality of superconducting qubits. The hybrid computing system according to claim 13.

15. The at least one processor-based device determines whether the superconducting qubit indexed by the device counter is floppy based at least in part on whether a change in the energy of the solution of the problem is less than a predetermined threshold when the state of the superconducting qubit is inverted. The hybrid computing system according to claim 14.

16. The at least one processor device of claim 14, wherein the superconducting qubits indexed by the device counter are floppy based at least in part on the spread of zero net bias from neighboring devices.

17. The hybrid computing system of claim 13, wherein the normalized floppiness metric is the number of times the device is determined to be floppy divided by the predetermined sample limit.

18. The hybrid computing system of claim 13, wherein the first predetermined device limit is the same as the second predetermined device limit.

19. The hybrid computing system of claim 13, wherein the plurality of samples includes at least 1000 samples.

20. The hybrid computing system of claim 13, wherein the termination criterion includes at least one of completing a predetermined number of iterations, reaching a predetermined upper limit of allowable computation time, or determining that a change in energy of the solution to the problem between successive iterations is less than a predetermined threshold.

21. The device is a region of qubits including a plurality of coupled qubits, The hybrid computing system of claim 13, wherein the at least one processor determines whether the region of qubits indexed by the device counter is floppy to determine whether the device indexed by the device counter is floppy.

22. The hybrid computing system of claim 13, wherein the problem is a difficult problem.

23. A degeneracy reduction method in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, and operates as a sample generator for providing samples, the method comprising: Receiving, by the quantum processor, a problem for calculation; Generating, by the quantum processor, one or more samples based on the problem; Determining the magnetic susceptibility for each of one or more qubits of the plurality of qubits based on the one or more samples; Determining a tunneling speed offset for at least one qubit of the one or more qubits based on the magnetic susceptibility of the one or more qubits; Tuning the tunneling speed of the at least one qubit based on the tunneling speed offset, the method comprising.

24. Determining a subset of the plurality of qubits to be tuned based on a target magnetic susceptibility The method according to claim 23, comprising The magnetic susceptibility of each qubit of the subset differs from the target magnetic susceptibility by more than a threshold amount; The at least one qubit includes the subset, the method.

25. The method according to claim 23, wherein determining the magnetic susceptibility of each of the one or more qubits includes measuring the magnetization response of each of the one or more qubits to a magnetic flux bias.

26. Determining the magnetic susceptibility of each of the one or more qubits comprises Generating one or more estimates of the qubit based on one or more samples; Refining the one or more estimates of the qubit; The method according to claim 23, comprising determining the magnetic susceptibility of the qubit based on the one or more estimates of the qubit.

27. Refining the one or more estimates of the qubit comprises Generating an initial estimate; and Repeatedly generating another estimate based on at least one of the initial estimate and one or more previously generated estimates, the method according to claim 26.

28. Repeatedly generating another estimate includes generating another estimate based on a mean field model, the method according to claim 27.

29. Each separate estimate includes an estimate of at least one of the current of the qubit and the magnetic flux of the qubit, Generating another estimate based on a mean field model includes generating at least one estimate based on an expected value of the current of an isolated qubit based on the magnetic flux of the qubit, the method according to claim 28.

30. Determining the magnetic susceptibility of each of one or more qubits of the plurality of qubits includes determining the derivative of the magnetic flux-current relationship of each of the one or more qubits based on at least one of the one or more estimations, according to the method of claim 29.

31. Determining the tunneling speed offset of at least one qubit includes: For each of the at least one qubit: Determining a target tunneling speed at which an isolated qubit model predicts a predicted magnetic susceptibility corresponding to the magnetic susceptibility of the qubit; Determining the tunneling speed offset based on the target tunneling speed, according to the method of claim 23.

32. Determining the target tunneling speed includes determining a sample target tunneling speed for each sample and determining the target tunneling speed based on a measure of the sample target tunneling speed, according to the method of claim 31.

33. Determining the target tunneling speed based on a measure of the sample target tunneling speed includes determining an average value of the sample target tunneling speed, according to the method of claim 32.

34. For each of the at least one qubit, the tunneling speed offset is determined based on a difference between the target tunneling speed of the qubit and a measure of a plurality of target tunneling speeds, according to the method of claim 32.

35. The measure of the plurality of target tunneling speeds includes a median value of the plurality of target tunneling speeds, according to the method of claim 34.

36. For each of the at least one qubit, determining the target tunneling speed includes reducing the magnitude of the target tunneling speed to be less than that predicted by the isolated qubit model, according to the method of claim 31.

37. A method of operating a digital processor for tuning the annealing speed of at least one qubit of a quantum processor, comprising: Encoding a problem, comprising receiving an encoding including one or more qubits; Modifying the encoding by representing one of the one or more qubits as a logical qubit, thereby generating a modified encoding of the problem, wherein the logical qubit includes a plurality of internal qubits of the quantum processor coupled by internal couplings, and the logical qubit has a reduced effective tunneling speed compared to the tunneling speed of the qubit before modification; Calculating the problem by the quantum processor based on the modified encoding. A method including this.

38. The method according to claim 37, including selecting at least one of the number of internal qubits and the internal coupling strength of the logical qubit such that the effective tunneling speed approximates a target tunneling speed.

39. The method according to claim 37, wherein the qubit includes an initial logical qubit.

40. The method according to claim 37, including selecting a topology in which the logical qubit affects the effective tunneling speed.

41. The method according to claim 40, wherein selecting a topology includes selecting the topology from the plurality of topologies based on a minimum internal coupling strength associated with each of the plurality of topologies.

42. The method according to claim 41, wherein selecting the topology from the plurality of topologies based on the minimum internal coupling strength includes selecting the topology based on a correspondence between the minimum internal coupling strength and the number of internal qubits coupled to qubits outside the logical qubit.

43. The method according to claim 37, further including modifying the effective tunneling speed of the logical qubit by determining a tunneling speed offset based on the characteristics of the logical qubit, and modifying the effective tunneling speed of the logical qubit by applying the tunneling speed offset to an annealing schedule.

44. The method according to claim 43, wherein the logical qubit has a chain topology, and determining the tunneling speed offset based on the characteristics of the logical qubit includes determining the tunneling speed offset based on the chain length.

45. Determining the tunneling speed offset includes determining a scaling factor and scaling an offset value by the scaling factor, the method according to claim 43.

46. Scaling the offset value by the scaling factor includes scaling the offset value based on the following formula, the method according to claim 45, 【Number 1】 where k is the length of the chain topology of the logical qubit.

47. Receiving an encoding of the problem includes receiving the encoding as a multiplication circuit that embeds a factorization problem, the method according to claim 44.

48. The characteristic includes the position of the logical qubit in the graph with respect to one or more other qubits, and determining the tunneling speed offset based on the characteristic of the logical qubit includes determining the tunneling speed offset based on the position of the logical qubit in the graph with respect to one or more other qubits, the method according to claim 43.

49. The graph includes an embedding graph, and determining the tunneling speed offset includes determining the tunneling speed offset based on the position of the logical qubit in the embedding graph with respect to one or more other qubits, the method according to claim 48.

50. Determining the tunneling speed offset includes determining the distance between the logical qubit and the origin and determining the tunneling speed offset based on the distance, the method according to claim 48.

51. Determining the tunneling speed offset includes determining the distance between the logical qubit and the edge of the graph and determining the tunneling speed offset based on the distance, the method according to claim 48.

52. Determining the tunneling speed offset includes determining the tunneling speed offset based on a gradient defined for at least a portion of the graph, the method according to claim 48.

53. The gradient includes a radial gradient having a first region proximate to the origin, and the annealing schedule is advanced relative to the annealing schedule within a second region, the second region being farther from the origin compared to the first region, the method according to claim 52.

54. The method according to claim 37, further comprising determining an effective tunneling speed of the logical qubit based on an annealing sub-schedule specific to the logical qubit and an annealing schedule defined over a plurality of qubits, wherein at least one of the plurality of qubits is not included within the logical qubit.

55. A method of operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits, the method comprising: receiving, via a user interface, a pause start and a pause duration as inputs by the digital processor; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, comprising: starting the quantum annealing evolution; when reaching the pause start, pausing the quantum annealing evolution for the pause duration; controlling to complete the quantum annealing evolution, and reading out the states of the plurality of qubits by the hybrid computing system.

56. The method according to claim 55, wherein receiving a pause start includes receiving a measure of progress through the quantum annealing evolution.

57. The method according to claim 55, wherein receiving a pause start and a pause duration includes receiving a pause start and a pause duration via an application programming interface.

58. The method according to claim 55, wherein controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor includes controlling, by the digital processor, a quantum annealing evolution performed by a plurality of superconducting flux qubits.

59. The method according to claim 55, wherein pausing the quantum annealing evolution for the pause duration includes selecting a subset of qubits, pausing the quantum annealing evolution with respect to one or more qubits not within the subset of qubits, and reverse annealing the subset of qubits while the one or more qubits are paused.

60. The method according to claim 59, further comprising annealing the subset of qubits in a forward direction after reverse annealing of the subset of qubits and before completing the quantum annealing evolution.

61. A method of operating a digital processor for reducing degeneracy in a hybrid computing system including a quantum processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of devices and operates as a sample generator for providing samples. In the method, sending a problem for calculation to the quantum processor; receiving one or more samples generated by the quantum processor based on the problem; determining a magnetic susceptibility for each of one or more qubits of the plurality of qubits based on the one or more samples; determining a tunneling speed offset for at least one qubit of the one or more qubits based on the magnetic susceptibility of the one or more qubits; tuning the tunneling speed of the at least one qubit based on the tunneling speed offset.

62. A method of operating a hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer including a plurality of qubits, encoding a computational problem by the digital processor within a first subset of the plurality of qubits; weakly coupling a second subset having no common part with the first subset of the plurality of qubits to the first subset; determining a magnetic resonance tunneling (MRT) peak width by the qubits of the second subset; adjusting an annealing schedule of the physical quantum annealer based at least in part on the MRT peak width.

63. Encoding a computational problem by the digital processor within a first subset of the plurality of qubits includes encoding a computational problem by the digital processor within a first plurality of superconducting qubits, and weakly coupling a second subset of the plurality of qubits to the first subset includes weakly coupling a second plurality of superconducting qubits. The method according to claim 62.

64. A method for operating a hybrid computing system including a digital processor communicably coupled to a physical quantum annealer, comprising: collecting one or more energy statistical values by parallel tempering by the physical quantum annealer; evaluating an expected result by the digital processor; determining, by the digital processor, a preferred annealing speed and a preferred annealing trajectory based at least in part on the one or more energy statistical values and the expected result.

65. The method according to claim 64, wherein determining a suitable annealing speed includes inverting a cumulative distribution.

66. The method according to claim 64, wherein determining a suitable annealing trajectory includes performing local search.

67. The method according to claim 64, wherein collecting one or more energy statistical values by parallel tempering by the physical quantum annealer includes collecting one or more energy statistical values by parallel tempering by a superconducting quantum processor.

68. The method according to claim 64, further comprising repeatedly determining, by the digital processor, the preferred annealing speed and the preferred annealing trajectory based at least in part on the one or more energy statistical values and the expected result until a change in the preferred annealing speed and the preferred annealing trajectory between iterations is less than a predetermined threshold.

69. A method for operating a hybrid computing system including a digital processor communicably coupled to a quantum processor, comprising: sending a computational problem to the quantum processor by the digital processor; generating one or more samples by the quantum processor; collecting the one or more samples by the digital processor; determining, by the digital processor, whether a qubit is floppy with respect to a sample; when it is determined that the qubit is floppy with respect to the sample, increasing a count of floppy qubits by the digital processor; calculating a metric by the digital processor based at least in part on the count of floppy qubits; defining, by the digital processor, auxiliary qubits within the quantum processor; A method comprising coupling, by the digital processor, the auxiliary qubit to at least one of the floppy qubits within the quantum processor. **Claim 70** The method of claim 69, wherein transmitting the computational problem to the quantum processor comprises transmitting the computational problem to a superconducting quantum processor. **Claim 71** The method of claim 70, wherein transmitting the computational problem to a superconducting quantum processor comprises transmitting the computational problem to a physical quantum annealer. **Claim 72** The method of claim 71, wherein determining, by the digital processor, whether a qubit is floppy for a sample comprises determining, by the digital processor, whether a superconducting qubit is floppy. **Claim 73** The method of claim 71, wherein calculating, by the digital processor, a metric based at least in part on the count of floppy qubits comprises calculating a normalized floppiness metric that describes a part of the one or more samples for which the qubit is floppy. **Claim 74** The method of claim 71, wherein coupling, by the digital processor, the auxiliary qubit to at least one of the floppy qubits within the quantum processor comprises selecting a strength of coupling between the floppy qubit and the auxiliary qubit to adjust a tunneling amplitude of the floppy qubit. **Claim 75** A method of operating a hybrid computing system comprising a digital processor communicatively coupled to a quantum processor comprising a plurality of qubits, the method comprising: receiving a first bias value of a first qubit of the plurality of qubits; coupling an auxiliary qubit to the first qubit; determining whether a modulus of the first bias value is less than or equal to a predetermined threshold; upon determining that the modulus of the first bias value is less than or equal to the predetermined threshold: providing, to the auxiliary qubit, a second bias value that is a negative bias value and has a modulus greater than the modulus of the first bias value; setting a strength of the coupling between the first qubit and the auxiliary qubit to be approximately equal to the first bias value; setting a zero bias to the first qubit. **Claim 76** The method according to claim 75, wherein receiving a first bias value of a first qubit among the plurality of qubits includes receiving a bias value of a superconducting qubit.

77. The method according to claim 75, wherein coupling an auxiliary qubit to the first qubit includes coupling a superconducting qubit to the first qubit.

78. The method according to claim 75, wherein determining whether the modulus of the first bias value is less than or equal to a predetermined threshold includes determining whether the modulus of the first bias value is less than or equal to 1.

79. A method of operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits. In the method, receiving an annealing schedule by the digital processor; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, starting the quantum annealing evolution; performing the quantum annealing evolution at least partially based on the annealing schedule; completing the quantum annealing evolution, including control, reading out the states of the plurality of qubits by the hybrid computing system, The method includes reading, wherein receiving an annealing schedule by the digital processor includes receiving at least one of respective tunneling speeds or respective persistent currents as a univalent function of time for each qubit of the plurality of qubits.

80. Receiving an annealing schedule by the digital processor is Receiving a first annealing schedule for qubits of a first subset of the plurality of qubits, where receiving the first annealing schedule includes receiving, for each qubit of the qubits of the first subset, at least one of a first tunneling speed or a first persistent current as a univalent function of time, and receiving a second annealing schedule for qubits of a second subset of the plurality of qubits, where receiving the second annealing schedule includes receiving, for each qubit of the qubits of the second subset, at least one of a second tunneling speed or a second persistent current as a univalent function of time, the receiving, Performing the quantum evolution based at least in part on the annealing schedule includes performing the quantum evolution of the qubits of the first subset based at least in part on the first annealing schedule and performing the quantum evolution of the second subset based at least in part on the second annealing schedule, the act, The method according to claim 79, comprising:

81. Each of the qubits of the first and second subsets includes respective first and second logical qubits, and receiving the first annealing schedule includes receiving the first annealing schedule of the first logical qubit, and receiving the second annealing schedule includes receiving the second annealing schedule of the second logical qubit, The method according to claim 80, comprising:

82. Receiving the annealing schedule by the digital processor includes receiving a vector as a univalent function of time, The method according to claim 79, comprising:

83. Receiving the annealing schedule by the digital processor includes receiving the lateral and longitudinal energy scales as a univalent function of time, The method according to claim 79, comprising:

84. Receiving the annealing schedule by the digital processor includes receiving a segmented linear annealing schedule, The method according to claim 79, comprising:

85. A method for operating a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits and a plurality of coupling devices, and each of the plurality of coupling devices selectively communicatively couples a pair of qubits. In the method, receiving an annealing schedule by the digital processor; controlling, by the digital processor, a quantum annealing evolution performed by the quantum processor, starting the quantum annealing evolution; performing the quantum annealing evolution at least partially based on the annealing schedule; completing the quantum annealing evolution, including control, reading out the states of the plurality of qubits by the hybrid computing system, wherein receiving an annealing schedule by the digital processor receiving, for each qubit of the plurality of qubits, a respective local bias as a unary function of time; and receiving, for each coupling device of the plurality of coupling devices, a respective coupling strength as a unary function of time. A method including receiving.

86. A method for selecting an annealing schedule for a problem in a hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, and the quantum processor includes a plurality of qubits. In the method, generating one or more annealing schedules; receiving an input annealing schedule and selecting an annealing schedule from the one or more annealing schedules based on an objective function that provides a measure of at least one characteristic of the input annealing schedule; transmitting the problem to the quantum processor by the digital processor; executing the problem in the quantum processor according to the annealing schedule. A method including.

87. The method according to claim 86, including selecting an objective function from a set of one or more objective functions.

88. The method according to claim 86, wherein generating the one or more annealing schedules includes performing an optimization algorithm based on the objective function.

89. The method according to claim 88, wherein performing the optimization algorithm includes performing parallel tempering.

90. The method according to claim 89, wherein performing parallel tempering includes measuring at least one of a model generated by applying parallel tempering to the problem modified by the input annealing schedule and a chain linking the models by the objective function.

91. The method according to claim 90, wherein measuring by the objective function includes calculating at most a threshold number of parallel tempering iterations, the threshold number being less than the number of iterations for solving the problem.

92. The method according to claim 88, wherein performing the optimization algorithm includes performing Bayesian optimization.

93. The method according to claim 92, wherein performing Bayesian optimization includes measuring the ground state distribution of the problem by the objective function according to the input annealing schedule.

94. The method according to claim 93, wherein measuring by the objective function includes calculating at least one of a measure of similarity between the ground state distributions and characteristics of one or more outliers of the ground state distributions.

95. Measuring by the objective function includes measuring the entropy of the ground state distribution. The method according to claim 94.

96. The method according to claim 94, wherein measuring by the objective function includes measuring the distance of the ground state distribution from a uniform distribution according to a distance metric.

97. The method according to claim 94, wherein measuring by the objective function includes measuring the Gini coefficient of the ground state distribution.

98. The method according to claim 94, wherein measuring by the objective function includes measuring the ratio of the maximum probability to the minimum probability of the ground state distribution.

99. The method according to claim 86, wherein selecting the annealing schedule from the one or more annealing schedules includes determining that the annealing schedule provides an optimal result compared to the one or more annealing schedules.

100. Generating the one or more annealing schedules includes generating a plurality of annealing schedules, selecting a tentative annealing schedule based on the objective function, and generating the one or more annealing schedules based on the tentative annealing schedule, the method according to claim 99.

101. A method for reducing sample bias in a hybrid computing system including an analog processor and a digital processor, wherein the analog processor and the digital processor are communicatively coupled to each other, and the analog processor includes a plurality of qubits, the method comprising: sending a computational problem to the analog processor by the digital processor; generating, by the analog processor, a first set of one or more samples; collecting, by the digital processor, the one or more samples of the first set; identifying, based on the one or more samples of the first set, one or more valleys, each including a set of equal-energy samples; selecting one of the one or more valleys based on valley selection criteria; for each qubit in the valley: determining a degeneracy metric of the qubit; determining an annealing schedule of the qubit based on the degeneracy metric; collecting, by the analog processor, a second set of one or more samples based on the annealing schedule of the qubits in the valley.

102. The method according to claim 101, wherein identifying the one or more valleys includes determining that a plurality of qubits are related by a series of equal-energy qubit flips.

103. Identifying the one or more valleys includes determining the membership of the plurality of qubits in the valley based on the equal-energy Hamming distance between the qubits of the plurality of qubits. The method according to claim 102.

104. Selecting the valley from the one or more valleys includes selecting, based on the number of samples of the one or more samples in the valley, a valley having at least the same number of samples as each of the other valleys of the one or more valleys, the method according to claim 101.

105. The method of claim 101, wherein determining the degeneracy metric of the qubit includes determining a normalized floppiness metric.

106. The method of claim 105, wherein determining the degeneracy metric of the qubit includes determining the normalized floppiness metric of the qubit based on the number of times the qubit was floppy within the sample of the valley.

107. The method of claim 101, wherein determining the annealing schedule of the qubit based on the degeneracy metric includes determining that the annealing offset is proportional to the degeneracy metric.

108. The method of claim 107, wherein determining the annealing schedule of the qubit based on the degeneracy metric includes advancing the qubit to the start of the anneal.

109. The method of claim 108, wherein advancing the qubit to the start of the anneal includes delaying at least one other qubit such that after the qubit has completed its anneal, at least one other qubit begins annealing.

110. The method of claim 107, wherein determining the annealing schedule of the qubit based on the degeneracy metric includes delaying the qubit until the end of the anneal.

111. The method of claim 101, wherein at least one qubit of the valley includes a region of qubits.

112. Identifying one or more other valleys, each including a set of equal energy samples, based on the one or more samples of the second set; Selecting another valley of the one or more other valleys based on the valley selection criteria; For each qubit in the other valley: Determining another degeneracy metric of the qubit; Determining another annealing schedule of the qubit based on the degeneracy metric; Collecting, by the analog processor, one or more samples of a third set based on the another annealing schedule of the qubit in the other valley. The method of claim 101 further includes the above steps.

113. Determining the annealing schedule of the qubit based on the degenerate metric includes generating a plurality of annealing schedules and selecting the annealing schedule from the plurality of annealing schedules based on one or more selection criteria, according to the method of claim 101.

114. Generating the plurality of annealing schedules includes generating a first annealing schedule and generating a plurality of scaled annealing schedules based on a plurality of scaling factors, according to the method of claim 113.

115. A method for controllably simulating noise in an annealing schedule used in a hybrid computing system, the hybrid computing system including an analog processor and a digital processor, the analog processor and the digital processor being communicatively coupled to each other, the method comprising: Receiving an input annealing schedule in the digital processor; Generating pseudo-noise; Modifying the input annealing schedule based on the pseudo-noise to generate an output annealing schedule; Providing the output annealing schedule to the analog processor.

116. Generating the pseudo-noise includes pseudo-randomly generating one or more modifications to be applied to the input annealing schedule, according to the method of claim 115.

117. Generating the pseudo-noise includes generating one or more annealing pauses and one or more annealing ramps, according to the method of claim 115.

118. Generating one or more annealing pauses and one or more annealing ramps includes generating the one or more annealing pauses and ramps ordered as alternating pairs of pauses and ramps, according to the method of claim 117.

119. Generating the pseudo-noise includes adding one or more modifications to the pseudo-noise based on one or more constraints, according to the method of claim 115.

120. Adding one or more modifications to the pseudo-noise based on one or more constraints includes requiring that the output annealing schedule deviate from the input annealing schedule by no more than a threshold amount, the method of claim 119.

121. Requiring that the output annealing schedule deviate from the input annealing schedule by no more than a threshold amount includes requiring that the output annealing schedule deviate from the input annealing schedule by no more than a threshold amount that varies over time and is based on the time-dependent amplitude of the input annealing schedule, the method of claim 120.

122. The threshold amount is a constant, the method of claim 120.

123. Adding one or more modifications includes, for each modification, pseudo-randomly determining at least one of the amplitude of the modification and the duration of the modification according to the one or more constraints, the method of claim 119.

124. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of devices, and operates as a sample generator that provides a sample, a hybrid computing system operable to perform the method of any one of claims 23 to 36.

125. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, a hybrid computing system operable to perform the method of any one of claims 37 to 54.

126. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, any one of claims 55 to 60 A hybrid computing system operable to perform the method described therein.

127. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, and the hybrid computing system is operable as a sample generator that provides samples and is operable to perform the method according to claim 61.

128. A hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer including a plurality of qubits, the hybrid computing system being operable to perform the method according to any one of claims 62 to 63.

129. A hybrid computing system including a digital processor communicatively coupled to a physical quantum annealer, the hybrid computing system being operable to perform the method according to any one of claims 64 to 68.

130. A hybrid computing system including a digital processor communicatively coupled to a quantum processor, the hybrid computing system being operable to perform the method according to any one of claims 69 to 74.

131. A hybrid computing system including a digital processor communicatively coupled to a quantum processor including a plurality of qubits, the hybrid computing system being operable to perform the method according to any one of claims 75 to 78.

132. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, and the hybrid computing system is operable to perform the method according to any one of claims 79 to 84.

133. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits and a plurality of coupling devices, and each of the plurality of coupling devices selectively communicatively couples a pair of qubits, and the hybrid computing system is operable to perform the method according to claim 85.

134. A hybrid computing system including a quantum processor and a digital processor, wherein the quantum processor and the digital processor are communicatively coupled to each other, the quantum processor includes a plurality of qubits, and the hybrid computing system is operable to perform the method according to any one of claims 86 to 100.

135. A hybrid computing system including an analog processor and a digital processor, wherein the analog processor and the digital processor are communicatively coupled to each other, the analog processor includes a plurality of qubits, and the hybrid computing system is operable to perform the method according to any one of claims 101 to 114.

136. A hybrid computing system including an analog processor and a digital processor, wherein the analog processor and the digital processor are communicatively coupled to each other, and the hybrid computing system is operable to perform the method according to any one of claims 115 to 123 and the hybrid computing system.

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