Power control circuit

Abstract

To determine which of the following should be prioritized, reducing inrush current or shortening recovery time, when recovering multiple memories from a low power consumption mode.SOLUTION: A power control circuit comprises a plurality of memory groups, each being a group of a plurality of memories that can be restored from a low power consumption mode by a control signal; a non-volatile memory in which a setting value can be written to set whether to recover the plurality of memory groups serially or in parallel when recovering the plurality of memories from the low power consumption mode; and a power management circuit that controls the control signal input to the plurality of memory groups in accordance with the setting value.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The technology of the present disclosure relates to a power control circuit.

Background Art

[0002] Patent Document 1 describes that "all or part of a plurality of memory modules (MDLij) whose setting and release of the low power consumption mode are controlled by a control signal belong to memory blocks (BLK0 to BLKm), and the control signal is input in parallel to the plurality of memory modules belonging to the same memory block to propagate through an in-module path, and a part of the memory modules output the control signal from the in-module path to an out-of-module path (EXR_0 to EXR_m) downstream, and a propagation path of the control signal is configured."

[0003] Patent Document 2 describes that "a semiconductor integrated circuit device including a plurality of semiconductor chips each of which can be activated or deactivated by a control signal, wherein the plurality of semiconductor chips are daisy-chain connected by wiring capable of propagating the control signal, and each of the plurality of semiconductor chips includes a timing adjustment circuit for shifting a processing timing corresponding to the captured control signal among the plurality of semiconductor chips."

[0004] Patent Document 3 describes that "an information processing apparatus having a plurality of memory modules capable of controlling a first power state and a second power state having lower power consumption than the first power state by a low power control signal, wherein when the plurality of memory modules return from the second power state to the first power state, they return in the order of a memory module that requires setting and a memory module that does not require setting, and control means is provided to perform setting on the returned memory module at the timing when the memory module that requires setting returns."

Prior Art Documents

Patent Documents

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-025843 [Patent Document 2] Japanese Patent Application Laid-Open No. 2007-164822 [Patent Document 3] Japanese Patent Application Laid-Open No. 2017-126239 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] In Patent Documents 1 to 3, in the technology of returning a plurality of memories from a low power consumption mode by a control signal, the plurality of memories are daisy-chain connected by signal lines for propagating the control signal, and the return timings are shifted to serially return the plurality of memories. Here, when returning a plurality of memories serially, the inrush current can be made relatively small compared to the case of returning the plurality of memories in parallel, but it takes a relatively long time to return. Thus, there is a trade-off relationship between the inrush current and the return time. However, at the design stage, it has sometimes been difficult to determine which of reducing the inrush current and shortening the return time should be prioritized.

[0007] Therefore, an object of the present disclosure is to provide a power control circuit that can retrospectively determine which of reducing the inrush current and shortening the return time should be prioritized when returning a plurality of memories from a low power consumption mode. [Means for Solving the Problems]

[0008] The power control circuit according to the present disclosure includes a plurality of memory groups obtained by grouping a plurality of memories each of which can be returned from a low power consumption mode by a control signal, and a non-volatile memory capable of writing a setting value for setting whether to return the plurality of memory groups serially or in parallel when returning the plurality of memories from the low power consumption mode, and a power management circuit that controls the control signal input to the plurality of memory groups according to the setting value. [Brief Description of the Drawings]

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Embodiments for Carrying Out the Invention

[0010] Hereinafter, an example of an embodiment of the technology of the present disclosure will be described with reference to the drawings. In each drawing, the same or equivalent components and parts are given the same reference numerals. Also, the dimensional ratios in the drawings may be exaggerated for convenience of explanation and may be different from the actual ratios.

[0011] In addition, when the term "connection" is used hereinafter, the term shall be construed broadly to mean an electrical connection, including not only a direct connection but also an indirect connection (for example, a connection via passive components).

[0012] Also, when the term "provided between ~" is used hereinafter, the term may be interpreted to mean an electrical connection position, rather than a physical arrangement position.

[0013] FIG. 1 is a diagram showing an example of the configuration of a power control circuit 100 according to the present embodiment. The power control circuit 100 may be provided as an integrated circuit (IC) in which various circuits and elements for realizing various functions are integrated on a substrate. Hereinafter, a case where the power control circuit 100 is provided as a large-scale integration (LSI) in which various circuits and elements are largely integrated on a substrate will be described as an example. However, the present invention is not limited thereto. The power control circuit 100 may be provided as a discrete circuit in which various circuits and elements for realizing various functions are individually combined.

[0014] The power control circuit 100 includes a plurality of memory groups 110a to 110c, an oscillator 120, a PROM 130, a PROM control circuit 140, a PMU 150, a CPU 160, a mask ROM 170, an external memory controller 180, and a firmware RAM 190.

[0015] The plurality of memory groups 110a to 110c (collectively referred to as "memory group 110") are a grouping of a plurality of memories 115a1 to 115c3 (collectively referred to as "memory 115").

[0016] The plurality of memories 115 may each be a memory that can be restored from a low power consumption mode by a control signal. Such memories include, for example, SRAM (Static Random Access Memory) that can be shifted between a low power consumption mode and a mode with higher power consumption than the low power consumption mode, such as a normal mode, by a control signal called a power down (PD) signal. Each of the plurality of memories 115 has an input terminal PDI for inputting an input control signal and an output terminal PDO for outputting an output control signal. When the input terminal PDI transitions from a first state (e.g., High indicating enable) to a second state (e.g., Low indicating disable), and the memory returns from the low power consumption mode to a mode with higher power consumption than the low power consumption mode, the output terminal PDO may be de-asserted, that is, transitioned from the first state to the second state.

[0017] As shown in this figure, the first memory group 110a may include memories 115a1 to 115a3 (collectively referred to as "memory 115a"). Similarly, the second memory group 110b may include memories 115b1 to 115b3 (collectively referred to as "memory 115b"). Similarly, the third memory group 110c may include memories 115c1 to 115c3 (collectively referred to as "memory 115c").

[0018] In the first memory group 110a, the output terminal PDO of the memory 115a1 may be connected to the input terminal PDI of the memory 115a2, and the output terminal PDO of the memory 115a2 may be connected to the input terminal PDI of the memory 115a3. Similarly, in the second memory group 110b, the output terminal PDO of the memory 115b1 may be connected to the input terminal PDI of the memory 115b2, and the output terminal PDO of the memory 115b2 may be connected to the input terminal PDI of the memory 115b3. Similarly, in the third memory group 110c, the output terminal PDO of the memory 115c1 may be connected to the input terminal PDI of the memory 115c2, and the output terminal PDO of the memory 115c2 may be connected to the input terminal PDI of the memory 115c3. In this way, at least one of the plurality of memory groups 110 may include at least two memories 115 daisy-chained by signal lines for propagating control signals.

[0019] In the above description, the case where nine memories 115 are grouped into three memory groups 110 is shown as an example. However, the number of memory groups 110 and the number of memories 115 included in each memory group 110 are not limited to this. For example, the number of memory groups 110 may be two, or four or more. Also, the number of memories 115 included in each memory group 110 may be one, two, or four or more. In this case, the number of memories 115 included in the plurality of memory groups 110 may be different from each other. That is, for example, the first memory group 110a may include one of the memories 115a, the second memory group 110b may include two of the memories 115b1 and b2, and the third memory group 110c may include three of the memories 115c1 to c3. The number of memories 115 included in the plurality of memory groups 110 may be different for each memory group 110.

[0020] The oscillator 120 generates a clock when the power supply voltage VCC rises. The oscillator 120 supplies the generated clock to each part within the power control circuit 100. At this time, the timing for supplying the clock of the oscillator 120 may be variable for each part.

[0021] The PROM 130 is a programmable ROM (Read Only Memory) that can only read data during normal times and cannot be written, but can be written in a specific procedure, and is an example of the "non-volatile memory" in the present disclosure. The PROM 130 may be, for example, an OTP (One Time PROM) that can only write data once. However, it is not limited to this. The PROM 130 may be a programmable ROM such as an EPROM (Erasable PROM) that allows writing and erasing of data.

[0022] The PROM control circuit 140 controls the writing (write) of data to the PROM 130 and the reading (read) of data from the PROM 130. At the time of writing data, the PROM control circuit 140 may control the writing of data from the ROM writer to the PROM 130 via an external interface. At the time of reading data, the PROM control circuit 140 may read the data written in the PROM 130 and latch it into a register (not shown).

[0023] At this time, a setting value for setting whether to serially resume or parallel resume among the plurality of memory groups 110 may be written in the PROM 130 when returning the plurality of memories 115 from the low power consumption mode. Such a setting value may be written in the PROM 130, for example, during the manufacturing process or the shipping process after the device evaluation of the LSI.

[0024] Thus, when the power control circuit 100 resumes a plurality of memories 115 from the low power consumption mode, it may include a non-volatile memory capable of writing a setting value for setting whether to resume them serially or in parallel among the plurality of memory groups 110. Such a non-volatile memory may be a programmable ROM capable of writing a setting value from a ROM writer via an interface. Such a programmable ROM may be a one-time programmable ROM capable of writing a setting value only once.

[0025] The PMU 150 is a power management unit that manages the power modes of the plurality of memories 115 and is an example of the "power control circuit" in the present disclosure. The PMU 150 controls a first input control signal Pda_in input to the first memory group 110a, a second input control signal Pdb_in input to the second memory group 110b, and a third input control signal Pdc_in input to the third memory group 110c (collectively referred to as "input control signal PD_in") according to the setting value read from the PROM 130. Then, the PMU 150 acquires a first output control signal Pda_out output from the first memory group 110a, a second output control signal Pdb_out output from the second memory group 110b, and a third output control signal Pdc_out output from the third memory group 110c (collectively referred to as "output control signal PD_out"). Thus, the power control circuit 100 may include a power management circuit that controls the input control signal PD_in input to the plurality of memory groups 110 according to the setting value.

[0026] The CPU 160 is a central processing unit.

[0027] The mask ROM 170 is a ROM incorporating a bootloader.

[0028] The external memory controller 180 accesses an external memory (not shown) and loads firmware from the external memory.

[0029] The RAM 190 for firmware is an area where the firmware loaded by the external memory controller 180 is expanded.

[0030] FIG. 2 is a diagram showing an example of the operation of the power control circuit 100 according to the present embodiment. In this figure, the power supply voltage VCC, the reset signal RST, the return setting, the first input control signal Pda_in, the second input control signal Pdb_in, and the third input control signal Pdc_in are shown from the top. At this point, it is assumed that the setting value indicating the above-mentioned return setting has already been written in the PROM 130.

[0031] First, in the reset operation after power-on, the PMU 150 enables the first to third input control signals Pda_in to Pdc_in. Therefore, all of the plurality of memories 115a1 to c3 start in the low power consumption mode.

[0032] Next, the clock of the oscillator 120 is supplied only to the PROM control circuit 140. In response to this, the PROM control circuit 140 accesses the PROM 130, reads the setting value written in the PROM 130 in the LSI manufacturing process, and latches it in the register.

[0033] When the PROM control circuit 140 completes the read operation of the setting value, the clock of the oscillator 120 is supplied to each part other than the CPU 160. At this point, the CPU 160 has not yet started.

[0034] Then, the PMU 150 returns the plurality of memories 115 according to the register output, that is, the setting value read from the PROM 130. Here, examples of the return setting include serial return, parallel return, and combined return. Details thereof will be described later.

[0035] When all of the plurality of memories 115 have returned, the clock of the oscillator 120 is supplied to the CPU 160. In response to this, the external memory controller 180 loads the firmware from the external memory by executing the boot loader from the mask ROM 170. Then, the firmware RAM 190 expands the firmware loaded by the external memory controller 180.

[0036] Thereafter, the power control circuit 100 switches to firmware control and executes system operation. Note that the transition to and return from the low power consumption mode of the plurality of memories 115 during the execution of the system operation are instructed by accessing the registers from the firmware to the PMU 150. The set value read from the PROM 130 is applied to the return setting at this time.

[0037] Next, as the return settings, serial return, parallel return, and combined return will be described respectively.

[0038] FIG. 3 is a diagram showing an example of a timing chart when the power control circuit 100 according to the present embodiment serially returns a plurality of memories 115 among a plurality of memory groups 110. In this figure, the power supply voltage VCC, the reset signal RST, the return setting, the first input control signal Pda_in, the first output control signal Pda_out, the second input control signal Pdb_in, the second output control signal Pdb_out, the third input control signal Pdc_in, and the third output control signal Pdc_out are shown from top to bottom.

[0039] This figure shows, as an example, a case where the set value read from the PROM 130 returns the first memory group 110a, the second memory group 110b, and the third memory group 110c in this order.

[0040] First, the PMU 150 transitions the first input control signal PDa_in from enabled to disabled. The first input control signal PDa_in is input to the input terminal PDI of the memory 115a1 provided upstream of the daisy chain in the first memory group 110a. Therefore, the memory 115a1 returns from the low power consumption mode in response to the input terminal PDI transitioning from enabled to disabled. And when the memory 115a1 returns from the low power consumption mode, it transitions the output terminal PDO from enabled to disabled.

[0041] The output terminal PDO of the memory 115a1 is connected to the input terminal PDI of the memory 115a2 provided in the middle of the daisy chain. Therefore, the memory 115a2 returns from the low power consumption mode in response to the input terminal PDI transitioning from enabled to disabled. And when the memory 115a2 returns from the low power consumption mode, it transitions the output terminal PDO from enabled to disabled.

[0042] The output terminal PDO of the memory 115a2 is connected to the input terminal PDI of the memory 115a3 provided downstream of the daisy chain. Therefore, the memory 115a3 returns from the low power consumption mode in response to the input terminal PDI transitioning from enabled to disabled. As a result, all the memories 115a included in the first memory group 110a return from the low power consumption mode. And when the memory 115a3 returns from the low power consumption mode, it transitions the output terminal PDO from enabled to disabled.

[0043] The output terminal PDO of the memory 115a3 is connected to the PMU 150. Therefore, the PMU 150 can obtain the output control signal output from the output terminal PDO of the memory 115a3 as the first output control signal PDa_out output from the first memory group 110.

[0044] Next, when the first output control signal PDa_out transitions from enabled to disabled, the PMU150 causes the second input control signal PDb_in to transition from enabled to disabled. Regarding the return operation of the memory 115b included in the second memory group 110b, since it may be the same as the return operation of the memory 115a included in the first memory group 110a, the description is omitted here. Then, when the memory 115b3 returns from the low power consumption mode, it causes the output terminal PDO to transition from enabled to disabled.

[0045] The output terminal PDO of the memory 115b3 is connected to the PMU150. Therefore, the PMU150 can obtain the output control signal output from the output terminal PDO of the memory 115b3 as the output control signal PDb_out output from the second memory group 110b.

[0046] Then, when the second output control signal PDb_out transitions from enabled to disabled, the PMU150 causes the third input control signal PDc_in to transition from enabled to disabled. Regarding the return operation of the memory 115c included in the third memory group 110c, since it may be the same as the return operation of the memory 115a included in the first memory group 110a, the description is omitted here. Then, when the memory 115c3 returns from the low power consumption mode, it causes the output terminal PDO to transition from enabled to disabled.

[0047] The output terminal PDO of the memory 115c3 is connected to the PMU150. Therefore, the PMU150 can obtain the output control signal output from the output terminal PDO of the memory 115c3 as the output control signal PDc_out output from the third memory group 110c.

[0048] When the third output control signal PDc_out transitions from enabled to disabled, the PMU150 determines that all of the plurality of memories 115 have returned from the low power consumption mode, and ends the return operation of the plurality of memories 115.

[0049] In this way, when the power management circuit (e.g., PMU 150) serially restores among a plurality of memory groups 110, in response to the control signal input to the previous memory group 110 among the plurality of memory groups 110 transitioning to the second state, when the control signal output from the previous memory group 110 transitions to the second state, the control signal input to the subsequent memory group 110 among the plurality of memory groups 110 may be transitioned to the second state.

[0050] As shown in this figure, when serially restoring between the first memory group 110a, the second memory group 110b, and the third memory group 110c, the first restoration time for restoring the memory 115a included in the first memory group 110a, the second restoration time for restoring the memory 115b included in the second memory group 110b, and the third restoration time for restoring the memory 115c included in the third memory group 110c are added together, and this time becomes the restoration time for restoring all the memories 115.

[0051] In this way, when serially restoring a plurality of memory groups 110, the restoration time becomes longer, but since the memories 115 are restored one by one, the inrush current can be reduced.

[0052] FIG. 4 is a diagram showing an example of a timing chart when the power control circuit 100 according to the present embodiment restores a plurality of memories 115 in parallel among a plurality of memory groups 110. In this figure, from top to bottom, the power supply voltage VCC, the reset signal RST, the restoration setting, the first input control signal PDa_in, the first output control signal PDa_out, the second input control signal PDb_in, the second output control signal PDb_out, the third input control signal PDc_in, and the third output control signal PDc_out are shown.

[0053] This figure shows, as an example, a case where the set value read from PROM130 is a value indicating that the first memory group 110a, the second memory group 110b, and the third memory group 110c are restored in parallel.

[0054] In this case, PMU150 simultaneously transitions the first input control signal Pda_in, the second input control signal Pdb_in, and the third input control signal Pdc_in from enabled to disabled. As a result, the memory 115a included in the first memory group 110a, the memory 115b included in the second memory group 110b, and the memory 115c included in the third memory group 110c simultaneously return from the low power consumption mode.

[0055] Even in this case, within each memory group 110, the memories 115 in the upstream, middle, and downstream of the daisy chain return from the low power consumption mode serially in that order.

[0056] When all of the first output control signal Pda_out, the second output control signal Pdb_out, and the third output control signal Pdc_out transition from enabled to disabled, PMU150 determines that all of the plurality of memories 115 have returned from the low power consumption mode, and ends the return operation of the plurality of memories 115.

[0057] In this way, when restoring in parallel among the plurality of memory groups 110, the power management circuit (for example, PMU150) may simultaneously transition the control signals input to the plurality of memory groups 110 to the second state.

[0058] As shown in this figure, when restoring in parallel among the first memory group 110a, the second memory group 110b, and the third memory group 110c, the first restoration time for restoring the memory 115a included in the first memory group 110a, the second restoration time for restoring the memory 115b included in the second memory group 110b, and the third restoration time for restoring the memory 115c included in the third memory group 110c, the longest one among them becomes the restoration time for restoring all the memories 115.

[0059] In this way, when restoring a plurality of memory groups 110 in parallel, the memory 115 is restored three by three in parallel, for example, so the inrush current becomes large, but the restoration time can be shortened.

[0060] FIG. 5 is a diagram showing a first example of a timing chart when the power control circuit 100 according to this embodiment restores a plurality of memories 115 in a combination of serial and parallel among a plurality of memory groups 110. In this figure, the power supply voltage VCC, the reset signal RST, the restoration setting, the first input control signal PDa_in, the first output control signal PDa_out, the second input control signal PDb_in, the second output control signal PDb_out, the third input control signal PDc_in, and the third output control signal PDc_out are shown from top to bottom.

[0061] This figure shows, as an example, a case where the set value read from the PROM 130 is a value indicating that the third memory group 110c is restored after the first memory group 110a and the second memory group 110b are restored in parallel.

[0062] First, the PMU 150 simultaneously transitions the first input control signal PDa_in and the second input control signal PDb_in from enable to disable. As a result, the memory 115a included in the first memory group 110a and the memory 115b included in the second memory group 110b simultaneously return from the low power consumption mode.

[0063] Next, when both the first output control signal PDa_out and the second output control signal PDb_out transition from enable to disable, the PMU 150 causes the third input control signal PDc_in to transition from enable to disable.

[0064] Then, when the third output control signal PDc_out transitions from enable to disable, the PMU 150 determines that all of the plurality of memories 115 have returned from the low power consumption mode, and ends the return operation of the plurality of memories 115.

[0065] In this way, when the power management circuit (for example, PMU 150) causes at least two of the plurality of memory groups 110 to return in parallel and causes at least two of the plurality of memory groups 110 to return serially with at least one of the plurality of memory groups 110, in response to the control signals input to the at least two memory groups 110 transitioning to the second state all at once, when all of the control signals output from the at least two memory groups 110 transition to the second state, the control signal input to at least one memory group 110 may be caused to transition to the second state.

[0066] As shown in this figure, when returning the third memory group 110c after returning the first memory group 110a and the second memory group 110b in parallel, the longest one of the first return time for returning the memories 115a included in the first memory group 110a and the second return time for returning the memories 115b included in the second memory group 110b, added to the third return time for returning the memories 115c included in the third memory group 110c, is the return time for returning all of the memories 115.

[0067] FIG. 6 is a diagram showing a second example of a timing chart when the power control circuit 100 according to the present embodiment returns a plurality of memories 115 by combining serial and parallel between a plurality of memory groups 110. In this figure, the power supply voltage VCC, the reset signal RST, the return setting, the first input control signal Pda_in, the first output control signal Pda_out, the second input control signal Pdb_in, the second output control signal Pdb_out, the third input control signal Pdc_in, and the third output control signal Pdc_out are shown from top to bottom.

[0068] This figure shows, as an example, a case where, after the set value read from the PROM 130 returns the first memory group 110a, the second memory group 110b and the third memory group 110c are returned in parallel.

[0069] First, the PMU 150 transitions the first input control signal Pda_in from enabled to disabled. As a result, the memory 115a included in the first memory group 110a returns from the low power consumption mode.

[0070] Next, when the first output control signal Pda_out transitions from enabled to disabled, the PMU 150 simultaneously transitions the second input control signal Pdb_in and the third input control signal Pdc_in from enabled to disabled.

[0071] Then, when both the second output control signal Pdb_out and the third output control signal Pdc_out transition from enabled to disabled, the PMU 150 determines that all of the plurality of memories 115 have returned from the low power consumption mode, and ends the return operation of the plurality of memories 115.

[0072] In this way, when the power management circuit (e.g., PMU 150) causes a return in parallel between at least two of the plurality of memory groups 110 and causes a return serially between the at least two memory groups and at least one of the plurality of memory groups 110, when the control signal output from at least one memory group 110 transitions to the second state in response to the control signal input to at least one memory group 110 transitioning to the second state, the control signals input to the at least two memory groups 110 may be simultaneously transitioned to the second state.

[0073] As shown in this figure, when the second memory group 110b and the third memory group 110c are returned in parallel after the first memory group 110a is returned, the first return time for returning the memory 115a included in the first memory group 110a, the second return time for returning the memory 115b included in the second memory group 110b, and the third return time for returning the memory 115c included in the third memory group 110c. The time obtained by adding the longest one of the return times is the return time for returning all the memories 115.

[0074] As shown in FIGS. 5 and 6, when returning the plurality of memory groups 110 in a combination of serial and parallel, the return time can be made shorter than when returning all the plurality of memory groups 110 serially, and the inrush current can be made smaller than when returning all the plurality of memory groups 110 in parallel.

[0075] Note that FIGS. 5 and 6 are an example of a combination of serial and parallel, and various other return settings may be provided according to the order of the memory groups 110 to be returned serially and the set of memory groups 110 to be returned in parallel.

[0076] Generally, when a memory 115 such as an SRAM resumes from a low power consumption mode, a large inrush current flows instantaneously. If multiple memories 115 are installed, the inrush current will flow for the number of installed units, which may cause malfunction such as the regulator supply not being able to catch up.

[0077] Here, it is conceivable to connect the control signals for resuming multiple memories 115 from the low power consumption mode in a daisy chain to resume the multiple memories 115 serially, or to connect the control signals in parallel to resume the multiple memories 115 in parallel.

[0078] However, when multiple memories 115 are resumed serially, the inrush current becomes small, but it takes a long time to resume all of the multiple memories 115, and there is a concern that the startup time requirement may not be met. Also, when multiple memories 115 are resumed in parallel, the time until all of the multiple memories 115 are resumed becomes short, but there is a concern that a large inrush current will flow and the circuit will malfunction.

[0079] Thus, the relationship between the inrush current and the resume time is a trade-off, and it may be difficult to determine which should be prioritized at the design stage. Therefore, it is desired to determine the resume setting retrospectively, such as after evaluating the device.

[0080] Also, in a system equipped with a CPU, it is possible to select the resume setting by firmware control. However, in a system that uses multiple memories 115 before the firmware starts up, it is necessary to optimize the resume setting immediately after startup when the power is turned on. Examples of such a system include a system in which a bootloader starts up after the power is turned on and firmware is loaded from an external memory, and an SRAM is used as the firmware expansion area or the data buffer of the external memory controller.

[0081] In contrast, when returning a plurality of memories 115 from the low power consumption mode, the power control circuit 100 according to the present embodiment includes a non-volatile memory capable of writing a setting value for setting whether to return serially or in parallel among a plurality of memory groups 110, and controls a control signal input to the plurality of memory groups 110 according to the setting value read from the non-volatile memory. Thereby, according to the power control circuit 100 according to the present embodiment, when returning a plurality of memories 115 from the low power consumption mode, it is possible to determine afterwards whether to prioritize reducing the inrush current or shortening the return time. Further, according to the power control circuit 100 according to the present embodiment, the inrush current and the return time can be optimized even when the firmware is not operating.

[0082] The present disclosure also includes the following content.

[0083] (Appendix 1) A plurality of memory groups obtained by grouping a plurality of memories, each of which is capable of returning from the low power consumption mode by a control signal, A non-volatile memory capable of writing a setting value for setting whether to return serially or in parallel among the plurality of memory groups when returning the plurality of memories from the low power consumption mode, A power management circuit that controls the control signal input to the plurality of memory groups according to the setting value, A power control circuit comprising: (Appendix 2) Each of the plurality of memories has an input terminal for inputting the control signal and an output terminal for outputting the control signal, and when returning from the low power consumption mode in response to the input terminal transitioning from a first state to a second state, the output terminal is transitioned from the first state to the second state. The power control circuit according to Appendix 1. (Appendix 3) When the power management circuit serially resumes between the plurality of memory groups, in response to the control signal input to the memory group in the previous stage among the plurality of memory groups being transitioned to the second state, when the control signal output from the memory group in the previous stage is transitioned to the second state, the control signal input to the memory group in the subsequent stage among the plurality of memory groups is transitioned to the second state. The power control circuit according to Appendix 2. (Appendix 4) When the power management circuit resumes in parallel between the plurality of memory groups, the control signal input to the plurality of memory groups is simultaneously transitioned to the second state. The power control circuit according to Appendix 2 or 3. (Appendix 5) When the power management circuit resumes in parallel between at least two memory groups among the plurality of memory groups and resumes serially between the at least two memory groups and at least one memory group among the plurality of memory groups, in response to the control signal input to the at least two memory groups being simultaneously transitioned to the second state, when all of the control signals output from the at least two memory groups are transitioned to the second state, the control signal input to the at least one memory group is transitioned to the second state. The power control circuit according to any one of Appendices 2 to 4. (Appendix 6) When the power management circuit resumes in parallel between at least two memory groups among the plurality of memory groups and resumes serially between the at least two memory groups and at least one memory group among the plurality of memory groups, when the control signal output from the at least one memory group is transitioned to the second state in response to the control signal input to the at least one memory group being transitioned to the second state, the control signal input to the at least two memory groups is simultaneously transitioned to the second state. The power control circuit according to any one of Supplementary Notes 2 to 5. (Supplementary Note 7) The power control circuit according to any one of Supplementary Notes 1 to 6, wherein the non-volatile memory is a programmable ROM capable of writing the set value from a ROM writer via an interface. (Supplementary Note 8) The power control circuit according to Supplementary Note 7, wherein the programmable ROM is a one-time programmable ROM capable of writing the set value only once. (Supplementary Note 9) At least one of the plurality of memory groups includes at least two memories daisy-chain connected by signal lines for propagating the control signal. The power control circuit according to any one of Supplementary Notes 1 to 8.

Explanation of Reference Numerals

[0084] 100 Power control circuit 110 Memory group 115 Memory 120 Oscillator 130 PROM (an example of "non-volatile memory") 140 PROM control circuit 150 PMU (an example of "power management circuit") 160 CPU 170 Mask ROM 180 External memory controller 190 RAM for firmware

Claims

1. A plurality of memory groups obtained by grouping a plurality of memories, each of which can be restored from a low power consumption mode by a control signal; A non-volatile memory in which a setting value for setting whether to restore the plurality of memories serially or in parallel among the plurality of memory groups can be written when restoring the plurality of memories from the low power consumption mode; A power management circuit that controls the control signal input to the plurality of memory groups according to the setting value; A power control circuit comprising:

2. Each of the plurality of memories has: An input terminal for inputting the control signal and an output terminal for outputting the control signal, When returning from the low power consumption mode in response to the input terminal transitioning from the first state to the second state, the output terminal is transitioned from the first state to the second state. The power control circuit according to claim 1.

3. When restoring the plurality of memory groups serially, the power management circuit, in response to the control signal input to the memory group in the previous stage among the plurality of memory groups transitioning to the second state, when the control signal output from the memory group in the previous stage transitions to the second state, causes the control signal input to the memory group in the subsequent stage among the plurality of memory groups to transition to the second state. The power control circuit according to claim 2.

4. When restoring the plurality of memory groups in parallel, the power management circuit simultaneously transitions the control signal input to the plurality of memory groups to the second state. The power control circuit according to claim 2.

5. When restoring in parallel between at least two memory groups among the plurality of memory groups and restoring serially between the at least two memory groups and at least one memory group among the plurality of memory groups, the power management circuit, in response to the control signals input to the at least two memory groups simultaneously transitioning to the second state, when all of the control signals output from the at least two memory groups transition to the second state, causes the control signal input to the at least one memory group to transition to the second state. The power control circuit according to claim 2.

6. When the power management circuit performs a parallel return between at least two of the plurality of memory groups and a serial return between the at least two memory groups and at least one of the plurality of memory groups, when the control signal output from the at least one memory group transitions to the second state in response to the control signal input to the at least one memory group transitioning to the second state, the control signals input to the at least two memory groups are simultaneously transitioned to the second state. The power control circuit according to claim 2.

7. The power control circuit according to any one of claims 1 to 6, wherein the non-volatile memory is a programmable ROM into which the set value can be written from a ROM writer via an interface.

8. The power control circuit according to claim 7, wherein the programmable ROM is a one-time programmable ROM into which the set value can be written only once.

9. At least one of the plurality of memory groups includes at least two memories connected in a daisy chain by signal lines that propagate the control signal. The power control circuit according to any one of claims 1 to 6.

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