Memory system

Abstract

To provide a memory system capable of reducing processing latency in response to a write request.SOLUTION: According to an embodiment, a memory system comprises a non-volatile memory including a plurality of blocks and a controller. The controller is configured to: assign a first erased block in which a data erase operation has been completed among the plurality of blocks as a general-purpose block; assign a second erased block as the write destination block corresponding to a first stream if two or more erased blocks in which the data erase operation has been completed are included in the plurality of blocks when the use of the first stream is initiated; and set a general-purpose block as the write destination block if two or more erased blocks in which the data erase operation has been completed are not included in the plurality of blocks when the use of the first stream is initiated.SELECTED DRAWING: Figure 10

Description

Technical Field

[0001] Embodiments of the present invention relate to a technique for controlling a non-volatile memory.

Background Art

[0002] In recent years, memory systems including non-volatile memories have become widely popular. As one such memory system, a solid state drive (SSD) including a NAND type flash memory is known. The SSD is used as a main storage of various computing devices.

[0003] A memory system may have a multi-stream function. The multi-stream function is a function of receiving a write request associated with one of a plurality of streams from a host and writing data associated with the write request to a block in a non-volatile memory assigned to the one stream. The plurality of streams are used, for example, to write data of different lifetimes to different blocks.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0005] When the use of a stream is started, for example, a block in which a data erasure operation has been completed (erased block) is assigned to the stream.

[0006] However, there may not be a sufficient number of erased blocks when the use of a stream is started. If the allocation of erased blocks to the stream whose use is started is delayed, the execution of processing in response to a write request associated with that stream is delayed.

[0007] One embodiment provides a memory system capable of reducing the delay in processing in response to a write request.

Means for Solving the Problem

[0008] According to an embodiment, a memory system is connectable to a host. The memory system includes a non-volatile memory and a controller. The non-volatile memory includes a plurality of blocks. The controller is electrically connected to the non-volatile memory. The controller manages a plurality of streams. The controller allocates, as a general-purpose block capable of writing data not associated with any of the plurality of streams and data associated with any of the plurality of streams, a first erased block in which a data erasure operation has been completed among the plurality of blocks. When the use of a first stream is started, if two or more erased blocks in which a data erasure operation has been completed are included in the plurality of blocks, the controller allocates a second erased block as a write destination block corresponding to the first stream. When the use of a first stream is started, if two or more erased blocks in which a data erasure operation has been completed are not included in the plurality of blocks, the controller sets a general-purpose block as a write destination block corresponding to the first stream.

Brief Description of the Drawings

[0009]

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BEST MODE FOR CARRYING OUT THE INVENTION

[0010] Hereinafter, embodiments will be described with reference to the drawings.

[0011] First, referring to FIG. 1, the configuration of the information processing system 1 including the memory system according to the embodiment will be described. The information processing system 1 includes a host device 2 and a memory system 3.

[0012] The host device 2 may be a storage server that stores a large amount of diverse data in the memory system 3, or may be a personal computer. Hereinafter, the host device 2 is also referred to as the host 2.

[0013] The memory system 3 is a storage device configured to write data to a non-volatile memory and read data from the non-volatile memory. The non-volatile memory is, for example, a NAND type flash memory 4. The memory system 3 is also referred to as a storage device or a semiconductor storage device. The memory system 3 is realized, for example, as an SSD including the NAND type flash memory 4. Hereinafter, the case where the non-volatile memory is the NAND type flash memory 4 will be mainly exemplified.

[0014] The memory system 3 has a multi-stream function. The multi-stream function receives a write request associated with one of a plurality of streams from the outside (here, the host 2), and writes user data associated with the write request to a block in the NAND type flash memory 4 assigned to that one stream. The plurality of streams are used, for example, to write user data with different lifetimes to different blocks. Receiving a write request associated with a stream means, more specifically, receiving a write request that designates that stream. The write request is, for example, a write command. The write request may include information (stream ID) that can uniquely identify the designated stream. Hereinafter, it is assumed that the write request is a write command.

[0015] The memory system 3 can be used as the storage of the host 2. The memory system 3 may be built into the host 2 or may be connected to the host 2 via a cable or a network.

[0016] The interface for connecting the host 2 and the memory system 3 is PCI Express TM (PCIe TM )、Ethernet TM 、Fibre channel, NVM Express TM (NVMe TM ) and other standards.

[0017] The host 2 includes, for example, a central processing unit (CPU) 21 and a random access memory (RAM) 22. The CPU 21 and the RAM 22 are connected via, for example, a bus 20.

[0018] The CPU 21 is, for example, at least one processor. The CPU 21 controls the operation of various components within the host 2.

[0019] The RAM 22 is, for example, volatile memory. The RAM 22 is, for example, dynamic random access memory (DRAM) or static random access memory (SRAM).

[0020] The memory system 3 includes, for example, a NAND type flash memory 4, a DRAM 5, and a controller 6.

[0021] The NAND flash memory 4 includes a plurality of blocks B0, B1, B2, ……, and Bm-1. The plurality of blocks B0, B1, B2, ……, and Bm-1 each function as a minimum unit of a data erase operation. A block may also be referred to as an erase block or a physical block. Each of the plurality of blocks B0, B1, B2, ……, and Bm-1 includes a plurality of pages P0, ……, and Pn-1. Each of the plurality of pages P0, ……, and Pn-1 includes a plurality of memory cells connected to a single word line. The plurality of pages P0, ……, and Pn-1 each function as a unit of a data write operation and a data read operation. Note that a word line may function as a unit of a data write operation and a data read operation.

[0022] There is an upper limit on the number of program / erase cycles (P / E cycles) for each block, which is referred to as the maximum P / E cycle number. One P / E cycle of a certain block includes a data erase operation for setting all the memory cells in this block to an erased state and a program operation for writing data to each page of this block.

[0023] The DRAM 5 is a volatile memory. The storage area of the DRAM 5 is allocated, for example, as a storage area for firmware (FW) 51, a cache area for a logical physical address translation table 52, and a storage area for control information 53. The control information 53 includes, for example, the target number of erased blocks. The storage area of the DRAM 5 may be further allocated as a buffer area for temporarily storing user data.

[0024] The FW 51 is a program for controlling the operation of the controller 6. The FW 51 is loaded, for example, from the NAND flash memory 4 to the DRAM 5.

[0025] The logical physical address translation table 52 is a table for managing the mapping between each logical address and each physical address. The logical address is an address used by the host 2 to address the storage area of the memory system 3. The logical address is, for example, a logical block address (LBA).

[0026] The number of target erased blocks is data indicating the number of erased blocks to be secured in the NAND flash memory 4. An erased block is a block in which the data erasure operation has been completed and the program operation has not been performed yet.

[0027] The controller 6 can be constituted by a circuit such as a System-on-a-chip (SoC). The controller 6 may be constituted by a plurality of semiconductor chips. The controller 6 is electrically connected to the NAND flash memory 4 and is configured to control the NAND flash memory 4. The functions of each part in the controller 6 may be realized by dedicated hardware in the controller 6 or may be realized by a processor that executes FW.

[0028] The controller 6 may function as a flash translation layer (FTL) configured to execute data management and block management of the NAND flash memory 4. The data management executed by this FTL includes (1) management of mapping information indicating the correspondence between each logical address and each physical address of the NAND flash memory 4, and (2) processing for hiding the difference between the data read / write operation in page units and the data erasure operation in block units. Block management includes management of bad blocks, wear leveling, and garbage collection (GC).

[0029] The management of the mapping between each logical address and each physical address is performed, for example, using a logical-physical address translation table 52. The controller 6 manages the mapping between each logical address and each physical address in specific management size units using the logical-physical address translation table 52. The physical address corresponding to a certain logical address indicates the physical storage location in the NAND-type flash memory 4 where the data of this logical address is written. The controller 6 manages a plurality of storage areas obtained by logically dividing the storage area of the NAND-type flash memory 4 using the logical-physical address translation table 52. The size of each of these plurality of storage areas is the above-described management size. These plurality of storage areas respectively correspond to a plurality of logical addresses. That is, each of these plurality of storage areas is specified by one logical address. The logical-physical address translation table 52 may be loaded from the NAND-type flash memory 4 into the DRAM 5 when the memory system 3 is activated.

[0030] Data writing to one memory cell is possible only once per P / E cycle. For this reason, the controller 6 writes the updated data corresponding to a certain logical address not to the physical storage location where the previous data corresponding to this logical address is stored, but to another physical storage location. Then, the controller 6 invalidates the previous data by updating the logical-physical address translation table 52 so as to associate this logical address with this other physical storage location. The data referred to from the logical-physical address translation table 52 (that is, the data associated with the logical address) is called valid data. Also, data not associated with any logical address is called invalid data. Valid data is data that may be read later from the host 2. Invalid data is data that is no longer likely to be read from the host 2.

[0031] Blocks within the NAND flash memory 4 are broadly classified into active blocks and free blocks. An active block stores valid data and is a block where new data cannot be written. A free block does not store valid data and is a block that can be used for writing new data after undergoing a data erasure operation. That is, a free block is used as a new write destination block after undergoing a data erasure operation. The write destination block can store valid data. A free block after the data erasure operation is completed is an erased block. Note that a free block during the data erasure operation is also referred to as an erasing block.

[0032] GC is a process of copying valid data within several active blocks where valid data and invalid data are mixed to another block (for example, an erased block). By GC, the valid data is copied to another block, and the block that becomes only invalid data is released as a free block. Therefore, by GC, the number of free blocks within the NAND flash memory 4 can be increased.

[0033] The controller 6 includes, for example, a host interface circuit (host I / F) 11, a DRAM interface circuit (DRAM I / F) 12, a NAND interface circuit (NAND I / F) 13, and a CPU 14. These host I / F 11, DRAM I / F 12, NAND I / F 13, and CPU 14 are connected via, for example, a bus 10.

[0034] The host I / F 11 is a circuit configured to receive various commands (e.g., I / O commands and various control commands) and data from host 2, and transmit responses to commands and data to host 2. The I / O commands include, for example, a write command and a read command. The control commands include, for example, an unmap command (trim command), an open command, and a close command. The unmap command is a command that requests invalidation of data corresponding to a specified logical address (or logical address range). The open command is a command that requests the start of use of a stream. The close command is a command that requests the end of use of a stream.

[0035] The DRAM I / F 12 is a DRAM control circuit configured to control access to the DRAM 5.

[0036] The NAND I / F 13 is a NAND control circuit configured to control the NAND flash memory 4. The NAND I / F 13 may be connected to a plurality of memory chips in the NAND flash memory 4 via a plurality of channels, respectively. By driving the plurality of memory chips in parallel, the access bandwidth between the controller 6 and the NAND flash memory 4 can be increased.

[0037] The CPU 14 is a processor configured to control the host I / F 11, the DRAM I / F 12, and the NAND I / F 13. The CPU 14 performs various processes by executing the FW 51 loaded from the NAND flash memory 4 to the DRAM 5. The FW 51 is a control program including a group of instructions for causing the CPU 14 to execute various processes. The CPU 14 can execute command processing and the like for processing various commands from host 2. The operation of the CPU 14 is controlled by the FW 51 executed by the CPU 14.

[0038] The functions of the respective parts within the controller 6 may be realized by dedicated hardware within the controller 6, or may be realized by the CPU 14 executing the FW 51.

[0039] The CPU 14 functions as, for example, a stream management unit 141, an allocation control unit 142, an erase control unit 143, and a write control unit 144. The CPU 14 functions as these respective parts, for example, by executing the FW 51.

[0040] The stream management unit 141 manages a plurality of streams. Specifically, the stream management unit 141 manages the start of use (open) and the end of use (close) of the streams.

[0041] In response to receiving from the host 2 a command indicating the start of use of a certain stream, the stream management unit 141 sets that stream to the open state. A command indicating the start of use of a stream is, for example, the first write command specifying that stream. Note that, as a command indicating the start of use of a stream, an open command specifying that stream may be used. Also, in response to transmitting to the host 2 a response to the open command, the stream management unit 141 may set the corresponding stream to the open state. The stream management unit 141 notifies, for example, the allocation control unit 142 of the opening of the stream.

[0042] In response to detecting either that a close command specifying the stream has been received from the host 2 or that a write command specifying the stream has not been received from the host 2 for a certain period of time, the stream management unit 141 sets that stream to the closed state. The stream management unit 141 notifies, for example, the allocation control unit 142 of the closing of the stream. Note that, after setting the stream to the closed state, in response to receiving from the host 2 a write command (or an open command specifying that stream) specifying that stream, the stream management unit 141 sets that stream to the open state again.

[0043] The allocation control unit 142 controls the allocation of general-purpose blocks and dedicated blocks and the setting of the write destination blocks.

[0044] A general-purpose block is a block that can write user data associated with a write command that does not specify any stream and user data associated with a write command that specifies a stream. A write command that does not specify any stream is also referred to as a non-stream write command. User data associated with a non-stream write command is also referred to as non-stream user data. Non-stream user data is user data that is not associated with any stream. A general-purpose block is used as a write destination block for non-stream user data and can also be used as a write destination block for user data associated with a stream.

[0045] A dedicated block is a block that can write only user data associated with a write command that specifies a corresponding stream. A write command that specifies a stream is also referred to as a stream write command. User data associated with a stream write command is also referred to as user data associated with a stream. A dedicated block is used as a write destination block for user data associated with a corresponding stream.

[0046] The allocation control unit 142 allocates an erased block in the NAND flash memory 4 as a general-purpose block. An erased block in the NAND flash memory 4 is a block that has not been allocated as either a general-purpose block or a dedicated block yet. Specifically, the allocation control unit 142 allocates an erased block as a general-purpose block, for example, in response to the activation of the memory system 3. Also, the allocation control unit 142 allocates a new erased block as a general-purpose block in response to the completion of data writing to the entire general-purpose block.

[0047] The allocation control unit 142 allocates an erased block in the NAND flash memory 4 as a dedicated block corresponding to a stream in the open state. Specifically, when a stream is opened, the allocation control unit 142 can allocate an erased block as a dedicated block corresponding to the stream. Further, in response to the completion of data writing to the entire dedicated block allocated to a stream, the allocation control unit 142 can allocate a new erased block as the dedicated block corresponding to the stream. If there is no erased block that can be allocated as a dedicated block corresponding to a stream, the allocation control unit 142 sets a general-purpose block as the write destination block of the stream. Further, in response to detecting the closure of a stream, the allocation control unit 142 can change the dedicated block corresponding to the stream to a general-purpose block.

[0048] The allocation control unit 142 determines the target number of erased blocks based on the number of streams in the open state. The allocation control unit 142 sets, for example, a number obtained by adding 1 to the number of streams in the open state as the target number of erased blocks. In this case, the target number of erased blocks corresponds to the total of the number of erased blocks to be allocated as dedicated blocks to each stream in the open state and the number of erased blocks to be allocated as general-purpose blocks.

[0049] The erase control unit 143 selects one free block from one or more free blocks in the NAND flash memory 4 and performs a data erase operation on the selected free block. Specifically, the erase control unit 143 controls the execution of the data erase operation on the free block based on the number of erased blocks included in the NAND flash memory 4 and the target number of erased blocks. The erase control unit 143 performs the data erase operation on the free block while the number of erased blocks included in the NAND flash memory 4 is less than the target number of erased blocks. The erase control unit 143 does not perform the data erase operation on the free block while the number of erased blocks included in the NAND flash memory 4 is greater than or equal to the target number of erased blocks.

[0050] The write control unit 144 performs processing according to the write command received from the host 2. Specifically, the write control unit 144 performs processing for writing the associated user data to the general-purpose block in response to a non-stream write command. The write control unit 144 performs processing for writing the associated user data to the write destination block corresponding to the stream in response to a stream write command. The write destination block corresponding to the stream is a dedicated block or a general-purpose block allocated to the stream.

[0051] In this way, the stream management unit 141, the allocation control unit 142, the erase control unit 143, and the write control unit 144 implement a data write operation corresponding to the multi-stream function. More specific operation examples of the stream management unit 141, the allocation control unit 142, the erase control unit 143, and the write control unit 144 will be described later with reference to FIGS. 5 to 9.

[0052] Here, in the memory system according to the comparative example, two cases where the execution of the write command is delayed will be described. The memory system of the comparative example has a multi-stream function. The delay in the execution of the write command occurs, for example, due to a shortage of erased blocks allocated as write destination blocks.

[0053] FIG. 2 shows a case (hereinafter referred to as the first case) where there is a shortage of erased blocks when a plurality of streams are opened in a short period in the memory system of the comparative example. In the first case, the 0th block WB0, the 1st block WB1, and the 2nd block WB2 are respectively allocated to the non-stream 30C, the 1st stream 31C, and the 2nd stream 32C. The 0th block WB0 stores the user data 41 of the non-stream 30C. The 1st block WB1 stores the user data 42 associated with the 1st stream 31C. The 2nd block WB2 does not store any data yet. The NAND type flash memory in the memory system includes one erased block EB0 and one erasing block EB1.

[0054] In the first case, two streams, the 3rd stream 33C and the 4th stream 34C, are simultaneously opened ((1) in FIG. 2). In response to the opening of the 3rd stream 33C, the erased block EB0 is allocated as the write destination block of the 3rd stream 33C ((2) in FIG. 2).

[0055] On the other hand, since no allocatable erased block is secured, in response to the opening of the 4th stream 34C, an erased block cannot be allocated as the write destination block of the 4th stream 34C. Therefore, until the data erasing operation for the erasing block EB1 is completed and the erased block EB1 is obtained, the erased block EB1 is not allocated to the 4th stream 34C ((3) in FIG. 2).

[0056] Therefore, in the memory system of the comparative example, in the first case, the execution of the write command specifying the fourth stream 34C is delayed.

[0057] FIG. 3 shows a case (hereinafter referred to as the second case) where an erased block is insufficient when data is written to the entire area of each of a plurality of blocks in a short period in the memory system of the comparative example. The relationships among the non-stream 30C, the first stream 31C, the second stream 32C, the zero-th block WB0, the first block WB1, the second block WB2, the erased block EB0, and the erasing block EB1 in the second case are the same as those in the first case.

[0058] In the second case, data is written to the entire area of each of the two blocks, i.e., the zero-th block WB0 and the first block WB1, in a short period (see (1) in FIG. 3). In response to the completion of the data writing to the entire zero-th block WB0, the erased block EB0 is newly assigned as the write destination block of the non-stream 30C (see (2) in FIG. 3).

[0059] On the other hand, since no assignable erased block is secured, in response to the completion of the data writing to the entire first block WB1, an erased block cannot be assigned as the write destination block of the first stream 31C. Therefore, until the data erasing operation for the erasing block EB1 is completed and the erased block EB1 is obtained, the erased block EB1 cannot be assigned to the first stream 31C (see (3) in FIG. 3).

[0060] Therefore, in the memory system of the comparative example, in the second case, the execution of the write command specifying the first stream 31C is delayed.

[0061] Furthermore, in the memory system of the comparative example, the storage area of the block assigned to the stream may be wasted.

[0062] FIG. 4 shows a case where the storage area of a block allocated to a stream becomes wasted in the memory system of the comparative example (hereinafter referred to as the third case). The relationships among the non-stream 30C, the first stream 31C, the second stream 32C, the block WB0, the block WB1, the block WB2, the erased block EB0, and the erasing block EB1 in the third case are the same as those in the first case.

[0063] In the third case, write commands are no longer received from the host in the first stream 31C and the second stream 32C (FIG. 4(1)). That is, the write command designating the first stream 31C and the write command designating the second stream 32C are no longer received from the host.

[0064] In this case, in the block WB1, after user data is written partway, since the write command designating the first stream 31C is not received, the storage area where data has not yet been written (unwritten area) becomes wasted (FIG. 4(2)). Also, in the block WB2, after being allocated to the second stream 32C, since the write command designating the second stream 32C is not received, the entire storage area becomes wasted (FIG. 4(3)).

[0065] Therefore, in the memory system of the comparative example, in the third case, since the write command designating a stream is no longer received from the host 2, the storage area of the block allocated to that stream may become wasted.

[0066] As described above, in the memory system of the comparative example, the execution of the write command designating a stream may be delayed, and the storage area of the block allocated to the stream may become wasted.

[0067] In contrast, in the memory system 3 according to the present embodiment, when the use of a stream is started, the controller 6, if there are two or more erased blocks, assigns an erased block (dedicated block) as the write destination block corresponding to the stream, and if there are no two or more erased blocks, sets a general-purpose block as the write destination block corresponding to the stream. That is, the controller 6 assigns an erased block (dedicated block) or sets a general-purpose block as the write destination block of the stream according to the number of erased blocks included in the NAND flash memory 4. Thereby, the controller 6 can execute the write command specifying the stream without delay regardless of whether there is an erased block that can be assigned as the write destination block of the stream.

[0068] Further, when the use of a stream ends, the controller 6 changes the dedicated block assigned to the stream to a general-purpose block. Thereby, the controller 6 can use the unwritten area of the dedicated block assigned to the stream that has ended its use without wasting it for storing user data.

[0069] Note that after the controller 6 changes the dedicated block assigned to the stream to a general-purpose block, in response to the resumption of the use of the stream, the controller 6 can change the general-purpose block back to a dedicated block again. Therefore, the controller 6 can also continuously assign the dedicated block to the stream whose use has been resumed.

[0070] With reference to FIGS. 5 to 9, the operations of the stream management unit 141, allocation control unit 142, erase control unit 143, and write control unit 144 of the memory system 3 will be specifically described.

[0071] FIG. 5 shows an example of an operation of allocating dedicated blocks to a stream whose use is started (i.e., a stream that becomes open) in the memory system 3. In the example shown in FIG. 5, it is assumed that a general-purpose block GB is allocated to a non-stream 30 and a first dedicated block DB1 is allocated to a first stream 31 (stream#1). The general-purpose block GB stores user data 61 of the non-stream 30. The first dedicated block DB1 stores user data 62 associated with the first stream 31. Since there is one open stream, the target number of erased blocks is, for example, 2 (= the number of open streams + 1). The NAND type flash memory 4 includes two erased blocks EB0 and EB1.

[0072] In response to receiving the first write command designating the second stream 32 (stream#2), the stream management unit 141 opens the second stream 32 (1) in FIG. 5.

[0073] Based on the number of open streams, the allocation control unit 142 changes the target number of erased blocks from 2 to 3 (2) in FIG. 5. That is, in response to the second stream 32 becoming open, the allocation control unit 142 increases the target number of erased blocks by 1. In response to the number of erased blocks becoming less than the target number of erased blocks, the erase control unit 143 starts a data erase operation on a free block.

[0074] Next, since the two or more erased blocks EB0 and EB1 are included in the NAND type flash memory 4, the allocation control unit 142 allocates the erased block EB0 as the dedicated block DB2 (second dedicated block DB2) of the second stream 32 (see (3) in FIG. 5). This is because even if the data writing to the entire general-purpose block GB is completed after the erased block EB0 is allocated to the second stream 32, the erased block EB1 can be allocated as the next general-purpose block GB. The allocation control unit 142 allocating the erased block EB0 as the second dedicated block DB2 means setting the second dedicated block DB2 (= erased block EB0) as the dedicated write destination block of the second stream 32. Note that the allocation control unit 142 may allocate the erased block EB1 as the second dedicated block DB2. The write control unit 144 writes the associated user data to the second dedicated block DB2 in response to the write command designating the second stream 32.

[0075] Thus, when the second stream 32 becomes open while two or more erased blocks are included in the NAND type flash memory 4, the allocation control unit 142 allocates any one of the erased blocks as the second dedicated block DB2 corresponding to the second stream 32. Thereby, the write control unit 144 can execute the write command of the second stream 32 without delay, using the second dedicated block DB2 as the write destination block.

[0076] Also, the allocation control unit 142 changes the target number of erased blocks according to the number of open streams.

[0077] In the NAND flash memory 4, the erased blocks that are secured and not used for data writing reduce the writable storage capacity in the memory system 3. Therefore, securing an excessive number of erased blocks may lead to a degradation in the performance of the memory system 3. An excessive number of erased blocks are, for example, the erased blocks corresponding to the maximum number of streams manageable by the memory system 3. Also, in this case, although the allocation of erased blocks to the open streams is not delayed, there are erased blocks that require time from when the data erasure operation is completed until they are actually used for data writing. In such erased blocks, the quality of the stored data may deteriorate.

[0078] In the memory system 3, the allocation control unit 142 sets the target number of erased blocks according to the number of open streams, so as not to secure an excessive number of erased blocks. Therefore, the memory system 3 can secure a sufficient total writable capacity even when the streams are not opened while maintaining the over-provisioning (OP).

[0079] FIG. 6 shows an example of an operation of setting a general-purpose block as a write destination block for a stream whose use is started in the memory system 3. Here, it is assumed that a general-purpose block GB is allocated to the non-stream 30. The general-purpose block GB stores the user data 63 of the non-stream 30. Since there are no open streams, the target number of erased blocks is, for example, 1. The NAND flash memory 4 includes one erased block EB0.

[0080] In response to receiving the first write command designating the first stream 31, the stream management unit 141 opens the first stream 31 ( (1) in FIG. 6).

[0081] The allocation control unit 142 changes the target number of erased blocks from 1 to 2 based on the number of open streams (item (2) in FIG. 6). That is, the allocation control unit 142 increases the target number of erased blocks by 1 in response to the first stream 31 becoming open. The erase control unit 143 starts a data erase operation on free blocks in response to the number of erased blocks becoming less than the target number of erased blocks. Here, the free block during the data erase operation is the erase-in-progress block EB1.

[0082] Since the NAND flash memory 4 contains only one erased block EB0 (that is, there are no two or more erased blocks), the allocation control unit 142 does not allocate the erased block EB0 to the first stream 31 (item (3) in FIG. 6). The allocation control unit 142 sets the general-purpose block GB as the write destination block for the first stream 31 (item (4) in FIG. 6).

[0083] As a result, the write control unit 144 can write the user data 64 associated with the write command of the first stream 31 to the general-purpose block GB without waiting for the completion of the data erase operation on the erase-in-progress block EB1. Therefore, even when the NAND flash memory 4 does not contain an erased block that can be allocated to the first stream 31 that has become open, the write control unit 144 can execute the write command of the first stream 31 without delay with the general-purpose block GB as the write destination block.

[0084] Note that the allocation control unit 142 can change the write destination block of the stream from the general-purpose block GB to a dedicated block.

[0085] FIG. 7 shows an example of an operation of changing the write destination block of the first stream 31 in the example shown in FIG. 6 from the general-purpose block GB to a dedicated block.

[0086] After setting the general-purpose block GB as the write destination block for the first stream 31, the allocation control unit 142 predicts whether a new erased block will be acquired before the data writing to the entire general-purpose block GB is completed. That is, the allocation control unit 142 predicts whether the data erasing operation on the erasing block EB1 by the erasing control unit 143 will be completed before the data writing to the entire general-purpose block GB is completed. For this prediction, for example, the maximum data writing speed for the blocks in the NAND flash memory 4 and the time required for the data erasing operation for one block (data erasing time) are used. The maximum data writing speed is, for example, the data writing speed when the writing performance based on the specifications of the memory system 3 is exhibited. The maximum data writing speed may be, for example, the maximum speed of the program operation in the NAND flash memory 4. The maximum data writing speed may be, for example, the maximum reception speed of user data from the host 2 in a certain period in the past.

[0087] More specifically, for example, the allocation control unit 142 calculates the time (first time) when the data writing to the entire general-purpose block GB is completed based on the size of the unwritten area in the general-purpose block GB (that is, the remaining storage capacity in the general-purpose block GB) and the maximum data writing speed for the blocks in the NAND flash memory 4. Further, the allocation control unit 142 calculates the time (second time) when the data erasing operation on the erasing block EB1 is completed based on the time when the data erasing operation on the erasing block EB1 is started and the data erasing time for one block. When the second time is earlier than the first time, the allocation control unit 142 predicts that a new erased block EB1 will be acquired before the data writing to the entire general-purpose block GB is completed. When the second time is after the first time, the allocation control unit 142 predicts that a new erased block EB1 will not be acquired before the data writing to the entire general-purpose block GB is completed.

[0088] If the allocation control unit 142 predicts that a new erased block EB1 will be acquired before the data writing to the entire general-purpose block GB is completed, it allocates the erased block EB0 as the first dedicated block DB1 corresponding to the first stream 31 (step (1) in FIG. 7). Then, the allocation control unit 142 changes the write destination block of the first stream 31 from the general-purpose block GB to the first dedicated block DB1 (step (2) in FIG. 7). That is, by the operations of steps (1) and (2) in FIG. 7, the erased block EB0 is allocated as the write destination block of the first stream 31.

[0089] As a result, the write control unit 144 can write the user data associated with the write command designating the first stream 31 to the first dedicated block DB1 instead of the general-purpose block GB.

[0090] Note that even when the data writing to the entire dedicated block allocated to the stream is completed, the allocation control unit 142 allocates a new erased block as the dedicated block corresponding to the stream (i.e., the dedicated write destination block) or sets a general-purpose block as the write destination block of the stream in the same manner as the operations shown in FIGS. 5 to 7.

[0091] FIG. 8 shows an example of an operation of using the dedicated block allocated to a stream whose use has ended (i.e., a stream for which a close has been detected) as a general-purpose block in the memory system 3. Here, it is assumed that the general-purpose block GB is allocated to the non-stream 30 and the first dedicated block DB1 is allocated to the first stream 31. The general-purpose block GB stores the user data 65 of the non-stream 30. The first dedicated block DB1 stores the user data 66 associated with the first stream 31. Since the number of target erased blocks is, for example, 2 because there is one open stream. The NAND type flash memory 4 includes two erased blocks EB0 and EB1.

[0092] The stream management unit 141 detects the close of the first stream 31 ((1) in FIG. 8). The stream management unit 141 detects the close of the first stream 31, for example, either by receiving a close command from the host 2 or by not receiving a write command specifying the first stream 31 from the host 2 for a certain period of time.

[0093] Based on the number of open streams, the allocation control unit 142 changes the target number of erased blocks from 2 to 1 ((2) in FIG. 8). That is, in response to detecting the close of the first stream 31, the allocation control unit 142 decreases the target number of erased blocks by 1. Then, the allocation control unit 142 changes the first dedicated block DB1 assigned to the first stream 31 to a general-purpose block ((3) in FIG. 8). The general-purpose block changed from the first dedicated block DB1 is referred to as the first general-purpose block DB1.

[0094] Next, in response to the completion of data writing to the entire general-purpose block GB ((4) in FIG. 8), the allocation control unit 142 changes the general-purpose block used as the write destination block (hereinafter, also referred to as the write destination general-purpose block) from the general-purpose block GB to the first general-purpose block DB1 ((5) in FIG. 8). That is, the first dedicated block DB1 assigned to the first stream 31 in which the close is detected is used as the new write destination general-purpose block.

[0095] Thereby, the write control unit 144 can write user data to the first general-purpose block DB1. User data such as the user data 67 of the non-stream 30 and user data associated with a stream to which no dedicated block is assigned can be written to the first general-purpose block DB1. Therefore, it can be used for storing user data without wasting the unwritten area in the first dedicated block DB1.

[0096] In addition, when the use of the first stream 31 in which a close is detected is resumed, the allocation control unit 142 can also return the first general-purpose block DB1 to the first dedicated block DB1.

[0097] FIG. 9 shows an example of an operation of returning to a dedicated block after changing a dedicated block assigned to a stream in which a close is detected in the memory system 3 to a general-purpose block. The operations from (1) to (3) in FIG. 9 are the same as the operations from (1) to (3) in FIG. 8.

[0098] After the stream management unit 141 changes the first dedicated block DB1 to the first general-purpose block DB1, for example, in response to receiving a write command specifying the first stream 31 from the host 2, the first stream 31 is opened again (in (4) in FIG. 9).

[0099] In response to the first stream 31 being opened again, the allocation control unit 142 returns the target number of erased blocks from 1 to 2 (in (5) in FIG. 9). Then, after the first dedicated block DB1 is changed to the first general-purpose block DB1, before new user data is written to the first general-purpose block DB1, in response to the first stream 31 being opened again, the allocation control unit 142 returns the first general-purpose block DB1 to the first dedicated block DB1 (in (6) in FIG. 9). That is, the allocation control unit 142 reallocates the first general-purpose block DB1 as the first dedicated block DB1 corresponding to the first stream 31.

[0100] Thus, before the light control unit 144 newly writes user data to the first general-purpose block DB1, when a write command specifying the first stream 31 is received from the host 2, the allocation control unit 142 returns the target number of erased blocks and the first general-purpose block DB1 to the state before the close of the first stream 31 is detected. Thereby, the light control unit 144 can continuously write the associated user data to the first dedicated block DB1 in response to the write command specifying the first stream 31. Therefore, for example, user data associated with a plurality of write commands each specifying the first stream 31 can be stored in the entire first dedicated block DB1.

[0101] For example, it is highly likely that consecutive write commands specifying the same stream are associated with continuous user data. The continuous user data may be unmapped simultaneously. For example, when all the user data stored in a block is unmapped simultaneously, that block becomes a free block without being a target for GC. Therefore, by storing the user data associated with the write commands specifying the same stream in the entire block, the processing amount for making that block a free block can be reduced.

[0102] Next, with reference to FIGS. 10 to 12, the processing executed in the memory system 3 will be described.

[0103] FIG. 10 is a flowchart showing an example of the procedure of the first allocation process executed by the CPU 14. The first allocation process is a process of setting a write destination block for an open stream. The CPU 14 executes the first allocation process, for example, in response to one stream becoming open. Hereinafter, the open stream is referred to as the first target stream.

[0104] First, the CPU 14 increments the number of erased blocks whose erasure has been completed by 1 (step S101). Next, the CPU 14 determines whether or not the NAND flash memory 4 contains two or more erased blocks (step S102).

[0105] When the NAND flash memory 4 contains two or more erased blocks (yes in step S102), the CPU 14 allocates an erased block as a dedicated block for the first target stream (step S103), and the processing by the CPU 14 proceeds to step S109. This dedicated block is used as a write destination block for the first target stream. That is, the user data associated with the write command designating the first target stream is written to this dedicated block.

[0106] When the NAND flash memory 4 does not contain two or more erased blocks (no in step S102), the CPU 14 sets a general-purpose block as the write destination block for the first target stream (step S104). As a result, the user data associated with the write command designating the first target stream is written to the general-purpose block instead of the dedicated block. Then, the CPU 14 determines whether or not the NAND flash memory 4 contains one erased block (step S105).

[0107] When the NAND flash memory 4 does not contain any erased blocks at all (no in step S105), the processing by the CPU 14 returns to step S105. That is, the processing of step S105 is repeatedly performed until it is determined that there is one erased block.

[0108] When the NAND flash memory 4 contains one erased block (yes in step S105), the CPU 14 determines whether a new erased block is acquired before the data writing to the entire general-purpose block is completed (step S106). The CPU 14 determines whether a new erased block is acquired before the data writing to the entire general-purpose block is completed, based on, for example, the maximum data writing speed for the blocks of the NAND flash memory 4 and the data erasing time for one block.

[0109] When a new erased block is not acquired before the data writing to the entire general-purpose block is completed (no in step S106), the process by the CPU 14 returns to step S105. That is, the processes of step S105 and step S106 are repeatedly performed until it is determined that there is one erased block in the NAND flash memory 4 and a new erased block is acquired before the data writing to the entire general-purpose block is completed.

[0110] When a new erased block is acquired before the data writing to the entire general-purpose block is completed (yes in step S106), the CPU 14 allocates the erased block as a dedicated block for the first target stream (step S107). Then, the CPU 14 changes the write destination block of the first target stream from the general-purpose block to the dedicated block (that is, the allocated erased block) (step S108), and the process by the CPU 14 proceeds to step S109.

[0111] After performing the process of either step S103 or step S108, the CPU 14 determines whether the target number of erased blocks exceeds the number of erased blocks (step S109). If the target number of erased blocks exceeds the number of erased blocks (yes in step S109), the CPU 14 selects one free block in the NAND flash memory 4 and starts a data erasing process for that free block (step S110), and ends the first allocation process. On the other hand, if the target number of erased blocks is less than or equal to the number of erased blocks (no in step S109), the CPU 14 ends the first allocation process.

[0112] Through the above first allocation process, when the NAND flash memory 4 contains two or more erased blocks, the CPU 14 allocates the erased blocks to the first target stream. Also, when the NAND flash memory 4 does not contain two or more erased blocks, the CPU 14 sets a general-purpose block as the write destination block for the first target stream. After that, when there is one erased block in the NAND flash memory 4 and a new erased block is acquired before the data writing to the entire general-purpose block is completed, the CPU 14 allocates the erased block (dedicated block) to the first target stream in response. Thereby, regardless of whether there is an erased block that can be allocated as the write destination block for the first target stream, the CPU 14 can execute the write command designating the first target stream without delay.

[0113] Note that, even when the data writing to the entire dedicated block assigned to the first target stream is completed, the CPU 14 similarly performs a process of newly setting the write destination block of the first target stream. This process is, for example, the process excluding the process of step S101 from the first allocation process. Therefore, even when the data writing to the entire dedicated block assigned to the first target stream is completed, the CPU 14 can execute the write command specifying the first target stream without delay regardless of whether there is a new erased block that can be assigned as the write destination block of the first target stream.

[0114] FIG. 11 is a flowchart showing an example of the procedure of the allocation change process executed by the CPU 14. The allocation change process is a process for using the dedicated block assigned to the stream in which a close is detected. The CPU 14 executes the allocation change process in response to detecting the close of one stream. Hereinafter, the stream in which a close is detected is referred to as the second target stream. It is assumed that a dedicated block is assigned to the second target stream.

[0115] First, the CPU 14 decreases the target number of erased blocks by 1 (step S201). The CPU 14 changes the dedicated block assigned to the second target stream to a general-purpose block (hereinafter referred to as the second general-purpose block) (step S202).

[0116] Next, the CPU 14 determines whether it has received a write command specifying the second target stream (step S203). That is, after detecting the close of the second target stream, the CPU 14 determines whether it has received the write command specifying the second target stream again.

[0117] When the write command specifying the second target stream is received (yes in step S203), the CPU 14 determines whether user data has been newly written to the second general-purpose block (step S204). That is, the CPU 14 determines whether any of the non-stream user data and the user data associated with the stream to which the dedicated block is not assigned has been written to the second general-purpose block after step S202.

[0118] When user data has been newly written to the second general-purpose block (yes in step S204), the CPU 14 executes the first allocation process for the second target stream (step S205) and ends the allocation change process. That is, since the dedicated block assigned to the second target stream has already been used as a general-purpose block, the CPU 14 executes the first allocation process to set a new write destination block for the second target stream. The procedure of the first allocation process is as described above with reference to FIG. 10.

[0119] When user data has not been newly written to the second general-purpose block (no in step S204), the CPU 14 returns the second general-purpose block to the dedicated block of the second target stream (step S206). This dedicated block is reused as the write destination block of the second target stream. Then, the CPU 14 increments the target number of erased blocks by 1 (step S207) and ends the allocation change process.

[0120] If the write command specifying the second target stream has not been received (no in step S203), the CPU 14 determines whether user data has been newly written to the second general-purpose block (step S208). If user data has not been newly written to the second general-purpose block (no in step S208), the process by the CPU 14 returns to step S203. That is, after the CPU 14 changes the dedicated block of the second target stream to the second general-purpose block, when the write command specifying the second target stream is received, the CPU 14 performs the processing from step S203 to step S207 to resume the use of the second target stream.

[0121] If user data has been newly written to the second general-purpose block (yes in step S208), the CPU 14 ends the allocation change process. That is, when user data has been newly written to the second general-purpose block without receiving the write command specifying the second target stream, it is determined that the second general-purpose block will be used as a general-purpose block.

[0122] Through the above allocation change process, the CPU 14 can use the dedicated block assigned to the closed second target stream as a general-purpose block. That is, the CPU 14 can use the unwritten storage area in the dedicated block as the storage area of the general-purpose block without wasting it. Also, after the CPU 14 changes the dedicated block to a general-purpose block, if the use of the second target stream is resumed before user data is newly written to the general-purpose block, the CPU 14 returns the general-purpose block to a dedicated block. In this way, the CPU 14 can effectively use the storage area of the block by changing the use of the assigned block according to the usage status of the second target stream.

[0123] FIG. 12 is a flowchart showing an example of the procedure of the second allocation process executed by the CPU 14. The second allocation process is a process of allocating general-purpose blocks. The CPU 14 executes the second allocation process, for example, in response to the completion of data writing to the entire general-purpose block (the general-purpose block of the write destination) used as the write destination block.

[0124] First, the CPU 14 determines whether there is a general-purpose block different from the current write destination general-purpose block included in the NAND flash memory 4 (step S31). The different general-purpose block is, for example, a general-purpose block changed from the dedicated block of the stream in response to the detection of the close of the stream.

[0125] If there is a different general-purpose block included in the NAND flash memory 4 (yes in step S31), the CPU 14 sets that different general-purpose block as the new write destination general-purpose block (step S32) and ends the second allocation process.

[0126] If there is no different general-purpose block included in the NAND flash memory 4 (no in step S31), the CPU 14 allocates the erased block as the new write destination general-purpose block (step S33) and ends the second allocation process.

[0127] By the above second allocation process, the CPU 14 can set either a different general-purpose block or an erased block as the new write destination general-purpose block in response to the completion of data writing to the entire current write destination general-purpose block.

[0128] When a different general-purpose block is set as the write destination general-purpose block, the CPU 14 can effectively use, for example, the unwritten area in the general-purpose block changed from the dedicated block.

[0129] Also, when an erased block is assigned as a general-purpose block to be written to, the CPU 14 can assign the erased block as a general-purpose block without delay. The CPU 14 secures an erased block so that the erased block can be newly assigned as a general-purpose block at the timing when data writing to the entire general-purpose block is completed. That is, there is no shortage of erased blocks that should be newly assigned as general-purpose blocks at the timing when data writing to the entire general-purpose block is completed.

[0130] Therefore, even when data writing to the entire general-purpose block to be written to is completed, the CPU 14 can write the associated user data to a new general-purpose block to be written to without delay in response to a non-stream write command or a write command specifying a stream to which no dedicated block is assigned.

[0131] As described above, according to the present embodiment, it is possible to reduce the delay in processing in response to a write request. The stream management unit 141 can manage a plurality of streams. The allocation control unit 142 allocates, as a general-purpose block to which data not associated with any of the plurality of streams and data associated with any of the plurality of streams can be written, a first erased block in which the data erasure operation has been completed among the plurality of blocks included in the NAND type flash memory 4. When the use of the first stream is started, the allocation control unit 142 allocates a second erased block as a write destination block corresponding to the first stream if two or more erased blocks in which the data erasure operation has been completed are included in the plurality of blocks. When the use of the first stream is started, the allocation control unit 142 sets a general-purpose block as a write destination block corresponding to the first stream if two or more erased blocks in which the data erasure operation has been completed are not included in the plurality of blocks.

[0132] As a result, in response to the write request received in the first stream (for example, a write command specifying the first stream), the light control unit 144 can write the associated user data without delay to the write destination block, which is either the second erased block or the general-purpose block. Therefore, in the memory system 3 having a multi-stream function, the delay in processing in response to a write request can be reduced.

[0133] Each of the various functions described in this embodiment may be implemented by a circuit (processing circuit). Examples of the processing circuit include a programmed processor such as a central processing unit (CPU). This processor executes each of the described functions by executing a computer program (group of instructions) stored in the memory. This processor may be a microprocessor including an electric circuit. Examples of the processing circuit also include a digital signal processor (DSP), an application specific integrated circuit (ASIC), a microcontroller, a controller, and other electric circuit components. Each of the other components other than the CPU described in this embodiment may also be implemented by a processing circuit.

[0134] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and their modifications are included in the scope and gist of the invention, and are included in the invention described in the claims and its equivalent scope.

Description of Reference Numerals

[0135] 1... Information processing system, 2... Host, 3... Memory system, 4... NAND flash memory, 5... DRAM, 6... Controller, 11... Host I / F, 12... DRAM I / F, 13... NAND I / F, 14... CPU, 141... Stream management unit, 142... Allocation control unit, 143... Erase control unit, 144... Write control unit, 51... FW, 52... Logical-physical address translation table, 53... Control information.

Claims

1. A memory system connectable to a host, comprising: a non-volatile memory including a plurality of blocks; electrically connected to the non-volatile memory, managing a plurality of streams, allocating, as a general-purpose block capable of writing data not associated with any of the plurality of streams and data associated with any of the plurality of streams, a first erased block in which a data erasure operation has been completed among the plurality of blocks; when the use of a first stream among the plurality of streams is started, if two or more erased blocks in which the data erasure operation has been completed are included in the plurality of blocks, allocating a second erased block as a write destination block corresponding to the first stream; when the use of the first stream is started, if two or more erased blocks in which the data erasure operation has been completed are not included in the plurality of blocks, configured to set the general-purpose block as a write destination block corresponding to the first stream a controller; A memory system.

2. After the controller further sets the general-purpose block as a write destination block corresponding to the first stream, if a third erased block in which the data erasure operation has been completed is included in the plurality of blocks and a new erased block is predicted to be acquired before the writing of data to the entire general-purpose block is completed, the controller is configured to allocate the third erased block as a write destination block corresponding to the first stream. The memory system according to claim 1.

3. The controller is configured to predict whether a new erased block will be acquired before the writing of data to the entire general-purpose block is completed, using the maximum data writing speed to the general-purpose block and the time required for the data erasure operation for the blocks in the non-volatile memory. The memory system according to claim 2.

4. The controller is further configured to change the third erased block allocated as a write destination block corresponding to the first stream to the general-purpose block in response to the end of the use of the first stream. The memory system according to claim 2.

5. After further changing the third erased block to the general-purpose block, before data is newly written to the third erased block changed to the general-purpose block, in response to the restart of the use of the first stream, the controller is configured to reassign the third erased block as the write destination block corresponding to the first stream. The memory system according to claim 4.

6. The controller is further configured to change the second erased block assigned as the write destination block corresponding to the first stream to the general-purpose block in response to the end of the use of the first stream. The memory system according to claim 1.

7. After further changing the second erased block to the general-purpose block, before data is newly written to the second erased block changed to the general-purpose block, in response to the restart of the use of the first stream, the controller is configured to reassign the second erased block as the write destination block corresponding to the first stream. The memory system according to claim 6.

8. The controller determines a second number of erased blocks to be secured based on a first number of streams in use, and is configured to perform the data erasure operation on the blocks that do not store valid data among the plurality of blocks so as to secure the second number of erased blocks. The memory system according to any one of claims 1 to 7.

9. The controller increases the second number by 1 when the use of the first stream is started, and decreases the second number by 1 when the use of the first stream ends. The memory system according to claim 8.

10. The controller is further configured to write the data associated with the first write request to the general-purpose block in response to receiving the first write request not specifying any stream from the host, and write the data associated with the second write request to the write destination block corresponding to the first stream in response to receiving the second write request specifying the first stream from the host. The memory system according to claim 1.

11. The controller is further When the writing of data to the entire second erased block assigned as the write destination block corresponding to the first stream is completed, if two or more erased blocks for which the data erasure operation has been completed are included in the plurality of blocks, a third erased block is assigned as the write destination block corresponding to the first stream, When the writing of data to the entire second erased block assigned as the write destination block corresponding to the first stream is completed, if two or more erased blocks for which the data erasure operation has been completed are not included in the plurality of blocks, it is configured to set the general-purpose block as the write destination block corresponding to the first stream, The memory system according to claim 1.

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