65 results about "Data erasure" patented technology

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register. Data is scrubbed in the background by moving data from a location in a memory array to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Status data is recorded for any writes that occur to the array location during the scrubbing. After scrubbing is complete, some or all portions of the scrubbed data are moved back to the array location. The status data is used to identify those portions to move back.

According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

The invention provides an FPGA remote updating method and a related device, and belongs to the technical field of FPGA remote updating. After a first FPGA board card receives a remote updating command, the state of a jump control area synchronization head is obtained from a jump control area, and which application bit stream area is updated is determined based on the state of the jump control area synchronization head; the first FPGA board card erases data in the first application bit stream area or the second application bit stream area; after the data of the first application bit stream area or the second application bit stream area is erased, the second FPGA board card transmits the update data to the first FPGA board card; the first FPGA board card reads back the updated data from the Flash memory, and performs CRC (Cyclic Redundancy Check) on the read-back updated data to obtain a CRC result; and based on a CRC result, determining whether remote updating of the first FPGA board card is completed or not. The method solves the problems that after FPGA logic codes are modified, programming needs to be conducted block by block, a large amount of time and manpower are occupied, and the project progress is seriously affected.

[Problem] To both recover a greater amount of valuable material from a used product obtained by mixing a reused item and a recycled item, suppressing the amount of waste to the extent possible, and create an environment that eliminates concerns regarding data leakage and allows a provider, who provides worn-out electronic devices, to provide a used item to a collector without anxiety. [Solution] A used product recovery device 1 comprises: an authentication unit 23 that authenticates a user 102; a data erasure unit 7 that erases data stored in a used product 103; a sorting unit (reused item accommodation unit 81 and recycled item accommodation unit 82) that classifies used products from which data has been erased into two or more types including reused items and recycled items; and an association information providing unit 21 that provides, to an external device 106 related to confirmation of data erasure with respect to the reused items and the like, association information indicating an association between the user 102 authenticated by the authentication unit 23 and the reused item or the like that the user 102 desires to have picked up.

Systems, methods, and apparatus for memory management operations in a memory device. In one approach, each of multiple banks in a memory array includes a scrub holding register. Data is scrubbed in the background by moving data from a location in a memory array to the scrub holding register. Data in the scrub holding register is scrubbed by error correction circuitry shared by the multiple banks. Status data is recorded for any writes that occur to the array location during the scrubbing. After scrubbing is complete, some or all portions of the scrubbed data are moved back to the array location. The status data is used to identify those portions to move back.

The invention provides a memory device and a data erasing method thereof, which can prolong the service life. The data erasing method includes performing a first data erasing action of a memory block, where the memory block includes first to Nth word lines, N being a positive integer greater than 1; for the first word line to the Nth word line of the memory block, sequentially executing an erase verification action one by one; finding out a failed word line of the memory cell which fails to be verified for the first time in the erasing verification action; and enabling the failed word line to the Nth word line to be at least one selected word line, enabling the rest word lines to be at least one unselected word line, shielding the at least one unselected word line, and executing a second data erasing action aiming at the storage unit of the at least one selected word line.

The application provides an embedded system one-key destruction method and system based on eMMC storage, and belongs to the technical field of memory data destruction. The embedded system one-key destruction method based on eMMC storage comprises the following steps: S1: a key drive detects that a destruction key is pressed down; S2: whether the time of pressing down the destruction key exceeds a first set value is judged, if not, no operation is performed, and if yes, the next step is performed; S3: an eMMC drive scanning function detects the destruction key, and if it is detected that the destruction key is pressed down, the next step is performed; S4: an erase function of the eMMC drive is executed to erase the data of the eMMC; and S5: data destruction is completed. The application has the beneficial effect that based on the existing structure, an external MCU is not needed, and one-key destruction operation of eMMC storage can be realized through pure software.

To enable notification to a specific user of the completion of data erasure while preventing leakage and tampering of information concerning data stored in an image forming apparatus.SOLUTION: The image forming apparatus includes erasure means for erasing data stored in a storage unit, and output means for outputting, in encrypted form, notification information indicating that the data has been erased when the erasure means erases the data.SELECTED DRAWING: Figure 7

A data erasure system (100) comprising a memory (101) comprising a plurality of banks (101a-n). The data erasure system (100) further comprises a processor (102) configured to write data to and / or read data from one of the plurality of banks (101a-n) at a time. The data erasure system (100) further comprises an erasure module (106) configured to perform an erasure operation by overwriting data on two or more of the plurality of banks (101a-n) concurrently, wherein overwriting data on one of the two or 10 more banks (101a-n) is independent of overwriting data on another of the two or more banks (101a-n).

The application discloses a data erasing method and an electronic device, relates to the technical field of data processing, and comprises the following steps: a processor only allows to start a write protection closing and a data erasing process when a management board is a secondary return board type, so that the miserasing operation of a non-target scene such as first production and operation and maintenance is avoided from a scene source. In addition, the closing of the write protection function is directly linked depending on a hardware pin, so that the risk of mistriggering or vulnerability at the software level is reduced. Therefore, the data erasing method provided by the application improves the security of data erasing processing on data in a target address range.

This invention discloses a method, apparatus, device, and medium for handling erasure coding data read failures, relating to the field of distributed storage systems. The method includes: if a target number of available data blocks exist, and any object storage device among the target number of object storage devices reports an error causing data read failure, then the primary object storage device sends an error message to the client, marks the status of the erroneous object storage device, and synchronizes the status marking information to the target object list so that the client can determine whether to perform data erasure coding; if the erroneous object storage device recovers or a new object storage device is added, then the target number of available data blocks are read to obtain the original data, the target data for which the read failed is determined based on the original data, and the target data is written to the target object storage device; the status of the target object storage device is modified by the primary object storage device so that the client can re-initiate the data read request. This improves the overall stability of the storage system.

The application provides a data erasing method, device and equipment of a memory and a medium. The data erasing method comprises the following steps: obtaining a first average wear degree and a second average wear degree; reading corresponding mapping tables according to a logical address to be erased; determining an erasing mode according to a comparison result of the first average wear degree and the second average wear degree; when the first mode is adopted, determining and emptying a mapping relationship of a largest mapping table item in the mapping tables according to the logical address to be erased; when the second mode is adopted, updating a corresponding physical address in a mapping relationship of a mapping table item in the mapping tables into a preset invalid data physical address; and erasing user data and invalid data. The application provides a data erasing method, device and equipment of a memory and a medium to solve the technical problem that the life of a mapping table block and the life of user data blocks are not synchronized.

The invention provides a scan chain protection method and a chip system. The chip system comprises a scan chain, an anomaly detection unit, a safety control unit and a risk assessment unit. The anomaly detection unit obtains state information of the scan chain; the risk assessment unit determines the current risk level of the scan chain according to the state information; and if the current risk level meets the data protection condition, the security control unit shields the scan chain and erases sensitive information in the chip system. Thus, when the risk assessment unit confirms that the current risk level of the scan chain reaches the preset data protection condition, the security control unit immediately shields the scan chain and erases the sensitive information, and the sensitive information exposure window period is shortened, so that slight attack is avoided, namely destructive defense actions are met, and the security of the security control unit is improved. And an attacker is effectively prevented from acquiring residual information by using a bypass attack means before data erasing is not completed.

The application discloses an end-side idle time computing power sharing and secure transaction method and system based on a hardware root of trust, and belongs to the technical field of distributed computing and data security. A hardware-level logically isolated secure execution environment is created in a trusted execution environment through a hardware root of trust built in an end-side device, so that bidirectional isolation of task data and device data is ensured. Each transaction is jointly signed by the hardware roots of trust of both parties, so that an unalterable transaction settlement voucher is formed. The system supports user control functions such as manually accepting or rejecting a request, starting or stopping idle time sharing, and externally requesting computing power. After the execution environment is destroyed, full zero overwrite is performed, and a verifiable data erasure certificate is generated. The application solves the core problem of bidirectional trust in idle time computing power sharing, supports transaction evidence storage and public welfare donation evidence storage in accordance with legal norms, and provides a secure and reliable technical foundation for constructing a global end-side distributed computing power network.

The invention relates to the field of data communication, in particular to power equipment, a firmware upgrading method and device thereof and a program product. The method comprises the following steps: receiving differential upgrading data; performing differential reduction according to the differential upgrading data and the first firmware data before upgrading to obtain reduction data of a non-standard firmware area of the second firmware data, determining an initial address of the non-standard firmware area and setting an upgrading identifier; in the system starting process, data erasing is carried out according to the upgrading identification and the initial address, restored data is written into the non-standard firmware area, and the upgrading identification is cleared after firmware upgrading is completed. In the firmware upgrading process, only a small amount of differential upgrading data needs to be transmitted, the reduction of data transmission error probability is facilitated, the upgrading success rate is improved, only data in the non-standard firmware area needs to be erased for writing, the data erasing time can be effectively shortened, the unavailable duration of equipment is shortened, and normal operation of a system is facilitated.

The present application discloses a data erasing method and system, a secure erasing switch, and a data erasing apparatus. The method comprises: in response to a user successfully logging in by using a login password, detecting all storage medium types and partition information of a target device, and generating a plurality of storage device entries, the storage device entries comprising storage description information of devices; in response to an erasure command, converting the storage device entries and settings information into a configuration file, wherein the settings information comprises erasure levels, erasure strategy entries, and erasure rule entries; parsing the configuration file, converting storage description information in the configuration file into execution scripts, and creating worker threads for the execution scripts; and mapping erasure rules into operation instances, and using the worker threads to traverse the operation instances to execute a data erasure operation of the target device. The present application can implement data erasure of various types of storage media.

This invention discloses an attitude switch. By incorporating an eccentric weight, the switch utilizes the change in detector attitude from vertical to horizontal. The eccentric weight, under the influence of gravity, drives the connecting shaft to rotate, moving it from the first control slot into the second control slot. This further releases the limiting effect of the positioning component on the push rod within the attitude switch, causing the push rod to actuate under the action of the elastic component. This actuates the toggle switch, completing its switching function and enabling data erasure. The switch features stable performance and high reliability. It can quickly activate when the detector attitude changes, triggering the self-destruct mechanism within the detector and effectively preventing the loss of technology carried by the detector.

The present disclosure provides a chip on-orbit reconfiguration method, device, equipment and storage medium, which can be applied to the field of FPGA on-orbit reconfiguration technology. The method comprises: in response to receiving a reconfiguration instruction sent by a management end, running the reconfiguration instruction to erase data in a target address region of a first storage chip indicated by the reconfiguration instruction; returning feedback information indicating that the data erasure has been completed to the management end; writing a configuration data packet into the target address region of the first storage chip; running a restart instruction to control a service chip to enter a restart state, wherein the service chip is configured to send a resource loading instruction to a master control chip in response to being in the restart state; and in response to the resource loading instruction based on the interface timing of a second storage chip connected to the service chip, the configuration data packet is sent to the service chip, wherein the service chip is configured to perform on-orbit reconfiguration based on the configuration data packet.

Semiconductor devices, controllers, and their operating methods are disclosed. In an embodiment, a controller includes an internal command generator configured to generate overwrite operation setting information in response to a data permanent erase request to perform an overwrite operation on a data storage area corresponding to the data permanent erase request; an overwrite data generator configured to generate a plurality of unit addresses corresponding to the data storage area based on the overwrite operation setting information, and to generate a plurality of pieces of overwrite data to be written to the data storage area corresponding to the plurality of unit addresses, respectively; and a storage area controller configured to control the data storage area to store the plurality of pieces of overwrite data corresponding to the plurality of unit addresses, respectively.

Embodiments of the present application disclose a memory data erasing method, a storage device and a storage system. The method comprises the following steps: obtaining an erasing pulse number N for data erasing of a target memory block; wherein N is an integer greater than or equal to 1; applying erasing pulses to the memory block in sequence according to the erasing pulse number N; and releasing erasing charges of the memory block after the Nth erasing pulse is applied.

A data erasure method includes: a first step of causing a management server to transmit a data erasure program for a memory drive device to an information processing apparatus using cryptographic processing by a first private key; a step in which, when the data erasure program is validated using a first public key, the information processing apparatus installs the data erasure program on the memory drive device; a second step of causing the management server to transmit an erase command to the information processing apparatus using cryptographic processing by the first private key to cause a processor of the memory drive device to run the data erasure program; and a step in which, when the erase command is validated using the first public key, the information processing apparatus transmits the erase command to the memory drive device to execute data erasure processing by the data erasure program.

This application provides a data deletion method, apparatus, electronic device, storage medium, and program product. The method includes: acquiring a first data block, the first data block being determined based on a first feature value corresponding to data to be deleted, the first feature value indicating the content of the data to be deleted; determining a first transmission bandwidth, the first transmission bandwidth being used to delete the first data block; dividing the first data block based on the first transmission bandwidth to obtain multiple second data blocks; and deleting the multiple second data blocks. Thus, by using the above method, the first data block can be divided based on the first transmission bandwidth to obtain multiple second data blocks, and then the multiple second data blocks can be deleted, solving the problem that traditional feature value deletion operations affect the normal execution of front-end services.

There are provided systems and methods for a secure data erasure framework using individualized encryption key management. A service provider, including an electronic transaction processor, may provide data management and secure erasure through individualized encryption keys that may be managed and deleted to render encrypted data unreadable. When a device interacts with a service provider and provides or generates user data, the user data may be stored in accordance with an encryption process that encrypts the data using an encryption key for a corresponding account. Thereafter, the encryption key may be stored by a key store and not replicated elsewhere. When data is needed, the key store may be used by a trusted decryption platform and not shared. As such, when data is required to be erased or deleted, the data may be removed from availability with the service provider by implementing a secure key deletion process.

The application discloses a data aggregation method, system and device based on a remainder system and a storage medium, which is a data aggregation scheme satisfying energy saving, reliability, non-plaintext transmission and tolerance to measurement error (one unlimited size and any small error). In the scheme, each source node only transmits compressed data, so that the energy of the sensor node can be saved, and the data erasure problem caused by failure or wireless network unreliability can be tolerated, so that the reliability is relatively high. Meanwhile, the compression of the source node to the sensing data is essentially a lightweight encryption. If the corresponding modulus is unknown, the sensing data cannot be obtained even if the compressed data is obtained, so the data transmission belongs to non-plaintext data transmission. In addition, one unlimited size measurement error can be tolerated, which is more in line with the actual needs.

A semiconductor device, a controller, and an operating method thereof are disclosed. In an embodiment, a controller includes an internal command generator configured to generate rewrite operation setting information to perform a rewrite operation on a data storage area corresponding to a data permanent erase request in response to the data permanent erase request, a rewrite data generator configured to generate a plurality of cell addresses corresponding to the data storage area based on the rewrite operation setting information, and generate a plurality of pieces of rewrite data to be respectively written to the data storage area corresponding to the plurality of cell addresses, and a storage area controller configured to control the data storage area to store the plurality of pieces of rewrite data corresponding to the plurality of cell addresses, respectively.

A measuring device, a control method, and a control program are provided to improve the user-friendliness of measuring biological data. A measuring device according to one aspect of the present invention includes a control unit (30) that performs measurements using a sensor that acquires biological data and a non-volatile memory (14a). Upon receiving a measurement instruction, the control unit (30) starts the measurement and the data erasure of the non-volatile memory (14a), and then, after the data erasure is complete, writes the biological data obtained during the measurement to the non-volatile memory (14a).

A semiconductor with 3D flash memory storing cells giving an extended life time includes a stack structure in each storing cell, a receiving space crossing through the stack structure, a blocking layer, at least one floating gate layer, and a channel layer. The stack structure includes at least one control gate layer, at least two dielectric layers, and at least one erasing layer. The receiving space comprises a first receiving portion communicating with several second receiving portions. The first receiving portion crosses through the stack structure and the second receiving portions are coplanar with the control gate layer. The blocking layer insulates the floating gate layer from the control gate layers. The erasing layer and floating gate layer form a passageway for electrons when data erasure is required in the semiconductor. A method for fabricating the semiconductor is also disclosed.

The present application provides a nonvolatile memory, a memory system, and a data erasing method of the memory, the method comprising: applying a first conduction voltage to a memory cell included in a first stack of a plurality of stacks to be erased; after applying the first conduction voltage, applying a source erasing voltage and a drain erasing voltage to a common source and a common drain, respectively; and applying a first voltage to a dummy memory cell included in a second stack of the plurality of stacks to be erased during a level ramp-up of the source erasing voltage and the drain erasing voltage to a peak level thereof.

This disclosure provides systems, methods, and devices for memory systems that support erasing data in a memory device using an update on a mapping table in a host device. In a first aspect, a method of erasing data in a flash memory system includes a host memory controller receiving a request to erase data on a memory device; and transmitting an update on a mapping table in the host device to the memory device, the update on the mapping table being associated with the data. Other aspects and features are also claimed and described.