Three-dimensional memory device and method for forming the same

Abstract

To provide a three-dimensional (3D) memory device and a method for forming the same.SOLUTION: In a specific embodiment, a 3D memory device includes: a stack structure including interleaved conductive layers and dielectric layers; a doped semiconductor layer; and a channel structure. The channel structure extends through the stack structure and contacts the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A portion of the gate dielectric portion faces, along the first direction, one of the conductive layers closest to the doped semiconductor layer.SELECTED DRAWING: Figure 1A

Description

Technical Field

[0001] The present disclosure relates to three-dimensional (3D) memory devices and methods of fabricating the same.

Background Art

[0002] Planar memory cells are scaled down to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication processes. However, when the feature size of the memory cells approaches the lower limit, planar processes and fabrication techniques become difficult and costly. As a result, the memory density for planar memory cells approaches the upper limit.

[0003] 3D memory architectures are capable of addressing the density limitations in planar memory cells. A 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array.

Summary of the Invention

Means for Solving the Problems

[0004] In one aspect, a 3D memory device includes a stack structure including interleaved conductive and dielectric layers, a doped semiconductor layer, and a channel structure that extends through the stack structure and is in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A portion of the gate dielectric portion faces one of the conductive layers closest to the doped semiconductor layer along the first direction.

[0005] In another aspect, a 3D memory device includes a stack structure including interleaved conductive and dielectric layers, and a channel structure extending through the stack structure. The conductive layers include one or more source select gate lines and a plurality of word lines. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A portion of the gate dielectric portion faces one or more source select gate lines along the first direction. The semiconductor channel includes a doped portion. A portion of the doped portion faces one or more source select gate lines along the first direction.

[0006] In yet another aspect, a system includes a 3D memory device configured to store data, and a controller circuit coupled to the 3D memory device. The 3D memory device includes a stack structure including interleaved conductive and dielectric layers, and a channel structure extending through the stack structure. The conductive layers include one or more source select gate lines and a plurality of word lines. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A portion of the gate dielectric portion faces one or more source select gate lines along the first direction. The semiconductor channel includes a doped portion. A portion of the doped portion faces one or more source select gate lines along the first direction. The controller circuit is configured to operate the composite dielectric film via the conductive layer.

[0007] In yet another aspect, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stack structure is formed over the fill layer. A channel structure is formed that extends through and beyond the stack structure and the fill layer. The channel structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a semiconductor channel. A portion of the channel structure that extends beyond the substrate and the fill layer is sequentially removed to expose a portion of the channel structure. A portion of the second dielectric layer of the channel structure is replaced with a fourth dielectric layer that includes a dielectric material different from the second dielectric layer.

[0008] The accompanying drawings are incorporated herein and form a part of the specification, and the accompanying drawings illustrate aspects of the present disclosure and, together with the description, serve to explain the principles of the present disclosure and also serve to enable one skilled in the art to make and use the present disclosure.

Brief Description of the Drawings

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DETAILED DESCRIPTION OF THE INVENTION

[0010] The present disclosure will be described with reference to the accompanying drawings.

[0011] Although specific configurations and arrangements are being discussed, it should be understood that this is being done for illustrative purposes only. As such, other configurations and arrangements may be used without departing from the scope of the present disclosure. Also, the present disclosure may be used in a variety of other applications. The functional and structural features as described in the present disclosure may be combined, adjusted, and modified in ways not specifically shown in relation to each other and in the drawings, and these combinations, adjustments, and modifications are intended to be within the scope of the present disclosure.

[0012] Generally, specialized terms can be understood at least in part from their usage in context. For example, as used herein, the term "one or more" can be used, at least in part depending on the context, to describe any feature, structure, or characteristic in the singular sense, or to describe a combination of features, structures, or characteristics in the plural sense. Similarly, terms such as "a", "an", or "the", although repeated, can be understood, at least in part depending on the context, to convey either the singular usage or the plural usage. Additionally, it can be understood that the term "based on" is not necessarily intended to convey an exclusive set of factors, and instead, although repeated, can, at least in part depending on the context, allow for the existence of additional factors not necessarily explicitly described.

[0013] As used in this disclosure, the meanings of "on", "above", and "over" should be construed in the broadest manner, where "on" not only means "directly on" something, but also includes meaning "on" something with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but can also include meaning that it is "above" or "over" (i.e., directly on) something with no intervening features or layers therebetween. This should be readily understood.

[0014] Furthermore, spatially relative terms such as "beneath", "below", "lower", "above", and "upper" may be used herein to describe a relationship of one element or feature to another element or feature as illustrated in the figures for the purpose of facilitating the description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. The device can be oriented in other ways (rotated 90 degrees or otherwise), and the spatially relative descriptors used herein can be interpreted accordingly.

[0015] As used herein, the term "substrate" refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on the substrate can be patterned or can remain unpatterned. Moreover, the substrate can include various semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from non-conductive materials such as glass, plastic, or sapphire wafers.

[0016] As used herein, the term "layer" refers to a portion of material that includes a region having a predetermined thickness. A layer can extend across the entirety of a structure below or above it, or can have an extent smaller than the extent of the structure below or above it. Further, a layer can be a region of a homogeneous or heterogeneous continuous structure having a thickness smaller than the thickness of the continuous structure. For example, a layer can be positioned between any pair of horizontal planes (or at the top and bottom surfaces) between the top and bottom surfaces of a continuous structure. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above, and / or below it. A layer can include a plurality of layers. For example, an interconnect layer can include one or more conductors and contact layers (interconnect lines and / or vertical interconnect access (via) contacts are formed therein) and one or more dielectric layers.

[0017] In some 3D NAND memory devices, a semiconductor layer is selectively grown to surround sidewall portions of a channel structure (e.g., known as sidewall-selective epitaxial growth (SEG)). Compared to another type of semiconductor layer that is epitaxial growth at the source end of the channel structure (e.g., bottom SEG), the formation of sidewall SEG avoids etching of the memory film and semiconductor channel at the bottom surface of the channel hole (known as SONO punch), thereby increasing the process window, especially when fabricating 3D NAND memory devices by advanced technologies (e.g., having 90 or more levels by a multi-deck architecture).

[0018] However, since an intrinsic (pure, undoped) semiconductor material (e.g., intrinsic polysilicon, etc.) is used to form the semiconductor channel, a relatively high potential barrier exists between the semiconductor channel and the sidewall portion SEG or the conductive layer in contact with the semiconductor channel, thereby introducing a high contact resistance therebetween. The electrical performance of the 3D memory device may be affected by the high contact resistance.

[0019] Moreover, the NAND memory string of the 3D NAND memory device includes a source select gate (SSG) transistor at the source end, which uses a portion of the memory film of the channel structure near the source end as a gate dielectric. However, since the memory film is typically a composite dielectric film having different dielectric materials (e.g., silicon nitride in the storage layer, etc.), the performance of the SSG transistor may be affected by the composite gate dielectric film.

[0020] To address the above problems, the present disclosure introduces a solution in which the contact resistance between the semiconductor channel and the sidewall portion SEG or the conductive layer can be reduced, and it is possible to improve the SSG transistor performance. In some implementations, the semiconductor channel is partially doped, and a part of the semiconductor channel forming the source contact is either left undoped or left with another part of the semiconductor channel forming a lowly doped memory cell while being highly doped to lower the potential barrier. In some implementations, one end of each channel structure is opened from the back side, exposing the doped part of each semiconductor channel, and the 3D memory device further includes a doped semiconductor layer that electrically connects the exposed doped part of the semiconductor channel to further reduce the contact resistance and sheet resistance. For example, the doped semiconductor layer includes a plug that extends the channel structure by replacing a part of the composite dielectric film and the capping layer of the channel structure, increasing the contact area, and further reducing the contact resistance. As a result, it is possible to improve the electrical performance of the 3D memory device.

[0021] Moreover, consistent with the scope of the present disclosure, a part of the composite dielectric film of the channel structure facing the SSG line can be a gate dielectric part having the same dielectric material (e.g., silicon oxide, etc.), thereby improving the performance of the corresponding SSG transistor. In some implementations, a part of the composite dielectric film having silicon nitride is exchanged with silicon oxide from the back side during the manufacturing process to form the gate dielectric part of the composite dielectric film.

[0022] FIG. 1A illustrates a side cross-sectional view of an exemplary 3D memory device 100 according to some aspects of the present disclosure. In some implementations, the 3D memory device 100 is a bonded chip that includes a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. According to some implementations, the first and second semiconductor structures 102 and 104 are joined at a bonding interface 106 therebetween. As shown in FIG. 1A, the first semiconductor structure 102 can include a substrate 101, which can include silicon (e.g., single-crystalline silicon, c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material.

[0023] The first semiconductor structure 102 of the 3D memory device 100 can include peripheral circuitry 108 on top of the substrate 101. It is noted that x and y axes are included in FIG. 1A to further illustrate the spatial relationship of the components within the 3D memory device 100 having the substrate 101. The substrate 101 includes two lateral surfaces (e.g., a top surface and a bottom surface) that extend laterally in the x direction (i.e., horizontally). As used herein, whether one component (e.g., a layer or a device) is “on,” “above,” or “below” another component (e.g., a layer or a device) of a semiconductor device is determined in the y direction (i.e., the vertical direction) with respect to the substrate of the semiconductor device (e.g., the substrate 101) when the substrate is positioned within the lowest plane of the semiconductor device (e.g., the 3D memory device 100) in the y direction. The same concept for explaining spatial relationships is applied throughout the present disclosure.

[0024] In some implementations, the peripheral circuit 108 is configured to control and sense the 3D memory device 100. The peripheral circuit 108 can be any suitable digital, analog, and / or mixed-signal control and sensing circuit used to facilitate the operation of the 3D memory device 100, including, but not limited to, page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive component of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit 108 can include transistors formed on the substrate 101, where all or part of the transistors are formed in the substrate 101 (e.g., below the upper surface of the substrate 101) and / or directly on the substrate 101. Isolation regions (e.g., shallow trench isolation (STI)) and doped regions (e.g., source and drain regions of transistors) can similarly be formed in the substrate 101. According to some implementations, the transistors are fast by advanced logic processes (e.g., technology nodes such as 90nm, 65nm, 45nm, 32nm, 28nm, 20nm, 16nm, 14nm, 10nm, 7nm, 5nm, 3nm, 2nm, etc.). It is understood that in some implementations, the peripheral circuit 108 can further include any other circuit compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLDs)) or memory circuits (e.g., static random access memory (SRAM) and dynamic RAM (DRAM)).

[0025] In some implementations, the first semiconductor structure 102 of the 3D memory device 100 further includes an interconnect layer (not shown) above the peripheral circuit 108 to transfer electrical signals to and from the peripheral circuit 108. The interconnect layer can include a plurality of interconnects (also referred to herein as contacts), including horizontal interconnect lines and vertical interconnect access (VIA) contacts. As used herein, the term interconnect can broadly include any suitable type of interconnect, such as middle-end-of-line (MEOL) interconnects and back-end-of-line (BEOL) interconnects. The interconnect layer can further include one or more interlayer dielectric (ILD) layers (also known as inter-metal dielectric (IMD) layers), and the interconnect lines and VIA contacts can be formed within the one or more interlayer dielectric (ILD) layers. That is, the interconnect layer can include interconnect lines and VIA contacts within a plurality of ILD layers. The interconnect lines and VIA contacts within the interconnect layer can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), silicide, or any combination thereof. The ILD layers within the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof.

[0026] As shown in FIG. 1A, the first semiconductor structure 102 of the 3D memory device 100 can further include a bonding layer 110 at the bonding interface 106 and above the interconnect layer and the peripheral circuits 108. The bonding layer 110 can include a plurality of bonding contacts 111 and a dielectric that electrically isolates the bonding contacts 111. The bonding contacts 111 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 110 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 111 and the surrounding dielectric in the bonding layer 110 can be used for hybrid bonding.

[0027] Similarly, as shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can also include a bonding layer 112 at the bonding interface 106 and above the bonding layer 110 of the first semiconductor structure 102. The bonding layer 112 can include a plurality of bonding contacts 113 and a dielectric that electrically isolates the bonding contacts 113. The bonding contacts 113 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The remaining area of the bonding layer 112 can be formed of a dielectric including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The bonding contacts 113 and the surrounding dielectric in the bonding layer 112 can be used for hybrid bonding. According to some implementations, the bonding contacts 113 are in contact with the bonding contacts 111 at the bonding interface 106.

[0028] As described in detail below, the second semiconductor structure 104 can be bonded on top of the first semiconductor structure 102 in a face-to-face manner at the bonding interface 106. In some implementations, the bonding interface 106 is disposed between the bonding layer 110 and the bonding layer 112 as a result of hybrid bonding (also known as "metal / dielectric hybrid bonding"), and hybrid bonding is a direct bonding technique (e.g., forming a bond between surfaces without using an intermediate layer (such as solder or adhesive)), and it is possible to simultaneously achieve metal-metal bonding and dielectric-dielectric bonding. In some implementations, the bonding interface 106 is the location where the bonding layers 112 and 110 meet and bond. In fact, the bonding interface 106 can be a layer having a specific thickness including the upper surface of the bonding layer 110 of the first semiconductor structure 102 and the bottom surface of the bonding layer 112 of the second semiconductor structure 104.

[0029] In some implementations, the second semiconductor structure 104 of the 3D memory device 100 further includes an interconnect layer (not shown) above the bonding layer 112 for transferring electrical signals. The interconnect layer can include a plurality of interconnects (such as MEOL interconnects and BEOL interconnects). The interconnect layer can further include one or more ILD layers, and interconnect lines and VIA contacts can be formed within the one or more ILD layers. The interconnect lines and VIA contacts in the interconnect layer can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. The ILD layers in the interconnect layer can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0030] In some implementations, the 3D memory device 100 is a NAND flash memory device, and the memory cells are provided in the form of an array of NAND memory strings within the NAND flash memory device. Each NAND memory string can include a respective channel structure 124. As shown in FIG. 1A, each channel structure 124 can extend vertically through a plurality of pairs each including a stacked conductive layer 116 and a stacked dielectric layer 118. The interleaved stacked conductive layers 116 and stacked dielectric layers 118 are part of the memory stack 114. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in the memory stack 114 determines the number of memory cells in the 3D memory device 100. In some implementations, the memory stack 114 can have a multi-deck architecture (not shown), which is understood to include a plurality of memory decks stacked on top of each other. The number of pairs of stacked conductive layers 116 and stacked dielectric layers 118 in each memory deck can be the same or different.

[0031] The memory stack 114 can include a plurality of interleaved stack conductive layers 116 and stack dielectric layers 118. The stack conductive layers 116 and stack dielectric layers 118 in the memory stack 114 can be vertically alternating. In other words, except for those at the top or bottom of the memory stack 114, each stack conductive layer 116 can be adjacent on both sides by two stack dielectric layers 118, and each stack dielectric layer 118 can be adjacent on both sides by two stack conductive layers 116. The stack conductive layer 116 can include a conductive material including, but not limited to, W, Co, Cu, Al, doped silicon, polysilicon, silicide, or any combination thereof. Each stack conductive layer 116 can include a gate electrode (gate line) surrounded by an adhesive layer and a gate dielectric layer. The gate electrode of the stack conductive layer 116 can extend horizontally as a word line and end in one or more staircase structures of the memory stack 114. The stack dielectric layer 118 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0032] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can also include a fill layer 120 above the memory stack 114. The fill layer 120 can include polysilicon, a high-k (high dielectric constant) dielectric, or a metal. For example, a high-k dielectric can include any dielectric material having a dielectric constant higher than that of silicon oxide (e.g., k>3.7). Different from some known solutions where the fill layer 120 acts as sidewall portions SEG surrounding the channel structure 124 and / or a conductive layer (e.g., a doped polysilicon layer, etc.) electrically connecting the channel structure 124, the fill layer 120 of the second semiconductor structure 104 of the 3D memory device 100 may not act as sidewall portions SEG and / or a conductive layer, and thus can include materials other than doped polysilicon, such as a dielectric (e.g., a high-k dielectric), a metal (e.g., W, Co, Cu, or Al), a metal silicide, or undoped polysilicon. It is understood that in some examples, the fill layer 120 can also include doped polysilicon.

[0033] In some implementations, each channel structure 124 includes a channel hole filled with a semiconductor channel 128 and a composite dielectric film 126. As shown in FIG. 1A, the remaining space in the channel hole can be partially filled by a capping layer 127 that includes a dielectric material (e.g., silicon oxide, etc.) and / or an air gap (not shown). The channel structure 124 can have a cylindrical shape (e.g., pillar shape). According to some implementations, the capping layer 127, the semiconductor channel 128, and the composite dielectric film 126 are arranged in this order radially from the center towards the outer surface of the pillar. The composite dielectric film 126 radially surrounds the semiconductor channel 128 along the lateral direction (e.g., the x direction in FIG. 1A). The composite dielectric film 126 can be formed laterally between the semiconductor channel 128 and the stack conductive layer 116 and the stack dielectric layer 118. Each channel structure 124 can extend vertically through the interleaved stack conductive layer 116 and stack dielectric layer 118 of the memory stack 114 and is in contact with the filling layer 120. That is, the channel structure 124 can extend through the memory stack 114 in the positive y direction. According to some implementations, the upper end of the composite dielectric film 126 is in the same plane as the interface between the filling layer 120 and the memory stack 114 (i.e., between the bottom surface of the filling layer 120 and the upper surface of the memory stack 114).

[0034] In some implementations, the semiconductor channel 128 includes silicon (e.g., amorphous silicon, polysilicon, or single-crystalline silicon, etc.). Also, referring to the enlarged side view of the channel structure 124 in FIG. 2A, the semiconductor channel 128 can include a doped portion 128a and an undoped portion 128b. As described below with respect to the manufacturing process, from the perspective of the manufacturing process, in some implementations, a part of the doped portion 128a of the semiconductor channel 128 extends beyond the memory stack 114 in a first direction (e.g., the positive y direction in FIG. 2A). That is, the upper end of the doped portion 128a can be above the interface between the filling layer 120 and the memory stack 114 (i.e., between the bottom surface of the filling layer 120 and the upper surface of the memory stack 114). As described below with respect to the plug 123 of the doped semiconductor layer 122, a part of the doped portion 128a that extends beyond the memory stack 114 can extend into the plug 123. That is, an extended part of the doped portion 128a can be embedded into the plug 123 and radially surrounded by the plug 123, as shown in the top view of the cross-section passing through the plug 123 in FIG. 2A. In some implementations, the plug 123 can have the same material with the same type of dopant and doping profile as an extended part of the doped portion 128a. As a result, the interface and boundary between an extended part of the doped portion 128a of the semiconductor channel 128 and the plug 123 of the doped semiconductor layer 122 can be indistinguishable, and thus it is understood that it cannot be discriminated within the 3D memory device 100. In other words, from the perspective of the structure, an extended part of the doped portion 128a into the plug 123 can also be considered not to be part of the semiconductor channel 128, and the doped portion 128a of the semiconductor channel 128 may not extend vertically beyond the memory stack 114.Instead, the upper ends of the semiconductor channel 128 and the composite dielectric film 126 can be coplanar with the interface between the fill layer 120 and the memory stack 114 (i.e., between the bottom surface of the fill layer 120 and the upper surface of the memory stack 114). That is, the upper end of the channel structure 124 can be in contact with the plug 123 of the doped semiconductor channel at the interface between the fill layer 120 and the memory stack 114.

[0035] In some implementations, the doped portion 128a of the semiconductor channel 128 extends beyond one of the stack conductive layers 116 in a second direction opposite to the first direction (e.g., the negative y direction in FIG. 2A). One or more of the stack conductive layers 116 near the fill layer 120 can be a source select gate line 201 (SSG line; sometimes referred to as a bottom select gate (BSG) line), and the remaining portions of the stack conductive layers 116 can include word lines 203. Also, according to some implementations, the doped portion 128a of the semiconductor channel 128 extends beyond the source select gate line 201 closest to the fill layer 120. When the second semiconductor structure 104 of the 3D memory device 100 includes two or more source select gate lines 201, it is understood that the doped portion 128a can extend beyond all of the source select gate lines 201. On the other hand, the doped portion 128a may not further extend along a second direction (e.g., the x direction in FIG. 2A) perpendicular to the first direction so as to face the word line 203. That is, the lower end of the doped portion 128a is, according to some implementations, between the source select gate line 201 and the word line 203 in the vertical direction.

[0036] In some embodiments, the doped portion 128a of the semiconductor channel 128 comprises N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., phosphorus (P), arsenic (Ar), or antimony (Sb), etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. In some embodiments, the doping concentration of the doped portion 128a is about 10 19 cm -3 to about 10 21 cm -3 , for example, between 10 19 cm -3 and 10 21 cm -3 (e.g., 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×10 20 cm -3 , 4×10 20 cm -3 , 5×10 20 cm -3 , 6×10 20 cm -3 , 7×10 20 cm -3 , 8×10 20 cm -3 , 9×10 20 cm -3 , 10 21 cm -3in any range bounded by a lower end by any of these values, or in any range defined by any two of these values). The doping concentration of the doped portion 128a disclosed herein can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor layer 122 as compared to the intrinsic semiconductor. In some examples, the diffusion of the dopant can be confined within the doped portion 128a of the semiconductor channel 128, and the remaining portion of the semiconductor channel 128 (i.e., the part facing the word line 203) is an undoped portion 128b that still contains an intrinsic semiconductor (e.g., intrinsic polysilicon, etc.) (i.e., the doping concentration is nominally zero). It is understood that the doping concentration profile described above can reduce the potential barrier, contact resistance, and sheet resistance in the doped portion 128a of the semiconductor channel 128, which creates an electrical connection for the source of the corresponding NAND memory string without changing the intrinsic properties of the undoped portion 128b of the semiconductor channel 128 that forms the memory cell of the NAND memory string.

[0037] As shown in FIG. 2A, in some implementations, the composite dielectric film 126 includes a gate dielectric portion 126a and a memory portion 126b along a vertical direction (e.g., the y-direction in FIG. 2A). The gate dielectric portion 126a and the memory portion 126b can be in contact with each other in the vertical direction. Similar to the doped portion 128a of the semiconductor channel 128, the gate dielectric portion 126a of the composite dielectric film 126 can extend beyond one of the stack conductive layers 116 in the vertical direction (e.g., the minus y-direction in FIG. 2A). That is, in some implementations, the gate dielectric portion 126a of the composite dielectric film 126 also extends beyond the source select gate line 201 closest to the fill layer 120. When the second semiconductor structure 104 of the 3D memory device 100 includes two or more source select gate lines 201, it is understood that the gate dielectric portion 126a can extend beyond all the source select gate lines 201. In other words, a part of the gate dielectric portion 126a of the composite dielectric film 126 faces at least one (e.g., one or more source select gate lines 201) of the stack conductive layers 116 closest to the doped semiconductor layer 122 along a lateral direction (e.g., the x-direction in FIG. 2A). Similar to the undoped portion 128b of the semiconductor channel 128, the memory portion 126b of the composite dielectric film 126 can face the word line 203 along a lateral direction (e.g., the x-direction in FIG. 2A).

[0038] As shown in the bottom plan view of the cross section passing through the memory portion 126b of the composite dielectric film 126 in FIG. 2A, the memory portion 126b can include a tunneling layer 214, a storage layer 213 (also known as a "charge trap layer"), and a blocking layer 211 that are stacked along the lateral direction (e.g., the x direction in FIG. 2A). The capping layer 127, the semiconductor channel 128 (e.g., the undoped portion 128b), the tunneling layer 214, the storage layer 213, and the blocking layer 211 of the memory portion 126b are arranged in this order radially from the center toward the outer surface of the pillar in some implementation forms. The tunneling layer 214 can include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer 213 can include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 211 can include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory portion 126b of the composite dielectric film 126 can include a composite layer of silicon oxide / silicon nitride / silicon oxide (ONO). In other words, the tunneling layer 214, the storage layer 213, and the blocking layer 211 can each include silicon oxide, silicon nitride, and silicon oxide, respectively.

[0039] As shown in a plan view of an intermediate cross-section through the gate dielectric portion 126a of the composite dielectric film 126 of FIG. 2A, the gate dielectric portion 126a can include a first gate dielectric layer 205, a second gate dielectric layer 207, and a third gate dielectric layer 209 that are stacked along a lateral direction (e.g., the x direction in FIG. 2A). The capping layer 127, the semiconductor channel 128 (e.g., the doped portion 128a), the third gate dielectric layer 209, the second gate dielectric layer 207, and the first gate dielectric layer 205 of the gate dielectric portion 126a are arranged in this order radially from the center toward the outer surface of the pillar in some implementation forms. In some implementation forms, the first, second, and third gate dielectric layers 205, 207, and 209 include the same dielectric material (e.g., silicon oxide, etc.). In this case, it is possible that the interfaces and boundaries between the first, second, and third gate dielectric layers 205, 207, and 209 become indistinguishable, and thus it is understood that they cannot be discriminated within the 3D memory device 100. In other words, the gate dielectric portion 126a of the composite dielectric film 126 can be considered to have a single dielectric layer having the same dielectric material (e.g., silicon oxide, etc.).

[0040] The first gate dielectric layer 205 can be in contact with the blocking layer 211 in the vertical direction, the second gate dielectric layer 207 can be in contact with the storage layer 213 in the vertical direction, and the third gate dielectric layer 209 can be in contact with the tunneling layer 214 in the vertical direction. In some implementations, the first gate dielectric layer 205 and the blocking layer 211 include the same dielectric material (e.g., silicon oxide, etc.). In some implementations, the third gate dielectric layer 209 and the tunneling layer 214 include the same dielectric material (e.g., silicon oxide, etc.). For example, each of the blocking layer 211, the tunneling layer 214, and the first and third gate dielectric layers 205 and 209 can include silicon oxide. In this case, the interfaces and boundaries between the first gate dielectric layer 205 and the blocking layer 211, and between the third gate dielectric layer 209 and the tunneling layer 214 can become indistinguishable, and thus it is understood that they cannot be discriminated within the 3D memory device 100. Conversely, in some implementations, the second gate dielectric layer 207 and the storage layer 213 have different dielectric materials. For example, the storage layer 213 can include silicon nitride, while the second gate dielectric layer 207 can include a dielectric material other than silicon nitride. In one example, the second gate dielectric layer 207 can include silicon oxide.

[0041] By facing the source select gate line 201, the gate dielectric portion 126a of the composite dielectric film 126 can act as the gate dielectric of the SSG transistor of the NAND memory string corresponding to the channel structure 124. Compared with the memory portion 126b (which includes the storage layer 213 having silicon nitride), the gate dielectric portion 126a has a more uniform dielectric material without silicon nitride (e.g., only silicon oxide), and it is possible to improve the performance of the SSG transistor. On the other hand, the memory portion 126b of the composite dielectric film 126 facing the word line 203 can maintain its function as the memory film (including the storage layer 213 having silicon nitride) of the memory cell of the NAND memory string corresponding to the channel structure 124. As described below with respect to the manufacturing process, three dielectric layers stacked along the horizontal direction can be formed first, and then the silicon nitride of the intermediate dielectric layer can be partially exchanged with silicon oxide to form the composite dielectric film 126 disclosed herein.

[0042] Consistent with the scope of the present disclosure, the gate dielectric portion 126a of the composite dielectric film 126 can include one or more air gaps (i.e., not completely filled with a dielectric material), as shown in FIG. 2B. In some implementations, the entire second dielectric layer 207 of the gate dielectric portion 126a is replaced with an air gap, as shown in FIG. 2B. In some examples, it is understood that only a portion of the second dielectric layer 207 of the gate dielectric portion 126a can be replaced with one or more air gaps. That is, the second dielectric layer 207 of the gate dielectric portion 126a can include air gaps within a dielectric material (e.g., silicon oxide, etc.). Although not shown, in some examples, it is further understood that the first dielectric layer 205 and / or the third dielectric layer 209 can be partially or completely filled with air gaps, similar to the second dielectric layer 207 of FIG. 2B. As a result, in some implementations, the gate dielectric portion 126a and the memory portion 126b of the composite dielectric film 126 may not be in complete vertical contact with each other; rather, there may be some space (e.g., an air gap) between them. In some implementations, the air gaps in the gate dielectric portion 126a of the composite dielectric film 126 are voids formed as a result of manufacturing variations or defects. In some implementations, the air gaps in the gate dielectric portion 126a of the composite dielectric film 126 are formed to avoid breakdown of the gate dielectric portion 126a due to, for example, the gate-induced drain leakage (GIDL) effect in an erase operation, due to the high voltage applied to the gate dielectric of the corresponding SSG transistor.

[0043] In some implementations, the channel structure 124 further includes a channel plug 129 at the bottom portion of the channel structure 124 (e.g., at the lower end). As used herein, when the substrate 101 is positioned at the lowest plane of the 3D memory device 100, the upper end of a component (e.g., the channel structure 124) is the end farther from the substrate 101 in the y direction, and the lower end of the component (e.g., the channel structure 124) is the end closer to the substrate 101 in the y direction. The channel plug 129 can include a semiconductor material (e.g., polysilicon). In some implementations, the channel plug 129 functions as the drain of the channel structure 124.

[0044] As shown in FIG. 1A, in some implementations, the second semiconductor structure 104 of the 3D memory device 100 includes a doped semiconductor layer 122. Each channel structure 124 can extend vertically through the memory stack 114 and can be in contact with the doped semiconductor layer 122. In some implementations, at least a portion of the doped portion 128a of each semiconductor channel 128 extends vertically beyond the memory stack 114, is in contact with the doped semiconductor layer 122, and the doped semiconductor layer 122 can electrically connect a plurality of channel structures 124 through those doped portions 128a of the semiconductor channels 128. For example, the doped semiconductor layer 122 can provide an electrical connection between the sources of the array of NAND memory strings (i.e., the array common source (ACS)) in the same block, regardless of the presence or absence of the fill layer 120 (depending on whether the fill layer 120 is conductive). In other words, the fill layer 120 may not need to include a conductive material (such as metal or doped polysilicon, etc.). The reason is that the doped semiconductor layer 122 alone can electrically connect the sources of a plurality of NAND memory strings. As a result, the material and dimensional constraints on the fill layer 120 can be relaxed.

[0045] As shown in FIG. 1A, in some implementations, the doped semiconductor layer 122 includes two parts: a plate 121 in contact with the filling layer 120, and plugs 123 that extend from the plate 121 into the filling layer 120 and are in contact with the semiconductor channels 128 of the channel structures 124. According to some implementations, the plate 121 of the doped semiconductor layer 122 is above the filling layer 120 and in contact with the filling layer 120. By extending horizontally above the plurality of channel structures 124, the plate 121 can connect the plurality of plugs 123, and each of the plurality of plugs 123 is in contact with a respective channel structure 124. Also, referring to FIG. 2A, the doped portion 128a of the semiconductor channel 128 extends into the plug 123 of the doped semiconductor layer 122 according to some implementations. As will be described in detail below regarding the fabrication of the 3D memory device 100, a part of the channel structure 124 can be removed to form a recess in the filling layer 120 in which the plug 123 can be formed. Also, the plug 123 of the doped semiconductor layer 122 can be in contact with the gate dielectric portion 126a and the capping layer 127 of the composite dielectric film 126 in the vertical direction. As shown in FIG. 2A, in some implementations, the plug 123 protrudes into the filling layer 120 such that the lower end of the plug 123 is in the same plane as the interface between the filling layer 120 and the memory stack 114. That is, according to some implementations, the composite dielectric film 126 and the capping layer 127 do not extend beyond the memory stack 114 due to the extension of the plug 123.

[0046] As described in detail below, the formation of the memory stack 114, as well as the formation of the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122, can occur on the opposite side of the fill layer 120, thereby avoiding any deposition or etching processes through the openings extending through the memory stack 114, thereby reducing fabrication complexity and cost and improving yield and vertical scalability.

[0047] Similar to the doped portion 128a of the semiconductor channel 128, in some implementations, the doped semiconductor layer 122 (including the plate 121 and the plug 123) also includes N-type doped polysilicon. The dopant can be any suitable N-type dopant (e.g., P, Ar, or Sb, etc.), which contributes free electrons and increases the conductivity of the intrinsic semiconductor. Similar to the doped portion 128a of the semiconductor channel 128, in some implementations, the doping concentration of the doped semiconductor layer 122 is from about 10 19 cm -3 to about 10 21 cm -3 , for example, from 10 19 cm -3 to 10 21 cm -3 (e.g., 10 19 cm -3 , 2×10 19 cm -3 , 3×10 19 cm -3 , 4×10 19 cm -3 , 5×10 19 cm -3 , 6×10 19 cm -3 , 7×10 19 cm -3 , 8×10 19 cm -3 , 9×10 19 cm -3 , 10 20 cm -3 , 2×10 20 cm -3 , 3×1020 cm -3 、 4×10 20 cm -3 、 5×10 20 cm -3 、 6×10 20 cm -3 、 7×10 20 cm -3 、 8×10 20 cm -3 、 9×10 20 cm -3 、 10 21 cm -3 、 any range defined by the lower end by any of these values, or any range defined by any two of these values), etc. The doping concentration of the doped semiconductor layer 122 disclosed in this specification can significantly reduce the contact resistance between the semiconductor channel 128 and the doped semiconductor channel 122 and the sheet resistance of the doped semiconductor layer 122 as compared with the intrinsic semiconductor. As described in detail below, in some implementations, the doped portion 128a of the semiconductor channel 128 and the doped semiconductor layer 122 have the same material with the same dopant (for example, N-type doped polysilicon), and also have a continuous doping profile due to the same local activation process implemented thereon. Therefore, the interface and boundary between the doped portion 128a of the semiconductor channel 128 and the plug 123 of the doped semiconductor layer 122 may become indistinguishable, and thus it is understood that it cannot be discriminated within the 3D memory device 100.

[0048] By doping and contacting the semiconductor channel 128 and the doped semiconductor layer 122, it is possible to reduce the contact resistance between NAND memory strings (i.e., in the ACS of NAND memory strings in the same block), thereby improving the electrical performance of the 3D memory device 100. As shown in FIGS. 1A and 2, by extending the plug 123 into the filling layer 120, the doped portion 128a of the semiconductor channel 128 can be embedded into the plug 123 of the doped semiconductor layer 122, thereby increasing the contact area between the semiconductor channel 128 and the doped semiconductor layer 122, which further reduces the contact resistance between them. The N-type doped semiconductor layer 122 can enable gate-induced drain leakage (GIDL)-assisted body biasing for the erase operation of the 3D memory device 100. GIDL around the source select gate line 201 can generate a hole current (i.e., source leakage current) from the source of the corresponding NAND memory string into the semiconductor channel 128 and raise the body potential for the erase operation. That is, the N-type doped semiconductor layer 122 is configured to generate GIDL-assisted body biasing when performing the erase operation according to some implementation forms. In some implementation forms, the GIDL effect can also be further enhanced by doping a part of the semiconductor channel 128 facing the source select gate line 201 and by replacing silicon nitride with silicon oxide in the portion of the composite dielectric film 126 facing the source select gate line 201.

[0049] As shown in FIG. 1A, the second semiconductor structure 104 of the 3D memory device 100 can further include an insulating structure 130 that extends vertically through the interleaved stack conductive layers 116 and stack dielectric layers 118 of the memory stack 114, respectively. According to some implementations, the insulating structure 130 terminates at the bottom surface of the fill layer 120, i.e., does not extend vertically into the fill layer 120. That is, the upper surface of the insulating structure 130 can be coplanar with the bottom surface of the fill layer 120. Also, each insulating structure 130 can extend laterally to separate distinct channel structures 124 into a plurality of blocks. That is, the memory stack 114 can be divided into a plurality of memory blocks by the insulating structures 130 such that an array of channel structures 124 can be separated into respective memory blocks. Unlike slit structures in existing 3D NAND memory devices (which include front-side ACS contacts), the insulating structure 130 does not include any contacts therein (i.e., does not function as a source contact) according to some implementations, and thus does not introduce parasitic capacitance and leakage current by the stack conductive layer 116. In some implementations, each insulating structure 130 includes one or more openings (e.g., slits) filled with one or more dielectric materials including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In one example, each insulating structure 130 can be filled with silicon oxide. In some examples (as shown in FIG. 1A), it is understood that the insulating structure 130 can be partially filled with a non-dielectric material (e.g., polysilicon, etc.) to adjust the mechanical properties (e.g., hardness and / or stress) of the insulating structure 130.

[0050] Moreover, as described in detail below, the openings for forming the insulating structure 130 are not used to form the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128, so increasing the number of interleaved stack conductive layers 116 and stack dielectric layers 118 will increase the aspect ratio of the openings (e.g., greater than 50), which will not affect the formation of the doped semiconductor layer 122 and the doped portions 128a of the semiconductor channel 128.

[0051] Instead of the front-side source contact, the 3D memory device 100 can include one or more back-side source contacts 132 in contact with the doped semiconductor layer 122 above the doped semiconductor layer 122, as shown in FIG. 1A. The source contact 132 and the memory stack 114 (and the insulating structure 130 therethrough) can be disposed on the opposite side of the fill layer 120 and can thus be seen as "back-side" source contacts. In some implementations, the source contact 132 is electrically connected to the semiconductor channel 128 of the channel structure 124 through the doped semiconductor layer 122. The source contact 132 can include any suitable type of contact. In some implementations, the source contact 132 includes a VIA contact. In some implementations, the source contact 132 includes a laterally extending wall-shaped contact. The source contact 132 can include one or more conductive layers such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., titanium nitride (TiN)).

[0052] As shown in FIG. 1A, 3D memory device 100 can further include a BEOL interconnect layer 133 that is electrically connected to source contact 132 above source contact 132 for pad out (e.g., to transfer electrical signals between 3D memory device 100 and an external circuit). In some implementations, interconnect layer 133 includes one or more ILD layers 134 on doped semiconductor layer 122 and a redistribution layer 136 on ILD layer 134. The upper end of source contact 132 is coplanar with the upper surface of ILD layer 134 and the bottom surface of redistribution layer 136, and source contact 132 extends vertically through ILD layer 134 to contact doped semiconductor layer 122 in some implementations. The ILD layer 134 in interconnect layer 133 can include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, a low-k dielectric, or any combination thereof. The redistribution layer 136 in interconnect layer 133 can include a conductive material including, but not limited to, W, Co, Cu, Al, silicide, or any combination thereof. In some implementations, interconnect layer 133 further includes a passivation layer 138 as an outermost layer for passivation and protection of 3D memory device 100. A portion of redistribution layer 136 can be exposed from passivation layer 138 as contact pad 140. That is, the interconnect layer 133 of 3D memory device 100 can also include contact pads 140 for wire bonding and / or bonding to an interposer. As described below with respect to the fabrication process, in some implementations, source contact 132 and redistribution layer 136 can be formed by the same process and can have the same material (e.g., Al). Thus, source contact 132 can, in some examples, also be viewed as part of BEOL interconnect layer 133.

[0053] In some embodiments, the second semiconductor structure 104 of the 3D memory device 100 further includes contacts 142 and 144 that pass through the doped semiconductor layer 122 and the fill layer 120. Since the doped semiconductor layer 122 can include polysilicon, the contacts 142 and 144 are, according to some embodiments, through silicon contacts (TSCs). In some embodiments, the contact 142 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the redistribution layer 136 such that the doped semiconductor layer 122 is electrically connected to the contact 142 through the source contact 132 of the interconnect layer 133 and the redistribution layer 136. In some embodiments, the contact 144 extends through the doped semiconductor layer 122, the fill layer 120, and the ILD layer 134 and contacts the contact pad 140. The contacts 142 and 144 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer, surrounded by an adhesive layer (e.g., tin). In some embodiments, at least the contact 144 further includes a spacer (e.g., a dielectric layer) for electrically isolating the contact 144 from the doped semiconductor layer 122 and the fill layer 120.

[0054] In some implementations, the 3D memory device 100 further includes peripheral contacts 146 and 148 that extend vertically outside the memory stack 114. Each peripheral contact 146 or 148 has a depth greater than the depth of the memory stack 114 and can extend vertically from the bonding layer 112 to the fill layer 120 in the peripheral region outside the memory stack 114. In some implementations, the peripheral contact 146 is below and in contact with the contact 142, and the doped semiconductor layer 122 is electrically connected to the peripheral circuit 108 in the first semiconductor structure 102 through at least the source contact 132, the redistribution layer 136, the contact 142, and the peripheral contact 146. In some implementations, the peripheral contact 148 is below and in contact with the contact 144, and the peripheral circuit 108 in the first semiconductor structure 102 is electrically connected to the contact pad 140 for pad out through at least the contact 144 and the peripheral contact 148. The peripheral contacts 146 and 148 can each include one or more conductive layers, such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., tin).

[0055] As shown in FIG. 1A, the 3D memory device 100 also includes various local contacts (also known as "C1") as part of the interconnect structure, which are in direct contact with the structures within the memory stack 114. In some implementations, the local contacts include channel local contacts 150, each of which is below and in contact with the lower end of a respective channel structure 124. Each channel local contact 150 can be electrically connected to a bit line contact (not shown) for bit line fanout. In some implementations, the local contacts further include word line local contacts 152, each of which is below and in contact with a respective stack conductive layer 116 (including the word line) in the staircase structure of the memory stack 114 for word line fanout. The local contacts (e.g., channel local contacts 150 and word line local contacts 152, etc.) can be electrically connected to the peripheral circuit 108 of the first semiconductor structure 102 through at least the bonding layers 112 and 110. The local contacts (e.g., channel local contacts 150 and word line local contacts 152, etc.) can each include one or more conductive layers such as a metal layer (e.g., W, Co, Cu, or Al) or a silicide layer surrounded by an adhesive layer (e.g., tin).

[0056] Although an exemplary 3D memory device 100 is shown in FIG. 1A, it is understood that any other suitable architecture of a 3D memory device can be applicable in the present disclosure without further detailed description by varying the relative positions of the first and second semiconductor structures 102 and 104, the use of backside source contacts 132 or known frontside source contacts (not shown), and / or the padout locations (e.g., through the first semiconductor structure 102 and / or the second semiconductor structure 104).

[0057] FIG. 1B illustrates a side cross-sectional view of another exemplary 3D memory device 160 according to some implementations of the present disclosure. The 3D memory device 160 is similar to the 3D memory device 100, except for the doped semiconductor layer 122 and the different structures at the upper ends of the composite dielectric film 126 and the capping layer 127. It is understood that the details of the other same structures of both the 3D memory devices 160 and 100 are not repeated for the sake of simplicity of explanation.

[0058] As shown in FIG. 1B, according to some implementations, the doped semiconductor layer 122 does not include any plugs (e.g., plug 123 in FIG. 1A) that extend into the fill layer 120. That is, in some implementations, the entire doped semiconductor layer 122 can be viewed as the plate 121. Without the plug 123 extending into the fill layer 120, the channel structure 124 (including the composite dielectric film 126 and the capping layer 127) can extend vertically (e.g., the positive y direction in FIG. 1B) beyond the memory stack 114 and be in contact with the doped semiconductor layer 122. That is, the upper ends of the composite dielectric film 126, the semiconductor channel 128, and the capping layer 127 can be coplanar with each other and be in contact with the doped semiconductor layer 122.

[0059] FIG. 7 illustrates a block diagram of an exemplary system 700 having a 3D memory device, according to some aspects of the present disclosure. System 700 can be a mobile phone, a desktop computer, a laptop computer, a tablet, a vehicle computer, a gaming console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having storage therein. As shown in FIG. 7, system 700 can include a host 708 and a memory system 702, and memory system 702 has one or more 3D memory devices 704 and a memory controller 706. Host 708 can be a processor (e.g., a central processing unit (CPU), etc.) of the electronic device, or a system-on-chip (SoC) (e.g., an application processor (AP), etc.). Host 708 can be configured to transmit data to 3D memory device 704 or to receive data from 3D memory device 704.

[0060] The 3D memory device 704 can be any 3D memory device disclosed herein (e.g., the 3D memory devices 100 and 160 shown in FIGS. 1A and 1B). In some implementations, each 3D memory device 704 includes NAND flash memory. Consistent with the scope of the present disclosure, the semiconductor channel of the 3D memory device 704 can be partially doped, with a portion of the semiconductor channel forming the source contact remaining undoped or leaving another portion of the semiconductor channel forming a lightly doped memory cell highly doped to reduce the potential barrier. One end of each channel structure of the 3D memory device 704 can be opened from the backside to expose the doped portion of each semiconductor channel. The 3D memory device 704 can further include a doped semiconductor layer that electrically connects the exposed doped portion of the semiconductor channel to further reduce contact resistance and sheet resistance. Moreover, the 3D memory device 704 can include a composite dielectric film having a gate dielectric portion facing the source select gate line. The gate dielectric portion can be free of silicon nitride (e.g., include only silicon oxide) and can act as the gate dielectric of an SSG transistor. As a result, the electrical performance of the 3D memory device 704 can be improved, and it improves the performance of the memory system 702 and the system 700, for example, achieving a higher operating speed.

[0061] A memory controller 706 (known as a controller circuit) is coupled to a 3D memory device 704 and a host 708, and in some implementations, is configured to control the 3D memory device 704. For example, the controller circuit can be configured to operate a composite dielectric film 126 via a stack conductive layer 116 (e.g., a source select gate line 201). The memory controller 706 can manage data stored in the 3D memory device 704 and communicate with the host 708. In some implementations, the memory controller 706 is designed to operate in a low duty cycle environment, such as in a Secure Digital (SD) card, a Compact Flash (CF) (registered trademark) card, a Universal Serial Bus (USB) flash drive, or other media for use in an electronic device (e.g., a personal computer, a digital camera, a mobile phone, etc.). In some implementations, the memory controller 706 is designed to operate in a high duty cycle environment SSD or an embedded multimedia card (eMMC) used as data storage for a mobile device (e.g., a smartphone, a tablet, a laptop computer, etc.) or an enterprise storage array. The memory controller 706 can be configured to control the operation of the 3D memory device 704 (e.g., read operation, erase operation, and program operation, etc.). Also, the memory controller 706 can be configured to manage various functions related to data stored or to be stored in the 3D memory device 704 (including, but not limited to, bad block management, garbage collection, logical address-to-physical address translation, wear leveling, etc.). In some implementations, the memory controller 706 is further configured to process an error correction code (ECC) with respect to data read from or written to the 3D memory device 704.Any other suitable functions can be similarly implemented by the memory controller 706, for example, forming a 3D memory device 704. The memory controller 706 can communicate with an external device (e.g., host 708) according to a specific communication protocol. For example, the memory controller 706 can communicate with an external device through at least one of various interface protocols (e.g., USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol, etc.).

[0062] Memory controllers 706 and one or more 3D memory devices 704 can be integrated into various types of storage devices, for example, they can be included in the same package (such as a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 702 can be implemented and packaged into different types of end - electronics products. In one example as shown in FIG. 8A, the memory controller 706 and a single 3D memory device 704 can be integrated into a memory card 802. The memory card 802 can include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a Memory Stick, a Multimedia Card (MMC, RS - MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 802 can further include a memory card connector 804 that electrically connects the memory card 802 to a host (such as the host 708 in FIG. 7). In another example as shown in FIG. 8B, the memory controller 706 and multiple 3D memory devices 704 can be integrated into an SSD 806. The SSD 806 can further include an SSD connector 808 that electrically connects the SSD 806 to a host (such as the host 708 in FIG. 7). In some implementations, the storage capacity and / or operating speed of the SSD 806 are greater than those of the memory card 802.

[0063] Figures 3A - 3Q illustrate a fabrication process for forming an exemplary 3D memory device according to some implementations of the present disclosure. FIG. 5 illustrates a flowchart of a method 500 for forming an exemplary 3D memory device according to some implementations of the present disclosure. Examples of the 3D memory devices depicted in FIGS. 3A - 3Q and FIG. 5 include the 3D memory device 100 depicted in FIG. 1A. FIGS. 3A - 3Q and FIG. 5 will be described together. It is understood that the operations shown in method 500 are not exhaustive and that other operations may be similarly performed before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously or in an order different from that shown in FIG. 5.

[0064] Referring to FIG. 5, method 500 begins at operation 502, where peripheral circuitry is formed on a first substrate. The first substrate can be a silicon substrate. As illustrated in FIG. 3G, a plurality of transistors are formed on silicon substrate 350 using a plurality of processes including, but not limited to, photolithography, etching, thin - film deposition, thermal expansion, implantation, chemical - mechanical polishing (CMP), and any other suitable processes. In some implementations, doped regions (not shown) are formed into silicon substrate 350 by ion implantation and / or thermal diffusion, which function, for example, as source and / or drain regions of the transistors. In some implementations, isolation regions (e.g., STI) are also formed into silicon substrate 350 by wet etching and / or dry etching and thin - film deposition. The transistors can form peripheral circuitry 352 on silicon substrate 350.

[0065] As shown in FIG. 3G, a bonding layer 348 is formed over the peripheral circuit 352. The bonding layer 348 includes bonding contacts that are electrically connected to the peripheral circuit 352. To form the bonding layer 348, an ILD layer is deposited using one or more thin film deposition processes, such as, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof; the bonding contacts through the ILD layer are formed using wet etching and / or dry etching (e.g., reactive ion etching (RIE)), followed by one or more thin film deposition processes such as ALD, CVD, PVD, any other suitable process, or any combination thereof.

[0066] As shown in FIG. 5, method 500 proceeds to operation 504, where a fill layer is formed over a second substrate and a stack structure is formed over the fill layer. The fill layer and the stack structure can be formed on the front side of the second substrate on which a semiconductor device can be formed. The second substrate can be a silicon substrate. Since the second substrate will be removed from the final product, the second substrate can be any suitable material (e.g., a portion of a dummy wafer made from glass, sapphire, plastic, silicon, etc., such as a carrier substrate) to reduce the cost of the second substrate. In some implementations, the substrate is a carrier substrate. In some implementations, the fill layer includes polysilicon, a high-k dielectric, or metal, and the stack structure includes a dielectric stack having interleaved stack dielectric layers and stack sacrificial layers. In some examples, it is understood that the stack structure can include a memory stack having interleaved stack dielectric layers (e.g., silicon oxide layers) and stack conductive layers (e.g., polysilicon layers).

[0067] In order to better control the gauging and surface flatness of various structures to be formed on the second substrate, various stop layers can be formed between the second substrate and the filling layer. In some implementations, a first stop layer and a second stop layer are sequentially formed between the second substrate and the filling layer. The first stop layer can include silicon oxide or silicon nitride, and the second stop layer can include silicon oxide or polysilicon. In some implementations, a third stop layer (e.g., a silicon nitride layer or a polysilicon layer, etc.) is formed between the second stop layer and the filling layer. In some implementations, a single stop layer (e.g., a silicon oxide layer or a high-k dielectric layer, etc.) is formed between the second substrate and the filling layer.

[0068] As shown in FIG. 3A, a first stop layer 303 is formed above the carrier substrate 302, a second stop layer 304 is formed on the first stop layer 303, and a filling layer 306 is formed on the second stop layer 304. The filling layer 306 can include polysilicon, a high-k dielectric, or a metal. The second stop layer 304 can act as an etching stop layer when etching the channel hole from the front side, and thus can include any suitable material having a high etching selectivity (e.g., greater than about 5) with respect to the material directly above the second stop layer 304 (e.g., silicon oxide or polysilicon, etc.). The first stop layer 303 can act as a CMP / etching stop layer when removing the carrier substrate 302 from the back side, and thus can include any suitable material other than the material of the carrier substrate 302 (e.g., silicon nitride or silicon oxide, etc.). In some examples, it is understood that a pad oxide layer (e.g., a silicon oxide layer) can be formed between the carrier substrate 302 and the first stop layer 303 to relieve the stress between different layers and avoid delamination.

[0069] As shown in FIG. 3A, the stack of the silicon oxide layer (pad oxide layer), the silicon nitride layer (first stop layer 303), and the silicon oxide layer (second stop layer 304) can be sequentially formed on the carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. In some implementations, the fill layer 306 is formed by depositing polysilicon or any other suitable material (such as a high-k dielectric or a metal, etc.) on the second stop layer 304 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. For ease of explanation, the combination of stop layers shown in FIG. 3A has been used throughout this disclosure to illustrate the fabrication process. However, it is understood that any other suitable combination of stop layers can similarly be used in other examples. In an example not shown, a single oxide layer or a high-k dielectric layer (as the first and second stop layers 303 and 304) can be formed on the carrier substrate 302 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

[0070] As shown in FIG. 3B, a dielectric stack 308 including a plurality of pairs of first dielectric layers (referred to herein as “stack sacrificial layers” 312) and second dielectric layers (referred to herein as “stack dielectric layers” 310; together referred to herein as “dielectric layer pairs”) is formed on the fill layer 306. The dielectric stack 308 includes interleaved stack sacrificial layers 312 and stack dielectric layers 310 according to some implementations. The stack dielectric layers 310 and the stack sacrificial layers 312 can be alternately formed on the fill layer 306 above the carrier substrate 302 to form the dielectric stack 308. In some implementations, each stack dielectric layer 310 includes a layer of silicon oxide, and each stack sacrificial layer 312 includes a layer of silicon nitride. The dielectric stack 308 can be formed by one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As shown in FIG. 3B, a staircase structure can be formed on the edge of the dielectric stack 308. The staircase structure can be formed by performing a plurality of so-called “trim etching” cycles on the dielectric layer pairs of the dielectric stack 308 toward the carrier substrate 302. Due to the repeated trim etching cycles applied to the dielectric layer pairs of the dielectric stack 308, the dielectric stack 308 can have one or more sloped edges and upper dielectric layer pairs that are shorter than the bottom ones, as shown in FIG. 3B.

[0071] As shown in FIG. 5, method 500 proceeds to operation 506, where a channel structure is formed that extends through and beyond the dielectric stack and the fill layer. The channel structure can include a first dielectric layer, a second dielectric layer, a third dielectric layer, and a semiconductor channel. In some implementations, to form the channel structure, a channel hole is formed that extends through the dielectric stack and the fill layer, which stops at the second stop layer, and the first dielectric layer, the second dielectric layer, the third dielectric layer, and the semiconductor channel are sequentially formed within the channel hole. In some implementations, the second dielectric layer includes a dielectric material different from the first and third dielectric layers. For example, the second dielectric layer can include silicon nitride.

[0072] As shown in FIG. 3B, each channel hole is an opening that extends vertically through and beyond the dielectric stack 308 and the fill layer 306, and it terminates at the second stop layer 304. In some implementations, a plurality of openings are formed, each of which is to be a location for growing an individual channel structure 314 in a later process. In some implementations, the fabrication process for forming the channel holes of the channel structure 314 includes wet etching and / or dry etching (such as deep RIE (DRIE), etc.). The etching of the channel holes continues, according to some implementations, until it is stopped by the second stop layer 304 (such as silicon oxide or polysilicon, etc.). In some implementations, the etching conditions (such as etching rate and time, etc.) can be controlled to ensure that each channel hole reaches and terminates at the second stop layer 304 in order to minimize the gouging variation between the channel holes and the channel structure 314 formed therein. Depending on the specific etching selectivity, one or more channel holes can extend slightly into the second stop layer 304, which is still understood to be stopped by the second stop layer 304 in the present disclosure.

[0073] As shown in FIG. 3B, a first dielectric layer 317, a second dielectric layer 316, a third dielectric layer 315, and a semiconductor channel 318 are sequentially formed in this order along the sidewall and bottom surface of the channel hole. In some implementations, the first, second, and third dielectric layers 317, 316, and 315 are first deposited in this order along the sidewall and bottom surface of the channel hole using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.) to form a memory film. Then, the semiconductor channel 318 can be formed by depositing a semiconductor material (e.g., polysilicon (e.g., undoped polysilicon), etc.) on the third dielectric layer 315 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, a first silicon oxide layer, a silicon nitride layer, a second silicon oxide layer, and a polysilicon layer (a "SONO" structure) are sequentially deposited to form the first dielectric layer 317, the second dielectric layer 316, the third dielectric layer 315, and the semiconductor channel 318.

[0074] As shown in FIG. 3B, a capping layer 319 is formed in the channel hole portion and on the semiconductor channel 318, and (for example, without or with an air gap) completely or partially fills the channel hole portion. The capping layer 319 can be formed by depositing a dielectric material (such as silicon oxide, etc.) using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). Then, a channel plug can be formed in the upper portion of the channel hole portion. By wet etching and / or dry etching a part of the semiconductor channel 318 and the capping layer 319 in the upper portion of the channel hole portion, a recess can be formed in the upper portion of the channel hole portion. Then, the channel plug can be formed by depositing a semiconductor material (such as polysilicon, etc.) into the recess by one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof, etc.). Thereby, according to some implementation forms, the channel structure 314 is formed through and beyond the dielectric stack 308 and the filling layer 306, which stops at the second stop layer 304.

[0075] As shown in FIG. 3C, the slit 320 is an opening that extends vertically through the dielectric stack 308 and stops at the filling layer 306. In some implementation forms, the manufacturing process for forming the slit 320 includes wet etching and / or dry etching (such as DRIE, etc.). Then, gate exchange can be performed through the slit 320 to exchange the dielectric stack 308 with the memory stack 330 (shown in FIG. 3E).

[0076] As shown in FIG. 3D, the lateral recess 322 is first formed by removing the stack sacrificial layer 312 (shown in FIG. 3C) through the slit 320. In some implementations, the stack sacrificial layer 312 is removed by applying an etchant through the slit 320, creating lateral recesses 322 interleaved between the stack dielectric layers 310. The etchant can include any suitable etchant that selectively etches the stack sacrificial layer 312 with respect to the stack dielectric layer 310.

[0077] As shown in FIG. 3E, a stack conductive layer 328 (including a gate electrode and an adhesive layer) is deposited into the lateral recesses 322 (shown in FIG. 3D) through the slit 320. In some implementations, a gate dielectric layer 332 is deposited into the lateral recesses 322 before the stack conductive layer 328, such that the stack conductive layer 328 is deposited on top of the gate dielectric layer 332. The stack conductive layer 328 (e.g., a metal layer, etc.) can be deposited using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, the gate dielectric layer 332 (e.g., a high-k dielectric layer, etc.) is similarly formed along the sidewalls and bottom of the slit 320. Thereby, a memory stack 330 including the interleaved stack conductive layer 328 and stack dielectric layer 310 is formed, and in some implementations, replaces the dielectric stack 308 (shown in FIG. 3D).

[0078] As shown in FIG. 3E, an insulating structure 336 is formed that extends vertically through the memory stack 330 and terminates at the upper surface of the fill layer 306. The insulating structure 336 is formed by depositing one or more dielectric materials (e.g., silicon oxide, etc.) into the slit 320 and can completely or partially fill the slit 320 (e.g., without or with an air gap) using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). In some implementations, the insulating structure 336 includes a gate dielectric layer 332 (e.g., including a high-k dielectric) and a dielectric capping layer 334 (e.g., including silicon oxide). In some implementations, the dielectric capping layer 334 can partially fill the slit 320, and a polysilicon core layer 335 can fill the remaining space of the slit 320 as part of the insulating structure 336 to adjust the mechanical properties (e.g., hardness or stress, etc.) of the insulating structure 336.

[0079] As shown in FIG. 3F, after the formation of the insulating structure 336, local contact portions (including channel local contact portion 344, word line local contact portion 342, and peripheral contact portions 338 and 340) are formed. A local dielectric layer can be formed over the memory stack 330 by depositing a dielectric material (such as silicon oxide or silicon nitride) over the memory stack 330 using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof). The contact openings are etched through the local dielectric layer (and any other ILD layer) using wet etching and / or dry etching (such as RIE), and then the contact openings are filled with a conductive material using one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof), whereby the channel local contact portion 344, the word line local contact portion 342, and the peripheral contact portions 338 and 340 can be formed.

[0080] As shown in FIG. 3F, a bonding layer 346 is formed over the channel local contact portion 344, the word line local contact portion 342, and the peripheral contact portions 338 and 340. The bonding layer 346 includes bonding contacts that are electrically connected to the channel local contact portion 344, the word line local contact portion 342, and the peripheral contact portions 338 and 340. To form the bonding layer 346, an ILD layer is deposited using one or more thin film deposition processes (such as CVD, PVD, ALD, or any combination thereof), and the bonding contacts are formed through the ILD layer using wet etching and / or dry etching (such as RIE), followed by one or more thin film deposition processes (such as ALD, CVD, PVD, any other suitable process, or any combination thereof).

[0081] As shown in FIG. 5, method 500 proceeds to operation 508, in which the first substrate and the second substrate are bonded in a face-to-face manner such that the memory stack is above the peripheral circuitry. The bonding can include hybrid bonding. As shown in FIG. 3G, carrier substrate 302 and components formed thereon (e.g., memory stack 330 and channel structure 314 formed therethrough) are turned upside down. According to some implementations, the downward-facing bonding layer 346 is bonded to the upward-facing bonding layer 348, i.e., bonded in a face-to-face manner, thereby forming a bonding interface 354 between carrier substrate 302 and silicon substrate 350. In some implementations, a processing process (e.g., plasma processing, wet processing, and / or heat treatment) is applied to the bonding surface prior to bonding. After bonding, the bonding contacts in bonding layer 346 and the bonding contacts in bonding layer 348 are aligned and in contact with each other such that memory stack 330 and channel structure 314 formed therethrough can be electrically connected to peripheral circuitry 352 and be above peripheral circuitry 352.

[0082] As shown in FIG. 5, method 500 proceeds to operation 510, where a portion of the channel structure extending beyond the second substrate and the filling layer is sequentially removed to expose a portion of the channel structure. The removal can be performed from the back side of the second substrate. As shown in FIG. 6, in some implementations, at 602, the second substrate is removed to sequentially remove a portion of the second substrate and the channel structure, which stops at the first stop layer; at 604, the first stop layer is removed, which stops at the second stop layer; at 606, the second stop layer and a portion of the channel structure are removed, which stops at the filling layer. In some implementations, the removed portion of the channel structure extends into the second stop layer, and the second stop layer and a portion of the channel structure extending into the second stop layer are polished.

[0083] As shown in FIG. 3H, the carrier substrate 302 (and the pad oxide layer between the carrier substrate 302 and the first stop layer 303 shown in FIG. 3G) is completely removed from the back side until it is stopped by the first stop layer 303 (e.g., a silicon nitride layer). The carrier substrate 302 can be completely removed using CMP, grinding, dry etching, and / or wet etching. In some implementations, the carrier substrate 302 is peeled off. In some implementations where the carrier substrate 302 contains silicon and the first stop layer 303 contains silicon nitride, the carrier substrate 302 can be removed using silicon CMP, which can automatically stop when it reaches the first stop layer 303 having a material other than silicon (i.e., acts as a backside CMP stop layer). In some implementations, the carrier substrate 302 (silicon substrate) is removed using wet etching with tetramethylammonium hydroxide (TMAH), which automatically stops when it reaches the first stop layer 303 having a material other than silicon (i.e., acts as a backside etching stop layer). The first stop layer 303 can ensure complete removal of the carrier substrate 302 without concern for thickness uniformity after thinning.

[0084] As shown in FIG. 3I, the first and second stop layers 303 and 304 (shown in FIG. 3H) can then be similarly completely removed using wet etching with a suitable etchant (e.g., phosphoric acid and hydrofluoric acid, etc.) until stopped by a fill layer 306 having a material different from the second stop layer 304 (e.g., polysilicon). As shown in FIG. 3I, a portion of the channel structure 314 extending beyond the fill layer 306 is removed such that the upper end of the channel structure 314 is flush with the upper surface of the fill layer 306. In some implementations where a portion of the channel structure 314 extends into the second stop layer 304, the second stop layer 304 and the portion of the channel structure 314 extending into the second stop layer 304 are removed together by polishing (e.g., CMP, etc.), which stops at the fill layer 306. It is understood that the removal of the upper end of the channel structure 314 may be skipped if the channel structure 314 does not extend beyond the fill layer 306 into the second stop layer 304.

[0085] Removal of a portion of the channel structure 314 from the back side is much less difficult and has a higher production yield compared to known solutions using front side wet etching through an opening (e.g., slit 320 in FIG. 3D) in a dielectric stack 308 / memory stack 330 having a high aspect ratio (e.g., greater than 50). By avoiding the problems introduced by the high aspect ratio of the slit 320, it is possible to reduce the complexity and cost of fabrication and increase the yield. Also, vertical scalability (e.g., an increase in the level of the dielectric stack 308 / memory stack 330) can be similarly improved.

[0086] As shown in FIG. 5, method 500 proceeds to operation 512, where a portion of the second dielectric layer of the channel structure is exchanged with a fourth dielectric layer that includes a dielectric material different from the second dielectric layer. As shown in FIG. 6, in some implementations, to exchange a portion of the second dielectric layer of the channel structure with the fourth dielectric layer, a portion of the second dielectric layer is etched back at 608 to form a recess, and the fourth dielectric layer is deposited at 610 to fill the recess.

[0087] As shown in FIG. 3J, a portion of the second dielectric layer 316 is removed to form a recess 321 surrounded by upper portions of the first and third dielectric layers 317 and 315. For example, a portion of the second dielectric layer 316 of the channel structure 314 can be etched back to form the recess 321 using, for example, dry etching and / or wet etching. The etching of the second dielectric layer 316 can be controlled by controlling the etching time and / or etching rate so that the etching does not continue beyond the source select gate line (e.g., one or more stack conductive layers 328 closest to the fill layer 306).

[0088] As shown in FIG. 3K, the fourth dielectric layer 323 is deposited to partially or completely fill the recess 321 (in FIG. 3J), and a removed part of the second dielectric layer 316 is to be replaced by the fourth dielectric layer 323. The fourth dielectric layer 323 can be in contact with the remaining part of the second dielectric layer 316 along the vertical direction, and can also be in contact with the first and third dielectric layers 317 and 315 respectively along the horizontal direction. In some implementations, the fourth dielectric layer 323 includes silicon oxide (the same dielectric material as the first and third dielectric layers 317 and 315), while the second dielectric layer 316 includes silicon nitride. To form the fourth dielectric layer 323, a dielectric material (e.g., silicon nitride) can be deposited into the recess 321 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.), and followed by CMP to remove the excess dielectric material.

[0089] In some examples, it is understood that the recess 321 can be partially filled by the fourth dielectric layer 323 and an air gap can also be formed within the fourth dielectric layer 323. In some examples, the recess 321 may not be filled at all by the fourth dielectric layer 323, and it is further understood that the recess 321 remains as an air gap in the final product of the 3D memory device.

[0090] As shown in FIG. 6, in some implementations, a part of the first, third, and fourth dielectric layers extending into the filling layer is removed at 612 to form a recess, and a part of the semiconductor channel exposed by the recess is doped at 614.

[0091] As shown in FIG. 3L, a portion of the first, third, and fourth dielectric layers 317, 315, and 323 and the capping layer 319 are removed to form a recess 325, exposing an upper portion of the semiconductor channel 318. For example, the first, third, and fourth dielectric layers 317, 315, and 323 and the capping layer 319 of the channel structure 314 can have the same dielectric material (e.g., silicon oxide, etc.), and thus, using wet etching with hydrofluoric acid as the etchant, it is possible to selectively etch back with respect to the semiconductor channel 318 having polysilicon. The etching of the first, third, and fourth dielectric layers 317, 315, and 323 and the capping layer 319 can be controlled by controlling the etching time and / or the etching rate so that the etching does not continue into the memory stack 330 beyond the fill layer 306. The formation of the recess 325 can expose a portion of the semiconductor channel 318. In some implementations, the upper portion of the semiconductor channel 318 exposed by the recess 325 is doped to increase its conductivity. For example, an inclined ion implantation process can be implemented to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) exposed by the recess 325 with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb, etc.) to a desired doping concentration.

[0092] As shown in FIG. 5, method 500 proceeds to operation 514, where a doped semiconductor layer is formed in contact with the exposed portion of the semiconductor channel. In some implementations, the dopant includes an N-type dopant. As shown in FIG. 6, in some implementations, to form the doped semiconductor layer, at 616, a layer of polysilicon is deposited into the recess and on top of the fill layer, and at 612, the deposited layer of polysilicon is doped.

[0093] As shown in FIG. 3M, a doped semiconductor layer 360 is formed in the recess 325 (shown in FIG. 3J), which surrounds and contacts an exposed portion of the semiconductor channel 318 and the outside of the recess 321 over the fill layer 306. In some implementations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited in the recess 325 in contact with the exposed portion of the semiconductor channel 318, the first, third, and fourth dielectric layers 317, 315, and 323, and the capping layer 319, and also deposited outside the recess 321 in contact with the fill layer 306, using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb, etc.) using ion implantation and / or thermal diffusion. In some implementations, in-situ doping with an N-type dopant (e.g., P, As, or Sb, etc.) is performed when depositing the semiconductor layer into the recess 325 and over the fill layer 306 to form the doped semiconductor layer 360. In some implementations, a CMP process can be performed to remove any excess doped semiconductor layer 360, if necessary.

[0094] As shown in FIG. 5, method 500 proceeds to operation 516, where a doped semiconductor layer and a portion of the semiconductor channel in contact with the doped semiconductor layer are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer and a portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel for local activation. The confined area can be between the stack structure and the doped semiconductor layer. In some implementations, the doping concentration of the doped semiconductor layer and the doping concentration of the portion of the semiconductor channel in contact with the doped semiconductor layer are each between 10 19 cm -3 and 10 21 cm -3 after activation.

[0095] As shown in FIG. 3N, a doped semiconductor layer 360 and a portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 are locally activated. In some implementations, heat is applied to a confined area having the doped semiconductor layer 360 and a portion of the semiconductor channel 318 to activate dopants therein (e.g., an N-type dopant (e.g., P, As, or Sb), etc.). For example, the confined area can be between the memory stack 330 and the doped semiconductor layer 360 in the vertical direction. The heat can be applied and focused by any suitable technique (e.g., annealing, laser, ultrasonic, or any other suitable thermal process, etc.). In some implementations, the confined area that may be affected by heat during the local activation process does not extend up to and beyond the bonding interface 354 to avoid heating the Cu interconnects used to connect the bonding interface 354 and the peripheral circuit 352. The local activation process can activate the dopants doped into the doped semiconductor layer 360 (and, if the semiconductor channel 318 is already doped, the exposed portion of the semiconductor channel 318). As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the exposed portion of the semiconductor channel 318 are each 10 19 cm -3 to 10 21 cm -3It lies therebetween. In some implementations, the local activation process is controlled such that dopants within the doped semiconductor layer 360 (and, when the semiconductor channel 318 is already doped, the exposed portion of the semiconductor channel 318) can diffuse from the source of the channel structure 314 towards the drain of the channel structure 314, as described above with respect to FIG. 2A, across the source select gate line (e.g., one or more stack conductive layers 328 closest to the fill layer 306), but not facing the word line. When a portion of the semiconductor channel 318 is not yet doped, the doped semiconductor layer 360 acts as a doping source during the local activation process and can diffuse dopants from the doped semiconductor layer 360 into the semiconductor channel 318 such that at least a portion of the semiconductor channel 318 in contact with the doped semiconductor layer 360 can become a doped portion, and the doped semiconductor layer 360 and the doped portion of the semiconductor channel 318 can have the same dopant and doping concentration.

[0096] The local activation process can activate the dopants such that the dopants occupy the silicon lattice, reduce the contact resistance between the doped semiconductor layer 360 and the semiconductor channel 318, and also reduce the sheet resistance of the doped semiconductor layer 360. On the other hand, by confining the heat during the local activation process within an area without a thermosensitive structure, any potential damage to the thermosensitive structure (e.g., the bonding interface 354 and Cu interconnects used to connect the peripheral circuit 352, etc.) can be reduced or avoided.

[0097] As shown in FIG. 5, method 500 proceeds to operation 518, where a source contact is formed in contact with a doped semiconductor layer. As shown in FIG. 3O, one or more ILD layers 356 are formed over the doped semiconductor layer 360. The ILD layer 356 can be formed by depositing a dielectric material over the upper surface of the doped semiconductor layer 360 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof). As shown in FIG. 3P, a source contact opening 358 can be formed through the ILD layer 356 to expose a portion of the doped semiconductor layer 360. In some implementations, the source contact opening 358 is formed using wet etching and / or dry etching (e.g., RIE, etc.).

[0098] As shown in FIG. 3Q, source contacts (as part of the conductive layer 370) are formed in respective source contact openings 358 (shown in FIG. 3P) at the backside of the fill layer 306. According to some implementations, the source contacts are above and in contact with the doped semiconductor layer 360. In some implementations, a conductive layer 370 (e.g., Al, etc.) is deposited into the source contact openings 358 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof) to fill the source contact openings 358. Then, a planarization process (e.g., CMP, etc.) can be performed to remove the excess conductive layer 370.

[0099] As shown in FIG. 3Q, in some implementations, the conductive layer 370 also includes a redistribution layer that is above and in contact with the source contact. That is, according to some implementations, the conductive layer 370 is deposited not only into the source contact opening 358 as a source contact but also outside the source contact opening 358 on the ILD layer 356 as a redistribution layer that electrically connects multiple source contacts.

[0100] As shown in FIG. 3Q, in some implementations, the conductive layer 370 further includes contacts that extend through the ILD layer 356, the doped semiconductor layer 360, and the fill layer 306. That is, the conductive layer 370 is deposited not only into the source contact opening 358 as a source contact but also into the contact openings 363 and 361 (shown in FIG. 3P) as contacts that are electrically connected to the peripheral contacts 338 and 340. As shown in FIGS. 3Q and 3P, the contact openings 363 and 361 that extend through the spacer layer 371, the ILD layer 356, the doped semiconductor layer 360, and the fill layer 306 are formed using wet etching and / or dry etching (e.g., RIE, etc.). In some implementations, the contact openings 363 and 361 are patterned using lithography so as to be aligned with the peripheral contacts 338 and 340, respectively. The etching of the contact openings 363 and 361 can stop at the upper ends of the peripheral contacts 338 and 340 to expose the peripheral contacts 338 and 340. As shown in FIG. 3P, spacers 362 are formed from the spacer layer 371 along the sidewall portions of the contact openings 363 and 361 to electrically isolate the doped semiconductor layer 360.

[0101] Figures 4A and 4B illustrate a fabrication process for forming another exemplary 3D memory device according to some implementations of the present disclosure. The example of the 3D memory device depicted in FIGS. 4A and 4B includes the 3D memory device 160 depicted in FIG. 1B. As shown in FIG. 4A, unlike FIG. 3L where the recess 325 is formed by etching back the first, third, and fourth dielectric layers 317, 315, and 323 and the capping layer 319, the upper portion of the semiconductor channel 318 is doped to increase its conductivity without first etching back the first, third, and fourth dielectric layers 317, 315, and 323 and the capping layer 319 to expose a portion of the semiconductor channel 318. For example, an inclined ion implantation process can be implemented to dope the upper portion of the semiconductor channel 318 (e.g., including polysilicon) to a desired doping concentration with any suitable dopant (e.g., an N-type dopant such as P, As, or Sb).

[0102] In some implementations, to form a doped semiconductor layer, a layer of polysilicon is deposited on the fill layer, and the deposited layer of polysilicon is doped. As shown in FIG. 4A, a doped semiconductor layer 360 is formed on the fill layer 306 and on the upper end of the channel structure 314. In some implementations, to form the doped semiconductor layer 360, a semiconductor layer (e.g., polysilicon) is deposited on the fill layer 306 using one or more thin film deposition processes (e.g., ALD, CVD, PVD, any other suitable process, or any combination thereof, etc.). The deposited semiconductor layer can be doped with an N-type dopant (e.g., P, As, or Sb, etc.) using ion implantation and / or thermal diffusion. In some implementations, in-situ doping of an N-type dopant (e.g., P, As, or Sb, etc.) is performed when depositing the semiconductor layer on the fill layer 306 to form the doped semiconductor layer 360. In some implementations, a CMP process can be performed, if necessary, to remove any excess doped semiconductor layer 360.

[0103] As shown in FIG. 4B, the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318 are locally activated. In some implementations, heat is applied to a confined area having the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318 to activate the dopants therein (e.g., an N-type dopant (e.g., P, As, or Sb)). The local activation process can activate the dopants doped into the doped portions of the doped semiconductor layer 360 and the semiconductor channel 318. As a result, the doping concentration of the doped semiconductor layer 360 and the doping concentration of the doped portion of the semiconductor channel 318 are each, after activation, from 10 19 cm -3 to 10 21 cm -3It lies between. In some implementations, the local activation process is controlled such that dopants in the doped semiconductor layer 360 and the doped portions of the semiconductor channel 318 can diffuse from the source of the channel structure 314 towards the drain of the channel structure 314 through the source select gate line (e.g., one or more stack conductive layers 328 closest to the fill layer 306) as described above with respect to FIG. 2A, but without facing the word line.

[0104] According to one aspect of the present disclosure, a 3D memory device includes a stack structure including interleaved conductive and dielectric layers, a doped semiconductor layer, and a channel structure that extends through the stack structure and is in contact with the doped semiconductor layer. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces one of the conductive layers closest to the doped semiconductor layer along the first direction.

[0105] In some implementations, the memory portion of the composite dielectric film includes a blocking layer, a storage layer, and a tunneling layer stacked along the first direction, and the gate dielectric portion of the composite dielectric film includes a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer.

[0106] In some implementations, the blocking layer and the first gate dielectric layer include the same dielectric material, the tunneling layer and the third gate dielectric layer include the same dielectric material, and the storage layer and the second gate dielectric layer include different dielectric materials.

[0107] In some implementations, the storage layer includes silicon nitride.

[0108] In some implementations, each of the blocking layer, the tunneling layer, and the first and third gate dielectric layers includes silicon oxide.

[0109] In some implementations, the first, second, and third dielectric layers include the same dielectric material.

[0110] In some implementations, one of the conductive layers includes a source select gate line.

[0111] In some implementations, the semiconductor channel includes a doped portion, and a part of the doped portion faces one of the conductive layers closest to the doped semiconductor layer along a first direction.

[0112] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

[0113] In some implementations, the 3D memory device further includes a filling layer between the stack structure and the doped semiconductor layer.

[0114] In some implementations, the doped semiconductor layer includes a plate and a plug, the plug extends from the plate into the filling layer, and is in contact with the semiconductor channel.

[0115] In some implementations, the doped semiconductor layer is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0116] In some implementations, the composite dielectric film radially surrounds the semiconductor channel along a first direction.

[0117] According to another aspect of the present disclosure, a 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure. The conductive layers include one or more source select gate lines and a plurality of word lines. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces one or more source select gate lines along the first direction. The semiconductor channel includes a doped portion. A part of the doped portion faces one or more source select gate lines along the first direction.

[0118] In some implementations, the composite dielectric film radially surrounds the semiconductor channel along the first direction.

[0119] In some implementations, the 3D memory device further includes a doped semiconductor layer in contact with the doped portion of the semiconductor channel. In some implementations, the source select gate line is closer to the doped semiconductor layer than the word line.

[0120] In some implementations, the memory portion of the composite dielectric film includes a blocking layer, a storage layer, and a tunneling layer stacked along the first direction, and the gate dielectric portion of the composite dielectric film includes a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer.

[0121] In some implementations, the blocking layer and the first gate dielectric layer include the same dielectric material, the tunneling layer and the third gate dielectric layer include the same dielectric material, and the storage layer and the second gate dielectric layer include different dielectric materials.

[0122] In some implementations, the storage layer includes silicon nitride.

[0123] In some implementations, each of the blocking layer, the tunneling layer, and the first and third gate dielectric layers includes silicon oxide.

[0124] In some implementations, the first, second, and third dielectric layers include the same dielectric material.

[0125] In some implementations, the 3D memory device further includes a filling layer between the stack structure and the doped semiconductor layer.

[0126] In some implementations, the doped semiconductor layer includes a plate and a plug, the plug extends from the plate into the filling layer, and is in contact with the semiconductor channel.

[0127] In some implementations, the doped semiconductor layer is configured to generate a GIDL-assisted body bias when performing an erase operation.

[0128] In some implementations, the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

[0129] According to yet another aspect of the present disclosure, the system includes a 3D memory device configured to store data and a controller circuit coupled to the 3D memory device. The 3D memory device includes a stack structure including interleaved conductive layers and dielectric layers, and a channel structure extending through the stack structure. The conductive layers include one or more source select gate lines and a plurality of word lines. The channel structure includes a composite dielectric film and a semiconductor channel along a first direction. The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction. A part of the gate dielectric portion faces one or more source select gate lines along the first direction. The semiconductor channel includes a doped portion. A part of the doped portion faces one or more source select gate lines along the first direction. The controller circuit is configured to operate the composite dielectric film via the conductive layer.

[0130] According to yet a further aspect of the present disclosure, a method for forming a 3D memory device is provided. A fill layer is formed over a substrate. A stack structure is formed over the fill layer. A channel structure is formed extending through and beyond the stack structure and the fill layer. The channel structure includes a first dielectric layer, a second dielectric layer, a third dielectric layer, and a semiconductor channel. The substrate and a part of the channel structure extending beyond the fill layer are sequentially removed to expose a part of the channel structure. A part of the second dielectric layer of the channel structure is replaced with a fourth dielectric layer including a dielectric material different from the second dielectric layer.

[0131] In some implementations, the second dielectric layer includes a dielectric material different from the first and third dielectric layers.

[0132] In some implementations, the second dielectric layer includes silicon nitride.

[0133] In some embodiments, to replace a portion of the second dielectric layer of the channel structure with a fourth dielectric layer, a portion of the second dielectric layer is etched back to form a recess, and the fourth dielectric layer is deposited to fill the recess.

[0134] In some embodiments, a doped semiconductor layer is formed in contact with the semiconductor channel, and a portion of the doped semiconductor layer and the semiconductor channel in contact with the doped semiconductor layer are locally activated.

[0135] In some embodiments, to locally activate, heat is applied in a confined area having the doped semiconductor layer and a portion of the semiconductor channel to activate dopants in the doped semiconductor layer and the portion of the semiconductor channel.

[0136] In some embodiments, the confined area is between the stack structure and the doped semiconductor layer.

[0137] In some embodiments, a portion of the semiconductor channel is doped before forming the doped semiconductor layer.

[0138] In some embodiments, portions of the first, third, and fourth dielectric layers extending into the filling layer are removed to form a recess.

[0139] In some embodiments, to form the doped semiconductor layer, a layer of polysilicon is deposited into the recess and on the filling layer, and the deposited layer of polysilicon is doped.

[0140] In some embodiments, a first stop layer and a second stop layer are sequentially formed between the substrate and the filling layer.

[0141] In some implementations, the first stop layer includes silicon oxide or silicon nitride, the second stop layer includes silicon oxide or polysilicon, and the fill layer includes polysilicon, a high-k dielectric, or a metal.

[0142] In some implementations, to form a channel structure, a channel hole extending through the stack structure and the fill layer is formed, which stops at the second stop layer, and the first dielectric layer, the second dielectric layer, the third dielectric layer, and the semiconductor channel are sequentially formed in the channel hole.

[0143] In some implementations, to sequentially remove a portion of the substrate and the channel structure, the substrate is removed, stopping at the first stop layer, the first stop layer is removed, stopping at the second stop layer, the second stop layer and a portion of the channel structure are removed, and stopping at the fill layer.

[0144] In some implementations, after locally activating the doped semiconductor layer, a source contact is formed in contact with the doped semiconductor layer.

[0145] The foregoing description of specific implementations can be readily modified and / or adapted for various applications. Accordingly, such adaptations and modifications are intended to be within the meaning and scope of the equivalents of the disclosed implementations, based on the teachings and guidance presented herein.

[0146] The breadth and scope of the present disclosure should not be limited by any of the exemplary embodiments described above, but should be defined only in accordance with the appended claims and their equivalents.

Description of Reference Numerals

[0147] 100 3D memory device 101 Substrate 102 First semiconductor structure 104 Second semiconductor structure 106 Bonding interface 108 Peripheral circuit 110 Bonding layer 111 Bonding contact 112 Bonding layer 113 Bonding contact 114 Memory stack 116 Stack conductive layer 118 Stack dielectric layer 120 Filling layer 121 Plate 122 Doped semiconductor layer 123 Plug 124 Channel structure 126 Composite dielectric film 126a Gate dielectric portion 126b Memory portion 127 Capping layer 128 Semiconductor channel 128a Doped portion 128b Undoped portion 129 Channel plug 130 Insulating structure 132 Source contact 133 Interconnect layer 134 ILD layer 136 Redistribution layer 138 Passivation layer 140 Contact pad 142 Contact 144 Contact 146 Peripheral contact 148 Peripheral contact 150 Channel local contact 152 Word line local contact 160 3D memory device 201 Source select gate line 203 Word line 205 First gate dielectric layer 207 Second gate dielectric layer 209 Third gate dielectric layer 211 Blocking layer 213 Storage layer 214 Tunneling layer 302 Carrier substrate 303 First stop layer 304 Second stop layer 306 Filling layer 308 Dielectric stack 310 Stacked dielectric layer 312 Stacked sacrificial layer 314 Channel structure 315 Third dielectric layer 316 Second dielectric layer 317 First dielectric layer 318 Semiconductor channel 319 Capping layer 320 Slit 321 Recess 322 Lateral recess 323 Fourth dielectric layer 325 Recess 328 Stacked conductive layer 330 Memory stack 332 Gate dielectric layer 334 Dielectric capping layer 335 Polysilicon core layer 336 Insulating structure 338 Peripheral contact 340 Peripheral contact 342 Word line local contact 344 Channel local contact 346 Bonding layer 348 Bonding layer 350 Silicon substrate 352 Peripheral circuit 354 Bonding interface 356 ILD layer 358 Source contact opening 360 Doped semiconductor layer 361 Contact opening 362 Spacer 363 Contact part opening 370 Conductive layer 371 Spacer layer 700 System 702 Memory system 704 3D memory device 706 Memory controller 708 Host 802 Memory card 804 Memory card connector 806 SSD 808 SSD connector

Claims

1. A three-dimensional (3D) memory device, wherein the 3D memory device comprises: A stack structure including interleaved conductive layers and dielectric layers; A doped semiconductor layer; A channel structure extending through the stack structure and in contact with the doped semiconductor layer, the channel structure including a composite dielectric film and a semiconductor channel along a first direction, the composite dielectric film including a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction, and a part of the gate dielectric portion facing one of the conductive layers closest to the doped semiconductor layer along the first direction; a channel structure A 3D memory device comprising.

2. The memory portion of the composite dielectric film includes a blocking layer, a storage layer, and a tunneling layer stacked along the first direction; The gate dielectric portion of the composite dielectric film includes a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer. The 3D memory device according to claim 1.

3. The blocking layer and the first gate dielectric layer include the same dielectric material; The tunneling layer and the third gate dielectric layer include the same dielectric material; The storage layer and the second gate dielectric layer include different dielectric materials. The 3D memory device according to claim 2.

4. The storage layer includes silicon nitride. The 3D memory device according to claim 2.

5. Each of the blocking layer, the tunneling layer, and the first and third gate dielectric layers includes silicon oxide. The 3D memory device according to claim 3 or 4.

6. The first, second, and third dielectric layers include the same dielectric material. The 3D memory device according to claim 2.

7. One of the conductive layers includes a source select gate line. The 3D memory device according to any one of claims 1 to 6.

8. The semiconductor channel includes a doped portion; A part of the doped portion faces one of the conductive layers closest to the doped semiconductor layer along the first direction. The 3D memory device according to any one of claims 1 to 7.

9. The 3D memory device according to claim 8, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

10. The 3D memory device according to any one of claims 1 to 9, further comprising a filling layer between the stack structure and the doped semiconductor layer.

11. The 3D memory device according to claim 10, wherein the doped semiconductor layer includes a plate and a plug, the plug extends from the plate into the filling layer, and is in contact with the semiconductor channel.

12. The 3D memory device according to any one of claims 1 to 11, wherein the doped semiconductor layer is configured to generate a gate-induced drain leakage (GIDL)-assisted body bias when performing an erase operation.

13. The 3D memory device according to any one of claims 1 to 12, wherein the composite dielectric film radially surrounds the semiconductor channel along the first direction.

14. A three-dimensional (3D) memory device, the 3D memory device comprising: A stack structure including interleaved conductive layers and dielectric layers, the conductive layers including one or more source select gate lines and a plurality of word lines; A channel structure extending through the stack structure, the channel structure including a composite dielectric film and a semiconductor channel along a first direction; Including The composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction, and a part of the gate dielectric portion faces the one or more source select gate lines along the first direction. The semiconductor channel includes a doped portion, and a part of the doped portion faces the one or more source select gate lines along the first direction.

15. The 3D memory device according to claim 14, wherein the composite dielectric film radially surrounds the semiconductor channel along the first direction.

16. The 3D memory device according to claim 14 or 15, further comprising a doped semiconductor layer in contact with the doped portion of the semiconductor channel, wherein the source select gate line is closer to the doped semiconductor layer than the word line.

17. The memory portion of the composite dielectric film includes a blocking layer, a storage layer, and a tunneling layer stacked along the first direction. The 3D memory device according to claim 16, wherein the gate dielectric portion of the composite dielectric film includes a first gate dielectric layer, a second gate dielectric layer, and a third gate dielectric layer.

18. The blocking layer and the first gate dielectric layer include the same dielectric material. The tunneling layer and the third gate dielectric layer include the same dielectric material. The 3D memory device according to claim 17, wherein the storage layer and the second gate dielectric layer include different dielectric materials.

19. The 3D memory device according to claim 17, wherein the storage layer includes silicon nitride.

20. The 3D memory device according to claim 18 or 19, wherein each of the blocking layer, the tunneling layer, and the first and third gate dielectric layers includes silicon oxide.

21. The 3D memory device according to claim 17, wherein the first, second, and third dielectric layers include the same dielectric material.

22. The 3D memory device according to any one of claims 16 to 21, further comprising a filling layer between the stack structure and the doped semiconductor layer.

23. The 3D memory device according to claim 22, wherein the doped semiconductor layer includes a plate and a plug, the plug extends from the plate into the filling layer, and is in contact with the semiconductor channel.

24. The 3D memory device according to any one of claims 16 to 23, wherein the doped semiconductor layer is configured to generate a gate-induced drain leakage (GIDL)-assisted body bias when performing an erase operation.

25. The 3D memory device according to any one of claims 14 to 24, wherein the doped portion of the semiconductor channel and the doped semiconductor layer each include N-type doped polysilicon.

26. A system, wherein the system includes a three-dimensional (3D) memory device configured to store data, wherein the 3D memory device is a stack structure including interleaved conductive layers and dielectric layers, wherein the conductive layers include one or more source select gate lines and a plurality of word lines, is a channel structure extending through the memory stack, wherein the channel structure includes a composite dielectric film and a semiconductor channel along a first direction, and includes the composite dielectric film includes a gate dielectric portion and a memory portion along a second direction perpendicular to the first direction, a part of the gate dielectric portion faces the one or more source select gate lines along the first direction, and a part of the memory portion faces the plurality of word lines along the first direction, the semiconductor channel includes a doped portion, and a part of the doped portion faces the one or more source select gate lines along the first direction, furthermore, the system includes a controller circuit, wherein the controller circuit is connected to the 3D memory device and is configured to operate the composite dielectric film through the conductive layer.

27. A method for forming a three-dimensional (3D) memory device, the method including: forming a filling layer above a substrate; forming a stack structure above the filling layer; forming a channel structure extending through and beyond the stack structure and the filling layer, the channel structure including a first dielectric layer, a second dielectric layer, a third dielectric layer, and a semiconductor channel; sequentially removing the substrate and a part of the channel structure extending beyond the filling layer to expose a part of the channel structure; replacing a part of the second dielectric layer of the channel structure with a fourth dielectric layer including a dielectric material different from that of the second dielectric layer. The method as described above.

28. The method according to claim 27, wherein the second dielectric layer includes a dielectric material different from that of the first and third dielectric layers.

29. The method according to claim 27 or 28, wherein the second dielectric layer contains silicon nitride.

30. The step of exchanging a part of the second dielectric layer of the channel structure with the fourth dielectric layer includes: etching back a part of the second dielectric layer to form a recess; and depositing the fourth dielectric layer to fill the recess. The method according to any one of claims 27 to 29.

31. forming a doped semiconductor layer in contact with the semiconductor channel; and locally activating the doped semiconductor layer and a part of the semiconductor channel in contact with the doped semiconductor layer. The method according to any one of claims 27 to 30, further comprising:

32. The step of locally activating includes applying heat in a confined area having the doped semiconductor layer and the part of the semiconductor channel, and activating dopants in the doped semiconductor layer and the part of the semiconductor channel. The method according to claim 31.

33. The method according to claim 32, wherein the confined area is between the stack structure and the doped semiconductor layer.

34. The method according to any one of claims 31 to 33, further comprising doping a part of the semiconductor channel before forming the doped semiconductor layer.

35. The method according to any one of claims 31 to 34, further comprising removing a part of the first, third, and fourth dielectric layers extending into the filling layer to form a recess.

36. The step of forming the doped semiconductor layer includes: depositing a layer of polysilicon into the recess and on the filling layer; and doping the deposited layer of polysilicon. The method according to claim 35.

37. The step of forming the doped semiconductor layer includes: depositing a layer of polysilicon on the filling layer; and doping the deposited layer of polysilicon. The method according to any one of claims 31 to 36.

38. The method according to any one of claims 27 to 37, further comprising sequentially forming a first stop layer and a second stop layer between the substrate and the filling layer.

39. The method according to claim 38, wherein the first stop layer contains silicon oxide or silicon nitride, the second stop layer contains silicon oxide or polysilicon, and the filling layer contains polysilicon, a high dielectric constant (high-k) dielectric, or a metal.

40. The step of forming the channel structure includes: forming a channel hole extending through the stack structure and the filling layer and stopping at the second stop layer; sequentially forming the first dielectric layer, the second dielectric layer, the third dielectric layer, and the semiconductor channel in the channel hole. The method according to claim 38 or 39.

41. The step of sequentially removing the substrate and the part of the channel structure includes: removing the substrate and stopping at the first stop layer; removing the first stop layer and stopping at the second stop layer; removing the second stop layer and the part of the channel structure and stopping at the filling layer. The method according to claim 40.

42. The method according to any one of claims 31 to 37, further including forming a source contact in contact with the doped semiconductor layer after locally activating the doped semiconductor layer.

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