Control of metal contamination from metal-containing photoresist

Abstract

To control a metal-containing contaminated material on a semiconductor substrate to deal with metal-containing contaminations generated during the photoresist development operation.SOLUTION: According to the technique, a substrate can be involved in at least one of post-development baking processing of subjecting the substrate to baking at temperatures of approximately 160-300°C over approximately 1 to 10 minutes; chemical processing of exposing the substrate to reactive processing gas; plasma processing of exposing the substrate to plasma generated from the plasma generation gas; optical processing of exposing the substrate to light; and cleaning processing of the back side and the edges.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] Incorporation by Reference The PCT Request Form is filed simultaneously with this specification as part of this application. Each application for which this application claims benefit or priority, as identified in the simultaneously filed PCT Request Form, is hereby incorporated by reference into this specification in its entirety and for all purposes.

[0002] Embodiments within this specification relate to the field of semiconductor processing. In particular, various embodiments relate to patterning a semiconductor substrate using photolithography and related processes. Various techniques for controlling metal contamination are discussed.

Background Art

[0003] Fabrication of semiconductor devices such as integrated circuits is a multi-step process involving photolithography. Generally, the process includes deposition of materials onto a wafer and patterning the materials through lithographic techniques to form structural features of the semiconductor device (e.g., transistors and circuits). Steps of a typical photolithography process known in the art include preparing a substrate, applying a photoresist by spin coating or the like, exposing the photoresist to light in a desired pattern, causing the exposed regions of the photoresist to be at least somewhat dissolved in a developer, developing the photoresist pattern by applying a developer to remove either the exposed or unexposed regions of the photoresist, and performing subsequent processing to create features on the regions of the substrate where the photoresist has been removed, such as by etching or material deposition.

[0004] The evolution of semiconductor design has been driven by, and has created, the need to create ever smaller features on semiconductor substrate materials. Such technological progress has been characterized by "Moore's Law," which states that the density of transistors in integrated circuits doubles every two years. In fact, due to advances in chip design and manufacturing, modern microprocessors can contain billions of transistors and other circuit features on a single chip. Individual features on such chips can be on the order of 22 nanometers (nm) or less, and in some cases less than 10 nm.

[0005] One challenge in manufacturing devices with such small features is the ability to reliably and reproducibly create photolithography masks with sufficient resolution. Current photolithography processes typically use 193 nanometer (nm) ultraviolet (UV) light to expose photoresist. The fact that the light has a wavelength significantly larger than the desired size of the features to be created on the semiconductor substrate presents an inherent problem. Achieving feature sizes smaller than the wavelength of the light requires the use of complex resolution enhancement techniques such as multipatterning. Thus, there is significant interest and research effort in developing photolithography techniques that use shorter wavelength light, such as extreme ultraviolet (EUV) radiation, which has a wavelength in the range of 10 nm to 15 nm, for example 13.5 nm.

[0006] However, EUV photolithography processes can present challenges, including low power output and optical losses during patterning. Conventional chemically amplified resists (CARs) similar to those used in 193 nm UV lithography, when used in EUV lithography, particularly when they have low absorption coefficients in the EUV region and diffusion of photoactivated species can result in blurring or line edge roughness, have potential drawbacks. Further, small features patterned in conventional CAR materials can result in high aspect ratios with a risk of pattern collapse in order to provide the etch resistance required to pattern underlying device layers. Thus, there remains a need for improved EUV photoresist materials having properties such as reduced thickness, greater absorbance, and greater etch resistance.

[0007] The background description provided herein is for the purpose of generally presenting the context of the present technology. The achievements of the inventors named herein are not admitted, expressly or impliedly, as prior art to the present technology, to the extent that they are described in this background section of the application and in aspects of the description that do not qualify as prior art at the time of filing. SUMMARY OF THE INVENTION

[0008] Various embodiments herein relate to methods, apparatuses, and systems for controlling contamination on a substrate. The substrate is typically a semiconductor substrate. In one aspect of the disclosed embodiments, a method for controlling contamination on a substrate is provided, the method comprising: (a) either (i) treating a front side of the substrate to cause formation of contamination containing metal on a back side of the substrate, or (ii) receiving a substrate with contamination on the back side of the substrate, and (b) heating the substrate in a post-treatment bake process after (a), wherein heating the substrate reduces metal contamination on the back side of the substrate.

[0009] In some embodiments, processing the front side of the substrate can include at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, pulling out a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist. In these or other embodiments, (a) can include either (i) developing a layer of photoresist on the substrate, or (ii) receiving a substrate with a layer of photoresist developed on the front side of the substrate and contamination on the back side of the substrate, where the metal in the contamination originates from the layer of photoresist on the front side of the substrate, and the post-treatment bake process of (b) is a post-develop bake process that occurs when the layer of photoresist is at least partially developed. In these or other embodiments, during the post-develop bake process of (b), the substrate can be baked at a temperature of about 160 - 300 °C for a duration of about 1 - 10 minutes.

[0010] In these or other embodiments, the method may further include exposing the substrate to a processing gas, the processing gas including at least one gas selected from the group consisting of N2, H2, Ar, He, Xe, and combinations thereof. In these or other embodiments, the method may further include exposing the substrate to a reactive processing gas to increase the volatility of a metal-containing material on the substrate, the metal-containing material including a metal. In some embodiments, the method may further include exposing the substrate to a reactive processing gas to increase the stability of a metal-containing material on the substrate, the metal-containing material including a metal. In these or other embodiments, the method may further include exposing the substrate to a reactive processing gas selected from the group consisting of a chlorine-containing gas, an oxygen-containing gas, a fluorine-containing gas, ammonia (NH3), hydrogen iodide (HI), diatomic iodine (I2), and combinations thereof. In some cases, the substrate may be exposed to a chlorine-containing gas, the chlorine-containing gas including at least one gas selected from the group consisting of BCl3, Cl2, HCl, SiCl4, SOCl2, PCl3, and combinations thereof. In some cases, the substrate may be exposed to an oxygen-containing gas, the oxygen-containing gas including at least one gas selected from the group consisting of O2, O3, H2O, SO2, CO2, CO, COS, H2O2, NO x , and combinations thereof. In some cases, the substrate may be exposed to a fluorine-containing gas, the fluorine-containing gas including at least one gas selected from the group consisting of HF, C x F y H z , NF3, SF6, F2, and combinations thereof.

[0011] In these or other embodiments, the method may further include exposing the substrate to plasma to increase the volatility of the metal-containing material on the substrate, where the metal-containing material contains metal. In some embodiments, the method may further include exposing the substrate to plasma to increase the stability of the metal-containing material on the substrate, where the metal-containing material contains metal. In these or other embodiments, the method may further include exposing the substrate to a plasma generated from a plasma-generating gas that includes at least one gas selected from the group consisting of diatomic hydrogen (H2), diatomic nitrogen (N2), argon, helium, krypton, methane (CH4), an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, hydrogen halide, and combinations thereof. x In some embodiments, the plasma-generating gas may include an oxygen-containing gas, and the oxygen-containing gas may include at least one gas selected from the group consisting of O2, O3, CO, CO2, COS, SO2, NO

[0012] In these or other embodiments, heating the substrate in the post-development bake process may reduce the concentration of metal on the back side of the substrate by at least one order of magnitude. In these or other embodiments, the method may further include exposing the substrate to plasma, heating the substrate in the post-development bake process, and exposing the substrate to plasma may reduce the concentration of metal on the back side of the substrate by at least two orders of magnitude.

[0013] In these or other embodiments, the method may further include exposing the substrate to light to reduce the concentration of metal on the back side of the substrate. In some embodiments, the light may include at least one of UV wavelength, visible wavelength, or IR wavelength. In some embodiments, the light may be provided by an IR lamp or a plurality of LEDs, and the substrate may be heated to a temperature of about 250 to 400 °C for a duration of about 60 seconds or less while the substrate is exposed to the light.

[0014] In these or other embodiments, heating the substrate in the post-development bake process may begin while the layer of photoresist is still developed on the substrate.

[0015] In these or other embodiments, the method may further include transferring the substrate from a first processing chamber to a second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber. In these or other embodiments, (a) may occur in the processing chamber, and the method may further include heating the processing chamber to a temperature of about 40 °C or higher while the layer of photoresist is developed in (a). In these or other embodiments, (a) may occur in the processing chamber, and the method may further include purging the processing chamber while maintaining the processing chamber at a temperature of about 100 °C or higher, and the purge occurs after (a). In some embodiments, the method may further include sweeping the processing chamber with an inert gas, and the purge and the sweep are part of a pump purge sequence.

[0016] In these or other embodiments, the method may further include performing a wet cleaning on the back side of the substrate after (a) and (b). In these or other embodiments, performing a wet cleaning on the back side of the substrate may further reduce the concentration of metal on the back side of the substrate by at least one order of magnitude. In these or other embodiments, the wet cleaning may also clean the bevel edge region on the front side of the substrate. In these or other embodiments, performing a wet cleaning on the back side of the substrate may include exposing the back side of the substrate to dilute HF. In these or other embodiments, performing a wet cleaning on the back side of the substrate may include exposing the back side of the substrate to dilute HCl or to a standard cleaning 1 solution containing NH4OH, H2O2, and H2O.

[0017] Various Embodiment In some embodiments, the layer of photoresist may be formed using dry deposition. In other embodiments, the layer of photoresist may be formed using wet deposition. In various embodiments, the layer of photoresist may be developed using a dry process. In some embodiments, the layer of photoresist may be developed using a halogen-containing chemistry Substance and may be developed using a wet process.

[0018] In various embodiments, the post-development bake process of (b) may occur within the processing chamber and the following conditions: (i) the pressure within the processing chamber may be maintained at about 0.01 to 1 torr, (ii) a chlorine-containing gas may be provided to the processing chamber at a rate of about 200 to 10,000 sccm for a duration of about 1 to 10 minutes, (iii) the temperature of one or more components of the processing chamber may be maintained at about 20 to 150 °C, and (iv) the substrate may not be exposed to plasma during (b), may be used during the post-development bake process of (b).

[0019] In various embodiments, the photoresist layer can be developed in (a) within a processing chamber, (b) can occur within the same processing chamber as (a), and the method can use the following conditions: (i) the pressure within the processing chamber can be about 0.01 - 1 torr, (ii) a purge gas flow can be provided to the processing chamber at a rate of about 200 - 10,000 sccm, the purge gas includes at least one gas selected from the group consisting of diatomic nitrogen (N2), noble gases, and combinations thereof, and the purge gas is provided to the processing chamber for a duration of about 1 - 10 minutes, and (iii) one or more components of the processing chamber can be maintained at about 100 - 300 °C, and the substrate support within the processing chamber can be maintained at about 120 - 300 °C, and can further include purging the processing chamber using these conditions.

[0020] In various embodiments, (a) can occur within a first processing chamber, (b) can occur within a second processing chamber, and the following conditions: (i) the pressure within the second processing chamber can be maintained at about 0.1 - 760 torr, (ii) a gas flow can be provided to the second processing chamber at a rate of about 200 - 10,000 sccm for a duration of about 1 - 10 minutes, the substrate can be exposed to the gas flow, and the gas flow includes at least one of diatomic nitrogen (N2), diatomic oxygen (O2), water (H2O), noble gases, or combinations thereof, and (iii) the substrate can be baked at a temperature of about 140 - 300 °C and can be used during the post-development bake process of (b).

[0021] In these or other embodiments, the method may be under the following conditions: (i) the pressure in the processing chamber can be about 0.1 to 1 torr; (ii) the plasma generating gas can be provided at a rate of about 50 to 5,000 over a duration of about 3 to 30 seconds, and the plasma generating gas can include at least one gas or gas mixture selected from the group consisting of (a) H2, (b) H2 and N2, (c) H2 and noble gas, (d) N2 without H2, (e) noble gas without H2, (f) oxygen-containing gas, (g) fluorine-containing gas, and (h) combinations thereof; and (iii) the plasma is generated from the plasma generating gas and the substrate is exposed to the plasma. The method may further include exposing the substrate to the plasma in the processing chamber.

[0022] In these or other embodiments, at least one of (a) and (b) can occur within the processing chamber, and the method may further include cleaning the processing chamber to remove metal from the inner surface of the processing chamber. In some embodiments, the processing chamber can be cleaned using the following conditions: (i) the pressure in the processing chamber can be about 0.1 to 10 torr; (ii) a plasma containing H radicals can be exposed to the processing chamber, and the H radicals react with the metal on the inner surface of the processing chamber to form metal hydrides; (iii) the plasma can be generated using about 300 to 4,000 watts of RF power; and (iv) the processing chamber can be maintained at about 25 to 250 °C. In these or other embodiments, the processing chamber can be cleaned using the following conditions: (i) the pressure in the processing chamber can be about 0.1 to 10 torr and can be cycled between a lower pressure and a higher pressure as part of a pumping and purging process; (ii) the processing chamber is not exposed to plasma during cleaning; (iii) a gas flow can be provided to the processing chamber during cleaning, and the gas flow includes at least one gas selected from the group consisting of diatomic nitrogen (N2), diatomic oxygen (O2), noble gas, and combinations thereof; and (iv) the processing chamber can be maintained at about 25 to 250 °C.

[0023] In these or other embodiments, the method may further include performing a wet cleaning on the backside of the substrate using the following conditions: (i) in a first step, the substrate may be exposed to a first cleaning liquid provided at a rate of about 1 to 3 L / min, the first cleaning liquid including dilute HF; (ii) in a second step, the substrate may be exposed to a second cleaning liquid provided at a rate of about 1 to 3 L / min, the second cleaning liquid including a solution selected from the group consisting of dilute HCl, standard clean 1, and combinations thereof; (iii) the first step and the second step together may have a duration of about 20 to 300 seconds; and (iv) the substrate may be maintained at about 15 to 60 °C.

[0024] In these or other embodiments, the concentration of metal in at least one of the backside or the bevel edge region of the substrate may be reduced by at least one order of magnitude to about 1E11 atoms / cm 2 or less. In these or other embodiments, the concentration of metal in at least one of the backside or the bevel edge region of the substrate may be reduced by at least one order of magnitude to about 1E10 atoms / cm 2 or less.

[0025] In these or other embodiments, the metal may be tin.

[0026] In another aspect of the disclosed embodiments, a system for processing a substrate is provided, the system including a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, and a controller configured to cause any one or more of the claimed methods or the methods otherwise described herein.

[0027] In another aspect of the disclosed embodiments, a system for processing a substrate is provided, the system including a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, and a controller configured to (a) (i) process a front side of the substrate such that, on a back side of the substrate, formation of contamination including metal is caused, or (ii) receive a substrate with contamination on the back side of the substrate, and (b) after (a), heat the substrate in a post-treatment bake process, wherein heating the substrate causes a reduction in the concentration of metal on the back side of the substrate.

[0028] In some embodiments, processing the front side of the substrate may include at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, withdrawing a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist.

[0029] In these or other embodiments, the controller may be configured to cause (a) by either (i) developing a layer of photoresist on the substrate or (ii) causing either a layer of photoresist developed on the front side of the substrate and a substrate with contamination on the back side of the substrate to be received, wherein the metal in the contamination results from the layer of photoresist on the front side of the substrate, and the post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed.

[0030] In various embodiments, both (a) and (b) may occur within the same processing chamber. In other embodiments, (a) may occur within the processing chamber and (b) may occur within a second processing chamber, the second processing chamber being a different processing chamber from the processing chamber.

[0031] In these or other embodiments, the system may further include a plasma generator configured to provide plasma within a processing chamber.

[0032] In some cases, the plasma generator can be a remote plasma generator such that plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber. These and other aspects are further described below with reference to the drawings.

Brief Description of the Drawings

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[0054] The present disclosure generally relates to the field of semiconductor processing. In certain aspects, the present disclosure is directed to processes and apparatuses for the treatment and cleaning of photoresists (e.g., EUV-sensitive metal and / or metal oxide-containing photoresists) to remove unwanted photoresist, as well as related materials such as metals and metal bromides deposited on the backside and bevel edges of a substrate, for example, in the context of photoresist patterning.

[0055] In this specification, reference is made in detail to particular embodiments of the present disclosure. Examples of particular embodiments are illustrated in the accompanying drawings. While the present disclosure is described in conjunction with these particular embodiments, it should be understood that the present disclosure is not intended to be limited to such particular embodiments. In contrast, it is intended to cover alternatives, modifications, and equivalents as may be included within the spirit and scope of the present disclosure. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure may be practiced without some or all of these specific details. In other instances, well-known process operations have not been described in detail so as not to unnecessarily obscure the present disclosure.

[0056] For example, the present disclosure is provided primarily in the context of photoresist deposition, development, and processing, but the embodiments are not so limited. The various techniques described herein can also be applied in other contexts, particularly when it is desired to limit the gas emission of metal-containing species such as metal halides from a substrate and / or remove metal-containing species from the substrate (which is not limited, but particularly the backside and bevel edge regions of the substrate). Such techniques can be particularly useful when the metal is tin and / or the undesirable material is tin bromide, but other metals and halogens can be used as well. Examples of other processes that can benefit from one or more implementations of the disclosed techniques include, but are not limited to, in-situ cleaning, mandrel extraction, smoothing operations, and photoresist descum operations. The processes described herein as occurring "after development" can occur after other types of operations (e.g., deposition, etching, processing, etc.) in the contexts listed above. For example, the post-development bake (PDB) operation can instead be performed as a post-deposition bake, post-etch bake, post-processing bake, etc. In some such cases, the photoresist layer described herein can be replaced with another metal-containing or metal halide-containing layer. For purposes of clarity and conciseness, the present disclosure focuses on embodiments in the context of photoresist deposition, development, and processing.

[0057] Introduction The patterning of thin films in semiconductor processing is often an important step in semiconductor fabrication. Patterning involves lithography. In conventional photolithography such as 193 nm photolithography, a pattern is printed by emitting photons from a photon source onto a mask and printing the pattern onto a photosensitive photoresist, thereby causing a chemical reaction within the photoresist that removes specific portions of the photoresist after development to form the pattern.

[0058] Advanced technology nodes (such as those defined by the International Technology Roadmap for Semiconductors) include node 22nm, 16nm, and beyond. At the 16nm node, for example, the width of a typical via or line within a damascene structure is typically about 30nm or less. Scaling of features on advanced semiconductor integrated circuits (ICs) and other devices has driven lithography to improve resolution.

[0059] Extreme ultraviolet (EUV) lithography can extend lithography technology by shifting to imaging source wavelengths smaller than those achievable with conventional photolithography methods. EUV light sources with wavelengths of approximately 10 - 20nm, or 11 - 14nm, such as 13.5nm, can be used for state-of-the-art lithography tools, also referred to as scanners. EUV radiation is strongly absorbed by a wide range of solid and fluid materials, including quartz and water vapor, and also operates as such in a vacuum.

[0060] EUV lithography utilizes an EUV resist that is patterned to form a mask for use in etching underlying layers. The EUV resist can be a polymer-based chemically amplified resist (CAR) produced by liquid-based spin-on technology. Alternatives to CAR are available from Inpria, Corvallis, OR, and are also, for example, metal oxide-containing films that are directly photo-patternable, such as those described in U.S. Patent Publication No. 2017 / 0102612 and U.S. Patent No. 2016 / 0116839, which patents are incorporated herein by reference at least for their disclosures of such directly photo-patternable metal oxide-containing films. Such films can be produced by spin-on technology or dry deposition. The metal oxide-containing films can be patterned directly (i.e., without the use of a separate photoresist) by EUV exposure in a vacuum atmosphere to provide sub-30nm patterning resolution, such as described in U.S. Patent No. 9,996,004, titled "EUV PHOTOPATTERNING OF VAPOR-DEPOSITED METAL OXIDE-CONTAINING HARDMASKS," issued June 12, 2018, and / or Application PCT / US No. 19 / 31618, titled "METHODS FOR MAKING EUV PATTERNABLE HARD MASKS," filed May 9, 2019, the disclosures of which are incorporated herein by reference at least with respect to the composition, deposition, and patterning of the directly photo-patternable metal oxide films for forming EUV resist masks. Generally, patterning involves exposing the EUV resist to EUV radiation to form a photo-pattern in the resist, followed by development to remove a portion of the resist by the photo-pattern to form a mask.

[0061] This disclosure relates to lithographic patterning techniques and materials exemplified by EUV lithography, but it should also be understood that this disclosure is applicable to other next-generation lithography techniques. In addition to EUV including the standard 13.5 nm EUV wavelength currently in use and development, the radiation sources most relevant to such lithography generally refer to DUV (deep UV), which generally refers to the use of 248 nm or 193 nm excimer laser sources, X-rays, which formally include EUV in the lower energy range of the X-ray range, and e-beams, which can cover a wide range of energy ranges. Specific methods may depend on the specific materials and applications used in semiconductor substrates and final semiconductor devices. Therefore, the methods described in this application are merely illustrative of methods and materials that can be used in this technology.

[0062] An EUV resist that can be directly photo-patterned can consist of or contain metals and / or metal oxides mixed within an organic component. Metals / metal oxides are very promising in that they can enhance EUV photon absorption, generate secondary electrons, and / or exhibit increased etch selectivity with respect to underlying film stacks and device layers.

[0063] During the application of a photoresist film (e.g., an EUV photoresist film) to a substrate by either conventional wet processing, e.g., spin-on processing, or dry deposition, there can be some unintentional deposition of resist material on the backside and / or side edges of the wafer. Similarly, the development of a photoresist film on a substrate can cause contamination (e.g., including metals and metal halides) within these same regions. This backside and side edge contamination can cause downstream processing problems, including contamination of patterning (scanner), development tools, and downstream processing and metrology tools. Such contamination can harm the performance of the tools as well as the films deposited on the front side of the wafer. In many cases, the removal of this backside and side edge deposition is performed by wet cleaning techniques, but dry cleaning techniques can also be used.

[0064] FIG. 22 illustrates a pair of semiconductor substrates loaded into a Front Opening Unified Pod (FOUP) and shows how metal contamination arising from a first substrate during a dry development step can redeposit onto a second substrate. Such redeposition can occur when multiple substrates are stored in a single FOUP or similar enclosure. A FOUP is a special container designed to securely hold semiconductor substrates in a controlled embodiment and allows substrates to be transferred between different apparatuses as needed for processing and / or measurement. In a first stage, prior to development of the photoresist, the first substrate is in a first slot of the FOUP and the second substrate is in a second slot of the FOUP. Each substrate includes a layer of photoresist 2201 that includes both exposed and unexposed portions. In a second stage, the photoresist 2201 is developed. In this example, a dry development process is used. However, in various other embodiments, a wet development process may be used. The development process selectively removes either the exposed or unexposed portions of the photoresist 2201, thereby forming a pattern in the photoresist. During the development process, some of the development by-products (e.g., R-SnBr x , 1 ≦ x ≦ 3) are undesirably redeposited on the front side of the substrate. In a third stage, the substrate contaminated by the development by-products is loaded into the first slot of the FOUP. Over time, the contamination from the front side of the substrate in the first slot can be transferred to the back side of the substrate in the second slot. Such spread of contamination is undesirable.

[0065] The present disclosure provides various techniques for minimizing the gas evolution of metal and / or metal halide species from metal-containing films on a substrate. In some cases, the method involves treating the substrate to make potentially contaminating species more volatile so that they can be removed from the substrate and the processing chamber. In some cases, the method involves treating the substrate to make potentially contaminating species more stable so that they are less likely to evolve as gases from the substrate during downstream processing. In various cases, the method involves cleaning the backside and bevel edge regions of the substrate after photoresist development to address contamination generated during development. These techniques can be combined as desired for a particular application. In various embodiments, the technology can also act to prevent or reduce unwanted surface movement and / or unwanted reactions on the substrate. Advantageously, the techniques herein show little or negligible impact on the patterns defined in the photoresist. Furthermore, such techniques can provide an improvement in line width roughness (LWR).

[0066] The specific operations provided herein can be limited to specific regions to ensure removal of material from the backside and bevel edge regions without film degradation on the front side of the substrate. These operations can include, for example, backside and bevel edge cleaning operations. Other operations described herein can act on the front side of the substrate, or on the entire substrate, for example, to intentionally modify metal-containing species on one or more substrate surfaces.

[0067] In some embodiments, the unwanted material on the substrate includes EUV resist material. In some embodiments, the unwanted material includes metals, metal halides, and / or organometallic halides resulting from the reaction of metals in the EUV resist material with halogens in the development chemistry Substance These can be referred to as etch by-products or development by-products. Such by-products can be up to about 1E16 atoms / cm of metal bromides and metal chlorides, which are about two to three orders of magnitude greater than what is typically acceptable in device manufacturing.2 It tends to remain particularly in the metal-containing photoresist material that can be held at the concentration of. In some cases, the metal is tin, the metal halide is SnBr x and / or the organometallic halide is RSnBrx. In these or other cases, the metal is tin, the metal halide is SnClx, and / or the organometallic halide is RSnClx. Other metals and halides can be used as well. In many cases, the undesirable materials are deposited on the back side and the bevel edge region of the substrate.

[0068] Figure 1 presents a flowchart of an exemplary method for depositing and developing a photoresist according to some embodiments. The operations of process 100 may be performed in a different order and / or with different operations, fewer operations, or additional operations. One or more operations of process 100 may be performed using the apparatus described in any one of FIGS. 6-9. In some embodiments, the operations of process 100 may be performed at least partially according to software stored on one or more non-transitory computer-readable media.

[0069] In block 102 of process 100, a layer of photoresist is deposited. This can be either a dry deposition process such as a vapor deposition process or a wet process such as a spin-on deposition process.

[0070] The photoresist can be a metal-containing EUV resist. Generally speaking, conventional chemically amplified photoresist materials do not contain large amounts of metal and are not troubled to the same extent by related metal contamination problems. As such, the methods herein can be practiced on any type of photoresist or other film, although they can have the greatest value in countermeasures against contamination from metal-containing EUV resists. EUV-sensitive metal or metal oxide-containing films can be deposited on a semiconductor substrate by any suitable technique including wet (e.g., spin-on) or dry (e.g., CVD) deposition techniques. For example, the processes described have been demonstrated for EUV photoresist compositions based on organotin oxides and are applicable to both commercially available spin-coatable formulations (such as those available from Inpria Corp, Corvallis, OR) and formulations applied using dry vacuum deposition techniques further described below. The photoresists described in this disclosure are often described as metal-containing EUV resist materials, but it should be understood that the process operations of this disclosure can be applied to any other film such as a silicon-based film or a carbon-based film.

[0071] The semiconductor substrate can include any material structure suitable for photolithography processing, particularly suitable for the production of integrated circuits and other semiconductor devices. In some embodiments, the semiconductor substrate is a silicon wafer. The semiconductor substrate can be a silicon wafer having an irregular surface topography with features created thereon ("underlying features"). As used herein, the front side of the substrate is the surface on which the film is intentionally deposited or the surface that will be exposed to EUV during processing. The back side of the substrate is the opposite side of the front side. The underlying features can include regions where material has been removed (e.g., by etching) or regions where material has been added (e.g., by deposition) during processing prior to performing the methods of this disclosure. Such preprocessing can include the methods of this disclosure or other processing methods in an iterative process in which two or more layers of features are formed on the substrate.

[0072] The EUV-sensitive thin film can be deposited on a semiconductor substrate, and such a film can operate as a resist for subsequent EUV lithography and processing. Such an EUV-sensitive thin film includes materials that undergo changes such as the loss of bulky pendant substituents that adhere to metal atoms in a low-density M-OH-rich material upon exposure to EUV, enabling their cross-linking to a higher-density M-O-M-bonded metal oxide material. Through EUV patterning, regions of the film with modified physical or chemical properties relative to the unexposed regions are created. These properties can be utilized in subsequent processing, such as dissolving either the unexposed or exposed regions, or selectively depositing material on either the exposed or unexposed regions. In some embodiments, the unexposed film has a more hydrophobic surface under the conditions under which such subsequent processing is carried out. For example, the removal of material can be carried out by leveraging differences in the chemical composition, density, and cross-linking of the film. The removal can be by wet or dry processing, as further described below.

[0073] The thin film, in various embodiments, is an organometallic material, such as an organotin material containing tin oxide, or other metal oxide materials / portions. The organometallic compound can be made in a gas-phase reaction of an organometallic precursor with a counter-reactant. In various embodiments, the organometallic compound is formed by mixing a specific combination of organometallic precursors having bulky alkyl or fluoroalkyl groups with a counter-reactant and polymerizing this mixture in the gas phase to produce a low-density EUV-sensitive material that deposits on a semiconductor substrate.

[0074] In various embodiments, the organometallic precursor includes at least one alkyl group on each metal atom that can avoid a gas-phase reaction, although other ligands or ions coordinating to the metal atom can be replaced by the counter-reactant. The organometallic precursors include those of the following formula, M a R b L c (Formula 1) Wherein, M is an element having a high-patterned radiation absorption cross-section, and R is C n H 2n+1 etc., is alkyl, preferably n≧3, L is a ligand, an ion, or another moiety that reacts with a counter-reactant, a≧1, b≧1, and c≧1.

[0075] In various embodiments, M has an atomic absorption cross-section equal to or greater than 1×10 7 cm 2 / mol. M can be selected from the group consisting of, for example, tin, hafnium, tellurium, bismuth, indium, iodine, antimony, germanium, and combinations thereof. In some embodiments, M is tin. R can be fluorinated, for example, having the formula C n F x H (2n+1) . In various embodiments, R has at least one beta-hydrogen or beta-fluorine. For example, R can be selected from the group consisting of i-propyl, n-propyl, t-butyl, i-butyl, n-butyl, sec-butyl, n-pentyl, i-pentyl, t-pentyl, sec-pentyl, and mixtures thereof. L can be any moiety that is readily displaced by a counter-reactant to form an M-OH moiety, such as a moiety selected from the group consisting of amines (dialkylamino, monoalkylamino, etc.), alkoxy, carboxylate, halogen, and mixtures thereof.

[0076] The organometallic precursor can be any of various candidate organometallic precursors. For example, when M is tin, such precursors include similar alkyl(tris)(t-butoxy)tin compounds such as t-butyltris(dimethylamino)tin, i-butyltris(dimethylamino)tin, n-butyltris(dimethylamino)tin, sec-butyltris(dimethylamino)tin, i-propyl(tris)dimethylaminotin, n-propyltris(diethylamino)tin, and t-butyltris(t-butoxy)tin. In some embodiments, the organometallic precursor is partially fluorinated.

[0077] The counter-reactant has the ability to replace a reactive moiety, ligand, or ion (e.g., L in Formula 1 above) so as to link at least two metal atoms by a chemical bond. The counter-reactant can include water, peroxide (e.g., hydrogen peroxide), divalent or polyvalent alcohols, fluorinated divalent or polyvalent alcohols, fluorinated glycols, and other sources of hydroxy moieties. In various embodiments, the counter-reactant reacts with the organometallic precursor by forming an oxygen bridge between adjacent metal atoms. Other potential counter-reactants include hydrogen sulfide and hydrogen disulfide, which can crosslink metal atoms via sulfur bridges.

[0078] The thin film can include optional materials in addition to the organometallic precursor and the counter-reactant to modify the chemical or physical properties of the film, such as modifying the film's sensitivity to EUV or enhancing its etch resistance. Such optional materials can be introduced, for example, by doping during vapor phase formation, either before deposition onto the semiconductor substrate, after deposition of the thin film, or both. In some embodiments, a gentle remote H2 plasma can be introduced to replace some of the Sn-L bonds with Sn-H, thereby increasing the reactivity of the resist under EUV.

[0079] In various embodiments, EUV-patternable films are made or deposited on semiconductor substrates using any of a number of deposition facilities and processes known in the art. In such processes, the polymerized organometallic material is formed on the surface of the semiconductor substrate either in the gas phase or in situ. Suitable processes include, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD using CVD components such as a discontinuous ALD-like process in which the metal precursor and the counter-reactant are separated either in time or space.

[0080] Generally, the method includes mixing a vapor stream of an organometallic precursor with a vapor stream of a counter-reactant to form a polymerized organometallic material, and depositing the organometallic material onto the surface of a semiconductor substrate. In some embodiments, two or more organometallic precursors are included in the vapor stream. In some embodiments, two or more counter-reactants are included in the vapor stream. As will be appreciated by those skilled in the art, the mixing and deposition aspects of the present process can occur simultaneously in a substantially continuous process.

[0081] In an exemplary continuous CVD process, two or more gas streams within separate inlet paths of an organometallic precursor and a counter-reactant source are introduced into a deposition chamber of a CVD apparatus, where they mix and react in the gas phase to form an aggregated polymerized material (e.g., by metal-oxygen-metal bond formation). This flow can be introduced, for example, using separate injection inlets or a dual-plenum showerhead. The apparatus is configured to allow the streams of the organometallic precursor and the counter-reactant to be mixed within the chamber and for the organometallic precursor and the counter-reactant to react to form a polymerized organometallic material. Without limiting the mechanism, function, or utility of the present technology, the product from such a gas-phase reaction is thought to have a higher molecular weight as metal atoms are cross-linked by the counter-reactant and then condensed or otherwise deposited onto a semiconductor substrate. In various embodiments, the steric hindrance of bulky alkyl groups prevents the formation of a dense network and produces a porous low-density film.

[0082] The CVD process is generally carried out under reduced pressure, such as from 10 mTorr to 10 Torr. In some embodiments, the process is carried out at 0.5 to 2 Torr. In some embodiments, the temperature of the semiconductor substrate is the same as or lower than the temperature of the reaction stream. For example, the substrate temperature can be from 0 °C to 250 °C, or from ambient temperature (e.g., 23 °C) to 150 °C. In various processes, the deposition of the polymerized organometallic material onto the substrate occurs at a rate inversely proportional to the surface temperature.

[0083] In some embodiments, the EUV-patternable film is fabricated or deposited on a semiconductor substrate using wet deposition facilities and processes among a number known in the art. For example, an organometallic material is formed by spin coating onto the surface of a semiconductor substrate.

[0084] The thickness of the EUV-patternable film formed on the surface of the semiconductor substrate can vary according to surface characteristics, the materials used, and processing conditions. In various embodiments, the film thickness can range from 0.5 nm to 100 nm and can be thick enough to absorb most of the EUV light under EUV patterning conditions. For example, the overall absorbance of the resist film can be 30% or less (e.g., 10% or less, or 5% or less) so that the resist material at the bottom of the resist film is sufficiently exposed. In some embodiments, the film thickness is 5 nm to 40 nm, or 10 nm to 20 nm. Without limiting the mechanism, function, or utility of the present disclosure, unlike the wet spin-coat deposition process, the dry deposition process presents fewer restrictions on the surface adhesion properties of the substrate and can therefore be applied to a wide range of substrates. Furthermore, as discussed above, the deposited film fits well with the surface features and has the advantage of forming a mask on a substrate such as a substrate with underlying features without having to “fill” such features or otherwise planarize them.

[0085] In block 104, a cleaning process is performed to clean the back side and bevel edges of the semiconductor substrate. The back side and bevel edge cleaning may non-selectively etch the EUV resist film in order to equally remove films with various levels of oxidation or cross-linking at the back side and bevel edges of the substrate. During the application of an EUV-patternable film by either a wet deposition process or a dry deposition process, there may be some unintended deposition of resist material on the substrate bevel edges and / or back side. Unintended deposition can lead to undesirable particles moving later to the top surface of the semiconductor substrate and becoming particle defects. Furthermore, this bevel edge and back side deposition can cause downstream processing problems, including contamination of patterning tools (scanners), developing tools, and metrology tools, which may later act to contaminate other substrates. Removal of this bevel edge and back side deposition can be achieved by using wet cleaning techniques or dry cleaning techniques, either alone or in combination with other techniques described herein.

[0086] State-of-the-art techniques for cleaning spin-coated organometallic photoresists are by wet cleaning processes. Examples are described below with reference to FIGS. 2A - 2D. Edge bead removal (EBR) is performed on the wet tracks on both the front and back sides of the wafer. Nozzles are positioned over the edges of the wafer on both the front and back sides of the wafer, and the solvent is dispensed while the wafer is rotating. An organic solvent (e.g., PGME, PGMEA, 2-heptanone) dissolves the photoresist on the edge to clean the bevel edge region. If the back side is contaminated, the wafer may proceed to another wet cleaning station for back side cleaning of the wafer. In the case of spin coating, the area of the wafer in contact with the chuck typically remains clean, and separate back side cleaning is not always used. Additional ones such as dilute hydrofluoric acid (dHF), dilute hydrochloric acid (dHCl), dilute sulfuric acid, or standard clean 1 (SC-1) Cleaning solution may be necessary to reduce metal contamination. A back side scrub is generally performed before entering the EUV scanner.

[0087] Dry backside and bevel edge cleaning techniques can be used in place of wet techniques. Dry backside and bevel edge cleaning can be performed using an etching gas. The etching gas can be hydrogen gas, hydrogen halide, hydrogen gas and halide gas, or boron trichloride. The processing chamber can be equipped with a substrate support having a plurality of minimum contact area (MCA) supports that tilt the substrate so that the etching gas can access the backside of the substrate. The substrate support can be a carrier ring as described below in connection with FIG. 5A. The etching gas can be delivered in a first etching gas from below the substrate support. The gas distributor can deliver a curtain gas at the center of the front side of the substrate to limit the etching gas from reaching the center of the front side. The gas distributor can also deliver the etching gas in a second etching gas flow at the peripheral edge of the front side of the substrate. A heat source, such as a radiant heat source, can be applied to the substrate during dry backside and bevel edge cleaning. The radiant heat source can be positioned below the substrate support. Both backside cleaning and bevel edge cleaning are performed in the same processing chamber. In some embodiments, the deposition operation as well as dry backside and bevel edge cleaning are performed in the same processing chamber. In some embodiments, the post-application bake (PAB) as well as dry backside and bevel edge cleaning are performed in the same processing chamber. Integration of tools / chambers within a single chamber increases throughput, reduces cost, and reduces the potential for contamination that would otherwise occur during transfer.

[0088] In some embodiments, the dry cleaning process involves a vapor and / or plasma having one or more of the following gases: HBr, HCl, HI, BCl3, SOCl2, Cl2, BBr3, H2, O2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the dry cleaning process can use the same chemistry as the dry development process described herein. Substance For example, backside and bevel edge cleaning can use hydrogen halide development chemistry Substancecan be used. In the case of the backside and bevel cleaning process, the vapor and / or plasma must be limited to specific regions of the substrate to ensure that only the backside and bevel deposits are removed without any film degradation on the front side of the substrate.

[0089] The process conditions can be optimized for backside and bevel cleaning. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow can result in increased etching rate. Suitable process conditions for dry bevel and backside cleaning can be, depending on the photoresist Of the film composition and properties, a reactant flow of 100 - 10000 sccm (e.g., 500 sccm HCl, HBr, HI, or H2 and Cl2, Br2, or I2, BCl3, or H2), a temperature of 20°C - 120°C (e.g., 100°C), a pressure of 20 mTorr - atmospheric pressure (e.g., 300 mTorr), a plasma power of 0 W - 500 W at a high frequency (e.g., 13.56 MHz), and a time of about 10 - 150 seconds. These conditions are suitable for some processing reactors, e.g., the Kiyo etching tool available from Lam Research Corporation, Fremont, CA, but it should be understood that a wider range of process conditions can be used according to the capabilities of the processing reactor.

[0090] The backside and bevel cleaning in block 104 is depicted before the PAB process in block 106, but it should be understood that the backside and bevel cleaning of block 104 can be performed at any stage during process 100 after the deposition of the photoresist in block 102 and before the development in block 112. Thus, the backside and bevel cleaning of block 104 can be performed after photoresist deposition, after PAB processing, after EUV exposure, or after PEB processing. As further discussed below, additional backside and bevel cleaning can be performed later in process 100, for example, as described in connection with block 118. The first backside and bevel cleaning operation in block 104 targets the removal of unwanted deposits resulting from the photoresist deposition in block 102, while the second backside and bevel cleaning operation in block 118 targets the removal of unwanted contamination generated during photoresist development in block 112. In some embodiments, one or both of the backside and bevel cleaning operations 104 and 118 can be omitted.

[0091] Wet or dry backside and bevel cleaning operations can alternatively be extended to a complete photoresist removal or photoresist "rework" where the applied EUV photoresist is removed and the semiconductor substrate is prepared for photoresist re - application, such as when the original photoresist has been damaged or is otherwise defective. Since photoresist rework must be achieved without damaging the underlying semiconductor substrate, oxygen - based etching should be avoided. Instead, a halide - containing chemistry as described herein SubstanceVariant forms can be used. It should be understood that the photoresist rework operation can be applied at any stage during process 100. Thus, the photoresist rework operation can be applied after photoresist deposition, after the first or second bevel and backside cleaning, after PAB treatment, after EUV exposure, after PEB treatment, after development, after PDB treatment, and after chemical, plasma, and / or optical treatment. In some embodiments, the photoresist rework can be performed selectively with respect to the underlying layer, but for non-selective removal of exposed and unexposed regions of the photoresist.

[0092] In some embodiments, the photoresist rework process involves vapors and / or plasmas having one or more of the following gases: HBr, HCl, HI, BCl3, Cl2, BBr3, H2, PCl3, CH4, methanol, ammonia, formic acid, NF3, HF. In some embodiments, the photoresist rework process can use the same chemistry as the dry development process described herein. Substance For example, the photoresist rework process can use hydrogen halide development chemistry. Substance can be used.

[0093] Process conditions can be optimized for photoresist rework. In some embodiments, higher temperature, higher pressure, and / or higher reactant flow can lead to increased etching rates. Suitable process conditions for photoresist rework, depending on the photoresist Of the film composition and properties, are a reactant flow of 100 - 500 sccm (e.g., 500 sccm HCl, HBr, HI, BCl3 or H2 and Cl2 or Br2), a temperature of -10 - 140 °C (e.g., 80 °C), a pressure of 20 - 1000 mTorr (e.g., 300 mTorr), a plasma power of 300 W - 800 W (e.g., 500 W) at a high frequency (e.g., 13.56 MHz), 0 - 200 V. bThe wafer bias (higher biases can be used with harder underlying substrate materials), and can be a time of about 20 seconds to 3 minutes sufficient to completely remove the EUV photoresist. In some embodiments, the photoresist rework can be performed without the application of plasma. The photoresist rework can be performed thermally using a halide-containing gas such as hydrogen bromide (e.g., HBr) at an elevated temperature (e.g., 80°C to 120°C). These conditions are suitable for some processing reactors, such as the Kiyo etching tool available from Lam Research Corporation, Fremont, CA, but it should be understood that a wider range of process conditions can be used according to the capabilities of the processing reactor.

[0094] In block 106 of process 100, an optional post-application bake (PAB) is performed after the deposition of the EUV-patternable film and before EUV exposure, and / or after backside and bevel cleaning. The PAB process can involve a combination of heat treatment, chemical exposure, and moisture to increase the EUV sensitivity of the EUV-patternable film, and reduce the EUV dose required to develop a pattern in the EUV-patternable film. The PAB treatment temperature can be adjusted and optimized to increase the sensitivity of the EUV-patternable film. For example, the treatment temperature can be about 90°C to about 200°C, or about 150°C to about 190°C. In some embodiments, the PAB process can be performed with an ambient gas flowing in the range of 100 to 10,000 sccm, a water content in the amount of a few percent to up to 100% (e.g., 20% to 50%), a pressure between atmosphere and vacuum, and a treatment duration of about 1 to 15 minutes, e.g., about 2 minutes. In some embodiments, the PAB process is performed at a temperature of about 100°C to 200°C for about 1 to 2 minutes.

[0095] In block 108 of process 100, the metal-containing EUV resist film is exposed to EUV radiation to develop the pattern. Generally speaking, EUV exposure causes changes in the chemical composition and cross-linking in the metal-containing EUV resist film, creating a contrast in the etching sensitivity that can be utilized for subsequent development.

[0096] The metal-containing EUV resist film can then be patterned, typically under a relatively high vacuum, by exposing certain regions of the film to EUV light. Among the several useful ones within this specification, EUV devices and imaging methods include those known in the art. In particular, as discussed above, the exposed regions of the film with modified physical or chemical properties relative to the unexposed regions are created through EUV patterning. For example, in the exposed regions, metal-carbon bond cleavage can occur via beta-hydrogen elimination, leaving a reactive and accessible metal hydride functionality that can be converted to hydroxides and cross-linked metal oxide moieties by metal-oxygen cross-linking, which can be used to create a chemical contrast either as a negative resist or as a template for a hard mask. Generally, the larger the number of beta Hs in the alkyl group, the more sensitive the resulting film. After exposure, the metal-containing EUV resist film can be baked to cause additional cross-linking of the metal oxide film. The property differences between the exposed and unexposed regions can be utilized in subsequent processes such as dissolving the unexposed regions or depositing material on the exposed regions. For example, the pattern can be developed using a dry process to form a metal oxide-containing mask. Among the several useful methods and apparatuses in such a process are those described in PCT patent application PCT / US2019 / 067540, filed on December 19, 2019, which is hereby incorporated by reference for its disclosure of such methods and apparatuses.

[0097] In particular, in various embodiments, the hydrocarbon-terminated tin oxide present on the surface is converted to hydrogen-terminated tin oxide in the exposed regions of the imaging layer, particularly when the exposure is carried out in vacuum using EUV. However, removing the exposed imaging layer from vacuum into air, or the controlled introduction of oxygen, ozone, H2O2, or water can result in the oxidation of surface Sn-H to Sn-OH. The difference in properties between the exposed and non-exposed regions can be utilized in subsequent processing by reacting the irradiated region, non-irradiated region, or both, with one or more reagents to selectively add material to or remove material from the imaging layer.

[0098] Without limiting the mechanism, function, or utility of the present technology, for example, EUV exposure at a dose of 10 mJ / cm 2 ~100 mJ / cm 2 can reduce steric hindrance and provide space for the collapse of the low-density film. In addition, the reactive metal-H bonds generated in the beta-hydrogen elimination reaction can react with neighboring active groups such as hydroxyls in the film, leading to further cross-linking and densification, creating a chemical contrast between the exposed and non-exposed regions.

[0099] After exposure of the metal-containing EUV resist film to EUV light, a photopatterned metal-containing EUV resist is provided. The photopatterned metal-containing EUV resist includes EUV-exposed regions and non-exposed regions.

[0100] In block 110 of process 100, an optional post-exposure bake (PEB) is performed to further increase the contrast in the etch sensitivity of the photopatterned metal-containing EUV resist. The photopatterned metal-containing EUV resist is heat-treated in the presence of various chemical species to promote cross-linking in the EUV-exposed regions of the photopatterned metal-containing EUV resist.

[0101] In various embodiments, the bake strategy involves careful control of the bake environment, introduction of reactive gases, and / or careful control of the ramp rate of the bake temperature. Examples of useful reactive gases include, for example, air, H2O, H2O2 vapor, CO2, CO, O2, O3, CH4, CH3OH, N2, H2, NH3, N2O, NO, alcohol, acetylacetone, formic acid, Ar, He, or mixtures thereof. The PEB process is designed to (1) drive complete vaporization of organic fragments generated during EUV exposure, (2) oxidize metal hydride species (other products from the beta-H removal reaction during EUV exposure) to metal hydroxides, and (3) promote cross-linking between neighboring -OH groups to form a cross-linked metal oxide network. The bake temperature is carefully selected to achieve optimal EUV lithography performance. Too low a PEB temperature leads to incomplete removal of organic fragments, as well as insufficient cross-linking and, consequently, a smaller chemical contrast for development at a given dose. Too high a PEB temperature also has adverse effects, including severe oxidation and film shrinkage in the non-exposed regions (in this example, the regions removed by development of the patterned film to form the mask), as well as unwanted interdiffusion at the interface between the photo-patterned metal-containing EUV resist and the underlying layer, both of which contribute to loss of chemical contrast and an increase in defect density due to insoluble scum. The PEB process temperature can be from about 100°C to about 300°C, from about 170°C to about 290°C, or from about 200°C to about 240°C. In some embodiments, the PEB process can be performed with an ambient gas flowing in the range of 100 - 10000 sccm, a water content in an amount from a few percent to up to 100% (e.g., 20% - 50%), a pressure between atmospheric and vacuum, and a process duration of about 1 - 15 minutes, e.g., about 2 minutes. In some embodiments, the PEB heat treatment can be repeated to further increase the etch selectivity.

[0102] In block 112 of process 100, the optically patterned metal-containing EUV resist is developed to form a resist mask. In various embodiments, the exposed regions are removed (positive-type) or the unexposed regions are removed (negative-type). In some embodiments, development can include selective deposition on either the exposed or unexposed regions of the optically patterned metal-containing EUV resist, followed by an etching operation. In various embodiments, these processes can be dry processes or wet processes. An example of a process for development involves an organotin oxide-containing EUV-sensitive photoresist thin film (e.g., 10 - 30 nm thick such as 20 nm) being subjected to EUV exposure dose and post-exposure bake and then developed. The photoresist film can be deposited based on a gas-phase reaction of an organotin precursor such as isopropyl(tris)(dimethylamino)tin and water vapor, or can be a spin-on film containing tin clusters within an organic matrix.

[0103] The optically patterned metal-containing EUV resist is developed by exposure to development chemistry Substance In some embodiments, the development chemistry Substance includes halide-containing chemistry Substance For example, bromine-containing chemistry Substance , chlorine-containing chemistry Substance , and / or fluorine-containing chemistry Substance can be used. In various embodiments, the halide-containing chemistry Substance is a hydrogen halide such as HBr, HCl, HI, and HF. Dry development techniques are further discussed in PCT patent application No. PCT / US2020 / 039615, filed on June 25, 2020, which is hereby incorporated by reference in its entirety.

[0104] The developing operation in block 112 can be optimized in certain embodiments. Such optimization can be particularly useful when dry developing techniques are used. The optimization can be performed to reduce metals and / or metal halides that can release gas from the photoresist on the substrate and can deposit on the backside and bevel edge regions of the substrate. Certain optimization techniques can facilitate the removal of certain types of potential contaminants, while other techniques can passivate contaminant species to reduce their ability to release gas during downstream gas emissions. The various optimizations described herein can be combined as desired for a particular application.

[0105] In various embodiments, the photoresist developing operation in block 112 can be optimized by performing the development within a heated processing chamber. Such heating reduces the overall byproduct concentration / accumulation within the chamber, which results in less undesirable byproduct deposition on the substrate. In various embodiments, the processing chamber and / or showerhead are maintained at a temperature increase, e.g., about 40°C or more, or about 65°C or more, or about 80°C or more, or about 100°C or more. In these or other cases, the processing chamber and showerhead can be maintained at a maximum temperature of about 300°C or less, or about 250°C or less, or about 200°C or less, or about 150°C or less, or about 100°C or less, or about 80°C or less. In some cases, the temperature is actively controlled and varied during dry development. In such cases, the temperature is actively increased during dry development. In other such cases, the temperature is actively decreased during dry development.

[0106] In these or other embodiments, the photoresist development operation at block 112 can be optimized by performing a high-temperature purge step in an inert atmosphere under reduced pressure. The purge step can be performed in the same processing chamber where the development operation occurs, at the end of, or immediately after, the photoresist development operation at block 112. Example gases that can be provided to establish an inert atmosphere include, for example, Ar, He, N2, Kr, Xe, and H2. Combinations of such gases can also be used. Example gas flow rates can be from about 200 to 10,000 sccm. The purge can have a duration of from about 1 to 10 minutes, in some cases at least about 2 minutes, or at least about 5 minutes. The purge step can be performed at a pressure of from about 5 mTorr to about 10 Torr. In some cases, the pressure can be at least about 10 mTorr. In these or other embodiments, the pressure can be about 1 Torr or less. The temperature during the purge step (e.g., the temperature of the processing chamber, showerhead, and / or substrate support) can be maintained at an elevated temperature, e.g., about 100 °C or higher, or about 120 °C or higher. In some cases, the processing chamber can be maintained at a temperature of from about 100 to 250 °C, or from about 100 to 300 °C, and the substrate support can be maintained at a temperature of from about 120 to 250 °C, or from about 120 to 300 °C.

[0107] In these or other embodiments, a pump purge sequence can be used at or near the end of the development process at block 112. Such a process can involve one or more cycles of pumping the processing chamber down to a reduced pressure and sweeping the processing chamber with an inert gas. This pumping and purging increases the efficiency of removing halogens and metal halides from the substrate and chamber.

[0108] In these or other cases, optimization may involve heat treatments such as the bake step described below in connection with block 114. In these or other cases, optimization may involve chemical, plasma, and / or optical treatments such as the processing operations described below in connection with block 116. As such, the operations described in connection with blocks 114 and / or 116 may overlap with the photoresist development operation in block 112, towards the end of the development operation in some cases. In other embodiments, the operations of blocks 114 and / or 116 may occur after the photoresist development operation of block 112 is completed.

[0109] In block 114, the substrate is exposed to a post - development bake (PDB). The PDB occurs after some or all of the photoresist has been developed in block 112. This step is referred to as a "post - development bake", but it should be understood that this step may also overlap to some extent with the development step, as explained above.

[0110] Similar to the photoresist deposition step in block 102, the photoresist development step in block 112 can cause metal and metal halide contamination on the back side and bevel edges of the substrate. As mentioned above, in many cases, development is performed using a halide - containing chemical such as HBr. Substance In some cases, the halide chemistry Substance reacts with the metal in the photoresist, partially dissolving the photoresist and causing the formation of metal halides and / or other metal - containing species that can redeposit on the substrate, for example, on the back side and bevel edges of the substrate. Such contamination is harmful for the reasons explained above, including continuous gas evolution and contamination of other substrates and downstream processing equipment and metrology tools.

[0111] PDB processing can involve a combination of heat treatment, optional chemical exposure, optional plasma exposure, and optional light exposure (discussed further in relation to block 116) to reduce the potential for metal and metal halides to emit gas during downstream processing. The heat treatment involves exposing the substrate to an elevated temperature. For example, the substrate can be baked at a temperature of about 160 - 300 °C for a duration of about 1 - 10 minutes. In some cases, the temperature can be maintained at about 160 - 250 °C, or about 160 - 220 °C. Such a bake can involve heating the substrate support, the processing chamber, the showerhead, and / or the processing gas. In some cases, the walls of the processing chamber can be heated and / or maintained at an elevated temperature. An example temperature for the chamber walls can be about 20 - 120 °C. In some cases, the pressure during PDB processing can be maintained at a minimum of about 0.01 torr or 0.1 torr, and a maximum of about 1 torr, 10 torr, or atmospheric pressure (e.g., about 760 torr). Example processing gases that can be provided to the processing chamber during PDB processing include, but are not limited to, N2, a mixture of N2 / O2, He, Ar, Xe, H2, chlorine-containing gases, fluorine-containing gases, oxygen-containing gases, and combinations thereof. Example chlorine-containing gases, fluorine-containing gases, and oxygen-containing gases are discussed below. An example flow rate is about 200 - 10,000 sccm.

[0112] PDB processing desorbs physically adsorbed metal halide species (e.g., in various embodiments, SnBr x and / or other tin halides or metal halides) from the substrate surface. However, PDB processing can be ineffective in completely removing metal halide species from relevant portions of the substrate (e.g., the backside and bevel edge regions), and chemisorbed halide species (e.g., metal halide species) can remain on the substrate after PDB processing. Furthermore, the metal-containing photoresist on the front side of the substrate continues to be a source of further gas emission and associated contamination. In various embodiments, the remaining chemisorbed species / contamination can be removed in the wet cleaning operation described below in block 118.

[0113] In some embodiments, the PDB process is a heat treatment that does not involve exposing the substrate to reactive chemistry Substance or plasma. If reactive chemistry Substance or plasma is not used in connection with the PDB process at block 114, the use of the pumping and purge sequences described above is particularly beneficial in reducing contamination on the substrate. In embodiments where the PDB process is a heat treatment and no further cleaning steps are used (e.g., blocks 116 and 118 are omitted), outgassing can still be a problem over longer time frames, such as several days. In such embodiments, the queue time for a particular substrate after the substrate has been exposed to the PDB process at block 114 and before the substrate is used for further processing can be controlled using, for example, a maximum queue time of about 1 day, about 2 days, about 3 days, or about 5 days. Such control of the queue time limits the amount of outgassing / recontamination that occurs from each substrate, thereby limiting contamination on the substrate, nearby substrates, and downstream processing equipment and metrology tools. Without wishing to be bound by theory or mechanism of action, the mechanism of recontamination is thought to be a surface hopping or diffusion mechanism. Additional pump purge sequences, as well as queue time control, can limit such recontamination. Of course, such techniques are particularly beneficial in embodiments where the substrate is not subjected to further cleaning after the PDB process, but it should be understood that pump purge sequences, as well as queue time control, can also be used in other embodiments where further cleaning steps are used. Further, such pump purge sequences can be implemented at any time during the method of FIG. 1, in connection with operations, for example, at blocks 112, 114, and / or 116.

[0114] In some embodiments, the PDB process of block 114 subjects the substrate to reactive chemistry, as described in connection with block 116 Substancemay involve exposure to plasma and / or light. In some other embodiments, the operations described in connection with block 116 may occur after the PDB processing of block 114. As described above, the PDB processing of block 114 may also overlap with the photoresist development step in block 112. As such, it should be understood that the operations of block 116 may also overlap with the operations of block 112. In other cases, after the operations of blocks 112 and / or 114 are completed, the substrate may be, for example, within the same or a different processing chamber as the processing chamber in which the operations of blocks 112 and / or 114 occur, Operation of block 116 may be exposed to chemical processing, plasma processing, and / or light processing.

[0115] Block 116 optionally involves exposing the substrate to chemical processing, plasma processing, and / or light processing. Such processing may be combined as desired for a particular application. In some cases, this processing is intended to modify a metal-containing species (e.g., a metal or metal halide) to make it more volatile, thereby enabling the metal-containing species to be removed from the substrate and the processing chamber by a vacuum connection. Such processing benefits from relatively high temperatures and low pressures (e.g., may involve one or more purges) to facilitate the removal of volatile species.

[0116] One technique for achieving such increased volatility is to expose the substrate to a chlorine-containing chemical Substance (e.g., one or more of BCl3, Cl2, HCl, SiCl4, SOCl2, and PCl3). This technique is particularly beneficial when the photoresist is developed in block 112 using a bromine-based chemical such as HBr. The chlorine-containing chemical in block 116 Substance SubstanceExposure of the substrate results in the formation of species that are more volatile than the contaminant species that were previously present (e.g., metals and metal bromides), such as metal chlorides. Another technique to achieve increased volatility is to expose the substrate to hydrogen (e.g., H2) at a relatively high temperature, such as at least about 200 °C, or at least about 250 °C. The chemical exposure can have a duration of from about 1 to 10 minutes. Increasing the volatility of the contaminant species facilitates the removal of the contaminant species from the substrate and the processing chamber. In various embodiments where the substrate is exposed to chemical processing, plasma processing, and / or optical processing, the processing chamber can be purged after processing (e.g., using the purge and / or pump purge sequences described above).

[0117] In some cases, the treatment of block 116 is intended to modify the metal-containing species so that it is more stable, thereby reducing the risk that such species will outgas and cause contamination. One technique for achieving such increased stability is to expose the substrate to an oxygen-containing chemical Substance (e.g., one or more of O2, O3, H2O, SO2, CO2, CO, COS, NO x (e.g., NO2, NO, and N2O, etc.), and H2O2 vapor) to form metal oxides from metal halides. Another technique for achieving increased stability is to expose the substrate to a fluorine-containing chemical Substance (e.g., one or more of HF, C x F y H z , NF3, SF6, and F2) to form metal fluorides from other metal halides such as metal bromides or metal chlorides. Other chemicals that can be used to promote the stability of the metal-containing species include, but are not limited to, NH3 (particularly useful at high temperatures such as above about 200 °C), HI, and I2. Substance

[0118] ​In certain implementations where block 116 involves chemical processing, the process gas can flow at a rate of about 200 to 10,000 sccm. An exemplary exposure time is about 1 to 10 minutes. An exemplary temperature (e.g., of one or more of the substrate support, chamber, showerhead, process gas, etc.) can be about 20 to 150 °C.

[0119] In various embodiments, the processing of block 116 involves exposing the substrate to plasma. The plasma treatment can act to suppress gas emission and related contamination mechanisms. In many cases, the plasma is a remotely generated plasma delivered to the processing chamber. In other cases, a DC plasma can be generated in-situ with the substrate. The plasma is generated from a plasma generating gas. For example, H2, N2, Ar, He, Kr, Xe, CH4, oxygen-based gases (e.g., O2, O3, CO, CO2, COS, SO2, NO x , H2O), fluorine-based gases (e.g., NF3, C x F y (e.g., CF4, etc.), C x H y F z(e.g., CH3F3, CH2F2, CHF3, etc.), F2, SF6), chlorine-based gases (e.g., one or more of BCl3, Cl2, HCl, SiCl4, SOCl2, and PCl3), and hydrogen halides (e.g., HBr, HI, etc.). In some specific embodiments, the plasma generating gas can include a mixture of H2 / N2, a mixture of H2 / Ar, a mixture of H2 / He, a mixture of H2 / Kr, a mixture of H2 / Xe, a mixture of H2 / CH4, a mixture of CH4 / O2, a mixture of one or more oxygen-based gases and an inert gas, a mixture of one or more fluorine-based gases and an inert gas, or a mixture of one or more chlorine-based gases and an inert gas. An example flow rate for the plasma generating gas can be about 50 to 10,000 sccm. In some cases, the flow rate is at least about 100 sccm. In these or other cases, the flow rate can be about 5,000 sccm or less. In some cases where an oxygen-containing plasma is used, the duration of plasma exposure can be particularly short (e.g., about 1 to 30 seconds, or about 1 to 5 seconds) to prevent the oxygen-containing plasma from attacking any exposed carbon-based materials such as a carbon-containing underlayer, and is sometimes referred to as a flash.

[0120] During the plasma treatment of block 116, the pressure in the processing chamber can be maintained as low as about 5 mTorr and as high as about 10 Torr. In some cases, the pressure is, for example, about 5 - 300 mTorr in embodiments where the processing chamber includes or is in fluid communication with a turbopump. In some cases, the pressure is, for example, about 100 mTorr to about 10 Torr in embodiments where the processing chamber is or includes a rough pump. The higher the pressure (e.g., 100 mTorr - 10 Torr), the more beneficial it can be to minimize damage to the substrate as a result of plasma exposure. In some cases where the plasma treatment is targeted at passivating contaminant species, a relatively higher pressure, for example, about 0.1 - 10 Torr, or about 0.1 - 5 Torr can be used. The substrate can be exposed to the plasma for a duration of about 1 - 120 seconds. The plasma can be generated at one or more frequencies, for example, a low frequency of about 13.6 kHz and a high frequency of about 10 MHz. Other frequencies such as, for example, 400 kHz, 1 MHz, 2 MHz, 27 MHz, 60 MHz, etc. can also be used. For example, if the plasma is transformer-coupled plasma or capacitively coupled plasma generated in-situ, the plasma can be generated using about 50 - 300 W of RF power. If the plasma is generated remotely using, for example, a microwave plasma source in a microwave stripline chamber, the plasma can be generated at these powers or even higher powers (e.g., about 3000 W or less, and in some cases, about 1000 - 3000 W). The duty cycle of the plasma (e.g., TCP plasma) can be about 10% - 100% CW.

[0121] In some cases, for example, when the plasma is generated in-situ (e.g., TCP or CCP), the pressure can be about 5 to 300 mTorr, the temperature of the processing chamber, showerhead, substrate support, etc. can be about 20 to 140 °C, and the plasma can be generated with about 50 to 300 W of RF power. In some other cases, for example, when the plasma is generated remotely (e.g., in a microwave stripline chamber sometimes referred to as MWS), the pressure can be from a minimum of about 100 mTorr to a maximum of about 10 Torr or 1 Torr, the temperature of the processing chamber, showerhead, substrate support, etc. can be about 100 to 300 °C, and the plasma can be generated with about 500 to 3000 W of power.

[0122] In various embodiments where the plasma is generated remotely, the following conditions can be used. The pressure in the processing chamber is maintained at about 0.1 to 1 Torr, the process gas is flowed at a rate of about 50 to 5000 sccm, the substrate is exposed to the remote plasma for a duration of about 3 to 30 seconds, and the remote plasma is generated from a hydrogen-containing gas (e.g., H2, or H2 combined with one or more of N2, Ar, He, Kr, or Xe). Example power levels, frequencies, and other plasma generation conditions are further discussed above and below.

[0123] In some cases, plasma treatment can facilitate the removal of metal or metal halide species. In some such cases, plasma treatment can modify contaminant species to form more volatile species. In other cases, plasma treatment can facilitate the formation of more stable species from metal or metal halide species. As explained above, the formation of more volatile species can reduce gas emissions / contamination by removing contaminant species from the substrate / chamber, while the formation of more stable species can reduce gas emissions / contamination by reducing the likelihood that such species can volatilize during downstream processing or queue time.

[0124] In various implementation forms, the plasma generation gas contains at least H2 (for example, in some cases, H2 / N2, H2 / Ar, H2 / He, etc.). The addition of gentle H2 plasma treatment enables the reduction of the amount of chemisorbed metal halides (for example, in some cases, tin bromide) on the back side and the bevel edge region of the substrate. This enables an increased maximum queue time after processing before the substrate is used for further processing. The maximum queue time is based on the rate at which the contaminant species is releasing gas and the maximum allowable concentration of the contamination. In some cases, the exposure of the substrate to the plasma generated from H2 / N2 or H2 / inert gas, in conjunction with the wet cleaning operation described below in relation to block 118, provides a metal concentration (for example, on the back side and the bevel edge region of the substrate) of about 1E10 atoms / cm 2 as follows. Such results are highly desirable. Furthermore, it has been shown that such treatment can achieve these results without causing undesirable damage to the photoresist pattern and other materials on the front side of the substrate.

[0125] In some implementation forms, the plasma generation gas contains at least one oxygen-containing species such as those described above. The oxygen-containing species can react with the metal or metal halide to form metal oxides. In some implementation forms, the plasma generation gas contains at least one fluorine-containing species such as those listed above. The fluorine-containing species can react with the metal or metal halide (for example, in some cases, metal bromide) to form metal fluorides. The metal oxides and metal fluorides may be more stable than the previously existing contaminant species, thereby reducing the risk of gas release and related contamination.

[0126] In various embodiments, the processing at block 116 involves exposing the substrate to light. The duration of the light exposure can be from about 1 to 120 seconds. In some cases, the light is provided as part of a rapid thermal annealing that exposes the substrate to a relatively high temperature (e.g., about 250 - 400 °C) over a relatively short time period (e.g., about 60 seconds or less). In certain cases, a similar rapid thermal annealing process can be provided without substantial light exposure. The light can be provided by a lamp or an assembly of LEDs, either of which can provide light at UV wavelengths, visible wavelengths, and / or IR wavelengths. In some specific cases, a lamp that provides UV light is used. In these or other cases, an LED that provides visible light is used. The LED can be provided within the substrate support or other structures. In some cases, the light exposure can occur using a module dedicated to such exposure. In other cases, the light exposure can occur within a processing chamber that is also used for other purposes such as one or more operations within FIG. 1. In various embodiments, the light exposure at block 116 can be performed using the LUMIER™ module available from Lam Research of Fremont, CA. In some cases, the PDB processing at block 114 can similarly be generated using such a module. Other apparatuses can also be used.

[0127] Returning to the embodiment of FIG. 1, the method continues at block 118, where a wet clean is performed to remove contamination from the backside and bevel edge regions of the substrate. Generally, the details provided above in connection with the wet clean at block 104 can also apply to the wet clean at block 118. While the wet clean at block 104 targets contamination that occurs during the deposition of the photoresist at block 102, the wet clean at block 118 Of block 112 targets contamination that occurs during the development of the photoresist.

[0128] In some embodiments, the wet cleaning at block 118 involves exposing the relevant portion of the substrate to one or more of dilute HF, dilute HCl, or standard clean 1 (SC-1, a mixture of NH4OH:H2O2:H2O). In many cases, a two-step wet cleaning process is used, where the first step involves exposing the substrate to dilute HF and the second step involves exposing the substrate to standard clean 1 or dilute HCl. Dilute HF can be up to about 49% (by weight) HF, which corresponds to commercially available HF solutions. This solution can be diluted, for example, with water to up to about 1:1000 (by volume). Dilute HCl can be up to about 4% (by weight) HCl and can be diluted with water to up to about 1:100 (by volume) and in some cases up to about 1:10 (by volume). Each wet cleaning step can have a duration of about 20 to 300 seconds. The substrate, and / or the solution used to process the substrate, can be maintained at a temperature of about 15 to 60°C. An example flow rate for this solution can be about 1 to 3 L / min.

[0129] The experimental results shown in the accompanying figures illustrate that the wet cleaning process is very effective in reducing the concentration of metal / metal halides on the back side of the substrate, thus preventing such metals from outgassing and causing contamination problems. The wet cleaning process is particularly effective when combined with one or more of the optimizations described in connection with photoresist development at block 112, one or more of the bake strategies described in connection with the PDB process at block 114, and / or one or more of the process strategies described in connection with block 116.

[0130] Another technique that can be used to minimize metal gas evolution and contamination involves periodically cleaning the processing chambers used to process the substrates. As described above, the various operations illustrated in FIG. 1 can be implemented in one or more apparatuses, each of which includes a processing chamber. Any or all of these processing chambers must be periodically cleaned to remove metal-containing contaminants from the inner surface of the processing chamber. Such chamber cleaning helps reduce the redeposition of contaminant species onto the substrates to be processed later. In some cases, the chamber cleaning can be at a frequency of once per substrate. For example, the chamber can be cleaned after each substrate is processed. In other cases, this frequency can be less, for example, every two substrates, every five substrates, or every ten substrates. Different processing chambers can benefit from different frequencies of cleaning depending on the processes occurring within the associated chamber. A method for dry chamber cleaning is further discussed in PCT Application No. PCT / US2020 / 070187, filed Jun. 25, 2020, which is hereby incorporated by reference in its entirety.

[0131] In various embodiments, cleaning the associated processing chamber involves exposing the chamber to a gas chemistry that provides H radicals Substance and / or a plasma. The H radicals react with the metal to form, for example, metal hydrides. In a particular example, the metal is tin, and the exposure of the chamber to the plasma results in Sn x H yresults in the formation of species. Chamber cleaning typically occurs without a substrate present within the chamber in order to avoid damaging the substrate and the materials thereon. In some cases, the cleaning occurs automatically and may be referred to as a waferless auto cleaning process (WAC). The chamber pressure during chamber cleaning can be from about 0.1 to 10 Torr, for example, from about 0.3 to 9 Torr. The pressure can be varied between multiple pressures while the process gas is being supplied. In some cases, the pressure is varied between a lower pressure (e.g., about 1 Torr or less, in some cases about 0.5 Torr) and a higher pressure (e.g., about 5 Torr or more, in some cases about 9 Torr). The pressure can be varied as part of a pump and purge sequence. Exemplary process gases can include, but are not limited to, H2, other hydrogen-containing species that generate H radicals, N2, O2, N2+O2, Ar, and other inert gases. In some cases, the chamber is cleaned without exposure to plasma. In other cases where plasma is used, the plasma can be generated remotely and delivered to the chamber being cleaned, or it can be generated directly in-situ within the chamber being cleaned. In some embodiments, the plasma is generated from a mixture of CH4 and O2 or NH3 and O2. The plasma is at about 13.56 kHz low frequency and / or about 10 MHzIt can be generated at one or more frequencies, such as high frequencies. For example, other frequencies such as 400 kHz, 1 MHz, 2 MHz, 27 MHz, 60 MHz, etc. can also be used similarly. The plasma can be generated using RF power of about 300 - 4000 W. The plasma can have a duty cycle of about 10% - CW. The processing chamber, substrate support, shower head, etc. can be maintained at a temperature of about 25 - 220 °C during cleaning. In some embodiments, while the chamber is being cleaned, one or more specific heat sources can be used to heat one or more of the processing chamber, substrate support, shower head, etc. For example, in some cases, an IR heat source can be used. In these or other embodiments, an LED chuck / substrate support can be used. Other heat sources can be used where appropriate.

[0132] In some cases, for example, when the plasma is generated in-situ (e.g., TCP or CCP), the pressure can be about 5 - 300 mTorr, the temperature of the processing chamber, shower head, substrate support, etc. can be about 20 - 140 °C, and the plasma can be generated with RF power of about 50 - 300 W. In some other cases, for example, when the plasma is generated remotely (e.g., in an MWS or other remote plasma chamber), the pressure can be about 100 mTorr - about 10 Torr, the temperature of the processing chamber, shower head, substrate support, etc. can be about 100 - 300 °C, and the plasma can be generated with power of about 1000 - 4000 W, for example, about 1000 - 3000 W.

[0133] In some other embodiments, a dry cleaning process such as that described above in relation to block 104 can be used instead of or in addition to the wet cleaning process in block 118.

[0134] In many cases, the substrate processed using the techniques described herein provides a metal concentration of about 1E11 atoms / cm2 or less, e.g., about 1E10 atoms / cm2 or less, on the back side and / or the bevel edge region of the substrate. In various embodiments, the techniques described herein can be used to reduce the concentration of metal on the back side and / or the bevel edge region of the substrate to a level that is one, two, or even three orders of magnitude lower than would be achieved separately without such techniques (e.g., the development operation in block 112 is conventional dry development and the operations in blocks 114, 116, and 118 are omitted). In some cases, the operations described in blocks 114, 116, and 118 operate to reduce the concentration of metal on the back side and / or the bevel edge region of the substrate as compared to the concentration that exists after the development step in block 112.

[0135] In some cases, existing apparatuses can be modified to perform one or more of the processes described herein. For example, an apparatus used to develop a photoresist (e.g., using dry or wet techniques) can be modified to include any one or more of the following features: (1) a substrate support configured to reach the temperature increase described herein, (2) piping for providing a suitable gas for processing the substrate by chemical or plasma treatment, (3) a plasma generator configured to provide plasma to the processing chamber, (4) one or more light sources configured to provide UV, visible, and / or IR radiation onto the substrate, and / or (5) a controller configured to cause any of the methods described herein. Similarly, an apparatus used to bake a substrate can be modified to include any one or more of these features.

[0136] Referring to FIG. 1, in some embodiments, the photoresist is developed at block 112 in a first processing chamber, the PDB process is performed at block 114 in a second processing chamber, the chemical, plasma, and / or optical processing at block 116 is performed in a third processing chamber, and the wet cleaning is performed in a fourth processing chamber. In other embodiments, some of these steps are combined within a single processing chamber. For example, developing the photoresist at block 112 and performing the PDB at block 114 can occur in a first processing chamber, the processing at block 116 can occur in a second chamber, and the wet cleaning can occur in a third chamber. In another embodiment, developing the photoresist at block 112, performing the PDB at block 114, and performing the processing at block 116 all occur in a first chamber, and the wet cleaning at block 118 occurs in a second chamber. The chamber used to perform the PDB at block 114 can be the same as or different from the chamber used to perform the PAB at block 106 and / or the PEB at block 110. In various embodiments, any two or more of the chambers described herein can be combined within a multi-chamber apparatus / tool that serves multiple purposes. Appropriate substrate handling facilities, load locks, etc. can be provided to transfer the substrate between chambers as needed. Further, a controller can be provided to control the process operations as described herein. In certain embodiments, the multi-chamber apparatus includes at least one chamber configured for dry processing (e.g., to perform one or more of the operations at blocks 112, 114, and 116, e.g., vapor-based / plasma-based processing), and at least one chamber configured for wet processing (e.g., to perform the cleaning operation at block 118).

[0137] Figures 2A - 2D show schematic cross - sectional views of various processing stages of back - side and bevel edge cleaning using wet cleaning techniques. These techniques can be used in conjunction with, for example, the wet cleaning techniques described in connection with blocks 104 and 118.

[0138] As shown in Figure 2A, EUV resist material can be deposited on the front side, back side, and bevel edges of the substrate. As described above, such deposition can occur through wet spin - on techniques or dry vapor / plasma - based techniques. The EUV resist material deposited on the back side and bevel edges, as well as associated metal and metal halide contamination, increase the potential for contamination on the front side of the substrate and downstream tools. Such EUV resist material and metal - containing contamination are undesirable. It is desirable to remove the EUV resist material and metal - containing contamination from the back side and bevel edges of the substrate. In some cases, it is desirable to remove any EUV resist material or other metal - containing contamination deposited on the front side of the substrate, including the EUV resist material deposited on the peripheral portion of the front side of the substrate.

[0139] As shown in Figure 2B, the unwanted material deposited on the bevel edge of the substrate is removed by wet bevel edge cleaning. In a standard edge bead removal process, an organic solvent such as PGME, PGMEA, or 2 - heptanone is dispensed to remove the EUV resist material deposited on the bevel edge within the first processing chamber (chamber 1). The first processing chamber can be a spin - cleaning tool. The organic solvent can be dispensed at a low - temperature / mild temperature such as about 20°C. Any heating of the flammable solvent poses a significant fire / explosion hazard. The substrate optionally undergoes a rinse / dry operation before proceeding to the second processing chamber (chamber 2).

[0140] As shown in FIG. 2C, unwanted materials deposited on the back side of the substrate are removed by wet backside cleaning. The wet backside cleaning can be performed in a second processing chamber. The second processing chamber can be another spin cleaning tool capable of cleaning the back side of the substrate. For example, the wet backside cleaning can use a cleaning agent such as dHF, dHCl, dilute sulfuric acid, or SC-1. The cleaning agent can be dispensed at a low / moderate temperature such as about 20° C. The wet backside cleaning can also remove materials on the bevel edge region, but it is typically inefficient in achieving uniform or complete removal of materials on the bevel edge region. Thus, the backside cleaning and the bevel edge cleaning are sometimes separated into a first processing chamber and a second processing chamber. The substrate undergoes a rinse / dry operation before proceeding to a third processing chamber (chamber 3).

[0141] As shown in FIG. 2D, the substrate is transferred to a third processing chamber for an optional PAB heat treatment. In some embodiments, the third processing chamber is an oven or includes a hot plate, whereby the substrate is exposed to a temperature increase. The PAB heat treatment increases the substrate temperature to a temperature increase such as about 90° C. to 200° C. This stabilizes the lithographic properties of the EUV resist on the front side of the substrate for EUV exposure. The PAB heat treatment is a dry process.

[0142] In contrast to wet backside and bevel edge cleaning techniques, dry backside and bevel edge cleaning techniques can be less expensive and more environmentally safe. The dry backside and bevel edge cleaning techniques can integrate chambers, and as a result, the dry processing steps can be performed in fewer tools / chambers. The dry backside and bevel edge cleaning techniques can address the non-uniformity issues associated with wet backside and bevel edge cleaning techniques.

[0143] In some cases, dry backside and bevel edge cleaning techniques use plasma to remove material from the backside and bevel edges of a substrate. Existing hardware may limit the plasma to the backside and bevel edges of the substrate to remove material. In some other cases, dry backside and bevel edge cleaning can be achieved without applying plasma. For example, dry backside and bevel edge cleaning utilizes an etching gas that is limited to a specific region of the substrate to remove material (e.g., EUV resist material) from the backside and bevel edges of the substrate. Dry backside and bevel edge cleaning exposes the substrate to elevated temperatures to facilitate non-selective removal of material at the backside and bevel edges.

[0144] Figures 3A - 3C show cross-sectional schematic views of various processing stages of dry backside and bevel edge cleaning of a photoresist material according to some embodiments. Deposition of the photoresist material (e.g., EUV resist material) can be performed using wet or dry deposition techniques. Wet deposition techniques include spin coating. Dry deposition techniques include chemical vapor deposition (CVD) or atomic layer deposition (ALD).

[0145] As shown in FIG. 3A, EUV resist materials as well as associated metal and metal halide contamination can be deposited on the front side, back side, and bevel edges of the substrate. The unwanted materials deposited on the back side and bevel edges increase the potential for contamination on the front side of the substrate and downstream tools. It is desired to remove the unwanted materials from the back side and bevel edges of the substrate. In some cases, it is desired to remove any unwanted materials deposited on the front side of the substrate, including EUV resist materials as well as associated metal and metal halide contamination deposited on the peripheral portion of the front side of the substrate. For example, it may be desired to remove the unwanted materials from about several millimeters from the edge (e.g., about 1.5 mm) on the front side. In some embodiments, the EUV resist material is an organometallic-containing resist material or an organometallic oxide. The EUV resist material may include elements selected from the group consisting of tin, hafnium, tellurium, bismuth, indium, antimony, iodine, and germanium. The unwanted metal or metal halide contamination can result from the reaction of the metal in the EUV resist material with halogen-based chemistry Substance and. The metal in the EUV resist material can have a high patterning radiation absorption cross section. In some embodiments, this element can have a high EUV absorption cross section. In some embodiments, the EUV resist material can generally consist of Sn, O, and C. For example, the EUV resist material includes organotin oxide.

[0146] As shown in FIG. 3B, the EUV resist material deposited on the back side and the bevel edges of the substrate is removed by dry cleaning. Dry cleaning can expose the back side and bevel edges of the substrate to an etching gas. In some embodiments, the etching gas is hydrogen halide, hydrogen gas, a mixture of hydrogen gas and halide gas, or boron trichloride (BCl3). In one example, the etching gas is a hydrogen halide such as HCl, HBr, or HI. In another example, the etching gas is hydrogen gas (H2). In yet another example, the etching gas is a mixture of H2 and Cl2, Br2, or I2. In still yet another example, the etching gas is BCl3. Although the present disclosure is not limited to any particular theory or mechanism of operation, in some cases, the present approach utilizes the chemical reactivity of the EUV photoresist material and associated contaminants with cleaning chemistry Substance (e.g., HCl, HBr, HI, H2 and Cl2, Br2, or I2, BCl3) to form volatile products using vapor. The EUV resist material and associated contaminants can be processed and / or removed using vapor and / or plasma at various temperatures. It is believed that the higher the temperature, pressure, and / or reaction stream, the more the reactivity can be accelerated or enhanced. In some embodiments, the EUV resist material and / or associated contaminants can be removed at an etching rate of up to 1 nm / second. In some embodiments, the etching gas is activated by a remote plasma source. This can further accelerate or enhance the reactivity. In some embodiments, the etching gas is delivered with a carrier gas such as argon, helium, nitrogen, or other suitable carrier gas.

[0147] In some embodiments, the photoresist material is not an EUV resist material, but rather a silicon-based or carbon-based material. The etching gas for removing such materials can be different from that for removing EUV resist materials. In some embodiments, the etching gas includes oxidation gases such as O2, CO2, N2O, and the like for removing carbon-based materials. In some embodiments, the etching gas is C x F y or C x F y H z and the like, fluorine-based gases, or chlorine-based gases.

[0148] The inert curtain gas can be delivered to the front side of the substrate to confine the etching gas to the back side and the bevel edges of the substrate. The curtain gas can include gases such as nitrogen (N2), oxygen (O2), water (H2O), argon (Ar), helium (He), xenon (Xe), neon (Ne), or mixtures thereof. The curtain gas is flowed over the front side of the substrate to protect at least the central region of the front side of the substrate from the etching gas. When the curtain gas is flowed over the front side, the curtain gas spreads across the front side to protect the EUV resist material deposited on the front side.

[0149] Curtain gas can be flowed simultaneously with the etching gas. A first etching gas flow can be introduced to the back side of the substrate. The first etching gas flow can spread across the back side of the substrate, and the back side of the substrate can be accessible when the substrate is supported by an MCA support on a carrier ring. In some embodiments, a second etching gas flow can be introduced to the peripheral portion of the front side of the substrate. The second etching gas flow can flow along the peripheral portion of the front side and can wrap around the bevel edge of the substrate. The first etching gas flow can be introduced from one or more lower gas inlets positioned under the substrate support, and the second etching gas flow can be introduced from one or more peripheral gas inlets of a gas distributor positioned above the substrate support. The gas distributor can include a modular ring having one or more peripheral gas inlets. The modular ring can adjust the space between one or more peripheral gas inlets and the front side of the substrate. In some embodiments, the curtain gas is flowed from one or more central gas inlets of the gas distributor, and a first gap separating one or more peripheral gas inlets from the front side is larger than a second gap separating one or more central gas inlets from the front side.

[0150] The substrate can be heated to a temperature increase during dry cleaning, and the temperature increase is about 20°C to about 170°C, about 20°C to about 140°C, about 40°C to about 140°C, or about 100°C. In some embodiments, the dry cleaning can be performed at an elevated pressure. The pressure in the processing chamber can be about 0.02 torr to atmospheric pressure, 0.1 torr to atmospheric pressure, or about 1 torr to atmospheric pressure. In some embodiments, the dry cleaning can be performed using a high flow rate of etching gas. The etching gas flow rate can be about 50 sccm to about 10,000 sccm, about 100 sccm to about 10,000 sccm, or about 200 sccm to about 5,000 sccm. Different from wet cleaning techniques, the non-plasma thermal cleaning technique of the present disclosure can adjust process parameters such as temperature, pressure, and gas flow rate to control the etching rate. A high etching rate can be achieved to remove non-exposed EUV resist material using higher temperature and / or pressure and flow rate.

[0151] Both backside cleaning and bevel edge cleaning are performed not in separate processing chambers but within a first processing chamber (Chamber 1). This reduces the potential for tool contamination that could occur between cleaning operations. A single path can be implemented for essentially multiple process steps within a single tool. This also reduces costs and increases throughput. Wet cleaning or rinse / dry operations are not performed in the dry backside and bevel edge cleaning of the present disclosure.

[0152] In some embodiments, dry backside and bevel cleaning includes exposure to an etching gas followed by a purge. The purge introduces a purge gas to pump / purge residual etching gas from the first processing chamber. It should be understood that the purge can be useful for removing residual etching gas or etching by-products from the processing chamber to avoid unwanted etching of the front side of the substrate during substrate transfer. The purge can flow an inert gas and / or a reactive gas. The reactive gas can react with the residual etching gas to facilitate ease of removal. The reactive gas can be, for example, a tin-based precursor such as an organotin precursor. The inert gas can be Ar, He, Ne, Xe, or N2. The chamber pressure can be from about 0.1 Torr to about 6 Torr. The purge gas flow can be from about 10 sccm to about 10000 sccm, or from about 50 sccm to about 5000 sccm. In some embodiments, the pumping / purging can be carried out at an elevated temperature such as from about 20 °C to about 140 °C or from about 80 °C to about 120 °C. The elevated temperature can facilitate removal of residual etching gas from the first processing chamber. In some embodiments, the chamber walls and other components can be heated to release residual etching gas. The residual etching gas (e.g., a halide gas or a halide-containing gas) can be exhausted through an exhaust line during the pumping / purging. In some embodiments, the pump / purge operation can also be referred to as dehalogenation. Halide compounds can readily adhere to the chamber walls, chamber components, or wafers. When the halide adheres to the wafer, the halide (e.g., bromine) is released from the wafer during EUV scanning, thereby increasing the risk of corroding or damaging the scanner.

[0153] In some embodiments, the duration of the dry backside and bevel cleaning is from about 10 seconds to about 150 seconds. In some embodiments, the endpoints of the backside and bevel cleaning are detected by one or more sensors. The one or more sensors are for the EUV resist deposited on the backside and bevel of the substrate Presence or absencecan be detected. One or more sensors may include an IR sensor and / or an optical sensor.

[0154] As shown in FIG. 3C, the substrate is exposed to an optional PAB heat treatment. In some embodiments, the PAB heat treatment is performed in the same processing chamber (i.e., the first processing chamber) as the dry backside and bevel edge cleaning. In such a manner, the dry backside and bevel edge cleaning are integrated with the PAB heat treatment. This can further reduce the potential for contamination, reduce costs, and increase throughput. This may have a minimal or beneficial impact on lithography performance. In some embodiments, the PAB heat treatment is performed in a second processing chamber (chamber 2) different from the dry backside and bevel edge cleaning. The PAB treatment is a dry treatment.

[0155] The PAB heat treatment raises the substrate temperature to a temperature increase such as from about 100°C to about 170°C or from about 120°C to about 150°C. In some embodiments, the substrate temperature can be controlled using a radiant heat source such as an IR lamp or one or more LEDs. The radiant heat source can be positioned under the substrate. Alternatively, the radiant heat source can be positioned above the substrate. The substrate temperature can be actively controlled by a thermometer within a feedback control loop established with the radiant heat source. The atmosphere during the PAB heat treatment can be controlled by flowing an inert gas such as N2, Ar, He, Xe, or Ne, and the inert gas can be mixed with O2 and / or H2O. The flow rate of the inert gas can be from about 10 sccm to about 10000 sccm, or from about 50 sccm to about 5000 sccm. The pressure during the PAB heat treatment can be controlled to be from about 0.02 torr to atmospheric pressure, from about 0.1 torr to atmospheric pressure, or from about 1 torr to atmospheric pressure.

[0156] Device The present disclosure provides various hardware implementations for achieving the methods described herein. In many cases, two or more operations described in FIG. 1 can occur within the same processing chamber. In various embodiments, at least two processing chambers are provided, one configured to perform a dry process and one configured to perform a wet process. Such chambers can be combined on a single tool as described herein.

[0157] FIG. 4 shows a schematic diagram of a processing chamber for performing dry backside and bevel edge cleaning according to some embodiments. An apparatus or tool for performing dry backside and bevel edge cleaning can include a processing chamber. The processing chamber can be integrated not only to perform both backside cleaning and bevel edge cleaning, but also to perform one or more additional dry processing techniques such as PAB process deposition, PEB process, EUV exposure, PDB process, chemical / plasma / optical processing, dry development, etc. The apparatus can include a substrate support within the processing chamber to support the substrate. In some embodiments, the substrate support can receive the substrate after deposition of material (e.g., EUV resist material) on the front side, back side, and bevel edges of the substrate. A plurality of minimum contact areas (MCAs) can be configured to extend from the major surface of the substrate support to lift the substrate so that the etching gas can access the back side of the substrate. The apparatus further includes a gas distributor on the substrate support, which is coupled to the processing chamber to deliver a curtain gas to the front side of the substrate. The apparatus further includes an etching gas delivery source under the substrate support, which is coupled to the processing chamber to deliver the etching gas to the back side of the substrate. The apparatus can further include a heat source, such as a radiant heat source, under the substrate support.

[0158] The substrate support may include a carrier ring. The carrier ring may have an annular shape for supporting the substrate. FIG. 5A shows a perspective view of a carrier ring for supporting a substrate in a processing chamber according to some embodiments. Substrates in the semiconductor industry typically have a diameter of 200 mm, 300 mm, or 450 mm. The outer diameter of the carrier ring is larger than the diameter of the substrate, and the inner diameter of the annular shape is smaller than the diameter of the substrate. The inner diameter may be about 280 mm or less, about 240 mm or less, or about 200 mm or less. In other words, the substrate may be gripped by a ring having a radius of about 140 mm or less. A plurality of MCA supports may extend from the major surface of the carrier ring to contact the back side of the substrate. In some embodiments, the plurality of MCA supports may be symmetrically arranged around the center of the carrier ring. For example, the plurality of MCA supports may include three MCA supports, four MCA supports, five MCA supports, six MCA supports, or more. The MCA support may be a pin. The plurality of MCA supports may include any suitable insulating material. The insulating material may be a soft material such as perfluoroalkoxy alkane (PFA) to avoid scratching the substrate. FIG. 5B shows a schematic cross-sectional view of a carrier ring that supports and contacts the back side of a substrate according to some embodiments.

[0159] The position of the MCA support may be optimized for a preceding deposition process to avoid contacting the substrate if the substrate has backside deposition. In other words, the plurality of MCA supports may be configured to contact regions on the back side of the substrate when there is little backside deposition (e.g., photoresist deposition). Such an arrangement may be determined based on knowledge or data ascertained from one or more previous deposition operations indicating little backside deposition. For example, the MCA support may contact the back side of the substrate in a region closer to the center of the substrate than to the edge of the substrate. At the same time, the position of the MCA support does not prevent the etching gas from accessing regions having backside deposition.

[0160] The plurality of MCA supports provide minimal contact with the back side of the substrate. The plurality of MCA supports can lift the substrate above the major surface of the carrier ring to a height that allows gas to flow to the back side of the substrate. In some embodiments, this height is from about 0.025 mm to about 0.5 mm or from about 0.05 mm to about 0.25 mm. In some embodiments, the MCA support is extendable / retractable from the major surface of the substrate support. In some embodiments, this height is adjustable so that the gap size is controlled. In some embodiments, the back side of the substrate is supported by an MCA support with a shift mechanism or a rotation mechanism so that the area where the MCA support directly touches and the substrate can be cleaned. The etching gas can be blocked by accessing the area in direct contact with the MCA support. This area is very small relative to the substrate, but it can still have unacceptably high metal contamination. Therefore, this area also needs to be cleaned as well. In other words, the MCA support can shift or rotate its position to contact different points on the back side of the substrate. The shift mechanism can be incorporated into the lift pins used during substrate transfer. After the first part of the cleaning that cleans the entire substrate except for the area where the MCA support touches, the carrier ring can lower the substrate onto the lift pins. The lift pins move the substrate approximately several tens of microns by a multiple of the MCA area. Then, the carrier ring returns to the process position, and the second cleaning is performed to clean the area where the MCA support first touches. In some embodiments, the back side of the substrate is supported by areas of the MCA support, and the carrier ring is divided into two or more areas for each of the X MCA supports, where X is any integer value. In this case, the cleaning process can be divided into several steps. Between each step, one or more of the split ring portions are moved away from the substrate surface to allow cleaning in that area. All areas must be lifted / cleaned at least once during cleaning. A minimum number of areas need to remain in place so that the substrate is securely held in the process position. For example, the carrier ring can be divided into two areas of three pins each.The carrier ring and the plurality of MCA supports can be configured in a manner that adjusts the etching gas flow on the back side of the substrate. Specifically, the height of the MCA supports, the inner diameter of the carrier ring, the positioning of the MCA supports, and other aspects of the carrier ring can be designed to regulate the gas flow between the curtain gas from above and the etching gas from below, ensuring that both the back side and the bevel edges are etched while a specific area on the front side of the substrate is not etched.

[0161] Returning to FIG. 4, the etching gas delivery source and the radiant heat source can be positioned below the substrate support (e.g., a carrier ring). The etching gas delivery source can include one or more lower gas inlets or nozzles for delivering etching gas to the back side of the substrate. The radiant heat source can be spaced from the back side of the substrate, but can heat the substrate to a temperature rise by radiant heating. The radiant heat source can provide controlled ramping capabilities, pulsing, and rapid temperature changes. In some embodiments, the radiant heat source includes one or more IR lamps or one or more LEDs. To enable rapid temperature changes, the heat source can be in the range of 1 to 10 kW. In some embodiments, the substrate support can be configured to rotate. For controllability of the substrate temperature, one or more IR lamps or one or more LEDs can be divided into zones for controlled heating of various regions of the substrate. Additionally, one or more lamps or one or more LEDs can each be independently controllable. By pulsing the LEDs, the temperature ramp-up of the wafer can be controlled. The radiant heat source can also serve to prevent stray light from reaching the front side of the substrate. In some embodiments, the etching gas delivery source includes one or more holes passing through the radiant heat source. In some embodiments, the etching gas delivery source includes one or more holes positioned outside the radiant heat source. The positioning of the one or more holes may not be important since non-uniformity of the etching gas flow on the back side of the substrate is not critical for material removal on the back side of the substrate. Thus, the etching gas delivery source can be positioned in any manner such that the etching gas can reach or otherwise access the back side of the substrate.

[0162] The gas distributor is positioned on the substrate support to deliver curtain gas to the front side of the substrate. The gas distributor may include one or more central gas inlets for directing the curtain gas flow towards the center of the front side of the substrate. In some embodiments, the gas distributor may include one or more peripheral gas inlets for directing the etching gas flow towards the periphery of the front side of the substrate. It should be understood that the periphery of the front side of the substrate may occupy an area of 15% or less, 10% or less, or 5% or less of the front side of the substrate. In some embodiments, the gas distributor includes a top plate, which includes a plurality of holes disposed in the central region of the top plate and a plurality of holes disposed in the peripheral region of the top plate. In some embodiments, the gas distributor includes modular rings of different diameters. In some cases, the modular rings may have different shapes. The etching gas may be delivered through one of the modular rings, and the curtain gas may be delivered through another of the modular rings. Thus, the gas distributor includes at least modular rings for one or more peripheral gas inlets, and at least one modular ring is configured to adjust the spacing of one or more peripheral gas inlets from the front side of the substrate. The removal at the bevel edge can be adjusted by adjusting the spacing of one or more peripheral gas inlets within the modular rings. Additionally or alternatively, the gas distributor includes one or more nozzles for directing the etching gas flow towards the bevel edge of the substrate.

[0163] The gas distributor can be configured such that a first gap separating one or more peripheral gas inlets from the front side of the substrate is larger than a second gap separating one or more central gas inlets from the front side of the substrate. In some embodiments, the first gap is at least twice as large as the second gap. The second gap may be as small as possible without touching the EUV resist film on the front side of the substrate. As shown in FIG. 4, the gas distributor can have a stepped design. In such a way, the curtain gas flow can be provided at a higher pressure and delivered across a smaller gap at the center of the substrate, and the etching gas flow can be provided at a lower pressure and delivered across a larger gap at the periphery of the substrate. The etching gas flow delivered from above the substrate support can be referred to as the "second etching gas flow", while the etching gas flow delivered from below the substrate support can be referred to as the "first etching gas flow". The second etching gas flow delivered at the periphery of the substrate can envelop portions of the front side and the bevel edge region of the substrate. For example, the etching gas flow can envelop 5 mm or less, 3 mm or less, or 1.5 mm or less of the front side of the substrate. The curtain gas flow prevents the etching gas from reaching the remainder of the front side of the substrate.

[0164] In addition to, or in place of, the radiant heat source, the apparatus can further include one or more heaters. The one or more heaters can provide substrate temperature control. In some embodiments, the one or more heaters are coupled to the gas distributor and on the substrate. The one or more heaters can be radiant heat sources. In some embodiments, the one or more heaters are configured to provide ambient heating within the processing chamber. In some embodiments, the one or more heaters provide substrate temperature control within a range of 20°C to 170°C or 20°C to 140°C, or other temperature ranges described herein.

[0165] The apparatus may further include one or more sensors for detecting the presence of film deposition on the back side and / or bevel edges of the substrate. In some embodiments, the one or more sensors include optical devices such as IR sensors that serve as endpoint detection.

[0166] FIG. 6 depicts a schematic view of an embodiment of a process station 600 having a process chamber body 602 for maintaining a low-pressure environment suitable for the described dry backside and bevel edge cleaning embodiments. A plurality of process stations 600 may be included in a general low-pressure process tool environment. For example, FIG. 7 depicts an embodiment of a multi-station process tool 700 such as a VECTOR® process tool available from Lam Research Corporation, Fremont, CA. In some embodiments, one or more hardware parameters of the process station 600, including those discussed in detail below, may be programmatically adjusted by one or more computer controllers 750 thereby.

[0167] The process station may be configured as a module within a cluster tool. FIG. 9 depicts a semiconductor process cluster tool architecture having a vacuum-integrated deposition and patterning module suitable for implementation of the embodiments described herein. Such a cluster process tool architecture may include a resist deposition module, a resist exposure module (EUV scanner), a resist development module, and an etching module, as described above and further described below with reference to FIGS. 8 and 9. Additionally, such a cluster tool architecture may include a process chamber configured to perform backside and bevel edge region cleaning using, for example, wet techniques for wet processing.

[0168] Returning to FIG. 6, process station 600 is in fluid communication with a reactant delivery system 601a for delivering process gas to a distribution showerhead 606. Reactant delivery system 601a optionally includes a mixing vessel 604 for mixing and / or conditioning the process gas for delivery to showerhead 606. One or more mixing vessel inlet valves 620 may control the introduction of process gas into mixing vessel 604. If plasma exposure is used, the plasma may also be delivered to showerhead 606 or generated within process station 600. As described above, in at least some embodiments, non-plasma thermal exposure is preferred.

[0169] FIG. 6 includes an optional evaporation point 603 for evaporating liquid reactants to be supplied to mixing vessel 604. In some embodiments, a liquid flow controller (LFC) upstream of evaporation point 603 may be provided to control the mass flow of liquid for evaporation and delivery to process station 600. For example, the LFC may include a thermal mass flow meter (MFM) located downstream of the LFC. At this time, the plunger valve of the LFC may be adjusted in response to a feedback control signal provided by a proportional-integral-derivative (PID) controller in electrical communication with the MFM.

[0170] Showerhead 606 distributes process gas toward substrate 612. In the embodiment shown in FIG. 6, substrate 612 is positioned directly below showerhead 606 and is shown riding on stage 608. Showerhead 606 may have any suitable shape and may have any suitable number and arrangement of ports for distributing process gas to substrate 612.

[0171] In some embodiments, stage 608 may be raised or lowered to expose substrate 612 to the volume between substrate 612 and showerhead 606. In some embodiments, the height of the stage is a suitable computer ControllerIt should be understood that it can be adjusted by a program. In some embodiments, the showerhead 606 may have a plurality of plenum volumes with multiple temperature controls. In some embodiments, the stage 608 may be replaced with a carrier ring for supporting the substrate 612.

[0172] In some embodiments, the stage 608 may be temperature-controlled by a heater 610. Alternatively, the substrate 612 supported by the carrier ring may be heated by a radiant heat source positioned below the substrate 612. In some embodiments, the substrate 612 is a dry backside and bevel edge cleaning chemistry such as HBr or HCl, as described in the disclosed embodiments. Substance During non-plasma thermal exposure of the resist to the chemistry, it can be heated to a temperature higher than 0°C and up to a maximum of 300°C or more, for example, about 65 - 80°C, such as 50 - 120°C. In some embodiments, the heater 610 of the stage 608 may include a plurality of independently controllable temperature control zones.

[0173] Furthermore, in some embodiments, the pressure control for the process station 600 may be provided by a butterfly valve 618. As shown in the embodiment of FIG. 6, the butterfly valve 618 throttles the vacuum provided by a downstream vacuum pump (not shown). However, in some embodiments, the pressure control of the process station 600 may also be adjusted by changing the flow rate of one or more gases introduced into the process station 600.

[0174] In some embodiments, a portion of the showerhead 606 can be adjusted relative to the pedestal 608 to vary the volume between the substrate 612 and the showerhead 606. Further, it should be understood that the vertical position of the pedestal 608 and / or the showerhead 606 can be varied by any suitable mechanism within the scope of the present disclosure. In some embodiments, the pedestal 608 can include a rotation axis for rotating the orientation of the substrate 612. In some embodiments, one or more of these exemplary adjustments can be implemented programmatically by one or more suitable computers Controller It should be understood that it can be implemented by a program by.

[0175] When plasma can be used, for example, in mild plasma-based dry cleaning embodiments and / or etching operations performed within the same chamber, the showerhead 606 and the pedestal 608 are in electrical communication with a radio frequency (RF) power source 614 and a matching network 616 to supply power to the plasma. In some embodiments, the plasma energy can be controlled by controlling one or more of the process station pressure, gas concentration, RF source power, RF source frequency, and plasma power pulse timing. For example, the RF power source 614 and the matching network 616 can be operated at any suitable power to form a plasma having radical species of a desired composition. An example of suitable power is up to about 500 W.

[0176] In some embodiments, Controller The instructions for can be provided by input / output control (IOC) sequencing instructions. In one example, the instructions for setting the conditions for a process phase can be included in the corresponding recipe phase of a process recipe. In some cases, the process recipe phases can be arranged sequentially such that all instructions for a process phase are executed simultaneously with that process phase. In some embodiments, the instructions for setting one or more reactor parameters can be included in the recipe phase. For example, the recipe phase can be a dry cleaning chemistry such as HBr or HClSubstance It may include instructions for setting the flow rate of the reactant gas and time delay instructions for the recipe phase. In some embodiments, Controller may include any of the features described below with respect to the system controller 750 of FIG. 7.

[0177] As described above, one or more process stations may be included within a multi-station processing tool. FIG. 7 shows a schematic diagram of an embodiment of a multi-station processing tool 700 having an inbound load lock 702 and an outbound load lock 704, and either or both of the inbound load lock 702 and the outbound load lock 704 may include a remote plasma source. A robot 706 at atmospheric pressure is configured to move a wafer from a cassette loaded through a pod 708 into the inbound load lock 702 via an atmospheric port 710. The wafer is placed on a stage 712 within the inbound load lock 702 by the robot 706, the atmospheric port 710 is closed, and the load lock is pumped down. If the inbound load lock 702 includes a remote plasma source, the wafer may be exposed to remote plasma treatment to treat the silicon nitride surface within the load lock before being introduced into the processing chamber 714. Additionally, the wafer may also be heated within the inbound load lock 702, for example, to remove moisture and absorbed gases. Next, the chamber transfer port 716 to the processing chamber 714 is opened, and another robot (not shown) places the wafer into the reactor onto the stage of the first station shown within the reactor for processing. It should be understood that the embodiment shown in FIG. 7 includes a load lock, but in some embodiments, direct access of the wafer into the process station may be provided.

[0178] The described processing chamber 714 includes four process stations numbered 1 to 4 in the embodiment shown in FIG. 7. Each station has a heated stage (shown as 718 in the case of station 1) and a gas line inlet. It should be understood that in some embodiments, each process station may have different or multiple purposes. For example, in some embodiments, the process station may be switchable between a dry cleaning process mode and a deposition process mode. Additionally or alternatively, in some embodiments, the processing chamber 714 may include one or more pairs of corresponding dry cleaning and deposition process stations. It should be understood that the described processing chamber 714 includes four stations, but the processing chamber according to the present disclosure may have any suitable number of stations. For example, in some embodiments, the processing chamber may have five or more stations, while in other embodiments, the processing chamber may have three or fewer stations.

[0179] FIG. 7 depicts an embodiment of a wafer handling system 790 for transferring wafers within the processing chamber 714. In some embodiments, the wafer handling system 790 may transfer wafers between various process stations and / or between a process station and a load lock. It should be understood that any suitable wafer handling system may be used. Non-limiting examples include a wafer rotary conveyor and a wafer handling robot. FIG. 7 also depicts an embodiment of a system controller 750 used to control the process conditions and the hardware state of the process tool 700. The system controller 750 may include one or more memory devices 756, one or more mass storage devices 754, and one or more processors 752. The processor 752 may include a CPU or computer, analog and / or digital input / output connections, a stepper motor control board, and the like.

[0180] In some embodiments, system controller 750 controls all of the activities of process tool 700. System controller 750 executes system control software 758 that is stored in mass storage device 754, read into memory device 756, and executed on processor 752. Alternatively, control logic may be hard-coded within controller 750. Application specific integrated circuits, programmable logic devices (e.g., field programmable gate arrays, or FPGAs), and the like may be used for these purposes. Whenever "software" or "code" is used in the following discussion, functionally equivalent hard-coded logic may be used therein. System control software 758 may include instructions for controlling timing, gas mixtures, gas flow rates, chamber and / or station pressures, chamber and / or station temperatures, wafer temperatures, target power levels, RF power levels, susceptor pedestal, chuck and / or susceptor positions, and other parameters of the particular processes performed by process tool 700. System control software 758 may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be described to control the operation of the process tool components used to perform various process tool processes. System control software 758 may be encoded in any suitable computer-readable programming language.

[0181] In some embodiments, system control software 758 may include input / output control (IOC) sequencing instructions for controlling the various parameters described above. Other computer software and / or programs stored in mass storage device 754 and / or memory device 756 associated with system controller 750 may be used in some embodiments. Examples of programs or program areas for this purpose include a substrate positioning program, a process gas control program, a pressure control program, a heater control program, and a plasma control program.

[0182] The substrate positioning program may include program code for process tool components used to load a substrate onto the stage 718 and to control the spacing between the substrate and other parts of the process tool 700.

[0183] The process gas control program may include code for controlling a halide-containing gas component (e.g., HBr or HCl gas as described herein) and flow rate, and optionally code for flowing gas into one or more process stations prior to deposition to stabilize the pressure within the process station. The pressure control program may include code for controlling the pressure within the process station, for example, by adjusting a throttle valve within the exhaust system of the process station, the gas flow into the process station, etc.

[0184] The heater control program may include code for controlling the current to a heating device used to heat the substrate. Alternatively, the heater control program may control the delivery of a heat transfer gas (such as helium) to the substrate.

[0185] The plasma control program may include code for setting the RF power level applied to a process electrode within one or more process stations according to embodiments herein.

[0186] The pressure control program may include code for maintaining the pressure within the reaction chamber according to embodiments herein.

[0187] In some embodiments, there may be a user interface associated with the system controller 750. The user interface may include a display screen, a graphical software display of device and / or process conditions, and user input devices such as a pointing device, keyboard, touch screen, microphone, etc.

[0188] In some embodiments, the parameters adjusted by the system controller 750 may relate to process conditions. Non-limiting examples include process gas composition and flow rate, temperature, pressure, plasma conditions (such as RF bias power level), etc. These parameters may be provided to the user in the form of a recipe that can be input using a user interface.

[0189] Signals for monitoring the process may be provided from various process tool sensors to the analog and / or digital input connections of the system controller 750. Signals for controlling the process may be output at the analog and digital output connections of the process tool 700. Non-limiting examples of process tool sensors that can be monitored include mass flow controllers, pressure sensors (such as pressure gauges), thermocouples, etc. Appropriately programmed feedback and control algorithms may be used with the data from these sensors to maintain process conditions.

[0190] The system controller 750 may provide program instructions for performing the deposition process described above. The program instructions may control various process parameters such as DC power level, RF bias power level, pressure, temperature, etc. The instructions may control the parameters to operate development and / or etching processes according to the various embodiments described herein.

[0191] The system controller 750 typically includes one or more memory devices and one or more processors configured to execute instructions to cause the apparatus to perform the methods according to the disclosed embodiments. A machine-readable medium containing instructions for controlling the process operations according to the disclosed embodiments may be coupled to the system controller 750.

[0192] In some embodiments, the system controller 750 may be part of a system that may be part of the examples described above. Such systems may include semiconductor processing equipment, including processing tool(s), chamber(s), platform(s) for processing, and / or specific processing components (such as wafer stages, gas flow systems). These systems may be integrated with electronic devices for controlling the operation of the system before, during, and after the processing of semiconductor wafers or substrates. The electronic device may be referred to as a "controller" that may control various components or sub-parts of the system(s). The system controller 750 may be programmed to control any of the processes disclosed herein, depending on process conditions and / or the type of system, including delivery of process gases, temperature setting (e.g., heating and / or cooling), pressure setting, vacuum setting, power setting, radio frequency (RF) generator setting, RF matching circuit setting, frequency setting, flow rate setting, fluid delivery setting, position and motion setting, connection to or interfacing with specific systems, tools and other transfer tools, and / or wafer transfer into and out of load locks.

[0193] Broadly speaking, the system controller 750 can be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receives instructions, issues instructions, controls operations, enables cleaning operations, enables endpoint measurements, and performs similar functions. The integrated circuits can include a chip in the form of firmware that stores program instructions, a digital signal processor (DSP), a chip defined as an application-specific integrated circuit (ASIC), and / or one or more microprocessors, or a microcontroller that executes program instructions (e.g., software). The program instructions can be instructions communicated to the system controller 1450 in the form of various individual settings (or program files) that define operating parameters for performing a particular process on or for a semiconductor wafer or the system. The operating parameters can, in some embodiments, be part of a recipe defined by a process engineer to achieve one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of the wafer.

[0194] The system controller 750 may be part of or coupled to a computer that is integrated with, coupled to, separately network-connected to the system, or a combination thereof in some embodiments. For example, the system controller 750 may be within the “cloud” or within all or part of a fab host computer system, thereby enabling remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of fabrication operations, to investigate the history of past fabrication operations, to investigate trends or performance metrics from multiple fabrication operations, to change the parameters of the current process, to set process steps to follow the current process, or to initiate a new process. In some examples, a remote computer (e.g., a server) may provide a process recipe to the system through a network that may include a local network or the Internet. The remote computer may include a user interface that enables input or programming of parameters and / or settings that will later be communicated from the remote computer to the system. In some examples, the system controller 750 receives instructions in the form of data that specify parameters such that each of the process steps is performed during one or more operations. It should be understood that the parameters may be specific to the type of process to be performed and the type of tool that the system controller 750 interfaces with or is configured to control. Thus, as described above, the system controller 750 may be distributed, such as by being networked together and including one or more separate controllers that operate towards a common purpose such as the processes and controls described herein. An example of a distributed controller for such a purpose is one or more integrated circuits on a chamber that are in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that together control a process on the chamber.

[0195] Without limitation, example systems can include a plasma etching chamber or module, a wet deposition chamber or module, a dry deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a wet cleaning chamber or module, a dry cleaning chamber or module, an angled-edge etching chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an ALD chamber or module, an atomic layer etching (ALE) chamber or module, an ion implantation chamber or module, a track chamber or module, an EUV lithography chamber (scanner) or module, a wet photoresist development chamber or module, a dry photoresist development chamber, a chemical, plasma, and / or light-based processing chamber or module, and any other semiconductor processing system that can be associated with or used in the fabrication and / or manufacture of semiconductor wafers.

[0196] As described above, depending on the process step(s) to be performed by the tool, the system controller 750 can communicate with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, the main computer, another controller, or a tool used for material transfer that transports a wafer container to or from a tool location and / or a load port within a semiconductor manufacturing facility.

[0197] In certain embodiments, an inductively coupled plasma (ICP) reactor, which may be suitable for etching operations suitable for implementation of some embodiments, is described hereinafter. Although the ICP reactor is described herein, it should be understood that in some embodiments, capacitively coupled plasma reactors may also be used.

[0198] FIG. 8 schematically shows a cross-sectional view of an inductively coupled plasma apparatus 800 suitable for implementing a particular embodiment or aspect of the disclosed embodiments such as dry backside and bevel edge cleaning, an example of which is the Kiyo™ reactor produced by Lam Research Corp., Fremont, CA. In other embodiments, other tools or tool types having functionality for performing the dry backside and bevel edge cleaning described herein may be used for implementation.

[0199] The inductively coupled plasma apparatus 800 is structurally defined by a chamber wall 801 and a window 811 for overall processing ChamberIt includes. The chamber wall 801 can be fabricated from stainless steel, aluminum, or plastic. The window 811 can be fabricated from quartz or other dielectric materials. An optional internal plasma grid 850 divides the overall processing chamber into an upper sub-chamber 802 and a lower sub-chamber 803. In most embodiments, the plasma grid 850 can be removed so as to utilize the chamber space created in sub-chambers 802 and 803. The chuck 817 is positioned near the bottom inner surface within the lower sub-chamber 803. The chuck 817 is configured to receive and hold the semiconductor wafer 819 on which the etching and deposition processes are performed. The chuck 817 can be an electrostatic chuck for supporting the wafer 819 when it is present. In some embodiments, an edge ring (not shown) surrounds the chuck 817 and has an upper surface that is substantially planar with its upper surface when the wafer 819 is present on the chuck 817. The chuck 817 also includes electrostatic electrodes for chucking and de-chucking the wafer 819. A filter and a DC clamp power supply (not shown) can be provided for this purpose. Other control systems for lifting the wafer 819 from the chuck 817 can also be provided. The chuck 817 can be charged using the RF power supply 823. The RF power supply 823 is connected to the matching circuit 821 through the connection 827. The matching circuit 821 is connected to the chuck 817 through the connection 825. In this manner, the RF power supply 823 is connected to the chuck 817. In various embodiments, the bias power of the electrostatic chuck can be set to about 50V or can be set to different bias powers depending on the process implemented according to the disclosed embodiments. For example, the bias power can be about 20V ~about 100V, or can be about 30V~about 150V.

[0200] The elements for plasma generation include a coil 833 positioned above the window 811. In some embodiments, the coil is not used in the disclosed embodiments. The coil 833 is fabricated from a conductive material and includes at least one complete turn. The example of the coil 833 shown in FIG. 8 includes three turns. The cross-section of the coil 833 is shown with reference signs, where the coil with an "X" extends rotatably into the page, while the coil with a "●" extends rotatably out of the page. The elements for plasma generation also include an RF power supply 541 configured to supply RF power to the coil 833. Generally, the RF power supply 841 is connected to a matching circuit 839 through a connection 845. The matching circuit 839 is connected to the coil 833 through a connection 843. In this manner, the RF power supply 841 is connected to the coil 833. An optional Faraday shield 849a is positioned between the coil 833 and the window 811. The Faraday shield 849a can be maintained in a spaced relationship with respect to the coil 833. In some embodiments, the Faraday shield 849a is disposed immediately above the window 811. In some embodiments, a Faraday shield 849b is between the window 811 and the chuck 817. In some embodiments, the Faraday shield 849b is not maintained in a spaced relationship with respect to the coil 833. For example, the Faraday shield 849b can be immediately below the window 811 without a gap. The coil 833, the Faraday shield 849a, and the window 811 are each configured to be substantially parallel to each other. The Faraday shield 849a can prevent a metal or other species from depositing on the window 811 being processed Chamber in the process.

[0201] The process gas can flow into the processing chamber through one or more main gas inlets 860 positioned within the upper sub-chamber 802 and / or through one or more side gas inlets 870. Similarly, although not explicitly shown, similar gas inlets can be used to supply the process gas to the capacitively coupled plasma processing chamber. A vacuum pump, e.g., a one- or two-stage mechanical dry pump and / or a turbomolecular pump 840, processes the process gas Chamberfor extraction and for maintaining the pressure within the process Chamber It can be used. For example, a vacuum pump can be used to put the lower subchamber 803 into a vacuum state during the purge operation of ALD. A valve-controlled conduit can be used to selectively control the application of the vacuum environment provided by the vacuum pump to the process Chamber and fluidly connect it. This can be done by using a closed-loop controlled flow restriction device such as a throttle valve (not shown) or a pendulum valve (not shown) during the operation of the plasma process. Similarly, a vacuum pump and a valve-controlled fluid connection to the dose-coupled plasma processing chamber can also be used.

[0202] During operation of the apparatus 800, one or more process gases can be supplied through the gas inlets 860 and / or 870. In certain embodiments, the process gas can be supplied only through the main gas inlet 860 or only through the side gas inlet 870. In some cases, the gas inlets shown in the figure can be replaced by more complex gas inlets, such as one or more showerheads. The Faraday shield 849a and / or the optional grid 850 can include internal channels and holes that allow the delivery of the process gas to the process Chamber One or both of the Faraday shield 849a and the optional grid 850 can serve as a showerhead for the delivery of the process gas. In some embodiments, the liquid evaporation and delivery system is such that once the liquid reactant or precursor is vaporized, the vaporized reactant or precursor is introduced into the process through the gas inlets 860 and / or 870 and can be located upstream of the process Chamber Chamber

[0203] ​​Radio frequency power is supplied from an RF power source 841 to a coil 833, causing an RF current to flow through the coil 833. The RF current flowing through the coil 533 generates an electromagnetic field around the coil 833. This electromagnetic field generates an induced current within the upper subchamber 802. Physical and chemical interactions between the various generated ions and radicals and the wafer 819 etch features on the wafer 819 and selectively deposit a layer on the wafer 819.

[0204] When the plasma grid 850 is used such that both the upper subchamber 802 and the lower subchamber 803 are present, the induced current acts on the gas present within the upper subchamber 802 to generate an electron-ion plasma within the upper subchamber 802. An optional internal plasma grid 850 limits the amount of hot electrons within the lower subchamber 803. In some embodiments, the apparatus 800 is designed and operated such that the plasma present within the lower subchamber 803 is an ion-ion plasma.

[0205] Both the upper electron-ion plasma and the lower ion-ion plasma can include positive and negative ions, although the ion-ion plasma has a greater proportion of negative ions relative to positive ions. Volatile etching and / or deposition by-products can be removed from the lower subchamber 803 through the port 822. The chuck 817 disclosed herein can operate at a temperature increase ranging from about 10 °C to about 250 °C. The temperature depends on the process operation and specific recipe.

[0206] The apparatus 800 can be coupled to a facility (not shown) when installed within a cleaning chamber or fabrication facility. The facility includes piping that provides process gas, vacuum, temperature control, and environmental particle control. These facilities are coupled to the apparatus 800 when the apparatus 800 is installed within a target fabrication facility. Additionally, the apparatus 800 can be coupled to a transfer chamber that enables a robot to transfer semiconductor wafers into and out of the apparatus 800 using typical automation.

[0207] In some embodiments, system controller 830 (which may include one or more physical or logical controllers) controls some or all of the operations of the process. The system controller 830 may include one or more memory devices and one or more processors. In some embodiments, apparatus 800 includes a switching system for controlling flow rate and duration when the disclosed embodiments are implemented. In some embodiments, apparatus 800 may have a switching time of up to about 500 milliseconds or up to about 750 milliseconds. The switching time may depend on flow chemistry, the recipe selected, the reactor architecture, and other factors. Chamber Substance

[0208] In some embodiments, system controller 830 is part of a system that may be part of the examples described above. System controller 830 is further described above in connection with FIG. 7.

[0209] EUV lithography patterning can be performed using any suitable tool, often referred to as a scanner, such as the TWINSCAN NXE:3300B® platform supplied by ASML of Veldhoven, NL. The EUV lithography patterning tool can be a stand-alone device, into and out of which substrates are moved for deposition and etching as described herein. Or, as described below, the EUV lithography patterning tool can be a module on a larger multi-component tool. FIG. 9 depicts a semiconductor process cluster tool architecture having a vacuum transfer module interfacing with a vacuum-integrated deposition, backside and bevel cleaning, EUV patterning, and dry development / etching module suitable for implementation of the processes described herein. The process can be performed without such a vacuum-integrated device, although such a device can be advantageous in some embodiments.

[0210] ​​FIG. 9 depicts a semiconductor process cluster tool architecture having a vacuum-integrated deposition and patterning module that interfaces with a vacuum transfer module, suitable for implementation of the processes described herein. The placement of transfer modules for "transferring" wafers between multiple storage facilities and processing modules can be referred to as a "cluster tool architecture" system. The deposition and patterning modules are vacuum-integrated according to the requirements of a particular process. Other modules, such as for etching, may also be included on the cluster.

[0211] Vacuum transfer module (VTM) 938 interfaces with four processing modules 920a - 920d, which can be individually optimized to perform various fabrication processes. By way of example, processing modules 920a - 920d can be implemented to perform deposition, evaporation, ELD, dry development, etching, strip, and / or other semiconductor processes. For example, module 920a can be an ALD reactor operable to perform non-plasma thermal atomic layer deposition as described herein, such as a Vector tool available from Lam Research Corporation, Fremont, CA. Also, module 920b can be a PECVD tool such as Lam Vector™. It should be understood that the figures are not necessarily drawn to scale.

[0212] Airlocks 942 and 946, also known as load locks or transfer modules, interface with VTM 938 and patterning module 940. For example, as described above, a suitable patterning module can be a TWINSCAN NXE:3300B™ supplied by ASML, Veldhoven, NL. This tool architecture enables processed articles, such as semiconductor substrates or wafers, to be transferred under vacuum so that they do not react prior to exposure. The integration of the deposition module and the lithography tool is facilitated by the fact that EUVL also requires a much-reduced pressure, predicated on the strong optical absorption of incident photons by ambient gases such as H2O, O2, etc.

[0213] As described above, this integrated architecture is only one possible embodiment of the tools for the implementation of the described process. This process can also be implemented, for example, as a stand-alone or integrated into a cluster architecture with other tools (such as Lam Kiyo or Gamma tools) such as a more conventional stand-alone EUVL scanner and deposition reactor like the Lam Vector tool, but without the integrated patterned module, as described with reference to FIG. 9 for example.

[0214] Airlock 942 can be an "outward" load lock that refers to the transfer of the substrate from VTM 938 serving deposition module 920a to patterning module 940, and airlock 946 can be an "inward" load lock that refers to the transfer of the substrate returning from patterning module 940 to VTM 938. The inward load lock 946 can also provide an interface to the outside of the tool for access and egress of the substrate. Each process module has a facet that connects the module to VTM 938. For example, deposition process module 920a has facet 936. Inside each facet, sensors, such as sensors 1-18 as shown, are used to detect the passage of wafer 926 as wafer 926 is moved between the respective stations. The patterning module 940 and airlocks 942 and 946 can similarly be equipped with additional facets and sensors, not shown.

[0215] The main VTM robot 922 transfers the wafer 926 between modules including the airlocks 942 and 946. In one embodiment, the robot 922 has one arm, and in another embodiment, the robot 922 has two arms, and each arm has an end effector 924 for gripping a wafer such as the wafer 926 for transfer. The front-end robot 944 is used to transfer the wafer 926 from the outward airlock 942 into the patterning module 940 and from the patterning module 940 into the inward airlock 946. The front-end robot 944 can also transfer the wafer 926 between the inward load lock and the outside of the tool for access and withdrawal of the substrate. Since the inward airlock module 946 has the ability to match the environment between the atmosphere and the vacuum, the wafer 926 can move between the two pressure environments without being damaged.

[0216] Note that EUVL tools typically operate at a higher vacuum than deposition tools. In such cases, it is desirable to increase the vacuum environment of the substrate during transfer between the deposition and EUVL tools to allow the gas to be evacuated before the substrate enters the patterning tool. The outward airlock 942 holds the transferred wafer at a lower pressure that does not exceed the pressure within the patterning module 940 for a period of time and provides this function by exhausting any exhaust gas so that the optical elements of the patterning Module 940 are not contaminated by the exhaust gas from the substrate. A suitable pressure for the outward exhaust gas airlock does not exceed 1E-8 Torr.

[0217] In some embodiments, system controller 950 (which may include one or more physical or logical controllers) controls some or all of the operation of the cluster tool and / or its separate modules. Note that the controller may be local to the cluster architecture, or may be connected to and located external to the cluster architecture within the manufacturing floor or remotely over a network. System controller 950 may include one or more memory devices and one or more processors. The processors may include a central processing unit (CPU) or computer, analog and / or digital input / output connections, a stepper motor control board, and other similar components. Instructions for performing appropriate control operations are executed on the processor. These instructions may be stored in a memory device associated with the controller, or they may be provided over the network. In certain embodiments, the system controller executes system control software.

[0218] The system control software may include instructions for controlling the timing and / or degree of application of any aspect of the tool or module operation. The system control software may be configured in any suitable manner. For example, various process tool component subroutines or control objects may be described to control the operation of the process tool components required to perform various process tool processes. The system control software may be encoded in any suitable computer-readable programming language. In some embodiments, the system control software includes input / output control (IOC) sequencing instructions for controlling the various parameters described above. For example, each phase of a semiconductor manufacturing process may include one or more instructions for execution by the system controller. Instructions for setting process conditions for deposition, evaporation, patterning, and / or etching phases may be included in the corresponding recipe phases, for example.

[0219] In various embodiments, an apparatus for forming a negative pattern mask is provided. The apparatus can include a processing chamber for patterning, deposition, and etching, and a controller including instructions for forming a negative pattern mask. The instructions can include code for patterning features in a chemically amplified (CAR) resist on a semiconductor substrate by EUV exposure to expose a surface of the substrate within the processing chamber, developing the optically patterned resist, and using the patterned resist as a mask to etch a lower layer or layer stack. The development can be performed using a halide-containing chemical Substance that can be used.

[0220] Note that a computer controlling wafer movement can be local to a cluster architecture or can be located external to the cluster architecture within a manufacturing floor or remotely connected to the cluster architecture via a network. A controller as described above with respect to any of FIGS. 6, 7, or 8 can be implemented with the tool in FIG. 9.

[0221] FIG. 10 depicts a simplified diagram of a wet processing chamber 1000 according to various embodiments. The wet processing chamber 1000 can be used for one or more operations described herein, such as wet photoresist deposition, wet backside and bevel cleaning, and / or wet photoresist development. The wet processing chamber 1000 can include a substrate support 1002 configured to support a substrate 1001 during processing. In the embodiment of FIG. 10, the substrate support 1002 is at its periphery the substrate 1001It includes a series of pins 1004 that support it. This enables processing on one side of the substrate with minimal substrate contact on the opposite side. Such embodiments are particularly useful for processing the back side of the substrate because the substrate can be loaded upside down (e.g., with the front side down) without damaging the front side of the substrate. The substrate support 1002 can be configured to rotate during processing as indicated by the double arrows. The nozzle 1003 can be provided for dispensing the processing liquid onto the surface of the substrate 1001. Appropriate piping (not shown) can be provided to supply the processing liquid associated with the nozzle 1003 and to remove the processing liquid from the processing chamber 1000. In some cases, the processing liquid can be recycled.

[0222] Experimental results FIG. 11 depicts experimental results showing the concentration of tin on the back side of the substrate after various processing steps described herein. The results were taken at four different times: (A) after photoresist deposition, (B) after dry development of A and the photoresist, (C) after B, post-development bake, and H2 / N2 plasma treatment, and (D) after C and wet cleaning of the back side and bevel edges of the substrate. At each time point, three different measurements were taken, including (1) the center of the substrate, (2) 1 cm from the edge of the substrate, and (3) 0.5 cm from the edge of the substrate. As an example, the vertical bar A1 in FIG. 11 indicates the tin concentration on the substrate at location 1 at time A.

[0223] At time A, the concentration of tin is about 0.5E10 atoms / cm 2 ~1E10 atoms / cm 2 . At time B, the concentration of tin is substantially higher due to the contamination generated during the dry development step. For example, at time B, the concentration of tin is about 12E12 atoms / cm 2 ~15E12 atoms / cm 2 . The tin concentration is substantially reduced between times B and C as a result of the PDB treatment and the H2 / N2 plasma treatment. At time C, the concentration of tin is about 3E10 atoms / cm 2 ~13E10 atoms / cm 2extends to the range of. The tin concentration is further reduced between times C and D as a result of the wet backside and bevel edge cleaning operations. At time D, the tin concentration is <0.5E10 atoms / cm 2 is reduced to. These concentrations are comparable to, and even lower than, the starting concentration at time A.

[0224] Figure 12 depicts experimental results showing the concentration of tin contamination on the backside of the substrate after various processing steps described herein. The results were taken at five different times: (A) after photoresist deposition, (B) after dry development of A and the photoresist, (C) after post-development bake of B, (D) after wet cleaning of C and the backside and bevel edges of the substrate, and (E) after dry cleaning of the backside of the substrate with H2 plasma of D. At each time point, three different measurements were taken, including (1) the center of the substrate, (2) 1 cm from the edge of the substrate, and (3) 0.5 cm from the edge of the substrate. As an example, the vertical bar A1 in Figure 12 indicates the tin concentration on the substrate at location 1 at time A.

[0225] At time A, the concentration of tin is about 0.5E10 atoms / cm 2 ~1E10 atoms / cm 2 . At time B, the concentration of tin is substantially higher due to contamination generated during the dry development step. For example, at time B, the concentration of tin is about 12E12 atoms / cm 2 ~15E12 atoms / cm 2 . The tin concentration is substantially reduced between times B and C as a result of the post-development bake process. At time C, the concentration of tin is in the range of about 6E10 atoms / cm 2 ~65E10 atoms / cm 2 . The tin concentration is further reduced between times C and D as a result of the wet backside and bevel edge cleaning operations. At time D, the tin concentration is in the range of about 0.1E10 atoms / cm 2 ~0.2E10 atoms / cm 2 . The tin concentration continues to decrease between times D and E because the backside of the substrate is exposed to H2 plasma. At time E, the tin concentration is about 0.01E10 atoms / cm 2~0.05E10 atoms / cm 2 range.

[0226] In particular, FIG. 12 shows that post-develop bake enables a significant reduction in the tin concentration on the back side of the substrate. Further, back-side wet cleaning reduces the tin concentration to <1E10 atoms / cm 2 and the addition of H2 plasma to clean the back side of the substrate further reduces the back-side tin concentration by about 4 times.

[0227] FIGS. 13A and 13B depict experimental results showing the advantages of adding plasma treatment to post-develop bake. In this example, the process flow involved (1) depositing photoresist, (2) wet cleaning the back side of the substrate, (3) dry developing the photoresist, (4) performing post-develop bake (with and without a plasma treatment step), (5) wet cleaning the back side of the substrate again, (6) exposing the substrate to typical queue conditions for various durations, and (7) performing measurements to measure the concentration of tin on the back side of the substrate after different queue durations. The tin concentration was measured at three different times, including queue times of 0 days, 3 days, and 5 days. On day 0, day 3, and day 5, the tin concentration was measured at the center of the substrate and 0.5 cm from the edge of the substrate. Further, on day 5, the tin concentration was measured 0.5 cm from the edge of the substrate along the crescent shape (CM). The measurements were taken on the back side of the substrate.

[0228] Figure 13A shows the results when the post-development bake step did not include any plasma treatment. In contrast, Figure 13B shows the results when the post-development bake step included plasma treatment. The plasma treatment in this example involved exposing the substrate to H2 / N2 plasma during the post-development bake process. As shown in Figures 13A and 13B, both processing procedures resulted in similar backside tin concentrations when the queue time was 0 days or 3 days. When the queue time was increased to 5 days, the substrate exposed to plasma treatment during the post-development bake step showed a substantially lower backside tin concentration compared to the substrate not exposed to plasma during this step. These results indicate that plasma treatment during the post-development bake step does not have an adverse effect on the available queue time (e.g., the time available before the backside tin concentration rises to an unacceptable level as a result of the problems described herein). In fact, such plasma treatment can, in many cases, increase the available queue time.

[0229] Figure 14 shows the experimental results demonstrating the effectiveness of adding plasma treatment to the post-development bake. These results are consistent with those shown in Figures 13A and 13B. In the example of Figure 14, the process flow involved (1) depositing a photoresist, (2) wet cleaning the backside of the substrate, (3) dry developing the photoresist, (4) performing a post-development bake (with and without a plasma treatment step), (5) wet cleaning the backside of the substrate again, (6) exposing the substrate to typical queue conditions for a duration of about 2 days, and (7) performing measurements to determine the concentration of tin on the backside of the substrate after queuing. The plasma treatment during the post-development bake involved exposing the substrate to H2 / N2 plasma. As shown in Figure 14, when plasma treatment was not used during the post-development bake, the resulting backside tin concentration after a 2-day queue time was about 38E10 atoms / cm Duration . When plasma treatment was added to the post-development bake, the resulting backside tin concentration after a 2-day queue time was only about 4.2E10 atoms / cm 2 ​2 It was. This represents a nearly one-digit reduction in the backside tin concentration.

[0230] Figure 15 depicts a substrate divided into three different analysis zones (Z1 - Z3) and a table reporting the backside tin concentration within each zone. The first zone (Z1) corresponds to the central circular portion of the substrate up to a radius of approximately 75 mm. The second zone (Z1) corresponds to the intermediate annular portion of the substrate from a radius of approximately 75 mm to a radius of approximately 135 mm. The third zone (Z3) corresponds to the outer annular portion of the substrate from a radius of approximately 135 mm to a radius of approximately 148 mm. In this example, the process flow involved (1) depositing photoresist, (2) wet cleaning the backside of the substrate, (3) dry developing the photoresist, (4) performing a post-development bake with a plasma treatment step, (5) wet cleaning the backside of the substrate again, (6) exposing the substrate to typical queue conditions for a duration of about 4.5 days, and (7) performing measurements to determine the concentration of tin on the backside of the substrate after the queue Duration This was accompanied by performing measurements to determine the concentration of tin on the backside of the substrate after the queue. The plasma treatment during the post-development bake step involved exposing the substrate to an H2 / N2 plasma. The results in Figure 15 show that after this series of operations, most of the tin contamination remaining on the backside of the substrate is located in the third zone, for example, near the edge of the substrate.

[0231] Figures 16A and 16B depict experimental results showing improvements in line critical dimension (Figure 16A) and line width roughness (Figure 16B) over a typical EUV dose range as a result of a post-development bake step involving exposing the substrate to H2 / N2 plasma treatment. These figures show measurements taken at two times, including before and after the post-development bake step. Figure 16A shows that the post-development bake and plasma treatment steps resulted in a reduction in line critical dimension of approximately 0.4 - 0.5 nm over the EUV dose range. This represents a reduction of approximately 2 - 4% at each dose. Similarly, Figure 16B shows that the post-development bake and plasma treatment steps resulted in a reduction in line width roughness over the EUV dose range.

[0232] Figures 17A and 17B depict experimental results showing the concentration of residual bromine on the front side of the processed substrate (Figure 17A) and the concentration of tin contamination on the back side of the substrate (Figure 17B) in post-development bakes performed at various temperatures. In this example, the development process is a dry development process, and wet cleaning (or other cleaning processes) were not performed between the post-development bake process and the measurement. Figure 17A shows that exposing the substrate to the post-development bake process dramatically reduces the concentration of bromine in the substrate. As the temperature of the post-development bake increases, the residual bromine concentration substantially decreases. At higher temperatures (e.g., above about 250 °C), this benefit gradually diminishes. Figure 17B shows that as the post-development bake temperature increases, the concentration of tin contamination on the back side of the substrate decreases. The tin concentration decreases at both the center and the edge of the substrate, with the decrease being particularly large near the center of the substrate.

[0233] Figures 18A and 18B depict experimental results showing the advantage of periodically cleaning the processing chamber used to perform the post-development bake process. The first series of substrates shown in Figure 18A were processed using a post-development bake step without chamber cleaning being performed between substrates. The second series of substrates shown in Figure 18B were processed using a post-development bake step with the chamber being cleaned after each substrate was baked. In both cases, the tin concentration was measured after the 5th substrate was processed (e.g., after 5 substrates, after 10 substrates, etc.). Figure 18A shows that when the chamber is not periodically cleaned, the concentration of backside tin contamination continues to increase as additional substrates are processed. In fact, the backside tin concentration is more than about 2 orders of magnitude higher after 10 substrates are processed and reaches 2 over 100E10 atoms / cm 2 . Such an increase is large and undesirable. In contrast, Figure 18B shows that when the chamber is periodically cleaned, the concentration of backside tin contamination remains low and stable at a level below 2 1E10 atoms / cm. Such a low and stable tin concentration was achieved even when the starting concentration was orders of magnitude higher, exceeding

[0234] Figures 19A and 19B show experimental results related to the optimization of plasma processing according to various embodiments at lower temperatures. Figure 19A focuses on the effect of different carrier gases on the backside tin concentration, while Figure 19B focuses on the influence of the total flow rate on the backside tin concentration. In all of the examples related to Figures 19A and 19B, the plasma processing involves exposing the substrate to plasma generated from hydrogen (H2), and helium, nitrogen (N2), or a combination of helium and nitrogen is used as the carrier gas. Hydrogen was present at a concentration of approximately 5% by volume in each case. As shown in Figure 19A, the H2 / He plasma treatment resulted in a substantially lower backside tin concentration compared to the H2 / N2 plasma treatment. This suggests that helium provides better tin reduction results compared to nitrogen when acting as a carrier gas for hydrogen. Figure 19B shows the results from three different plasma treatments. The first plasma treatment involved a low flow situation where the substrate was exposed to plasma generated from H2 / He. The second plasma treatment involved an intermediate flow situation where the substrate was exposed to plasma generated from H2 / He, and the H2 / He flow was approximately twice the flow of the first plasma treatment. The third plasma treatment involved a high flow situation where the substrate was exposed to plasma generated from H2 / He / N2, and the H2 / He / N2 flow was approximately three times the H2 / He flow used in the first plasma treatment. In this example, doubling the flow rate of H2 / He resulted in reducing the concentration of backside tin contamination. The addition of a significant amount of N2 in the third plasma treatment resulted in increasing the backside tin contamination.

[0235] Additional Embodiments Figures 20 and 21 illustrate exemplary process flows according to various embodiments. In the example of FIG. 20, the substrate is processed using wet development techniques. In the example of FIG. 21, the substrate is processed using dry development techniques. The steps described in FIGS. 20 and 21 can be combined with any one or more of the techniques described herein. Further, any details provided herein regarding a particular step may also apply when practicing the corresponding step in FIGS. 20 and 21. For the sake of brevity, such details are not repeated.

[0236] The wet development method 2000 of FIG. 20 begins at operation 2001, where a photoresist is deposited on the substrate. The photoresist can be a metal-containing photoresist as described herein. In operation 2003, the substrate is cleaned using wet cleaning techniques, particularly targeting the backside and bevel edge regions of the substrate. In operation 2005, the substrate is exposed to a post-application bake. In operation 2007, the substrate is exposed to EUV radiation to begin patterning the photoresist. In operation 2009, the substrate is exposed to a post-exposure bake. In operation 2011, the photoresist is developed using wet development techniques. In operation 2013, the substrate can be exposed to metrology or further processing. The further processing can involve one or more of the techniques described herein.

[0237] The dry development method 2050 of FIG. 21 starts in a manner similar to the method of FIG. 20. For example, operations 2001, 2003, 2005, 2007, and 2009 are the same as those in FIG. 20. After operation 2009, the method of FIG. 21 continues with operation 2021, and the photoresist is developed using dry development technology. Next, in operation 2023, the substrate is exposed to a post-development bake. In operation 2025, the substrate is exposed to a chemical treatment. In various examples, the chemical treatment in operation 2025 can occur concurrently with the photoresist dry development in operation 2021 and / or the post-development bake in operation 2023. In other examples, the chemical treatment in operation 2025 can occur separately, for example, between operations 2021 and 2023, or between operations 2023 and 2027. In operation 2027, the substrate is exposed to a wet cleaning operation to clean the back side of the substrate. In operation 2029, the substrate can be exposed to measurement or further processing.

[0238] It should be understood that FIGS. 20 and 21 present some specific operations, but one or more of these steps can be omitted in various embodiments. Any subset of the steps shown in FIG. 20 or FIG. 21 can be used in various embodiments.

[0239] Conclusion A process and apparatus for controlling metal contamination on a semiconductor substrate are disclosed. In many embodiments, the process and apparatus can be used in connection with the deposition, development, and / or processing of metal-containing photoresists such as EUV photoresists. Other applications such as in-situ cleaning, mandrel extraction, planarization, and photoresist descumming applications can also benefit from the disclosed embodiments.

[0240] The examples and embodiments described in this specification are for illustrative purposes only, and it should be understood that various modifications or changes based on them will be proposed to those skilled in the art. Although various details have been omitted for the purpose of brevity, various design alternatives can be implemented. Therefore, this example is considered to be illustrative rather than restrictive, and the present disclosure is not limited to the details provided within this specification, but can be modified within the scope of the present disclosure. The present invention can also be realized, for example, in the following aspects. Application Example 1: A method for controlling contamination on a substrate, comprising: (a) (i) Treating the front side of the substrate to cause the formation of contamination containing metal on the back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; (b) After (a), heating the substrate in a post-treatment bake process, wherein heating the substrate reduces the concentration of the metal on the back side of the substrate; A method comprising the above. Application Example 2: The method according to claim 1, wherein treating the front side of the substrate comprises at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, extracting a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist. Application Example 3: The method according to claim 2, wherein (a) includes either (i) developing a layer of photoresist on the substrate or (ii) receiving a layer of photoresist developed on the front side of the substrate and the substrate having contamination on the back side of the substrate, the metal in the contamination originates from the layer of photoresist on the front side of the substrate, and the post-treatment bake process in (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. Application Example 4: The method of claim 3, wherein during the post-development bake process of (b), the substrate is baked at a temperature of about 160 to 300 °C for a duration of about 1 to 10 minutes. Application Example 5: The method of claim 3, further comprising exposing the substrate to a processing gas, the processing gas comprising at least one gas selected from the group consisting of N 2 、H 2 , Ar, He, Xe, and combinations thereof. Application Example 6: The method of claim 3, further comprising exposing the substrate to a reactive processing gas to increase the volatility of the metal-containing material on the substrate, the metal-containing material comprising the metal. Application Example 7: The method of claim 3, further comprising exposing the substrate to a reactive processing gas to increase the stability of the metal-containing material on the substrate, the metal-containing material comprising the metal. Application Example 8: The method of claim 3, further comprising exposing the substrate to a reactive processing gas selected from the group consisting of a chlorine-containing gas, an oxygen-containing gas, a fluorine-containing gas, ammonia (NH 3 ), hydrogen iodide (HI), diatomic iodine (I 2 ), and combinations thereof. Application Example 9: The method of claim 8, wherein the substrate is exposed to the chlorine-containing gas, the chlorine-containing gas comprising at least one gas selected from the group consisting of BCl 3 、Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 , and combinations thereof. Application Example 10: The method of claim 8, wherein the substrate is exposed to the oxygen-containing gas, the oxygen-containing gas comprising at least one gas selected from the group consisting of O 2 、O 3 、H 2 O, SO 2 , CO2, CO, COS, H 2 O 2 , NO x , and combinations thereof. Application Example 11: The method of claim 8, wherein the substrate is exposed to the fluorine-containing gas, the fluorine-containing gas comprising at least one gas selected from the group consisting of HF, C x F y H z , NF 3 , SF 6 、F 2 , and combinations thereof. Application Example 12: The method of claim 3, further comprising exposing the substrate to a plasma to increase the volatility of the metal-containing material on the substrate, the metal-containing material comprising the metal. Application Example 13: The method of claim 3, further comprising exposing the substrate to a plasma to increase the stability of the metal-containing material on the substrate, the metal-containing material comprising the metal. Application Example 14: The method of claim 3, wherein diatomic hydrogen (H 2 ) Two-atom nitrogen (N 2 ) Argon, helium, krypton, methane (CH 4 ) A method further comprising exposing the substrate to a plasma generated from a plasma generating gas containing at least one gas selected from the group consisting of oxygen-containing gas, fluorine-containing gas, chlorine-containing gas, hydrogen halide, and combinations thereof. Application Example 15: The method of claim 14, wherein the plasma generating gas contains an oxygen-containing gas, and the oxygen-containing gas contains O 2 、O 3 , CO, CO 2 , COS, SO 2 , NOx, H 2 O, and a method comprising at least one gas selected from the group consisting of combinations thereof. Application Example 16: The method of claim 14, wherein the plasma generating gas contains a fluorine-containing gas, and the fluorine-containing gas contains NF 3 , CF 4 , CH 3 F 3 , CH 2 F 2 , CHF 3 、F 2 , SF 6 , and a method comprising at least one gas selected from the group consisting of combinations thereof. Application Example 17: The method of claim 14, wherein the plasma generating gas contains the chlorine-containing gas, and the chlorine-containing gas contains BCl 3 、Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 , and a method comprising at least one gas selected from the group consisting of combinations thereof. Application Example 18: The method of claim 14, wherein the plasma generating gas contains (i) the diatomic hydrogen (H 2), and (ii) at least one of diatomic nitrogen (N 2 ) or noble gas. Application Example 19: The method of claim 3, wherein heating the substrate in the post-development bake process reduces the concentration of the metal on the back side of the substrate by at least one order of magnitude. Application Example 20: The method of claim 3, further comprising exposing the substrate to plasma, heating the substrate in the post-development bake process, and exposing the substrate to plasma reduces the concentration of the metal on the back side of the substrate by at least two orders of magnitude. Application Example 21: The method of claim 3, further comprising exposing the substrate to light to reduce the concentration of the metal on the back side of the substrate. Application Example 22: The method of claim 21, wherein the light includes at least one of UV wavelength, visible wavelength, or IR wavelength. Application Example 23: The method of claim 22, wherein the light is provided by an IR lamp or a plurality of LEDs, and the substrate is heated to a temperature of about 250 to 400 °C for a duration of about 60 seconds or less while the substrate is exposed to the light. Application Example 24: The method of claim 3, wherein heating the substrate in the post-development bake process begins while the layer of photoresist is still developed on the substrate. Application Example 25: The method of claim 3, further comprising transferring the substrate from the first processing chamber to the second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber. Application Example 26: The method of claim 3, wherein (a) occurs in a processing chamber, and the method further comprises heating the processing chamber to a temperature of about 40 °C or higher while the layer of photoresist is being developed in (a). Application Example 27: The method of claim 3, wherein (a) occurs in a processing chamber, and the method further comprises purging the processing chamber while maintaining the processing chamber at a temperature of about 100 °C or higher, and the purging occurs after (a). Application Example 28: The method of claim 27, wherein the method further comprises sweeping the processing chamber with an inert gas, and the purging and the sweeping are part of a pump purge sequence. Application Example 29: The method of claim 3, further comprising performing a wet cleaning on the back side of the substrate after (a) and (b). Application Example 30: The method of claim 29, wherein performing the wet cleaning on the back side of the substrate further reduces the concentration of the metal on the back side of the substrate by at least one order of magnitude. Application Example 31: The method of claim 29, wherein the wet cleaning also cleans the bevel edge region on the front side of the substrate. Application Example 32: The method of claim 29, wherein performing the wet cleaning on the back side of the substrate comprises exposing the back side of the substrate to dilute HF. Application Example 33: The method of claim 32, wherein performing the wet cleaning on the back side of the substrate further comprises exposing the back side of the substrate to dilute HCl or a standard cleaning 1 solution containing NH 4 OH, H 2 O 2 , and H 2 O. Application Example 34: The method of claim 3, wherein the layer of photoresist is formed using dry deposition. Application Example 35: The method of claim 3, wherein the layer of photoresist is formed using wet deposition. Application Example 36: The method of claim 3, wherein the layer of photoresist is developed using a dry process. Application Example 37: The method of claim 36, wherein the layer of photoresist is developed using a halogen-containing chemical. Application Example 38: The method of claim 3, wherein the layer of photoresist is developed using a wet process. Application Example 39: The method of claim 3, wherein the post-development bake process in (b) occurs in a processing chamber and has the following conditions: (i) The pressure in the processing chamber is maintained at about 0.01 to 1 torr. (ii) A chlorine-containing gas is provided to the processing chamber at a rate of about 200 to 10,000 sccm for a duration of about 1 to 10 minutes. (iii) The temperature of one or more components of the processing chamber is maintained at about 20 to 150 °C, and (iv) The substrate is not exposed to plasma during (b). These conditions are used during the post-development bake process in (b). Application Example 40: The method of claim 3, wherein the layer of photoresist is developed in (a) in a processing chamber, (b) occurs in the same processing chamber as (a), and the method has the following conditions: (i) The pressure in the processing chamber is about 0.01 to 1 torr. (ii) A purge gas flow is provided to the processing chamber at a rate of about 200 to 10,000 sccm. The purge gas contains at least one gas selected from the group consisting of diatomic nitrogen (N 2 )), noble gases, and combinations thereof, and the purge gas is provided to the processing chamber for a duration of about 1 to 10 minutes. Also, (iii) One or more components of the processing chamber are maintained at about 100 to 300 °C, and the substrate support in the processing chamber is maintained at about 120 to 300 °C. The method further includes purging the processing chamber using these conditions. Application Example 41: The method of claim 3, wherein (a) occurs in a first processing chamber and (b) occurs in a second processing chamber, and has the following conditions: (i) The pressure in the second processing chamber is about 0.1 to 760 torr. (ii) The gas flow is provided to the second processing chamber at a rate of about 200 - 10,000 sccm over a duration of about 1 - 10 minutes, the substrate is exposed to the gas flow, and the gas flow contains at least one of air, diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), water (H 2 O), noble gas, or a combination thereof, and (iii) the substrate is baked at a temperature of about 140 - 300 °C is used during the post - development bake process of (b), a method. Application Example 42: The method of claim 3, comprising the following conditions: (i) The pressure in the processing chamber is about 0.1 - 1 torr, (ii) The plasma - generating gas is provided at a rate of about 50 - 5,000 sccm over a duration of about 3 - 30 seconds, and the plasma - generating gas contains at least one gas or gas mixture selected from the group consisting of (a) H 2 , (b) H 2 and N 2 , (c) H 2 and noble gas, (d) N 2 without H 2 , (e) noble gas without H 2 , (f) oxygen - containing gas, (g) fluorine - containing gas, and (h) combinations thereof, and (iii) Plasma is generated from the plasma - generating gas and the substrate is exposed to the plasma further comprising exposing the substrate to plasma in the processing chamber under, a method. Application Example 43: The method of claim 3, wherein at least one of (a) and (b) occurs in the processing chamber, and the method further comprises cleaning the processing chamber to remove the metal from the inner surface of the processing chamber. Application Example 44: The method of claim 43, wherein the processing chamber has the following conditions: (i) The pressure in the processing chamber is about 0.1 - 10 torr, (ii) Plasma containing H radicals is exposed to the processing chamber, and the H radicals react with the metal on the inner surface of the processing chamber to form metal hydrides, (iii) The plasma is generated using RF power of about 300 - 4,000 watts, and (iv) The processing chamber is maintained at about 25 - 250 °C is used for cleaning, a method. Application Example 45: The method of claim 43, wherein the processing chamber has the following conditions: (i) The pressure in the processing chamber is about 0.1 - 10 torr and is cycled between a lower pressure and a higher pressure as part of a pumping and purging process. (ii) the processing chamber is not exposed to plasma during cleaning, (iii) a gas flow is provided to the processing chamber during cleaning, the gas flow comprising at least one gas selected from the group consisting of diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), noble gases, and combinations thereof, and (iv) the processing chamber is maintained at about 25 - 250 °C, is used for cleaning, a method. Application Example 46: The method of claim 3, comprising the following conditions: (i) In a first step, the substrate is exposed to a first cleaning liquid provided at a rate of about 1 - 3 L / min, the first cleaning liquid comprising dilute HF, (ii) In a second step, the substrate is exposed to a second cleaning liquid provided at a rate of about 1 - 3 L / min, the second cleaning liquid comprising a solution selected from the group consisting of dilute HCl, Standard Clean 1, and combinations thereof, (iii) The first step and the second step together have a duration of about 20 - 300 seconds, and (iv) the substrate is maintained at about 15 - 60 °C, further comprising performing wet cleaning on the back side of the substrate using this, a method. Application Example 47: The method of claim 3, wherein the concentration of the metal in at least one of the back side or the bevel edge region of the substrate is reduced by at least one order of magnitude to about 1E11 atoms / cm 2 or less. A method. Application Example 48: The method of claim 47, wherein the concentration of the metal in at least one of the back side or the bevel edge region of the substrate is reduced by at least one order of magnitude to about 1E10 atoms / cm 2 or less. A method. Application Example 49: The method of claim 3, wherein the metal is tin. A method. Application Example 50: A system for processing a substrate, comprising a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, a controller configured to cause any one or more of the methods of claims 1 - 49 or the methods separately described herein, A system comprising. Application Example 51: A system for processing a substrate, comprising a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, a controller configured to (a)(i) process a front side of the substrate to cause formation of contamination containing metal on a back side of the substrate, or (ii) receive the substrate with contamination on the back side of the substrate, and (b) after (a), heat the substrate in a post-treatment bake process, wherein heating the substrate reduces a concentration of the metal on the back side of the substrate, heating of the substrate, a system comprising the controller. Application Example 52: The system of claim 51, wherein processing the front side of the substrate includes at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, pulling out a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist. Application Example 53: The system of claim 52, wherein the controller is configured to cause (a) by either (i) developing a layer of photoresist on the substrate, or (ii) receiving the layer of photoresist developed on the front side of the substrate and the substrate having contamination on the back side of the substrate, the metal in the contamination results from the layer of photoresist on the front side of the substrate, the post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. Application Example 54: The system of claim 53, wherein both (a) and (b) occur in the same processing chamber. Application Example 55: The system of claim 53, wherein (a) occurs in the processing chamber and (b) occurs in a second processing chamber different from the processing chamber. Application Example 56: The system of claim 53, further comprising a plasma generator configured to provide plasma in the processing chamber. Application Example 57: The system of claim 56, wherein the plasma generator is a remote plasma generator such that the plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber.

Claims

1. A method for controlling contamination on a substrate, comprising: (a) either (i) treating the front side of the substrate to cause the formation of contamination containing metal on the back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate; and (b) heating the substrate in a post-treatment bake process after (a), wherein heating the substrate reduces the concentration of the metal on the back side of the substrate. A method as described above.

2. The method according to claim 1, wherein treating the front side of the substrate includes at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, extracting a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist.

3. The method according to claim 2, wherein (a) includes either (i) developing a layer of photoresist on the substrate, or (ii) receiving a layer of photoresist developed on the front side of the substrate and the substrate having contamination on the back side of the substrate, the metal in the contamination originates from the layer of photoresist on the front side of the substrate, and the post-treatment bake process in (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed.

4. The method according to claim 3, wherein during the post-development bake process in (b), the substrate is baked at a temperature of about 160 to 300 °C for a duration of about 1 to 10 minutes.

5. The method according to claim 3, further comprising exposing the substrate to a processing gas, the processing gas comprising at least one gas selected from the group consisting of N 2 , H 2 , Ar, He, Xe, and combinations thereof.

6. The method according to claim 3, further comprising exposing the substrate to a reactive treatment gas to increase the volatility of a metal-containing material on the substrate, wherein the metal-containing material contains the metal.

7. The method according to claim 3, further comprising exposing the substrate to a reactive treatment gas to increase the stability of a metal-containing material on the substrate, wherein the metal-containing material contains the metal.

8. The method according to claim 3, further comprising exposing the substrate to a reactive processing gas selected from the group consisting of a chlorine-containing gas, an oxygen-containing gas, a fluorine-containing gas, ammonia (NH 3 ), hydrogen iodide (HI), diatomic iodine (I 2 ), and combinations thereof.

9. The method according to claim 8, wherein the substrate is exposed to the chlorine-containing gas, and the chlorine-containing gas is BCl 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 , and a method comprising at least one gas selected from the group consisting of combinations thereof.

10. The method according to claim 8, wherein the substrate is exposed to the oxygen-containing gas, and the oxygen-containing gas contains at least one gas selected from the group consisting of O 2 , O 3 , H 2 O, SO 2 , CO2, CO, COS, H 2 O 2 , NO x , and combinations thereof.

11. The method according to claim 8, wherein the substrate is exposed to the fluorine-containing gas, and the fluorine-containing gas comprises at least one gas selected from the group consisting of HF, C x F y H z , NF 3 , SF 6 , F 2 , and combinations thereof.

12. The method according to claim 3, further comprising exposing the substrate to plasma to increase the volatility of the metal-containing material on the substrate, wherein the metal-containing material comprises the metal, the method.

13. The method according to claim 3, further comprising exposing the substrate to plasma to increase the stability of the metal-containing material on the substrate, wherein the metal-containing material comprises the metal, the method.

14. The method according to claim 3, wherein the substrate is further exposed to a plasma generated from a plasma generating gas containing at least one gas selected from the group consisting of diatomic hydrogen (H 2 ), diatomic nitrogen (N 2 ), argon, helium, krypton, methane (CH 4 ), an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, hydrogen halide, and combinations thereof.

15. The method according to claim 14, wherein the plasma generation gas includes an oxygen-containing gas, and the oxygen-containing gas contains O 2 , O 3 , CO, CO 2 , COS, SO 2 , NOx, H 2 O, and a method comprising at least one gas selected from the group consisting of combinations thereof.

16. The method according to claim 14, wherein the plasma generating gas includes a fluorine-containing gas, and the fluorine-containing gas is NF 3 , CF 4 , CH 3 F 3 , CH 2 F 2 , CHF 3 , F 2 , SF 6 , and a method comprising at least one gas selected from the group consisting of combinations thereof.

17. The method according to claim 14, wherein the plasma generation gas includes the chlorine-containing gas, and the chlorine-containing gas is BCl 3 , Cl 2 , HCl, SiCl 4 , SOCl 2 , PCl 3 , and a method comprising at least one gas selected from the group consisting of combinations thereof.

18. The method according to claim 14, wherein the plasma generating gas comprises (i) said diatomic hydrogen (H 2 ), and (ii) at least one of diatomic nitrogen (N 2 ) or a noble gas.

19. The method according to claim 3, wherein heating the substrate in the post-development bake process reduces the concentration of the metal on the back side of the substrate by at least one order of magnitude, the method.

20. The method according to claim 3, further comprising exposing the substrate to plasma, heating the substrate in the post-development bake process, and exposing the substrate to plasma reduces the concentration of the metal on the back side of the substrate by at least two orders of magnitude, the method.

21. The method according to claim 3, further comprising exposing the substrate to light to reduce the concentration of the metal on the back side of the substrate, the method.

22. The method according to claim 21, wherein the light comprises at least one of a UV wavelength, a visible wavelength, or an IR wavelength, the method.

23. The method according to claim 22, wherein the light is provided by an IR lamp or a plurality of LEDs, and the substrate is heated to a temperature of about 250 to 400 °C for a duration of about 60 seconds or less while the substrate is exposed to the light, the method.

24. The method according to claim 3, wherein heating the substrate in the post-development bake process starts while the layer of photoresist is still developed on the substrate, the method.

25. The method according to claim 3, further comprising transferring the substrate from the first processing chamber to the second processing chamber after (a), such that (a) occurs in the first processing chamber and (b) occurs in the second processing chamber, the method.

26. The method according to claim 3, wherein (a) occurs in a processing chamber, and the method further comprises heating the processing chamber to a temperature of about 40 °C or higher while the layer of photoresist is developed in (a), the method.

27. The method according to claim 3, wherein (a) occurs in a processing chamber, and the method further includes purging the processing chamber while maintaining the processing chamber at a temperature of about 100 °C or higher, and the purging occurs after (a).

28. The method according to claim 27, wherein the method further includes sweeping the processing chamber with an inert gas, and the purging and the sweeping are part of a pump purge sequence.

29. The method according to claim 3, further including performing a wet cleaning on the back side of the substrate after (a) and (b).

30. The method according to claim 29, wherein performing the wet cleaning on the back side of the substrate further reduces the concentration of the metal on the back side of the substrate by at least one order of magnitude.

31. The method according to claim 29, wherein the wet cleaning also cleans the bevel edge region on the front side of the substrate.

32. The method according to claim 29, wherein performing the wet cleaning on the back side of the substrate includes exposing the back side of the substrate to dilute HF.

33. The method according to claim 32, wherein performing the wet cleaning on the back side of the substrate comprises exposing the back side of the substrate to dilute HCl or a standard cleaning 1 solution containing NH 4 OH, H 2 O 2 and H 2 O. The method further comprises this exposure.

34. The method according to claim 3, wherein the layer of photoresist is formed using dry deposition.

35. The method according to claim 3, wherein the layer of photoresist is formed using wet deposition.

36. The method according to claim 3, wherein the layer of photoresist is developed using a dry process.

37. The method according to claim 36, wherein the layer of photoresist is developed using a halogen-containing chemical structure.

38. The method according to claim 3, wherein the layer of photoresist is developed using a wet process.

39. The method according to claim 3, wherein the post-development bake process of (b) occurs in a processing chamber and has the following conditions: (i) The pressure in the processing chamber is maintained at about 0.01 to 1 torr, (ii) A chlorine-containing gas is provided to the processing chamber at a rate of about 200 to 10,000 sccm for a duration of about 1 to 10 minutes, (iii) The temperature of one or more components of the processing chamber is maintained at about 20 to 150 °C, and (iv) The substrate is not exposed to plasma during (b) A method used during the post-development baking process of (b). **Claim 40** The method according to claim 3, wherein the layer of photoresist is developed in (a) in a processing chamber, (b) occurs in the same processing chamber as (a), and the method comprises the following conditions: (i) The pressure in the processing chamber is about 0.01 to 1 torr. (ii) The purge gas flow is provided to the processing chamber at a rate of about 200 to 10,000 sccm, and the purge gas contains at least one gas selected from the group consisting of diatomic nitrogen (N 2 )), noble gases, and combinations thereof, and the purge gas is provided to the processing chamber for a duration of about 1 to 10 minutes, and (iii) One or more components of the processing chamber are maintained at about 100 to 300 °C, and the substrate support in the processing chamber is maintained at about 120 to 300 °C. The method further comprising purging the processing chamber using the following. **Claim 41** The method according to claim 3, wherein (a) occurs in a first processing chamber and (b) occurs in a second processing chamber, and the following conditions: (i) The pressure in the second processing chamber is about 0.1 to 760 torr. (ii) The gas flow is provided to the second processing chamber at a rate of about 200 to 10,000 sccm over a duration of about 1 to 10 minutes, the substrate is exposed to the gas flow, and the gas flow comprises at least one of air, diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), water (H 2 O), noble gas, or a combination thereof, and (iii) The substrate is baked at a temperature of about 140 to 300 °C. A method used during the post-development baking process of (b). **Claim 42** The method according to claim 3, comprising the following conditions: (i) The pressure in the processing chamber is about 0.1 to 1 torr. (ii) The plasma generating gas is provided at a rate of about 50 to 5,000 sccm over a duration of about 3 to 30 seconds, and the plasma generating gas is (a) H 2 , (b) H 2 and N 2 , (c) H 2 and a noble gas, (d) N 2 without H 2 , (e) a noble gas without H 2 , (f) an oxygen-containing gas, (g) a fluorine-containing gas, and (h) at least one gas or gas mixture selected from the group consisting of combinations thereof, and (iii) Plasma is generated from the plasma-generating gas, and the substrate is exposed to the plasma. The method further comprising exposing the substrate to the plasma in the processing chamber under the following. **Claim 43** The method according to claim 3, wherein at least one of (a) and (b) occurs in a processing chamber, and the method further comprises cleaning the processing chamber to remove the metal from the inner surface of the processing chamber. **Claim 44** The method according to claim 43, wherein the processing chamber comprises the following conditions: (i) The pressure in the processing chamber is about 0.1 to 10 torr. (ii) A plasma containing H radicals is exposed to the processing chamber, and the H radicals react with the metal on the inner surface of the processing chamber to form metal hydrides. (iii) The plasma is generated using RF power of about 300 to 4,000 watts, and (iv) The processing chamber is maintained at about 25 to 250 °C. The method of cleaning using the following. **Claim 45** The method according to claim 43, wherein the processing chamber comprises the following conditions: (i) The pressure within the processing chamber is from about 0.1 to 10 Torr and is cycled between a lower pressure and a higher pressure as part of a pumping and purging process, (ii) The processing chamber is not exposed to plasma during cleaning, (iii) A gas stream is provided to the processing chamber during cleaning, and the gas stream comprises at least one gas selected from the group consisting of diatomic nitrogen (N 2 ), diatomic oxygen (O 2 ), noble gases, and combinations thereof, and (iv) The processing chamber is maintained at about 25 to 250 °C, and is cleaned using a method.

46. The method according to claim 3, comprising the following conditions: (i) In a first step, the substrate is exposed to a first cleaning liquid provided at a rate of about 1 to 3 L / min, and the first cleaning liquid contains dilute HF, (ii) In a second step, the substrate is exposed to a second cleaning liquid provided at a rate of about 1 to 3 L / min, and the second cleaning liquid contains a solution selected from the group consisting of dilute HCl, standard cleaning 1, and combinations thereof, (iii) The first step and the second step together have a duration of about 20 to 300 seconds, and (iv) The substrate is maintained at about 15 to 60 °C, and further comprising performing wet cleaning on the back side of the substrate using a method.

47. The method according to claim 3, wherein the concentration of the metal in at least one of the back side or the bevel edge region of the substrate is at least one order of magnitude lower to about 1E11 atoms / cm 2 The method.

48. The method according to claim 47, wherein the concentration of the metal in at least one of the back side or the bevel edge region of the substrate is at least one order of magnitude lower than about 1E10 atoms / cm 2 The method is reduced.

49. The method according to claim 3, wherein the metal is tin.

50. A system for processing a substrate, comprising: a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, and a controller configured to cause any one or more of the methods according to claims 1 to 49, or methods otherwise described herein. A system comprising the above components.

51. A system for processing a substrate, comprising: a processing chamber, an inlet to the processing chamber for introducing gas and / or plasma into the processing chamber, an outlet from the processing chamber for removing material from the processing chamber, a heater, a substrate support, a controller, wherein (a) (i) processing the front side of the substrate so as to cause the formation of contamination containing metal on the back side of the substrate, or (ii) receiving the substrate with contamination on the back side of the substrate, and After (b), heating the substrate in a post-treatment bake process, wherein heating the substrate reduces the concentration of the metal on the back side of the substrate, heating of the substrate A controller configured to cause A system comprising **Claim 52** The system according to claim 51, wherein processing the front side of the substrate includes at least one process selected from the group consisting of developing a layer of photoresist, in-situ cleaning the substrate, withdrawing a mandrel in a patterning application, smoothing features on the substrate, and descumming the layer of photoresist. A system **Claim 53** The system according to claim 52, wherein the controller is configured to cause (a) by causing either (i) developing a layer of photoresist on the substrate or (ii) receiving a layer of photoresist developed on the front side of the substrate and the substrate having contamination on the back side of the substrate, The metal in the contamination originates from the layer of photoresist on the front side of the substrate, The post-treatment bake process of (b) is a post-development bake process that occurs when the layer of photoresist is at least partially developed. A system **Claim 54** The system according to claim 53, wherein both (a) and (b) occur in the same processing chamber. A system **Claim 55** The system according to claim 53, wherein (a) occurs in the processing chamber and (b) occurs in a second processing chamber, the second processing chamber being a different processing chamber from the processing chamber. A system **Claim 56** The system according to claim 53, further comprising a plasma generator configured to provide plasma in the processing chamber. A system **Claim 57** The system according to claim 56, wherein the plasma generator is a remote plasma generator such that the plasma is generated at a first location outside the processing chamber and delivered to a second location inside the processing chamber. A system

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