Semiconductor device

Abstract

To provide a thin film transistor including an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn), in which the contact resistance of a source electrode or a drain electrode is reduced, and a manufacturing method for the thin film transistor.SOLUTION: The ohmic contact is formed by intentionally providing a buffer layer with higher carrier concentration than an IGZO semiconductor layer between a source electrode layer and a drain electrode layer, and the IGZO semiconductor layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a circuit composed of thin film transistors (hereinafter referred to as TFTs) using an oxide semiconductor film in a channel formation region, and a method for manufacturing the same. For example, the present invention relates to an electronic device incorporating, as components, an electro-optical device typified by a liquid crystal display panel or a light-emitting display device having an organic light-emitting element. In addition, in this specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics, and an electro-optical device, a semiconductor circuit, and an electronic device are all semiconductor devices.

[0002]

Background Art

[0003] In recent years, active matrix display devices (liquid crystal display devices, light-emitting display devices, electrophoresis display devices ) provided with switching elements composed of TFTs for each display pixel arranged in a matrix have been actively developed. An active matrix display device is provided with a switching element for each pixel (or one dot ), and is advantageous because it can be driven at a low voltage when the pixel density is increased compared to the simple matrix method.

[0004] In addition, techniques for manufacturing thin film transistors (TFTs) using an oxide semiconductor film in a channel formation region and applying them to electronic devices and optical devices have attracted attention. For example, TFTs using zinc oxide (ZnO) as an oxide semiconductor film, and TFTs using InGaO3(ZnO) are mentioned. Techniques for forming these TFTs using an oxide semiconductor film on a light-transmissive substrate and using them as switching elements of an image display device are disclosed in Patent Document 1 and Patent Document 2. m

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] For thin film transistors using an oxide semiconductor film in the channel formation region, high operating speed, relatively simple manufacturing processes, and sufficient reliability are required. When forming a thin film transistor, source electrodes and drain electrodes are made of a low-resistance metal material. In particular, when manufacturing a display device for large-area display, the problem of signal delay due to the resistance of the wiring becomes prominent. Therefore, as materials for the wiring and electrodes, it is desirable to use a metal material with a low electrical resistance value. On the other hand, if a thin film transistor structure is adopted in which the source electrode and the drain electrode made of a metal material with a low electrical resistance value are in direct contact with the oxide semiconductor film, the contact resistance may increase. One of the factors causing the increase in contact resistance is considered to be the formation of a Schottky junction at the contact surface between the source electrode and the drain electrode and the oxide semiconductor film.

[0007] In addition, a capacitance is formed at the portion where the source electrode and the drain electrode are in direct contact with the oxide semiconductor film, and the frequency characteristics (referred to as f characteristics) deteriorate, which may prevent the high-speed operation of the thin film transistor.

[0008]

[0009] ​​​​​​​​​​Using an oxide semiconductor film containing indium (In), gallium (Ga), and zinc (Zn) In a thin film transistor using the same, reducing the contact resistance of the source electrode or the drain electrode is one of the problems to provide a thin film transistor and a method of manufacturing the same.

[0010] In addition, improving the operating characteristics and reliability of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is also one of the problems.

[0011] In addition, reducing the variation in electrical characteristics of a thin film transistor using an oxide semiconductor film containing In, Ga, and Zn is also one of the problems. In particular, in a liquid crystal display device, when the variation between individual elements is large, display unevenness may occur due to the variation in TFT characteristics .

[0012] In addition, also in a display device having a light emitting element, the on-current (I of a TFT (a TFT that supplies current to a light emitting element disposed in a driving circuit or a pixel) disposed so that a constant current flows through a pixel electrode ) has a large variation, there is a risk that the luminance variation occurs in the display screen on .

[0013] As described above, one aspect of the present invention aims to solve at least one of the above problems.

Means for Solving the Problems

[0014] One aspect of the present invention uses an oxide semiconductor film containing In, Ga, and Zn as a semiconductor layer, and includes a thin film transistor in which a buffer layer is provided between the semiconductor layer and the source electrode layer and the drain electrode layer. is the gist.

[0015] ​In this specification, a semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an "IGZO semiconductor layer". The semiconductor layer formed using an oxide semiconductor film containing In, Ga, and Zn is also referred to as an "IGZO semiconductor layer".

[0016] An ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. An ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. An ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. An ohmic contact is required between the source electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible. Similarly, an ohmic contact is required between the drain electrode layer and the IGZO semiconductor layer, and furthermore, it is desirable to reduce the contact resistance as much as possible.

[0017] Therefore, an ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer. Therefore, an ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer. Therefore, an ohmic contact is formed by intentionally providing a buffer layer having a higher carrier concentration than the IGZO semiconductor layer between the source electrode layer and the drain electrode layer and the IGZO semiconductor layer.

[0018] As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation. As the buffer layer, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. The buffer layer may contain an impurity element for imparting an n-type. As the impurity element, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment after film formation.

[0019] The buffer layer functions as an n+ layer and can also be called a drain region or a source region. The buffer layer functions as an n+ layer and can also be called a drain region or a source region.

[0020] In order to reduce the variation in the electrical characteristics of the thin film transistor, the IGZO semiconductor layer is amorphous. It is preferably in a fast state.

[0021] One form of the semiconductor device disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, and an n-type conductive buffer layer on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer. And a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer, and a semiconductor layer on the buffer layer. A part of the semiconductor layer overlapping the gate electrode layer is in contact with the gate insulating layer and is provided between the source electrode layer and the drain electrode layer. The semiconductor layer and the buffer layer are oxide semiconductor layers containing indium, gallium, and zinc. The carrier concentration of the buffer layer is higher than that of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer through the buffer layer.

[0022] One form of the present invention solves at least one of the above problems.

[0023] In the above configuration, further, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. In the above configuration, further, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer. - layer In the above configuration, further, a second buffer layer having a carrier concentration higher than that of the semiconductor layer and lower than that of the buffer layer may be provided between the semiconductor layer and the buffer layer. The second buffer layer functions as an n layer.

[0024] As the carrier concentration of the oxide semiconductor film (IGZO film) containing In, Ga, and Zn increases, the hole mobility also increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 25. In the present invention, the carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the semiconductor layer is less than 1×10 As the carrier concentration of the oxide semiconductor film (IGZO film) containing In, Ga, and Zn increases, the hole mobility also increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 25. In the present invention, the carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the semiconductor layer is less than 1×10 As the carrier concentration of the oxide semiconductor film (IGZO film) containing In, Ga, and Zn increases, the hole mobility also increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 25. In the present invention, the carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the semiconductor layer is less than 1×10 As the carrier concentration of the oxide semiconductor film (IGZO film) containing In, Ga, and Zn increases, the hole mobility also increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 25. In the present invention, the carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the semiconductor layer is less than 1×10 As the carrier concentration of the oxide semiconductor film (IGZO film) containing In, Ga, and Zn increases, the hole mobility also increases. Therefore, the relationship between the carrier concentration and the hole mobility of the oxide semiconductor film containing In, Ga, and Zn is as shown in FIG. 25. In the present invention, the carrier concentration range (channel concentration range 1) of the IGZO film suitable as the channel of the semiconductor layer is less than 1×10 17 atoms / cm 3 Less than (more preferably 1×10 11at oms / cm 3 Above), the carrier concentration range of the IGZO film suitable as the buffer layer (buffer layer concentration range 2) is 1×10 18 atoms / cm 3 or more (more preferably 1×10 2 2 atoms / cm 3 or less) is preferable. The carrier concentration of the above IGZO film is the semiconductor layer and When used as, at room temperature, the value in a state where source, drain, and gate voltages are not applied There is.

[0025] If the carrier concentration range of IGZO for the channel exceeds the above range, there is a risk of becoming normally on as a thin film transistor Therefore, by using an IGZO film within the above carrier concentration range as the channel of the semiconductor layer, a highly reliable thin film transistor can be obtained.

[0026] Also, it is preferable to use a titanium film for the source electrode layer and the drain electrode layer. For example, using a stack of a titanium film, an aluminum film, and a titanium film results in low resistance and few hillocks in the aluminum film

[0027] Also, the side surface of the source electrode layer and the side surface of the drain electrode layer facing the side surface are covered with a buffer layer. Therefore, the channel length L of the thin film transistor corresponds to the interval between the first buffer layer covering the source electrode layer and the second buffer layer covering the drain electrode layer.

[0028]

[0028] Also, the configuration of the invention for realizing the above structure is to form a gate electrode layer on a substrate, form a gate insulating layer on the gate electrode layer, and form a source electrode layer and a drain electrode on the gate insulating layer layer Form a polar layer, and form a buffer layer having an n-type conductivity type on the source electrode layer and the drain electrode layer Form a semiconductor layer on the buffer layer. The semiconductor layer and the buffer layer are formed using an oxide semiconductor layer containing indium , gallium, and zinc. The carrier concentration of the buffer layer is higher than the carrier concentration of the semiconductor layer, and the semiconductor layer is electrically connected to the source electrode layer and the drain electrode layer via the buffer layer. This is a method for manufacturing a semiconductor device.

[0029] In the above manufacturing method, a part of the semiconductor layer is in contact with the gate insulating layer overlapping the gate electrode layer and is formed between the source electrode layer and the drain electrode layer.

[0030] The semiconductor layer, the buffer layer having an n-type conductivity type, the source electrode layer, and the drain electrode layer may be formed by sputtering (sputtering method). The gate insulating layer and the semiconductor layer are formed in an oxygen atmosphere (or oxygen 90% or more, rare gas (argon) 10% or less), and the buffer layer having an n-type conductivity type is preferably formed in a rare gas (argon) atmosphere.

[0031] Sputtering methods include the RF sputtering method using a high-frequency power source for the sputtering power source and the DC sputtering method , and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film .

[0032] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and deposit different material films in the same chamber, or can simultaneously discharge and deposit a plurality of types of materials in the same chamber.

[0033] ​ Also, a sputtering apparatus using a magnetron sputtering method equipped with a magnet mechanism inside the chamber or an ECR sputtering method using plasma generated using microwaves without using glow discharge There is a sputtering apparatus using this method.

[0034] Also, as a film formation method using the sputtering method, a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, or a bias sputtering method in which a voltage is also applied to the substrate during film formation There is also.

[0035] Using these various sputtering methods, a semiconductor layer, a buffer layer having an n-type conductivity type, a source electrode layer and a drain electrode layer are formed.

Advantages of the Invention

[0036] According to the present invention, a thin film transistor with low photocurrent, small parasitic capacitance, and high on / off ratio can be obtained, and a thin film transistor with good dynamic characteristics can be fabricated. Therefore, a semiconductor device having a thin film transistor with high electrical characteristics and high reliability can be provided .

Brief Description of the Drawings

[0037]

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Embodiments for Carrying Out the Invention

[0038] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is described in the following It is not limited to this, and those skilled in the art can easily understand that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the present invention described below, the same reference numerals are used in common between different drawings for the same part or parts having similar functions, and the

[0039] (Embodiment 1) In this embodiment, a thin film transistor and its manufacturing process will be described with reference to FIGS. 1 and 2.

[0040] Thin film transistors 171a and 171b, which are a type of bottom gate structure (also called a bottom contact structure) of this embodiment, are shown in FIGS. 1 and 2. FIG. 1(A) is a plan view, and FIG. 1 (B) is a cross-sectional view taken along line A1 - A2 in FIG. 1(A).

[0041] In FIG. 1, on a substrate 100, there are provided a gate electrode layer 101, a gate insulating layer 102, a source electrode layer or drain electrode layers 105a, 105b, buffer layers 104a, 104b having an n-type conductivity type, and a thin film transistor 171a having a semiconductor layer 103.

[0042] An oxide semiconductor film containing In, Ga, and Zn is used as the semiconductor layer 103, and between the source electrode layer or drain electrode layers 105a, 105b and the semiconductor layer 103 which is an IGZO semiconductor layer, buffer layers 104a, 104b having a higher carrier concentration than the semiconductor layer 103 are intentionally provided to form an ohmic contact.

[0043] As the buffer layers 104a and 104b, an oxide semiconductor film containing In, Ga, and Zn having an n-type conductivity type is used. Impurity elements that impart an n-type may be included in the buffer layers 104a and 104b. As the impurity elements, for example, magnesium, aluminum, titanium, iron, tin, calcium, germanium, scandium, yttrium, zirconium, hafnium, boron, thallium, lead, etc. can be used. When magnesium, aluminum, titanium, etc. are included in the buffer layer, there is an oxygen blocking effect, etc., and the oxygen concentration of the semiconductor layer can be maintained within an optimal range by heat treatment, etc. after film formation. In the present invention, the carrier concentration range of the semiconductor layer is less than 1×10 atoms / cm (more preferably 1×10 or more), and the carrier concentration range of the buffer layer

[0044] is preferably 1×10 17 atoms / cm 3 or more (1×10 or less). 11 atoms / cm 3 If the carrier concentration range of the IGZO film for the channel exceeds the above range, there is a risk of becoming a normally-on thin film transistor. Therefore, by using an IGZO film within the above carrier concentration range as the channel of the semiconductor layer, a highly reliable thin film transistor can be obtained. is preferably 18 atoms / cm 3 or more (1×10 22 atoms / cm 3 or less).

[0045] When a second buffer layer having a lower carrier concentration than the buffer layer functioning as an n-layer and a higher carrier concentration than the semiconductor layer is provided between the semiconductor layer and the buffer layer, the second buffer layer

[0046] The carrier concentration of the α layer may be set within the concentration range between the carrier concentrations of the semiconductor layer and the buffer layer. Yes.

[0047] The buffer layers 104a and 104b function as n+ layers and can also be referred to as the drain region or the source region. Yes.

[0048] The manufacturing method of the thin film transistor 171a in FIGS. 1(A) and 1(B) will be described with reference to FIGS. 3(A) to (E). ) is used for the description.

[0049] A gate electrode layer 101, a gate insulating layer 102, and a conductive film 117 are formed on the substrate 100 (see FIG. 3(A)). The substrate 100 may be a barium borosilicate glass, an aluminoborosilicate glass, or an aluminosilicate glass, etc., an alkali-free glass substrate, a ceramic substrate, or a plastic substrate having heat resistance capable of withstanding the processing temperature of this manufacturing process. Alternatively, a substrate having an insulating film provided on the surface of a metal substrate such as a stainless alloy may be applied. The size of the substrate 100 may be 320 mm × 400 mm, 370 mm × 470 mm, 550 mm × 650 mm, 600 mm × 720 mm, 680 mm × 880 mm, 730 mm × 920 mm, 1000 mm × 1200 mm, 1100 mm × 1250 mm, 1150 mm × 1300 mm, 1500 mm × 1800 mm, 1900 mm × 2200 mm, 2160 mm × 2460 mm, 2400 mm × 2800 mm, or 2850 mm × 3050 mm, etc. Yes. Yes. Yes. Yes. Yes. Yes. Yes. Yes. Yes. Yes.

[0050] An insulating film may also be formed as an underlayer film on the substrate 100. As the underlayer film, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film may be used by using a CVD method, a sputtering method, or the like. Yes. It may be formed of a single layer or a laminate of films.

[0051] The gate electrode layer 101 is formed using a metal material such as titanium, molybdenum, chromium, tantalum, tungsten, aluminum neodymium or an alloy material thereof. The gate electrode layer 101 is formed by forming a conductive film on the substrate 100 by sputtering or vacuum evaporation, forming a mask on the conductive film by photolithography technology or an inkjet method, and etching the conductive film using the mask. Also, a conductive nanoparticle such as silver, gold, or copper is ejected and fired by an inkjet method using a conductive nanoparticle to form the gate electrode layer 101. In addition, a nitride film of the above metal material may be provided between the substrate 100 and the gate electrode layer 101 as a barrier metal for improving the adhesion of the gate electrode layer 101 and preventing diffusion of the material of the gate electrode layer 101 into the substrate or the underlying film. Further, the gate electrode layer 101 may have a single-layer structure or a laminated structure. For example, a laminate of a molybdenum film and an aluminum film, a laminate of a molybdenum film, an aluminum and neodymium alloy film, a laminate of a titanium film and an aluminum film, a laminate of a titanium film, an aluminum film, and a titanium film, etc. may be used starting from the substrate 100 side. Also, the gate electrode layer 101 may have a single-layer structure or a laminated structure. For example, a laminate of a molybdenum film and an aluminum film, a laminate of a molybdenum film, an aluminum and neodymium alloy film, a laminate of a titanium film and an aluminum film, a laminate of a titanium film, an aluminum film, and a titanium film, etc. may be used starting from the substrate 100 side. film, a laminate of a titanium film, an aluminum film, and a titanium film, etc. may be used starting from the substrate 100 side. film, a laminate of a titanium film, an aluminum film, and a titanium film, etc. may be used starting from the substrate 100 side. .

[0052] Since a semiconductor film or wiring is formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent steps. Since a semiconductor film or wiring is formed on the gate electrode layer 101, it is desirable to process the end portion so that it has a tapered shape to prevent steps.

[0053] The gate insulating layer 102 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film using a CVD method, a sputtering method, or the like. The thin film transistor 171b shown in FIG. 2 is an example in which the gate insulating layer 102 is laminated. The gate insulating layer 102 can be formed of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film using a CVD method, a sputtering method, or the like. The thin film transistor 171b shown in FIG. 2 is an example in which the gate insulating layer 102 is laminated. The thin film transistor 171b shown in FIG. 2 is an example in which the gate insulating layer 102 is laminated.

[0054] As the gate insulating layer 102, a silicon nitride film or a silicon oxynitride film, and a silicon oxide film or a silicon nitride film can be laminated in this order. Note that instead of forming a two-layer gate insulating layer, a silicon nitride film or a silicon oxynitride film, a silicon oxide film or a silicon oxynitride film, and a silicon nitride film or a silicon oxynitride film can be laminated in three layers in this order from the substrate side. Also, the gate insulating layer can be formed of a single layer of a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride oxide film. Moreover, it is preferable to form the gate insulating layer 102 in an oxygen atmosphere (or an atmosphere of 90% or more oxygen and 10% or less rare gas (such as argon or helium)). Also, as the gate insulating layer 102, a silicon nitride film may be formed on the gate electrode layer 101 by plasma CVD method, and a silicon oxide film may be laminated on the silicon nitride film by sputtering method. A silicon nitride film and a silicon oxide film may be laminated in order on the gate electrode layer 101 by plasma CVD method, and a silicon oxide film may be further laminated on the silicon oxide film by sputtering method.

[0055] In this specification, the silicon oxynitride film means that, in terms of its composition, the oxygen content is higher than the nitrogen content, and when measured using Rutherford Backscattering Spectrometry (RBS) and Hydrogen Forward Scattering (HFS), the concentration range is such that oxygen is 50 to 70 atomic %, nitrogen is 0.5 to 15 atomic %, and Si is 25 to 35 atomic %.

[0056]

[0057] ​​​​​​​​​​refers to those containing hydrogen in the range of 0.1 to 10 atomic %. Also, the silicon oxynitride film means that in terms of its composition, the nitrogen content is higher than that of oxygen, and when measured using RBS and HFS, as the concentration range, oxygen is contained in the range of 5 to 30 atomic %, nitrogen is contained in the range of 20 to 55 atomic %, S i is contained in the range of 25 to 35 atomic %, and hydrogen is contained in the range of 10 to 30 atomic %. However, when the total of the atoms constituting the silicon oxynitride film or the silicon nitride oxide film is 100 atomic %, the content ratios of nitrogen, oxygen, Si, and hydrogen shall be within the above ranges.

[0058] Also, as the gate insulating layer 102, one or at least two kinds of compounds containing one or more of oxides, nitrides, oxynitrides, or nitroxides of aluminum, yttrium, or hafnium can also be used.

[0059] Also, the gate insulating layer 102 may contain a halogen element such as chlorine or fluorine. The concentration of the halogen element in the gate insulating layer 102 may be 1×10 atoms 15 / cm 3 or more and 1×10 20 atoms / cm 3 or less at the concentration peak.

[0060] The conductive film 117 is preferably formed of a single layer or a laminate of aluminum or an aluminum alloy added with a heat resistance improving element or a hillock preventing element such as copper, silicon, titanium, neodymium, scandium, or molybdenum. Also, the film on the side in contact with the semiconductor film having an n-type conductivity type formed in a later process is formed of titanium, tantalum, molybdenum, tungsten, or a nitride of these elements, and aluminum or an aluminum alloy is formed thereon. It may also be a laminated structure in which gold is formed. Further, it may be a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched by titanium, tantalum, molybdenum, tungsten, or nitrides of these elements. Here, as the conductive film 117, a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used. Using a laminate of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur in the aluminum film. The conductive film 117 is formed by a sputtering method or a vacuum evaporation method. Also, the conductive film 117 may be formed by discharging and baking using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as silver, gold, or copper. Next, a mask 118 is formed on the conductive film 117, and the conductive film 117 is processed by etching using the mask 118 to form the source electrode layer or the drain electrode layers 105a, 105b (see Fig. 3(B)).

[0061] Next, the mask 118 is removed, and a semiconductor film having an n-type conductivity type, which is an oxide semiconductor film containing In, Ga, and Zn, is formed on the source electrode layer or the drain electrode layers 105a, 105b. For example, IGZO may be used as the first target, and a material having an n-type conductivity type may be used as the second target, and a mixed film may be formed by simultaneously using a sputtering method (co-sputtering) and used as a buffer layer. Here, the upper and side surfaces of the source electrode layer or the drain electrode layers 105a, 105b are covered with a semiconductor film having an n-type conductivity type, and the semiconductor film having an n-type conductivity type is the source electrode layer or the drain electrode layer.

[0062] It may be a laminated structure. Further, it may be a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched by titanium, tantalum, molybdenum, tungsten, or nitrides of these elements. Here, as the conductive film 117, a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used. Using a laminate of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur in the aluminum film. The conductive film 117 is formed by a sputtering method or a vacuum evaporation method. Also, the conductive film 117 may be formed by discharging and baking using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as silver, gold, or copper.

[0063] Next, a mask 118 is formed on the conductive film 117, and the conductive film 117 is processed by etching using the mask 118 to form the source electrode layer or the drain electrode layers 105a, 105b (see Fig. 3(B)). Next, the mask 118 is removed, and a semiconductor film having an n-type conductivity type, which is an oxide semiconductor film containing In, Ga, and Zn, is formed on the source electrode layer or the drain electrode layers 105a, 105b. For example, IGZO may be used as the first target, and a material having an n-type conductivity type may be used as the second target, and a mixed film may be formed by simultaneously using a sputtering method (co-sputtering) and used as a buffer layer. Here, the upper and side surfaces of the source electrode layer or the drain electrode layers 105a, 105b are covered with a semiconductor film having an n-type conductivity type, and the semiconductor film having an n-type conductivity type is the source electrode layer or the drain electrode layer.

[0064] Next, the mask 118 is removed, and a semiconductor film having an n-type conductivity type, which is an oxide semiconductor film containing In, Ga, and Zn, is formed on the source electrode layer or the drain electrode layers 105a, 105b. For example, IGZO may be used as the first target, and a material having an n-type conductivity type may be used as the second target, and a mixed film may be formed by simultaneously using a sputtering method (co-sputtering) and used as a buffer layer. Here, the upper and side surfaces of the source electrode layer or the drain electrode layers 105a, 105b are covered with a semiconductor film having an n-type conductivity type, and the semiconductor film having an n-type conductivity type is the source electrode layer or the drain electrode layer. It may be a laminated structure. Further, it may be a laminated structure in which the upper and lower surfaces of aluminum or an aluminum alloy are sandwiched by titanium, tantalum, molybdenum, tungsten, or nitrides of these elements. Here, as the conductive film 117, a laminated conductive film of a titanium film, an aluminum film, and a titanium film is used. Using a laminate of a titanium film, an aluminum film, and a titanium film results in low resistance and makes it difficult for hillocks to occur in the aluminum film. The conductive film 117 is formed by a sputtering method or a vacuum evaporation method. Also, the conductive film 117 may be formed by discharging and baking using a screen printing method, an inkjet method, etc. with a conductive nanopaste such as silver, gold, or copper. Next, a mask 118 is formed on the conductive film 117, and the conductive film 117 is processed by etching using the mask 118 to form the source electrode layer or the drain electrode layers 105a, 105b (see Fig. 3(B)). Next, the mask 118 is removed, and a semiconductor film having an n-type conductivity type, which is an oxide semiconductor film containing In, Ga, and Zn, is formed on the source electrode layer or the drain electrode layers 105a, 105b. For example, IGZO may be used as the first target, and a material having an n-type conductivity type may be used as the second target, and a mixed film may be formed by simultaneously using a sputtering method (co-sputtering) and used as a buffer layer. Here, the upper and side surfaces of the source electrode layer or the drain electrode layers 105a, 105b are covered with a semiconductor film having an n-type conductivity type, and the semiconductor film having an n-type conductivity type is the source electrode layer or the drain The electrode layers 105a and 105b can be protected.

[0065] Next, a mask 116 is formed on the semiconductor film having n-type conductivity. The semiconductor film having n-type conductivity is processed by etching, and n-type semiconductor layers 115a, 1 15b is formed (see FIG. 3(C)). In this embodiment, the source or drain electrode layer 1 In order to protect 05a and 105b, a source electrode layer or The pattern shape covers the drain electrode layers 105a and 105b. The source electrode layer 105a and the drain electrode layer 105b may have a pattern shape other than that shown in FIG. At least the side surface close to the gate electrode is covered with a semiconductor film having n-type conductivity. However, the side surface far from the gate electrode does not have to be covered. In the drain electrode layers 105a and 105b, the side surface close to the gate electrode is of n-type conductivity. If the semiconductor film is not covered with the IGZO film, the side surface is in direct contact with the IGZO film that forms the channel. As a result, a Schottky junction is formed, which may increase the contact resistance.

[0066] Also, an n-type semiconductor formed by etching a semiconductor film having an n-type conductivity The distance between the layers 115a and 115b is the channel length of the thin film transistor. If the distance between 15a and 115b is constant and the distance is located above the gate electrode, Even if misalignment occurs, the electrical characteristics can be kept almost the same, eliminating the variation in thin-film transistors. In addition, the gap between the n-type semiconductor layers 115a and 115b can be reduced by etching. The conventional thin film transistor has a source electrode layer and The distance between the drain electrode layers becomes the channel length, but a metal film or hillock with high conductivity is likely to occur. Since a metal film with high conductivity is used, if the distance between the source electrode layer and the drain electrode layer is made narrow, there is a risk of short - circuiting. There was a risk of short - circuiting.

[0067] Next, the mask 116 is removed, and the semiconductor film 111 is formed on the n - type semiconductor layers 115a and 115b (see Fig. 3(D)). (See Fig. 3(D).)

[0068] As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn is formed. For example, as the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn may be formed with a film thickness of 50 nm using a sputtering method. The semiconductor film 111 is preferably formed in an oxygen atmosphere (or an atmosphere containing 90% or more oxygen and 10% or less rare gas (such as argon or helium)). As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn may be formed with a film thickness of 50 nm using a sputtering method. The semiconductor film 111 is preferably formed in an oxygen atmosphere (or an atmosphere containing 90% or more oxygen and 10% or less rare gas (such as argon or helium)). As the semiconductor film 111, an oxide semiconductor film containing In, Ga, and Zn may be formed with a film thickness of 50 nm using a sputtering method. The semiconductor film 111 is preferably formed in an oxygen atmosphere (or an atmosphere containing 90% or more oxygen and 10% or less rare gas (such as argon or helium)). 。

[0069] As other film - forming methods for oxide semiconductor films such as the semiconductor film 111 and the semiconductor film having an n - type conductivity type, vapor - phase methods such as pulsed laser deposition (PLD) method and electron beam evaporation method can be used. Among the vapor - phase methods, the PLD method is suitable in terms of easily controlling the composition of the material system, and the sputtering method is suitable in terms of mass - productivity as described above. As other film - forming methods for oxide semiconductor films such as the semiconductor film 111 and the semiconductor film having an n - type conductivity type, vapor - phase methods such as pulsed laser deposition (PLD) method and electron beam evaporation method can be used. Among the vapor - phase methods, the PLD method is suitable in terms of easily controlling the composition of the material system, and the sputtering method is suitable in terms of mass - productivity as described above. As other film - forming methods for oxide semiconductor films such as the semiconductor film 111 and the semiconductor film having an n - type conductivity type, vapor - phase methods such as pulsed laser deposition (PLD) method and electron beam evaporation method can be used. Among the vapor - phase methods, the PLD method is suitable in terms of easily controlling the composition of the material system, and the sputtering method is suitable in terms of mass - productivity as described above. As other film - forming methods for oxide semiconductor films such as the semiconductor film 111 and the semiconductor film having an n - type conductivity type, vapor - phase methods such as pulsed laser deposition (PLD) method and electron beam evaporation method can be used. Among the vapor - phase methods, the PLD method is suitable in terms of easily controlling the composition of the material system, and the sputtering method is suitable in terms of mass - productivity as described above.

[0070] As a specific example of the film - forming conditions for the semiconductor film 111, using an 8 - inch - diameter oxide semiconductor target containing In, Ga, and Zn, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the direct - current (DC) power supply is 0.5 kW, and film formation can be performed in an argon or oxygen atmosphere. As a specific example of the film - forming conditions for the semiconductor film 111, using an 8 - inch - diameter oxide semiconductor target containing In, Ga, and Zn, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the direct - current (DC) power supply is 0.5 kW, and film formation can be performed in an argon or oxygen atmosphere. As a specific example of the film - forming conditions for the semiconductor film 111, using an 8 - inch - diameter oxide semiconductor target containing In, Ga, and Zn, the distance between the substrate and the target is 170 mm, the pressure is 0.4 Pa, the direct - current (DC) power supply is 0.5 kW, and film formation can be performed in an argon or oxygen atmosphere. Also, when using a pulsed direct - current (DC) power supply, dust can be reduced, and the film - thickness distribution becomes uniform, which is preferable. Also, when using a pulsed direct - current (DC) power supply, dust can be reduced, and the film - thickness distribution becomes uniform, which is preferable.

[0071] Next, a mask 113 for processing the semiconductor film 111 is formed (see Fig. 3(E)). The mask The semiconductor layer 103 can be formed by etching the semiconductor film 111 using 113. This can be done.

[0072] Also, the buffer layers 104a and 104b are formed by etching using the same mask 113. Therefore, as shown in Fig. 1, the ends of the semiconductor layer 103 and the ends of the buffer layers 104a and 10 4b have substantially the same shape. Note that for etching IGZO semiconductor films such as the semiconductor film 111 and the n-type semiconductor layers 115a, 115b, organic acids such as citric acid and oxalic acid can be used as the etchant. For example, a 50-nm semiconductor film 111 can be etched in 150 seconds using ITO07N (manufactured by Kanto Chemical Co., Inc.).

[0073] Also, by etching the end of the semiconductor layer 103 into a shape having a taper, disconnection of the wiring due to a step shape can be prevented.

[0074] After that, the mask 113 is removed. Through the above steps, the thin-film transistor 171a can be formed . Note that the channel length L of the thin-film transistor 171a corresponds to the interval between the n-type semiconductor layers 1 15a and 115b (the interval between the buffer layers 104a and 104b). Therefore, without changing the interval between the n-type semiconductor layers 115a and 115b, the interval between the source electrode layer or the drain electrode layer 1 05a and 105b can be widened. By widening the interval between the source electrode layer or the drain electrode layer 10 5a and 105b, it is possible to prevent the occurrence of hillocks and short circuits between the source electrode layer and the drain electrode layer. Also, the source electrode layer or the drain By widening the distance between the in electrodes 105a and 105b, the area overlapping with the gate electrode can be reduced, and the parasitic capacitance with the gate electrode can be reduced, so that good electrical characteristics, such as high frequency characteristics (referred to as f characteristics), can be achieved in the thin film transistor.

[0075] Furthermore, an insulating film may be formed as a protective film on the thin film transistor 171a. The protective film can be formed in the same manner as the gate insulating layer. Note that the protective film is for preventing the intrusion of contaminating impurities such as organic substances, metal substances, and water vapor floating in the air, and a dense film is preferred. For example, a laminate of a silicon oxide film and a silicon nitride film may be formed as the protective film on the thin film transistor 171a.

[0076] Also, the oxide semiconductor films such as the semiconductor layer 103 and the buffer layers 104a and 104b are preferably heat-treated after film formation. The heat treatment may be performed at any step as long as it is after film formation but can be performed immediately after film formation, after the formation of the protective film, etc. Also, it may be combined with other heat treatments. The heat treatment temperature may be 300°C or higher and 400°C or lower, preferably 350°C. The heat treatment may be performed multiple times in a separate process for the semiconductor layer 103 and the buffer layers 104a and 104b.

[0077] Also, the manufacturing process of the thin film transistor 171b shown in FIG. 2 will be described with reference to FIG. 3. Note that the manufacturing process of the thin film transistor 171b shown in FIG. 2 is only partially different from that of the thin film transistor 171a in FIG. 1(B), and that part will be described below.

[0078] In FIG. 2, compared with FIG. 1(B), the gate insulating layer 102 has two layers, and the buffer layer The difference lies in that the position of the end portion is different from the position of the end portion of the semiconductor layer.

[0079] When etching using the mask 113 shown in FIG. 3(E), only the semiconductor layer 103 is selectively etched, and when the n-type semiconductor layers 115a and 115b are left remaining, the thin-film transistor 171b shown in FIG. 2 can be obtained. In FIG. 2, the n-type semiconductor layers 115a and 115b function as buffer layers. Further, when an interlayer insulating film is further formed on the thin-film transistor 171b and wiring is formed on the interlayer insulating film, even when the n-type semiconductor layers 115a and 115b remain at the bottom of the contact hole, good electrical connection can be made between the wiring, the source electrode layer, and the drain electrode layer.

[0080] In this embodiment, a thin-film transistor having a stacked structure of a gate electrode layer, a gate insulating layer, a source electrode layer, a drain electrode layer, a buffer layer (an oxide semiconductor layer containing In, Ga, and Zn and having an n-type conductivity type), and a semiconductor layer (an oxide semiconductor layer containing In, Ga, and Zn) is used. By using a buffer layer with a high carrier concentration such as an oxide semiconductor layer having an n-type conductivity type containing In, Ga, and Zn, the film thickness of the semiconductor layer can be made thin while suppressing the parasitic capacitance. Note that even if the buffer layer is thin, since the ratio with respect to the gate insulating layer is sufficient, the parasitic capacitance is sufficiently suppressed.

[0081] According to this embodiment, a thin-film transistor with low photocurrent, small parasitic capacitance, and a high on-off ratio can be obtained, and a thin-film transistor having good dynamic characteristics can be fabricated. Thus, a semiconductor device having a thin-film transistor with high electrical characteristics and high reliability can be provided. ​

[0082] (Embodiment 2) This embodiment is an example of a thin-film transistor with a multi-gate structure according to one form of the present invention. Therefore, the other operations can be performed in the same manner as in Embodiment 1, and descriptions of the same parts or parts having similar functions as those in Embodiment 1, and repetitive descriptions of processes are omitted.

[0083] In this embodiment, a thin-film transistor used in a semiconductor device will be described with reference to FIGS. 4(A)(B ), and FIGS. 5(A)(B).

[0084] FIG. 4(A) is a plan view showing a thin-film transistor, and FIG. 4(B) corresponds to a cross-sectional view showing the thin-film transistor 172a taken along line E1-E2 in FIG. 4(A).

[0085] As shown in FIGS. 4(A)(B), a multi-gate structure thin-film transistor 172a including a gate electrode layer 151a, 151b, a gate insulating layer 152, a source electrode layer or a drain electrode layer 155a, 155b, buffer layers 1 54a, 154b, 154c, and channel formation regions 153a, 153b of a semiconductor layer is provided on a substrate 150. In the multi-gate structure thin-film transistor 172a, the first channel length L1 corresponds to the interval between the buffer layers 154a, 154c, and the second channel length L2 corresponds to the interval between the buffer layers 154b, 154c.

[0086] The channel formation regions 153a, 153b of the semiconductor layer are oxide semiconductor layers containing In, Ga, and Zn, and the buffer layers 154a, 154b, 154c are n-type conductive oxide semiconductor layers containing In , Ga, and Zn. The source region or the drain region (n+ layer) The buffer layers 154a and 154b that function as [description not provided] have a higher carrier concentration than the channel formation regions 153a and 153b of the semiconductor layer.

[0087] The channel formation region 153a of the semiconductor layer and the channel formation region 153b of the semiconductor layer are electrically connected. Also, the channel formation region 153a of the semiconductor layer is connected to the source electrode layer or the drain electrode layer 155a via the buffer layer 154a, and the channel formation region 153 of the semiconductor layer is electrically connected to the source electrode layer or the drain electrode layer 155b via the buffer layer 154b. b is electrically connected to the source electrode layer or the drain electrode layer 155b via the buffer layer 154b. continue.

[0088] FIG. 5 shows a thin film transistor 172b having a multi-gate structure of another configuration. FIG. 5(A) is a plan view showing the thin film transistor 172b, and FIG. 5(B) corresponds to a cross-sectional view showing the thin film transistor 172b along line F 1-F2 in FIG. 5(A). In the thin film transistor 172b of FIG. 5, the semiconductor layer is divided into a plurality of parts, and a wiring layer 156 formed in the same process as the source electrode layer or the drain electrode layer 155a, 155b is provided, and the semiconductor layer 153c and the semiconductor layer 153d are electrically connected by the wiring layer 156 via the buffer layers 154c and 154d. are electrically connected by the wiring layer 156 via the buffer layers 154c and 154d. connected.

[0089] In the thin film transistor 172b having a multi-gate structure, the first channel length L1 is corresponding to the interval between the buffer layers 154a and 154c, and the second channel length L2 is the interval between the buffer layers 154b and 154d.

[0090] Thus, in the thin film transistor having a multi-gate structure according to one embodiment of the present invention, the semiconductor layer formed on each gate electrode layer may be provided continuously, or the buffer layer and the wiring layer A plurality of semiconductor layers may be electrically connected and provided via, for example.

[0091] The thin film transistor with a multi-gate structure according to one embodiment of the present invention has a small off-current, and a semiconductor device including such a thin film transistor can impart high electrical characteristics and high reliability.

[0092] In the present embodiment, as a multi-gate structure, an example of a gate electrode layer having two double-gate structures is shown. However, one embodiment of the present invention can also be applied to a triple-gate structure having more gate electrode layers.

[0093] The present embodiment can be implemented in appropriate combination with other embodiments.

[0094] (Embodiment 3) In the present embodiment, in a display device which is an example of a semiconductor device according to one embodiment of the present invention, an example of manufacturing at least a part of a drive circuit and a thin film transistor disposed in a pixel portion on the same substrate will be described below.

[0095] The thin film transistor disposed in the pixel portion is formed according to Embodiment 1 or Embodiment 2. Further, since the thin film transistor shown in Embodiment 1 or Embodiment 2 is an n-channel type TFT, a part of the drive circuit that can be configured by n-channel type TFTs in the drive circuit is formed on the same substrate as the thin film transistor in the pixel portion.

[0096] An example of a block diagram of an active matrix liquid crystal display device which is an example of a semiconductor device according to one embodiment of the present invention is shown in Fig. 6(A). The display device shown in Fig. 6(A) includes a pixel portion 5301 having a plurality of pixels each including a display element on a substrate 5300, and a scanning line drive circuit 530 for selecting each pixel. ​​​​​​​​​​​ It has 2 and a signal line driving circuit 5303 that controls the input of a video signal to a selected pixel. It does.

[0097] Also, the thin film transistor shown in any one of Embodiment 1 or Embodiment 2 is an n-channel type TFT, and the signal line driving circuit composed of n-channel type TFTs will be described with reference to FIG. 7. It will be described.

[0098] The signal line driving circuit shown in FIG. 7 includes a driver IC 5601, a switch group 5602_1 to 560 2_M, a first wiring 5611, a second wiring 5612, a third wiring 5613, and wirings 562 1_1 to 5621_M. Each of the switch groups 5602_1 to 5602_M includes a first thin film transistor 5603a, a second thin film transistor 5603b, and a third thin film transistor 5603c.

[0099] The driver IC 5601 is connected to the first wiring 5611, the second wiring 5612, the third wiring 5613 and the wirings 5621_1 to 5621_M. And each of the switch groups 5602_1 to 5602_M is connected to the first wiring 5611, the second wiring 5612, the third wiring 561 3 and the wirings 5621_1 to 5621_M corresponding to each of the switch groups 5602_1 to 5602_M. And each of the wirings 5621_1 to 5621_M is connected to three signal lines via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c. For example, the wiring 5621 _J in the J-th column (any one of the wirings 5621_1 to 5621_M) is the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603c included in the switch group 5602 _J. It has. and via the third thin film transistor 5603c, are connected to the signal line Sj-1, the signal line Sj, and the signal line S j+1.

[0100] Note that signals are input to the first wiring 5611, the second wiring 5612, and the third wiring 5613, respectively.

[0101] Note that the driver IC 5601 is preferably formed on a single crystal substrate. Further, the switch groups 5602_1 to 5602_M are preferably formed on the same substrate as the pixel portion. Therefore, the driver IC 5601 and the switch groups 5602_1 to 5602_ M may be connected via an FPC or the like.

[0102] Next, the operation of the signal line driving circuit shown in FIG. 7 will be described with reference to the timing chart of FIG. 8. The timing chart of FIG. 8 shows the timing when the scanning line Gi in the i-th row is selected. Further, the selection period of the scanning line Gi in the i-th row is divided into the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3. Further, the signal line driving circuit in FIG. 7 operates in the same manner as FIG. 8 even when the scanning lines of other rows are selected.

[0103] Note that the timing chart of FIG. 8 shows the case where the wiring 5621_J in the J-th column is connected to the signal line Sj-1, the signal line Sj, and the signal line Sj+1 via the first thin film transistor 5603a, the second thin film transistor 5603b, and the third thin film transistor 5603 c.

[0104] Note that the timing chart of FIG. 8 shows the timing when the scanning line Gi in the i-th row is selected, the first ​​​​​​​​​The on / off timing 5703a of the thin film transistor 5603a, the on / off timing 5703b of the second thin film transistor 5603b, the on / off timing 5703c of the third thin film transistor 5603c, and the signal 5721_J input to the wiring 5621_J in the J-th column are shown. For the wirings 5621_1 to 5621_M, different video signals are input during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, respectively. For example, the video signal input to the wiring 5621_J during the first sub-selection period T1 is input to the signal line Sj-1, the video signal input to the wiring 5621_J during the second sub-selection period T2 is input to the signal line Sj, and the video signal input to the wiring 5621_J during the third sub-selection period T3 is input to the signal line Sj+1. Furthermore, let the video signals input to the wiring 5621_J during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3 be Data_j-1, Data_j, and Data_j+1, respectively.

[0105] As shown in FIG. 8, during the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the video signal input to the wiring 5621_J is input to the signal line Sj. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the video signal input to the wiring 5621_J is input to the signal line Sj+1. Furthermore, during the first sub-selection period T1, the second sub-selection period T2, and the third sub-selection period T3, let the video signals input to the wiring 5621_J be Data_j-1, Data_j, and Data_j+1, respectively.

[0106] As shown in FIG. 8, during the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, the video signal input to the wiring 5621_J is input to the signal line Sj. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, the video signal input to the wiring 5621_J is input to the signal line Sj+1. ​The resulting Data_j is input to the signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 via the third thin film transistor 5603c.

[0107] From the above, the signal line driving circuit in FIG. 7 divides one gate selection period into three, so that a video signal can be input from one wiring 5621 to three signal lines during one gate selection period. Therefore, the signal line driving circuit in FIG. 7 can reduce the number of connections between the substrate on which the driver IC 5601 is formed and the substrate on which the pixel portion is formed to about 1 / 3 compared to the number of signal lines. By reducing the number of connections to about 1 / 3, the signal line driving circuit in FIG. 7 can

[0108] improve reliability, yield, etc. Note that as shown in FIG. 7, if one gate selection period is divided into a plurality of sub-selection periods, and a video signal can be input from one wiring to each of a plurality of signal lines

[0109] in each of the plurality of sub-selection periods, the arrangement, number, and driving method of the thin film transistors are not limited. For example, when a video signal is input from one wiring to each of three or more signal lines in each of three or more sub-selection periods, thin film transistors and wiring for controlling It is desirable to be divided into three sub-selection periods.

[0110] As another example, as shown in the timing chart of FIG. 9, one selection period can be divided into a pre-charge period Tp, a first sub-selection period T1, a second sub-selection period T2, and a third sub-selection period T3. Furthermore, the timing chart of FIG. 9 shows the timing at which the scanning line Gi in the i-th row is selected, the on / off timing 5803a of the first thin film transistor 5603a, the on / off timing 5803b of the second thin film transistor 5603b, the on / off timing 5803c of the third thin film transistor 5603c, and the signal 5821_J input to the wiring 5621_J in the J-th column. As shown in FIG. 9, during the pre-charge period Tp, the first thin film transistor 5603a, the second thin film transistor 5603b and the third thin film transistor 5603c are turned on. At this time, the pre-charge voltage Vp input to the wiring 5621_J is input to the signal lines Sj-1, Sj, and Sj+1 through the first thin film transistor 5603a, the second thin film transistor 5603b and the third thin film transistor 5603c respectively. During the first sub-selection period T1, the first thin film transistor 5603a is turned on, and the second thin film transistor 5603b and the third thin film transistor 5603c are turned off. At this time, Data_j-1 input to the wiring 5621_J is input to the signal line Sj-1 through the first thin film transistor 5603a. During the second sub-selection period T2, the second thin film transistor 5603b is turned on, and the first thin film transistor 5603a and the third thin film transistor 5603c are turned off. At this time, Data_j input to the wiring 5621_J is input to the signal line Sj through the second thin film transistor 5603b. During the third sub-selection period T3, the third thin film transistor 5603c is turned on, and the first thin film transistor 5603a and the second thin film transistor 5603b are turned off. At this time, Data_j+1 input to the wiring 5621_J is input to the signal line Sj+1 through the third thin film transistor 5603c. Data_j input to wiring 5621_J is input to signal line Sj via the second thin film transistor 5603b. In the third sub-selection period T3, the third thin film transistor 5 603c turns on, and the first thin film transistor 5603a and the second thin film transistor 56 03b turn off. At this time, Data_j+1 input to wiring 5621_J is input to signal line Sj+1 via the third thin film transistor 5603c.

[0111] From the above, the signal line driving circuit of FIG. 7 to which the timing chart of FIG. 9 is applied can pre-charge the signal line by providing a pre-charge selection period before the sub-selection period, so that the video signal can be written to the pixel at high speed. In FIG. 9, for those similar to FIG. 8, common reference numerals are used, and detailed descriptions of the same parts or parts having the same functions are omitted. Next, the configuration of the scanning line driving circuit will be described. The scanning line driving circuit has a shift register and a buffer. In some cases, it may also have a level shifter. In the scanning line driving

[0112] circuit, a selection signal is generated when a clock signal (CLK) and a start pulse signal (SP ) are input to the shift register. The generated selection signal is buffer-amplified in the buffer and supplied to the corresponding scanning line. To the scanning line, the gate electrodes of the transistors of the pixels for one line are connected. And since the transistors of the pixels for one line must be turned on all at once, a buffer that can pass a large current is used.

[0113] ​​​​​​​A form of a shift register used in a part of a scanning line driving circuit will be described with reference to FIGS. 10 and 11. Hereinbelow.

[0114] FIG. 10 shows the circuit configuration of the shift register. The shift register shown in FIG. 10 is composed of a plurality of flip-flops 5701_i (any one of flip-flops 5701_1 to 5701_n). Further, it operates with the input of a first clock signal, a second clock signal, a start pulse signal, and a reset signal. Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n).

[0115] The connection relationship of the shift register in FIG. 10 will be described. In the shift register of FIG. 10, the i-th stage flip-flop 5701_i (any one of flip-flops 5701_1 to 5701_n) has the first wiring 5501 shown in FIG. 11 connected to the seventh wiring 5717_i-1, the second wiring 5502 shown in FIG. 11 connected to the seventh wiring 5717_i+1, the third wiring 5503 shown in FIG. 11 connected to the seventh wiring 5717_i, and the sixth wiring 5506 shown in FIG. 11 connected to the fifth wiring 5715. Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n).

[0116] Also, the fourth wiring 5504 shown in FIG. 11 is connected to the second wiring 5712 in the flip-flops of odd-numbered stages and to the third wiring 5713 in the flip-flops of even-numbered stages, and the fifth wiring 5505 shown in FIG. 11 is connected to the fourth wiring 5714. Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n).

[0117] However, the first wiring 5501 shown in FIG. 11 of the first-stage flip-flop 5701_1 is connected to the first wiring 5711, and the second wiring 5502 shown in FIG. 11 of the n-th stage flip-flop 5701_n is connected to the sixth wiring 5716. Among flip-flops 5701_1 to 5701_n). Among flip-flops 5701_1 to 5701_n).

[0118] Incidentally, the first wiring 5711, the second wiring 5712, the third wiring 5713, and the sixth wiring 57 16 may be referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fourth wiring 5714 and the fifth wiring 5715 may be referred to as the first power supply line and the second power supply line, respectively.

[0119] Next, the details of the flip-flop shown in FIG. 10 are shown in FIG. 11. The flip-flop shown in FIG. 11 includes a first thin film transistor 5571, a second thin film transistor 5572, a third thin film transistor 5573, a fourth thin film transistor 5574, a fifth thin film transistor 5575, a sixth thin film transistor 5576, a seventh thin film transistor 5577, and an eighth thin film transistor 5578. Incidentally, the first thin film transistor 5571, the second thin film transistor 5572, the third thin film transistor 5573, the fourth thin film transistor 5574, the fifth thin film transistor 5575, the sixth thin film transistor 5576, the seventh thin film transistor 5577, and the eighth thin film transistor 5578 are n-channel type transistors, and are assumed to be in an on state when the gate-source voltage (Vgs) exceeds the threshold voltage (Vth).

[0120] Next, the connection configuration of the flip-flop shown in FIG. 10 is shown below.

[0121] A first electrode (either the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the fourth wiring 5504, and a second electrode (the other of the source electrode or the drain electrode) of the first thin film transistor 5571 is connected to the third wiring 5503.

[0122] The first electrode of the second thin film transistor 5572 is connected to the sixth wiring 5506, and the second electrode of the thin film transistor 5572 is connected to the third wiring 5503.

[0123] The first electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505, and the third electrode of the thin film transistor 5573 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the third thin film transistor 5573 is connected to the fifth wiring 5505.

[0124] The first electrode of the fourth thin film transistor 5574 is connected to the sixth wiring 5506, and the fourth electrode of the thin film transistor 5574 is connected to the gate electrode of the second thin film transistor 5572 and the gate electrode of the fourth thin film transistor 5574 is connected to the gate electrode of the first thin film transistor 5 571.

[0125] The first electrode of the fifth thin film transistor 5575 is connected to the fifth wiring 5505, and the fifth electrode of the thin film transistor 5575 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the fifth thin film transistor 5575 is connected to the first wiring 5501.

[0126] The first electrode of the sixth thin film transistor 5576 is connected to the sixth wiring 5506, and the sixth electrode of the thin film transistor 5576 is connected to the gate electrode of the first thin film transistor 5571 and the gate electrode of the sixth thin film transistor 5576 is connected to the gate electrode of the second thin film transistor 5 572.

[0127] The first electrode of the seventh thin film transistor 5577 is connected to the sixth wiring 5506, and the seventh​​ The second electrode of the thin film transistor 5577 is the gate electrode of the first thin film transistor 5571. , and the gate electrode of the seventh thin film transistor 5577 is connected to the second wiring 5502. A first electrode of the eighth thin film transistor 5578 is connected to the sixth wiring 5506. The second electrode of the eighth thin film transistor 5578 is connected to the gate of the second thin film transistor 5572. The gate electrode of the eighth thin film transistor 5578 is connected to the first wiring 550. Connected to 1.

[0128] The gate electrode of the first thin film transistor 5571 and the gate electrode of the fourth thin film transistor 5574 the gate electrode of the fifth thin film transistor 5575, the second electrode of the sixth thin film transistor The connection point of the second electrode of the seventh thin film transistor 5576 and the second electrode of the seventh thin film transistor 5577 is Further, the gate electrode of the second thin film transistor 5572, the gate electrode of the third thin film transistor 5543, a second electrode of the fourth thin film transistor 5573; a second electrode of the fourth thin film transistor 5574; The gate electrode of the sixth thin film transistor 5576 and the gate electrode of the eighth thin film transistor 5578 The connection point of the two electrodes is designated as node 5544.

[0129] The first wiring 5501, the second wiring 5502, the third wiring 5503 and the fourth wiring 5504 are 504 are referred to as the first signal line, the second signal line, the third signal line, and the fourth signal line, respectively. Furthermore, the fifth wiring 5505 may be connected to a first power supply line, and the sixth wiring 5506 may be connected to a second power supply line. It may be called a line.

[0130] In addition, the signal line driver circuit and the scanning line driver circuit may be the same as those shown in the first embodiment or the second embodiment. It is also possible to fabricate the device using only channel-type TFTs. Since the mobility of the transistors in the n-channel type TFT is high, the driving frequency of the driving circuit can be increased. In addition, the n-channel type TFT shown in Embodiment 1 or Embodiment 2 has a parasitic capacitance reduced by a buffer layer which is an oxide semiconductor layer containing indium, gallium, and zinc having an n-type, and thus has high frequency characteristics (referred to as f characteristics). For example, the scanning line driving circuit using the n-channel type TFT shown in Embodiment 1 or Embodiment 2 can be operated at high speed, so that it is possible to increase the frame frequency or realize black screen insertion. Furthermore, by increasing the channel width of the transistors in the scanning line driving circuit or arranging a plurality of scanning line driving circuits, it is possible to realize an even higher frame frequency. When arranging a plurality of scanning line driving circuits, the scanning line driving circuit for driving the even-numbered scanning lines is arranged on one side, and the scanning line driving circuit for driving the odd-numbered scanning lines is arranged on the opposite side, thereby realizing an increase in the frame frequency. Also, when manufacturing an active matrix light-emitting display device which is an example of the semiconductor device of one form of the present invention, since a plurality of thin film transistors are arranged in at least one pixel, it is preferable to arrange a plurality of scanning line driving circuits. An example of the block diagram of the active matrix light-emitting display device is shown in FIG. 6(B). The light-emitting display device shown in FIG. 6(B) has a pixel portion 5401 having a plurality of pixels provided with display elements on a substrate 5400, a first scanning line driving circuit 5402 and a second scanning line driving circuit for selecting each pixel.

[0131]

[0132]

[0133] The dynamic circuit 5404 and the signal line driving circuit 5403 that controls the input of the video signal to the selected pixel have.

[0134] When the video signal input to the pixel of the light-emitting display device shown in Fig. 6(B) is in digital format , the pixel becomes a light-emitting or non-light-emitting state by switching the transistor on and off . Therefore, gradation display can be performed using the area gradation method or the time gradation method. Area The gradation method is a driving method for performing gradation display by dividing one pixel into a plurality of sub-pixels and driving each sub-pixel independently based on a video signal . The time gradation method is a driving method for performing gradation display by controlling the period during which the pixel emits light .

[0135] Since the light-emitting element has a higher response speed than a liquid crystal element, etc., it is more suitable for the time gradation method than a liquid crystal element . Specifically, when performing display by the time gradation method, one frame period is divided into a plurality of sub-frame periods. Then, according to the video signal, the light-emitting element of the pixel is made to emit light or not emit light in each sub-frame period . By dividing into a plurality of sub-frame periods, the total length of the period during which the pixel actually emits light during one frame period can be controlled by the video signal, and gradation can be displayed .

[0136] Note that in the light-emitting display device shown in Fig. 6(B), when two, a switching TFT and a current control TFT, are arranged in one pixel, the signal input to the first scanning line, which is the gate wiring of the switching TFT, is generated by the first scanning line driving circuit 5402, and the signal input to the second scanning line, which is the gate wiring of the current control TFT, is generated by the second scanning line driving circuit 5404 . ​Although an example is shown, the signal input to the first scanning line and the signal input to the second scanning line may both be generated by a single scanning line driving circuit. Also, for example, depending on the number of transistors each switching element has, the first scanning line used to control the operation of the switching element may be provided in plural for each pixel. In this case, the signals input to the plural first scanning lines may all be generated by a single scanning line driving circuit, or they may be generated by plural scanning line driving circuits. Also, in a light-emitting display device as well, a part of the driving circuit that can be configured with n-channel type TFTs among the driving circuits can be formed on the same substrate as the thin-film transistors in the pixel portion. Also, the signal line driving circuit and the scanning line driving circuit can be fabricated only with the n-channel type TFTs shown in Embodiment 1 or Embodiment 2.

[0137] Further, the driving circuit described above is not limited to a liquid crystal display device or a light-emitting display device, and may be used for an electronic paper that drives electronic ink using an element electrically connected to a switching element. An electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to have a thin and light shape. Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro

[0138] Also, the driving circuit described above is not limited to a liquid crystal display device or a light-emitting display device, and may be used for an electronic paper that drives electronic ink using an element electrically connected to a switching element. An electronic paper is also called an electrophoretic display device (electrophoretic display), and has advantages such as being as easy to read as paper, having lower power consumption compared to other display devices, and being able to have a thin and light shape. Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro

[0139] Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro Although various forms of electrophoretic displays can be considered, it is a device in which microcapsules containing a first particle having a positive charge and a second particle having a negative charge are dispersed in plural in a solvent or a solute, and by applying an electric field to the microcapsules, the micro ​Move the particles in the capsule in opposite directions to each other and display only the color of the particles that have gathered on one side It is like this. The first particle or the second particle contains a dye and does not move in the absence of an electric field. Also, the color of the first particle and the color of the second particle are different (including colorless). including colorless).

[0140] In this way, the electrophoresis display is a display that utilizes the so-called dielectrophoretic effect in which a substance with a high dielectric constant moves to a high electric field region. The electrophoresis display does not require the polarizing plate and the counter substrate that are necessary for a liquid crystal display device, and the thickness and weight are halved.

[0141] A dispersion of the above microcapsules in a solvent is called electronic ink, and this electronic ink can be printed on the surfaces of glass, plastic, cloth, paper, etc. Also, color display is possible by using particles having a color filter or a pigment.

[0142] Also, if a plurality of the above microcapsules are appropriately arranged between two electrodes on an active matrix substrate, an active matrix type display device is completed, and display can be performed by applying an electric field to the microcapsules. For example, an active matrix substrate obtained by the thin film transistor of Embodiment 1 or Embodiment 2 can be used.

[0143] Note that the first particle and the second particle in the microcapsule are made of a conductor material, an insulator material, a semiconductor material, a magnetic material, a liquid crystal material, a ferroelectric material, an electroluminescent material, an electrochromic material, a magnetophoretic material, or a composite material thereof selected from one of these materials. or a composite material of these. ​​​​​​​​​​​Just use it.

[0144] Through the above steps, a display device with high reliability as a semiconductor device can be manufactured.

[0145] This embodiment is implemented by appropriately combining with the configuration described in the first or second embodiment. It is possible to implement this.

[0146] (Embodiment 4) A thin film transistor according to one embodiment of the present invention is manufactured, and the thin film transistor is used in a pixel portion and further in a driving By using the semiconductor device in the operating circuit, a semiconductor device having a display function (also called a display device) can be manufactured. In addition, a part or the whole of a driver circuit using a thin film transistor according to one embodiment of the present invention may be It is possible to form the element portion on the same substrate as the substrate, forming a system on panel.

[0147] The display device includes a display element. The display element may be a liquid crystal element (also called a liquid crystal display element), a light-emitting A light-emitting element (also called a light-emitting display element) can be used. A light-emitting element is a light-emitting element that emits light by applying a current or a voltage. This category includes elements whose brightness is controlled by a specific factor, such as inorganic EL (Electroluminescent) devices. These include organic EL elements, electronic inks, etc. A display medium whose contrast changes due to an electrical effect, such as a liquid crystal display, can also be used.

[0148] The display device includes a panel in which a display element is sealed, and a controller for the panel. and a module in which an IC or the like including the above-mentioned is mounted. Regarding the element substrate, which corresponds to one form before the display element is completed in the process of manufacturing a display device The element substrate includes a means for supplying a current to each of the plurality of pixels. The substrate may specifically be in a state where only the pixel electrodes of the display element are formed, or it may be in a state after forming a conductive film to be the pixel electrode and before etching to form the pixel electrode, and any form is applicable.

[0149] Note that the display device in this specification refers to an image display device, a display device, or a light source (including a lighting device). Also, a connector, for example, an FPC (Flexible pr inted circuit) or a TAB (Tape Automated Bon ding) tape or a TCP (Tape Carrier Package) attached module, a module with a printed wiring board provided at the end of the TAB tape or TCP, or a module in which an IC (integrated cir cuit) is directly mounted on the display element by the COG (Chip On Glass) method are all included in the display device.

[0150] In this embodiment, an example of a liquid crystal display device is shown as a semiconductor device of one form of the present invention.

[0151] FIGS. 12(A) and (B) show an active matrix type liquid crystal display device to which the present invention is applied. FIG. 12(A) is a plan view of the liquid crystal display device, and FIG. 12(B) is a cross-sectional view taken along line V-X in FIG. 12(A). As the thin film transistor 201 used in the semiconductor device, it can be manufactured in the same manner as the thin film transistor shown in Embodiment 2, and it is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistor shown in Embodiment 1 can also be applied as the thin film transistor 201 of this embodiment.

[0152] ​​​​​The liquid crystal display device of this embodiment shown in FIG. 12(A) includes a source wiring layer 202 and a multi-gate structure. The thin film transistor 201 , the gate wiring layer 203 , and the capacitor wiring layer 204 are included.

[0153] In addition, in FIG. 12B, the liquid crystal display device of the present embodiment has a multi-gate structure. A transistor 201, an insulating layer 211, an insulating layer 212, an insulating layer 213, and a display element The substrate 2 is provided with an electrode layer 255, an insulating layer 261 that functions as an alignment film, and a polarizing plate 268. 00, an insulating layer 263 that functions as an alignment film, an electrode layer 265 used for a display element, A colored layer 264 functioning as a filter, a substrate 266 provided with a polarizing plate 267, and a liquid crystal layer 268 are arranged in the liquid crystal layer 268. 62 and has a liquid crystal display element 260.

[0154] In addition, liquid crystals exhibiting a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases. When the temperature of cholesteric liquid crystal is increased, the phase immediately transitions from the cholesteric phase to the isotropic phase. The blue phase appears only in a narrow temperature range, so it is necessary to improve the temperature range. In order to achieve this, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer 262. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 10 μs to 1 It is short at 0.00μs, has optical isotropy so no alignment treatment is required, and has low viewing angle dependency. .

[0155] Although FIG. 12 shows an example of a transmissive liquid crystal display device, one embodiment of the present invention is a reflective liquid crystal display device. The present invention can also be applied to semi-transmissive liquid crystal display devices.

[0156] In the liquid crystal display device of FIG. 12, a polarizing plate 267 is provided on the outer side (the viewing side) of the substrate 266. In the example shown, a colored layer 264 and an electrode layer 265 used for a display element are provided in this order on the inside. The plate 267 may be provided on the inside of the substrate 266. The laminated structure of the polarizing plate and the colored layer may also be the same as that shown in FIG. It is not limited to B, and may be appropriately set depending on the materials of the polarizing plate and the colored layer and the manufacturing process conditions. In addition, a light-shielding film that functions as a black matrix may be provided.

[0157] In this embodiment, in order to reduce the surface unevenness of the thin film transistor, In order to improve the reliability of the transistor, the thin film transistor obtained in the second embodiment is provided with a protective film or The insulating layer 211, the insulating layer 212, and the insulating layer 213 function as a planarizing insulating film. The protective film is made of a material that can withstand organic matter, metals, water vapor, and other substances suspended in the air. The purpose of the protective film is to prevent the intrusion of contaminating impurities, and a dense film is preferable. Alternatively, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, or a silicon nitride film may be formed by sputtering or the like. The protective film may be a single layer or a multilayer of a silicon oxide film. A silicon oxide film may be formed by plasma CVD using silane gas and oxygen.

[0158] Organosilanes are ethyl silicate (TEOS: chemical formula Si(OC2H5)4), tetramethyl Silane (TMS: chemical formula Si(CH3)4), tetramethylcyclotetrasiloxane (T MCTS), Octamethylcyclotetrasiloxane (OMCTS), Hexamethyldisilane (HMDS), triethoxysilane (SiH(OC2H5)3), or tris(dimethylamino)silane (TDS). Compounds such as ethylaminosilane (SiH(N(CH3)2)3).

[0159] An insulating layer 211 is formed as the first layer of the protective film. The insulating layer 211 is a hiroma of an aluminum film. It is effective in preventing hooks. Here, as the insulating layer 211, a silicon oxide film is formed using the plasma CVD method. As the process gas for forming the silicon oxide film, TEOS and O2 are used, and the flow rate is TEOS\O2 = 15\750 (sccm). The substrate temperature in the film formation process is 300 °C.

[0160] Also, an insulating layer 212 is formed as the second layer of the protective film. Here, as the insulating layer 212, a silicon nitride film is formed using the plasma CVD method. For the process gas for forming the silicon nitride film, SiH4, N2, NH3 and H2 are used. Using a silicon nitride film as the first layer of the protective film can suppress the intrusion of mobile ions such as sodium into the semiconductor region and the change in the electrical characteristics of the TFT.

[0161] Also, after forming the protective film, annealing (300 °C to 400 °C) of the IGZO semiconductor layer may be performed.

[0162] Also, an insulating layer 213 is formed as a planarization insulating film. As the insulating layer 213, polyimide, acrylic, benzocyclobutene, polyamide, epoxy, etc., heat-resistant organic materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (borophosphorus glass), etc. can also be used. The siloxane-based resin may have at least one of fluorine, an alkyl group, or an aryl group in addition to hydrogen in the substituent. Note that the insulating layer 213 may be formed by laminating a plurality of insulating films formed of these materials.

[0163] The siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may have at least one of fluorine, an alkyl group, or an aromatic hydrocarbon in addition to hydrogen in the substituent. For the formation of the insulating layer 213, depending on the material, CVD method, sputtering method, SOG method, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 213 using a material liquid, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed simultaneously during the baking process. By combining the baking process of the insulating layer 213 and the annealing of the IGZO semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide.

[0164] Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. For the formation of the insulating layer 213, depending on the material, CVD method, sputtering method, SOG method, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 213 using a material liquid, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed simultaneously during the baking process. By combining the baking process of the insulating layer 213 and the annealing of the IGZO semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide. Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. For the formation of the insulating layer 213, depending on the material, CVD method, sputtering method, SOG method, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. When forming the insulating layer 213 using a material liquid, annealing (300°C to 400°C) of the IGZO semiconductor layer may be performed simultaneously during the baking process. By combining the baking process of the insulating layer 213 and the annealing of the IGZO semiconductor layer, it becomes possible to efficiently fabricate a semiconductor device. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide. Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm.

[0165] The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide. Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide. Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide.

[0166] Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. The electrode layers 255 and 265 that function as pixel electrode layers can use a conductive material having translucency such as indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide added with silicon oxide. Furthermore, as the electrode layers 255 and 265, they can be formed using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). The pixel electrode formed using the conductive composition has a sheet resistance of 10,000 Ω / sq or less and a transmittance of 70% or more at a wavelength of 550 nm. This is preferable. Also, the resistivity of the conductive polymer contained in the conductive composition is preferably 0.1 Ω·cm or less.

[0167] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives, or copolymers of two or more of these can be mentioned.

[0168] Through the above steps, a highly reliable liquid crystal display device can be fabricated as a semiconductor device.

[0169] This embodiment can be implemented in appropriate combination with the configuration described in any one of Embodiments 1 to 3.

[0170] (Embodiment 5) In this embodiment, an example of an electronic paper is shown as a semiconductor device according to one aspect of the present invention.

[0171] FIG. 13 shows an active matrix type electronic paper as an example of a semiconductor device to which the present invention is applied. As the thin film transistor 581 used in the semiconductor device, it can be fabricated in the same manner as the thin film transistor shown in Embodiment 2, and is a highly reliable thin film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin film transistor shown in Embodiment 1 can also be applied as the thin film transistor 581 of this embodiment.

[0172] The electronic paper in FIG. 13 is an example of a display device using the twist ball display method. The twist ball display method is an electrode layer that uses spherical particles painted white and black as display elements. It is arranged between the first electrode layer and the second electrode layer, and the display is performed by controlling the orientation of the spherical particles by generating a potential difference between the first electrode layer and the second electrode layer.

[0173] The thin film transistor 581 is a type of reverse staggered multi-gate structure (also called the bottom contact type), and is in contact with and electrically connected to the first electrode layer 587 through the source electrode layer or the drain electrode layer. There are black regions 590a and white regions 590b between the first electrode layer 587 and the second electrode layer 588, and spherical particles 589 including a cavity 594 filled with liquid around them are provided. The periphery of the spherical particles 589 is filled with a filler 595 such as resin (see Fig. 13). .

[0174] Also, instead of the twist ball, it is also possible to use an electrophoretic element. A transparent liquid and microcapsules with a diameter of about 10 μm to 200 μm encapsulating positively charged white fine particles and negatively charged black fine particles are used. The microcapsules provided between the first electrode layer and the second electrode layer When an electric field is applied by the first electrode layer and the second electrode layer, the white fine particles and the black fine particles move in opposite directions, and white or black can be displayed. A display element applying this principle is an electrophoretic display element, which is generally called electronic paper. Since the electrophoretic display element has a higher reflectance than the liquid crystal display element, no auxiliary light is required, and it also has low power consumption and can recognize the display part even in a dim place. Also even when no power is supplied to the display part, it is possible to hold the image once displayed. ​Therefore, even when the semiconductor device with a display function (also simply referred to as a display device or a semiconductor device including a display device) is separated from the radio wave transmission source, it is possible to save the displayed image.

[0175] Through the above steps, highly reliable electronic paper can be fabricated as a semiconductor device.

[0176] This embodiment can be implemented in appropriate combination with the configuration described in any one of Embodiments 1 to 3.

[0177] (Embodiment 6) In this embodiment, an example of a light-emitting display device is shown as a semiconductor device according to one aspect of the present invention. As the display element included in the display device, a light-emitting element using electroluminescence is shown here. The light-emitting element using electroluminescence is classified depending on whether the light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element, and the latter is called an inorganic EL element.

[0178] In the organic EL element, by applying a voltage to the light-emitting element, electrons and holes are respectively injected into the layer containing the light-emitting organic compound from a pair of electrodes, and a current flows. Then, when these carriers (electrons and holes) recombine, the light-emitting organic compound forms an excited state, and light is emitted when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is called a current-excited type light-emitting element.

[0179] The inorganic EL element is classified into a dispersed inorganic EL element and a thin-film inorganic EL element according to its element configuration. It is classified. The distributed inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder. It is formed, and the light-emitting mechanism is donor-acceptor recombination light emission that utilizes a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light-emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light-emitting mechanism is localized light emission that utilizes inner-shell electron transition of metal ions. Here, an organic EL element is used as the light-emitting element for explanation. It is used. Note that here, an organic EL element is used for explanation.

[0180] Figures 14(A) and 14(B) show an active matrix type light-emitting display device as an example of a semiconductor device to which the present invention is applied. Figure 14(A) is a plan view of the light-emitting display device, and Figure 14(B) is a cross-sectional view taken along line Y-Z in Figure 14(A). In addition, Figure 15 shows an equivalent circuit of the light-emitting display device shown in Figure 14. It is a plan view of the light-emitting display device, and Figure 14(B) is a cross-sectional view taken along line Y-Z in Figure 14(A). Note that Figure 15 shows an equivalent circuit of the light-emitting display device shown in Figure 14.

[0181] As the thin-film transistors 301 and 302 used in the semiconductor device, they can be manufactured in the same manner as the thin-film transistors shown in Embodiment 1 and Embodiment 2, and are highly reliable thin-film transistors including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. It can be manufactured in the same manner as the thin-film transistors shown in Embodiment 1 and Embodiment 2, and is a highly reliable thin-film transistor including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type.

[0182] The light-emitting display device of the present embodiment shown in Figures 14(A) and 15 includes a multi-gate structure thin-film transistor 301, a thin-film transistor 302, a light-emitting element 303, a capacitive element 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin-film transistors 301 and 302 are n-channel type thin-film transistors. It includes a multi-gate structure thin-film transistor 301, a thin-film transistor 302, a light-emitting element 303, a capacitive element 304, a source wiring layer 305, a gate wiring layer 306, and a power supply line 307. The thin-film transistors 301 and 302 are n-channel type thin-film transistors.

[0183] Also, in Figure 14(B), the light-emitting display device of the present embodiment includes a thin-film transistor 302. ​​​​, used for the insulating layer 311, insulating layer 312, insulating layer 313, partition wall 321, and light-emitting element 303 It has a first electrode layer 320, an electroluminescent layer 322, and a second electrode layer 323.

[0184] The insulating layer 313 is preferably formed using an organic resin such as acrylic, polyimide, or polyamide, or siloxane. It is preferably formed using.

[0185] In this embodiment, since the thin-film transistor 302 of the pixel is n-type, it is desirable to use a cathode as the first electrode layer 320 which is the pixel electrode layer. Specifically, as the cathode, a material with a small work function, for example, Ca, Al, CaF, MgAg, AlLi, etc. can be used. function, such as Ca, Al, CaF, MgAg, AlLi, etc., can be used. function, for example, Ca, Al, CaF, MgAg, AlLi, etc. can be used. It can be done.

[0186] The partition wall 321 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used to form an opening on the first electrode layer 320, and it is preferably formed so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. Specifically, a photosensitive material is used to form an opening on the first electrode layer 320, and it is preferably formed so that the side wall of the opening becomes an inclined surface formed with a continuous curvature. It is preferably formed so that the side wall of the opening becomes an inclined surface formed with a continuous curvature.

[0187] The electroluminescent layer 322 may be composed of a single layer or may be configured such that a plurality of layers are laminated. Either way is fine.

[0188] A second electrode layer 323 using an anode is formed so as to cover the electroluminescent layer 322. The second electrode layer 323 can be formed of a transparent conductive film having the transparency listed as the pixel electrode layer in Embodiment 4. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323 overlap each other to form the light-emitting element 303. After that, the light-emitting element 303 The electrode layer 323 can be formed of a transparent conductive film having the transparency listed as the pixel electrode layer in Embodiment 4. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323 overlap each other to form the light-emitting element 303. After that, the light-emitting element 303 using the conductive material having the transparency listed as the pixel electrode layer in Embodiment 4. In addition to the above transparent conductive film, a titanium nitride film or a titanium film may be used. The first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323 overlap each other to form the light-emitting element 303. After that, the light-emitting element 303 is formed by overlapping the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323. After that, the light-emitting element 303 is formed by overlapping the first electrode layer 320, the electroluminescent layer 322, and the second electrode layer 323. After that, the light-emitting element 303 A protective film may be formed on the second electrode layer 323 and the partition 32 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not penetrate. As the protective film, a silicon nitride film, a silicon oxynitride film, a DLC film, etc. can be formed.

[0189] Furthermore, in practice, when it is completed up to FIG. 14(B), it is hermetically sealed so as not to be further exposed to the outside air and has a high degree of protection and low outgassing. It is preferable to package (enclose) it with a protective film (laminated film, ultraviolet curable resin film, etc. ).

[0190] Next, the configuration of the light-emitting element will be described with reference to FIG. 16. Here, the case where the driving TFT is of the n type will be taken as an example to describe the cross-sectional structure of the pixel. The driving TFTs TFT7001, 7011, and 7021 used in the semiconductor devices of FIGS. 16(A), (B), and (C) can be manufactured in the same manner as the thin-film transistor shown in Embodiment 1, and are highly reliable thin-film transistors including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type. Also, the thin-film transistor shown in Embodiment 2 can be applied as TFT7001, 7011, and 7021.

[0191] For the light-emitting element, at least one of the anode or the cathode may be transparent in order to extract light. Thus, a thin-film transistor and a light-emitting element are formed on the substrate, and top emission that extracts light from the surface opposite to the substrate, bottom emission that extracts light from the surface on the substrate side, or double-sided emission that extracts light from both the substrate side and the surface opposite to the substrate There are light-emitting elements having a structure, and the pixel configuration shown in FIG. 16 can be applied to any light-emitting element having an emission structure.

[0192] The light-emitting element having a top emission structure will be described with reference to FIG. 16(A).​​​

[0193] FIG. 16(A) shows a cross-sectional view of a pixel when the TFT 7001, which is a driving TFT, is of the n-type and the light emitted from the light-emitting element 7002 escapes toward the anode 7005. In FIG. 16(A), the cathode 7003 of the light-emitting element 7002 and the TFT 7001, which is a driving TFT, are electrically connected, and a light-emitting layer 7004 and an anode 7005 are sequentially stacked on the cathode 7003. The cathode 7003 can be made of various materials as long as it is a conductive film having a low work function and reflecting light. For example, Ca, Al, CaF, MgAg, AlLi, etc. are desirable. And the light-emitting layer 7004 may be composed of a single layer or may be configured such that a plurality of layers are stacked. When it is composed of a plurality of layers, an electron injection layer , an electron transport layer, a light-emitting layer, a hole transport layer, and a hole injection layer are sequentially stacked on the cathode 7003. Note that it is not necessary to provide all of these layers. The anode 7005 is formed using a conductive material having light-transmitting properties, and for example, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide (hereinafter referred to as ITO), indium zinc oxide, or a light-transmitting conductive film such as indium tin oxide added with selenium may be used. The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 16(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow .

[0194] The region where the light-emitting layer 7004 is sandwiched between the cathode 7003 and the anode 7005 corresponds to the light-emitting element 7002. In the case of the pixel shown in FIG. 16(A), the light emitted from the light-emitting element 7002 is emitted toward the anode 7005 as indicated by the arrow .

[0195] Next, the light-emitting element with a bottom emission structure will be described with reference to FIG. 16(B). Driving TFT 7 011 is of the n-type, and when the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side, a cross-sectional view of the pixel is shown. In FIG. 16(B), on the transparent conductive film 7017 electrically connected to the driving TFT 7011, the cathode 7013 of the light-emitting element 7012 is formed, and the light-emitting layer 7014 and the anode 7015 are sequentially laminated on the cathode 7013. When the anode 7 015 has transparency, a shielding film 7016 for reflecting or shielding light may be formed so as to cover the anode. The cathode 7013 can be made of various materials as long as they are conductive materials with a small work function, similar to the case of FIG. 16(A). However, the film thickness should be such that light can pass through (preferably about 5 nm to 30 nm). For example, an aluminum film with a film thickness of 20 nm can be used as the cathode 7013. And the light-emitting layer 7 014 may be composed of a single layer or a plurality of layers laminated, similar to the case of FIG. 16(A). The anode 7015 does not necessarily need to transmit light, but as in FIG. 16(A), it can be formed using a transparent conductive material. And the shielding film 7016 can be made of, for example, a metal that reflects light, but is not limited to a metal film. For example, a resin added with a black pigment can also be used. The region sandwiched by the cathode 7013 and the anode 7015 with the light-emitting layer 7014 in between corresponds to the light-emitting element 7012. In the case of the pixel shown in FIG. 16(B), the light emitted from the light-emitting element 7012 is emitted toward the cathode 7013 side as indicated by the arrow.

[0196]

[0197] ​​​Next, a light emitting element having a dual emission structure will be described with reference to FIG. On a conductive film 7027 having a light-transmitting property and electrically connected to a driving TFT 7021, A cathode 7023 of the light-emitting element 7022 is formed, and a light-emitting layer 7024 is formed on the cathode 7023. The anode 7025 is laminated in order. The cathode 7023 is, as in the case of FIG. Various conductive materials with small thermal coefficients can be used. However, the thickness of the material should be For example, the cathode 7023 is made of Al having a thickness of 20 nm. The light-emitting layer 7024 can be formed of a single layer, as in FIG. The anode 70 may be configured as a single layer or as a laminate of multiple layers. 25 is formed using a conductive material having a light transmitting property, similar to FIG. It is possible.

[0198] The overlapping portion of the cathode 7023, the light-emitting layer 7024, and the anode 7025 constitutes the light-emitting element 70. In the case of the pixel shown in FIG. 16C, the light emitted from the light emitting element 7022 is is emitted toward both the anode 7025 side and the cathode 7023 side as indicated by the arrows.

[0199] Although the organic EL element has been described as the light-emitting element here, inorganic EL elements can also be used as the light-emitting element. It is also possible to provide an L element.

[0200] In this embodiment, a thin film transistor (driving TFT) that controls driving of a light emitting element is Although an example in which the light-emitting element is electrically connected has been shown, the current between the driving TFT and the light-emitting element is A control TFT may be connected.

[0201] Note that the semiconductor device shown in this embodiment is not limited to the configuration shown in FIG. 16, and various modifications based on the technical idea of the present invention are possible.

[0202] Through the above steps, a highly reliable light-emitting display device can be manufactured as a semiconductor device .

[0203] This embodiment can be implemented in appropriate combination with the configuration described in any one of Embodiments 1 to 3. It is possible to implement.

[0204] (Embodiment 7) The configuration of a display panel, which is one form of the semiconductor device of the present invention, is shown below. In this embodiment, a liquid crystal display panel (also referred to as a liquid crystal panel), which is one form of a liquid crystal display device having a liquid crystal element as a display element, and a light-emitting display panel (also referred to as a light-emitting panel), which is one form of a semiconductor device having a light-emitting element as a display element, will be described.

[0205] Next, the appearance and cross-section of a light-emitting display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 17. FIG. 17A is a top view of a panel in which an IGZO semiconductor layer formed on a first substrate and a highly reliable thin-film transistor and a light-emitting element including an IGZO semiconductor layer having an n-type conductivity type are sealed with a sealing material between the second substrate. FIG. 17( B) corresponds to a cross-sectional view taken along H-I in FIG. 17(A). A sealing material 4505 is provided so as to surround a pixel portion 4502, signal line driver circuits 4503a, 450 3b, and scanning line driver circuits 4504a, 4504b provided on a first substrate 4501. Further, the pixel portion 4502, signal line driver circuits 4503a, 4503b, and

[0206] A second substrate 4506 is provided over the scanning line driving circuits 4504a and 4504b. Thus, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 45 04a and 4504b are sealed together with the filling material 4507 by the first substrate 4501, the sealing material 4505, and the second substrate 4506.

[0207] Also, the pixel portion 4502, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b provided on the first substrate 4501 have a plurality of thin film transistors. In FIG. 17(B), the thin film transistor 4510 included in the pixel portion 4502 and the thin film transistor 4509 included in the signal line driving circuit 4503a are illustrated. The thin film transistors 4509 and 4510 correspond to thin film transistors including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type, and the thin film transistors shown in Embodiment 1 or Embodiment 2 can be applied. In the present embodiment, the thin film transistors 4509 and 4510 are n-channel type thin film transistors.

[0208] Also, 4511 corresponds to a light emitting element, and the first electrode layer 4517, which is a pixel electrode of the light emitting element 4511, is electrically connected to the source electrode layer or the drain electrode layer of the thin film transistor 4510. Note that the configuration of the light emitting element 4511 is not limited to the configuration shown in the present embodiment. The configuration of the light emitting element 4511 can be appropriately changed according to the direction of light extracted from the light emitting element 4511 or the like.

[0209]

[0210] Also, the signal line driving circuits 4503a and 4503b, and the scanning line driving circuits 4504a and 4504b Or, the various signals and potentials supplied to the pixel section 4502 are supplied from the FPCs 4518a and 4518 b.

[0211] In this embodiment, the connection terminal 4515 is formed from the same conductive film as the second electrode layer 4512, and the wiring 4516 is formed from the same conductive film as the first electrode layer 4517 included in the light-emitting element 4511.

[0212] The connection terminal 4515 is electrically connected to the terminal included in the FPC 4518a via the anisotropic conductive film 4519.

[0213] The second substrate located in the light extraction direction of the light from the light-emitting element 4511 must be translucent. In that case, a translucent material such as a glass plate, a plastic plate, a polyester film, or an acrylic film is used.

[0214] In addition to inert gases such as nitrogen and argon, an ultraviolet curable resin or a thermosetting resin can be used as the filler 4507, and PVC (polyvinyl chloride), acrylic, polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. In this embodiment, nitrogen is used as the filler.

[0215] If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), or a color filter may be appropriately provided on the light-emitting surface of the light-emitting element. In addition, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, an antiglare treatment that diffuses reflected light due to surface irregularities and reduces reflections can be performed.

[0216] The signal line drive circuits 4503a and 4503b, and the scanning line drive circuits 4504a and 4504b may be mounted by drive circuits formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate. Further, only the signal line drive circuit, or a part thereof, or only the scanning line drive circuit, or a part thereof may be separately formed and mounted, and the present embodiment is not limited to the configuration of FIG. 17. Next, the appearance and cross section of a liquid crystal display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 18. FIGS. 18(A1) and (A2) are top views of the panel in which the IGZO semiconductor layer formed on the first substrate 4001 and the reliable thin film transistors 4010, 4011, and liquid crystal elements 4013 including the IGZO semiconductor layer having an n-type conductivity type are sealed with a sealing material 4005 between the second substrate 4006, and FIG. 18(B) corresponds to a cross-sectional view taken along M-N in FIGS. 18(A1) and (A2). The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. Further, the second substrate 4006 is provided on the pixel portion 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The present invention is not limited to the above embodiment.

[0217] Next, the appearance and cross section of a liquid crystal display panel corresponding to one form of the semiconductor device of the present invention will be described with reference to FIG. 18. FIGS. 18(A1) and (A2) are top views of the panel in which the IGZO semiconductor layer formed on the first substrate 4001 and the reliable thin film transistors 4010, 4011, and liquid crystal elements 4013 including the IGZO semiconductor layer having an n-type conductivity type are sealed with a sealing material 4005 between the second substrate 4006. FIG. 18(B) corresponds to a cross-sectional view taken along M-N in FIGS. 18(A1) and (A2). The pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004 are surrounded by the sealing material 4005. The second substrate 4006 is provided on the pixel portion 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006.

[0218] The sealing material 4005 is provided so as to surround the pixel portion 4002 provided on the first substrate 4001 and the scanning line drive circuit 4004. The second substrate 4006 is provided on the pixel portion 4002 and the scanning line drive circuit 4004. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Therefore, the pixel portion 4002 and the scanning line drive circuit 4004 are sealed together with the liquid crystal layer 4008 by the first substrate 4001, the sealing material 4005, and the second substrate 4006. Further, a signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. The signal line drive circuit 4003 formed of a single crystal semiconductor film or a polycrystalline semiconductor film on a separately prepared substrate is mounted in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001.

[0219] In addition, the connection method of the separately formed driving circuit is not particularly limited, and a COG method, a wire bonding method, or a TAB method, etc. can be used. FIG. 18(A1) is an example of implementing the signal line driving circuit 4003 by the COG method, and FIG. 18(A2) is an example of implementing the signal line driving circuit 4003 by the TAB method.

[0220] Also, the pixel portion 4002 provided on the first substrate 4001 and the scanning line driving circuit 4004 have a plurality of thin film transistors. In FIG. 18(B), the thin films included in the pixel portion 4002 transistor 4010 and the thin film transistor 4011 included in the scanning line driving circuit 4004 are illustrated.

[0221] The thin film transistors 4010 and 4011 correspond to thin film transistors including an IGZO semiconductor layer and an IGZO semiconductor layer having an n-type conductivity type, and the thin film transistors shown in Embodiment 1 or Embodiment 2 can be applied. In the present embodiment, the thin film transistors 4010 and 4011 are n-channel type thin film transistors.

[0222] Also, the pixel electrode layer 4030 included in the liquid crystal element 4013 is electrically connected to the thin film transistor 4010. And the counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 40 06. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are each provided with insulating layers 4032 and 4033 that function as alignment films, and the liquid crystal layer 4008 is sandwiched via the insulating layers 4032 and 4033.

[0223]

[0223] Note that as the first substrate 4001 and the second substrate 4006, glass, metal (typically stainless), ceramics, or plastic can be used. As the plastic, an FRP (Fiberglass-Reinforced Plastics) board, a PV F (polyvinyl fluoride) film, a polyester film, or an acrylic resin film can be used. Also, a sheet having a structure in which an aluminum foil is sandwiched between a PVF film and a polyester film can be used.

[0224] Also, 4035 is a columnar spacer obtained by selectively etching an insulating film, and is provided to control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031. Note that a spherical spacer may be used.

[0225] Also, various signals and potentials supplied to the separately formed signal line driving circuit 4003, the scanning line driving circuit 4004, or the pixel portion 4002 are supplied from the FPC 4018.

[0226] In the present embodiment, the connection terminal 4015 is formed of the same conductive film as the pixel electrode layer 4030 included in the liquid crystal element 4013, and the wiring 4016 is formed of the same conductive film as the gate electrode layer of the thin film transistors 4010 and 4011.

[0227] The connection terminal 4015 is electrically connected to the terminal included in the FPC 4018 via the anisotropic conductive film 4019.

[0228] Also, in FIG. 18, the signal line driving circuit 4003 is separately formed and mounted on the first Although an example of the mounting is shown, the present embodiment is not limited to this configuration. Scanning line drive circuit may be separately formed and mounted, or a part of the signal line drive circuit or a part of the scanning line drive circuit may be separately formed and mounted.

[0229] FIG. 19 shows an example of configuring a liquid crystal display module as a semiconductor device using the TFT substrate 2600 manufactured by applying the present invention.

[0230] FIG. 19 is an example of a liquid crystal display module, in which the TFT substrate 2600 and the counter substrate 2601 are fixed by a sealing material 2602, and a pixel portion 2603 including TFTs and the like, a display element 2604 including a liquid crystal layer, and a coloring layer 2605 are provided therebetween to form a display region. The coloring layer 2605 is necessary when performing color display. In the case of the RGB method, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer. is necessary for color display. In the case of the RGB method, coloring layers corresponding to each color of red, green, and blue are provided corresponding to each pixel. Outside the TFT substrate 2600 and the counter substrate 2601, a polarizing plate 2606, a polarizing plate 2607, and a diffusion plate 2613 are disposed. The light source is composed of a cold cathode tube 2610 and a reflector 2611, and the circuit board 2612 is connected to the wiring circuit portion 2608 of the TFT substrate 2600 by a flexible printed circuit board 2609, and external circuits such as a control circuit and a power supply circuit are incorporated. Further, a retardation plate may be laminated between the polarizing plate and the liquid crystal layer.

[0231] Liquid crystal display modules include TN (Twisted Nematic) mode, IPS (In-Plane-Switching) mode, FFS (Fringe Field Switching) mode, MVA (Multi-domain Vertical Alignment) mode, etc. ​​​​​​​​​Alignment mode, PVA (Patterned Vertical Alig nment) mode, ASM (Axially Symmetric aligned Micro-cell) mode, OCB (Optical Compensated B irefringence) mode, FLC (Ferroelectric Liqui d Crystal) mode, AFLC (AntiFerroelectric Liq uid Crystal) mode, etc. can be used.

[0232] Through the above steps, a highly reliable display panel can be fabricated as a semiconductor device.

[0233] This embodiment can be implemented in appropriate combination with the configuration described in any one of Embodiments 1 to 6. It is possible to implement.

[0234] (Embodiment 8) One form of the semiconductor device of the present invention can be applied as electronic paper. Electronic paper can be used in electronic devices in any field as long as it displays information. For example, using electronic paper, it can be applied to electronic books (e-books), posters, in-vehicle advertisements on vehicles such as trains , and displays on various cards such as credit cards. An example of an electronic device is shown in FIGS. 20 and 21.

[0235] FIG. 20(A) shows a poster 2631 made of electronic paper. When the advertising medium is a paper printout, the advertisement is replaced manually, but with the electronic paper applying the present invention, the advertisement display can be changed in a short time. Also, the display will not be distorted. A stable image can be obtained. Note that the poster may also be configured to wirelessly transmit and receive information. This is good.

[0236] Also, FIG. 20(B) shows an in-vehicle advertisement 2632 in a vehicle such as a train. When the advertising medium is a paper print, the advertisement is exchanged manually. However, if an electronic paper according to the present invention is used, the advertisement display can be changed in a short time without much manual effort and a stable image can be obtained without the display being disrupted. Note that the in-vehicle advertisement may also be configured to wirelessly transmit and receive information.

[0237] Also, FIG. 21 shows an example of an electronic book 2700. For example, the electronic book 2700 is composed of two housings, a housing 2701 and a housing 2703. The housing 2701 and the housing 2703 are integrated by a shaft portion 2711, and can be opened and closed about the shaft portion 2711 as an axis. With such a configuration, it is possible to perform operations similar to those of a paper book.

[0238] A display unit 2705 is incorporated in the housing 2701, and a display unit 2707 is incorporated in the housing 2703. The display unit 2705 and the display unit 2707 may be configured to display consecutive screens or may be configured to display different screens. With a configuration of displaying different screens, for example, text can be displayed on the right display unit (display unit 2705 in FIG. 21), and an image can be displayed on the left display unit (display unit 2707 in FIG. 21).

[0239] Also, FIG. 21 shows an example in which the housing 2701 is provided with an operation unit and the like. For example, in the housing 2 701, a power supply 2721, operation keys 2723, a speaker 2725, and the like are provided. ​​​​​​。The page can be sent by the operation key 2723. Note that keys such as a board and a pointing device may be provided on the same surface as the display unit of the housing. Also, on the back surface or side surface of the housing, external connection terminals (such as earphone terminals, USB terminals, or terminals connectable to various cables such as an AC adapter and a USB cable), a recording medium insertion part, etc. may be provided. Furthermore, the electronic book 2700 may be configured to have a function as an electronic dictionary.

[0240] Also, the electronic book 2700 may be configured to be able to wirelessly transmit and receive information. By wireless means, it is also possible to purchase and download desired book data, etc. from an electronic book server.

[0241] This embodiment can be implemented by appropriately combining with any one of Embodiments 1 to 3 or the configuration described in Embodiment 5.

[0242] (Embodiment 9) The semiconductor device according to the present invention can be applied to various electronic devices (including gaming machines). Examples of the electronic device include a television device (also referred to as a TV or a television receiver), a monitor for a computer, a digital camera, a digital video camera, a digital photo frame, a mobile phone (also referred to as a mobile phone or a mobile phone device), a portable game machine, a portable information terminal, an audio reproduction device, a large gaming machine such as a pachinko machine, etc.

[0243] FIG. 22(A) shows an example of a television device 9600. The television device 96 00 has a display unit 9603 incorporated in a housing 9601. By the display unit 9603, an image ​​​​It is possible to display an image. Here, a configuration in which the housing 9601 is supported by the stand 9605 is shown. is shown.

[0244] The operation of the television device 9600 can be performed by operation switches provided in the housing 9601 or by a separate remote control unit 9610. The operation keys 9609 provided on the remote control unit 9610 can be used to operate channels and volume, and to operate the video displayed on the display unit 9603. In addition, the remote control unit 9610 may be configured to include a display unit 9607 for displaying information output from the remote control unit 9610.

[0245] Note that the television device 9600 is configured to include a receiver, a modem, etc. The receiver can receive general television broadcasts, and can further be connected to a communication network by wire or wirelessly via the modem, enabling one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0246] FIG. 22(B) shows an example of a digital photo frame 9700. For example, the digital photo frame 9700 has a display unit 9703 incorporated in a housing 9701. The display unit 9703 can display various images, and by displaying image data taken with, for example, a digital camera, it can function in the same way as a normal photo stand.

[0247] Note that the digital photo frame 9700 includes an operation unit, external connection terminals (terminals connectable to various cables such as USB terminals, USB cables), a recording medium insertion unit, etc. be adopted. These components may be incorporated on the same surface as the display unit, but it is preferable to provide them on the side or back surface because it improves the design. For example, in the recording medium insertion part of a digital photo frame, a memory storing image data taken with a digital camera can be inserted to capture the image data and display the captured image data on the display unit 9703.

[0248] Also, the digital photo frame 9700 may be configured to be able to wirelessly transmit and receive information. It can also be configured to capture and display desired image data wirelessly.

[0249] FIG. 23(A) shows a portable gaming machine, which is composed of two casings, a casing 9881 and a casing 9891, and is connected in an openable and closable manner by a connecting part 9893. A display unit 9882 is incorporated in the casing 9881, and a display unit 9883 is incorporated in the casing 9891. Further, the portable gaming machine shown in FIG. 23(A) also includes a speaker unit 9884, a recording medium insertion part 9886, an LED lamp 9890, input means (operation keys 9885, connection terminals 9887, a sensor 9888 (including functions for measuring force, displacement, position, speed, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature, chemical substances, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9889), etc. Of course, the configuration of the portable gaming machine is not limited to the above, and it may be any configuration as long as it includes at least the semiconductor device according to the present invention, and other accessory equipment may be provided as appropriate. The portable gaming machine shown in FIG. 23(A) has functions such as reading programs or data recorded on a recording medium and displaying them on the display unit, and performing wireless communication with other portable gaming machines. ​​​​​​​​​​​It has a function of sharing the information. Note that the functions of the portable gaming machine shown in Fig. 23(A) are not limited to this, and it can have various functions.

[0250] Fig. 23(B) shows an example of a slot machine 9900 which is a large-sized gaming machine. The slot machine 9900 has a display unit 9903 incorporated in a housing 9901. Further, the slot machine 9900 also includes operation means such as a start lever and a stop switch, a coin insertion port, a speaker, etc. Of course, the configuration of the slot machine 9900 is not limited to the above mentioned one, and any configuration can be used as long as it includes at least the semiconductor device according to the present invention, and other attached facilities can be provided as appropriate.

[0251] Fig. 24 shows an example of a mobile phone 1000. The mobile phone 1000 includes, in addition to a display unit 1002 incorporated in a housing 100 1, operation buttons 1003, an external connection port 1004, a speaker 1005, a microphone 1006, etc.

[0252] The mobile phone 1000 shown in Fig. 24 can input information by touching the display unit 1002 with a finger or the like. Further, operations such as making a call or sending an email can be performed by touching the display unit 100 2 with a finger or the like. The screen of the display unit 1002 mainly has three modes. The first is a display mode mainly for displaying images,

[0253] the second is an input mode mainly for inputting information such as characters. The third is a display + input mode in which the two modes of the display mode and the input mode are mixed.

[0254] ​​For example, when making a phone call or creating an email, the display unit 1002 may be set to the main character input mode, and an input operation on the characters displayed on the screen may be performed. In this case , it is preferable to display a keyboard or number buttons on most of the screen of the display unit 1002.

[0255] Also, by providing a detection device having sensors such as a gyro and an acceleration sensor inside the mobile phone 1000, the orientation (portrait or landscape) of the mobile phone 1000 can be determined, and the screen display of the display unit 1002 can be automatically switched.

[0256] In addition, the screen mode can be switched by touching the display unit 1002 or operating the operation button 1003 of the housing 1001. Also, it can be switched according to the type of image displayed on the display unit 1002. For example, if the image signal displayed on the display unit is video data, it is switched to the display mode, and if it is text data, it is switched to the input mode.

[0257] In the input mode, when the signal detected by the optical sensor of the display unit 1002 is detected and there is no touch operation on the display unit 1002 for a certain period, the screen mode may be controlled to be switched from the input mode to the display mode.

[0258] The display unit 1002 can also function as an image sensor. For example, by touching the palm or finger on the display unit 1002, fingerprint, palmprint, etc. can be imaged to perform personal authentication. Also, if a backlight that emits near-infrared light or a light source for a sensor that emits near-infrared light is used for the display unit, finger vein, palm vein, etc. can also be imaged.

Explanation of Signs

[0259] 100: Substrate 101: Gate electrode layer 102: Gate insulating layer 103: Semiconductor layer 104a, 104b: Buffer layer having an n-type conductivity type 105a, 105b: Source electrode layer or drain electrode layer 111: Semiconductor film 113, 116, 118: Mask 115a, 115b: n-type semiconductor layer 117: Conductive film 171a, 171b: Thin film transistor

Claims

【Claim 1】 a gate electrode layer, a gate insulating layer on the gate electrode layer, a source electrode layer and a drain electrode layer on the gate insulating layer, a wiring layer on the gate insulating layer, a first buffer layer on the source electrode layer, a second buffer layer on the drain electrode layer, a third buffer layer on the wiring layer, an oxide semiconductor layer having a channel formation region on the first to third buffer layers, and having, the wiring layer is located between the source electrode layer and the drain electrode layer, in a cross-sectional view, the source electrode layer does not have a region overlapping with the gate electrode layer, in a cross-sectional view, the drain electrode layer does not have a region overlapping with the gate electrode layer, in a cross-sectional view, the wiring layer does not have a region overlapping with the gate electrode layer, in a cross-sectional view, the first buffer layer has a region overlapping with the gate electrode layer, in a cross-sectional view, the second buffer layer has a region overlapping with the gate electrode layer, in a cross-sectional view, the third buffer layer has a region overlapping with the gate electrode layer, the oxide semiconductor layer has a region in contact with the gate insulating layer, a semiconductor device in which the carrier concentrations of the first to third buffer layers are higher than the carrier concentration of the oxide semiconductor layer.

Images