Programmable gain amplifier and circuit arrangement

Abstract

To provide a programmable gain amplifier or the like that can achieve amplification with a variable gain and noise reduction.SOLUTION: A programmable gain amplifier 50 includes: switches for input SI1, SI2 that are provided between input nodes of input signals VI1, VI2 and a node N1; an operational amplifier OP; a capacitor for sampling CS1 that is provided between the node N1 and the input terminal T1 of the operational amplifier OP; a capacitor for feedback CF1 that is provided between the input terminal T1 and an output terminal TQ1; a switch for reset SR1 that is provided between the input terminal T1 and the output terminal TQ1 in parallel with the capacitor for feedback CF1; and a noise cancellation circuit 52 that is provided between the input terminal T1 and the output terminal TQ1 in parallel with the capacitor for feedback CF1 and the switch for reset SR1, and includes a capacitor for noise cancellation CC1 and a switch SC1 connected in series.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a programmable gain amplifier, a circuit device, and the like.

Background Art

[0002] Conventionally, a programmable gain amplifier that performs amplification with variable gain has been known. For example, Patent Document 1 discloses a semiconductor device that amplifies input pixel information with a programmable gain amplifier and converts it into a digital value.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a programmable gain amplifier, kT / C noise generated in the capacitor of the input stage is amplified by the amplifier. For this reason, there is a problem that it is necessary to make the capacitance value of the capacitor in the input stage as large as possible in order to reduce kT / C noise.

Means for Solving the Problems

[0005] One aspect of the present disclosure relates to a programmable gain amplifier that amplifies the voltage difference between a first input signal and a second input signal with a variable gain, including a first input switch provided between a first input node of the first input signal and a first node, a second input switch provided between a second input node of the second input signal and the first node, an operational amplifier, a first sampling capacitor provided between the first node and a first input terminal of the operational amplifier, a first feedback capacitor provided between the first input terminal and a first output terminal of the operational amplifier and having a variable capacitance value according to the gain, a first reset switch provided in parallel with the first feedback capacitor between the first input terminal and the first output terminal, and a first noise cancellation circuit including a first noise cancellation capacitor and a first noise cancellation switch connected in series and provided in parallel with the first feedback capacitor and the first reset switch between the first input terminal and the first output terminal.

[0006] Another aspect of the present disclosure relates to a circuit device including the programmable gain amplifier described above and an A / D conversion circuit that A / D-converts an output signal of the programmable gain amplifier.

Brief Description of the Drawings

[0007]

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Mode for Carrying Out the Invention

[0008] Hereinafter, this embodiment will be described. Note that the embodiment described below does not unduly limit the content described in the claims. Also, not all of the configurations described in this embodiment are essential constituent elements.

[0009] 1. Programmable gain amplifier FIG. 1 shows a configuration example of a programmable gain amplifier 50 according to this embodiment. The programmable gain amplifier 50 is an amplifier that amplifies the voltage difference between an input signal VI1 and an input signal VI2 with a variable gain. For example, when the voltages of the input signals VI1 and VI2 are V1 and V2, and the gain is G, the programmable gain amplifier 50 outputs a signal of a voltage difference of G×(V1 - V2) obtained by amplifying the voltage difference of V1 - V2 with the gain G. In FIG. 1, with the ground GND as a reference, an output signal VQ1 of a voltage of G×(V1 - V2) is output.

[0010] The programmable gain amplifier 50 includes input switches SI1 and SI2, a sampling capacitor CS1, an operational amplifier OP, a feedback capacitor CF1, a noise cancellation circuit 52, and a reset switch SR1. The programmable gain amplifier 50 can also include a feedback switch SF1.

[0011] And the noise cancellation circuit 52, which is the first noise cancellation circuit, includes a noise cancellation capacitor CC1 and a switch SC1. Here, the input signals VI1 and VI2 are the first input signal and the second input signal respectively, and the switches SI1 and SI2 are the first input switch and the second input switch respectively. Also, the capacitor CS1 is the first sampling capacitor, the capacitor CC1 is the first noise cancellation capacitor, and the capacitor CF1 is the first feedback capacitor. Also, the switch SC1 is the first noise cancellation switch, the switch SR1 is the first reset switch, and the switch SF1 is the first feedback switch. Also, the switches SI1, SI2, SF1, SC1, and SR1 are composed of transistors such as MOS transistors. The same applies to other switches described later, which are also composed of transistors such as MOS transistors. Note that the programmable gain amplifier 50 of this embodiment is not limited to the configuration of FIG. 1, and various modifications such as omitting some of its components, adding other components, or changing its components to other types of components are possible.

[0012] In the programmable gain amplifier 50 configured as shown in FIG. 1, the accuracy is degraded due to the generation of thermal noise called kT / C noise. For example, the charge due to kT / C noise at the timing when the reset switch SR1 turns from on to off is accumulated in the sampling capacitor CS1, thereby degrading the accuracy of the programmable gain amplifier 50. Since the kT / C noise varies according to the temperature and also varies due to manufacturing variations of the transistor of the switch SR1, it hinders the improvement of accuracy. In this case, in order to suppress the degradation of accuracy due to the kT / C noise, the capacitance value of the sampling capacitor CS1 may be increased, but this leads to an increase in the circuit area. Therefore, in the present embodiment, by providing the noise canceling circuit 52 as shown in FIG. 1, the kT / C noise is reduced, and both high accuracy and miniaturization of the programmable gain amplifier 50 are achieved simultaneously.

[0013] The configuration of the programmable gain amplifier 50 in FIG. 1 will be described in detail. The switch SI1, which is the first input switch, is provided between the input node NI1 of the input signal VI1 and the node N1. For example, one end of the switch SI1 is connected to the input node NI1 and the other end is connected to the node N1. The switch SI2, which is the second input switch, is provided between the input node NI2 of the input signal VI2 and the node N1. For example, one end of the switch SI2 is connected to the input node NI2 and the other end is connected to the node N1. The input nodes NI1 and NI2 are the first input node and the second input node, respectively, and the node N1 is the first node. It should be noted that modified implementations such as providing other circuit elements between the input node NI1 or the input node NI2 and the node N1 are also possible.

[0014] The operational amplifier OP is, for example, a differential input and single output amplifier. The capacitor CS1, which is the first sampling capacitor, is provided between the node N1 and the input terminal T1 of the operational amplifier OP. In FIG. 1, the capacitance value of the sampling capacitor CS1 is denoted as C1. For example, one end of the capacitor CS1 is connected to the node N1 and the other end is connected to the input terminal T1 of the operational amplifier OP. The input terminal T2 of the operational amplifier OP is set to, for example, a common voltage VCM. The input terminal T1 is the first input terminal and the input terminal T2 is the second input terminal. As an example, the input terminal T1 is the inverting input terminal of the operational amplifier OP and the input terminal T2 is the non-inverting input terminal of the operational amplifier OP, but it is not limited thereto. It is also possible to implement variations such as providing other circuit elements between the capacitor CS1 and the input terminal T1 of the operational amplifier OP.

[0015] The capacitor CF1, which is the first feedback capacitor, is provided between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. The capacitor CF1 is, for example, a capacitor whose capacitance value is variable according to the gain of the programmable gain amplifier 50. In FIG. 1, the capacitance value of the feedback capacitor CF1 is denoted as C2. The output terminal TQ1 is the first output terminal, and the output signal VQ1 of the programmable gain amplifier 50 is output from the output terminal TQ1. The output signal VQ1 is, for example, a signal of the voltage difference obtained by amplifying the voltage difference between the input signal VI1 and the input signal VI2 by the gain of the programmable gain amplifier 50. Also, the switch SF1, which is the first feedback switch, is provided in series with the feedback capacitor CF1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. For example, one end of the capacitor CF1 is connected to the input terminal T1 of the operational amplifier OP and the other end is connected to one end of the switch SF1. One end of the switch SF1 is connected to the other end of the capacitor CF1 and the other end is connected to the output terminal TQ1 of the operational amplifier OP. It is also possible to implement variations such as substituting other circuit elements such as other switches instead of the switch SF1.

[0016] The switch SR1, which is the first reset switch, is provided in parallel with a feedback capacitor CF1 and the like between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. For example, one end of the switch SR1 is connected to the input terminal T1 of the operational amplifier OP, and the other end is connected to the output terminal TQ1 of the operational amplifier OP.

[0017] The noise canceling circuit 52, which is the first noise canceling circuit, is provided in parallel with the feedback capacitor CF1 and the reset switch SR1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. The noise canceling circuit 52 includes a capacitor CC1 and a switch SC1 connected in series. For example, one end of the capacitor CC1 is connected to the input terminal T1 of the operational amplifier OP, and the other end is connected to the switch SC1. One end of the switch SC1 is connected to the other end of the capacitor CC1, and the other end is connected to the output terminal TQ1 of the operational amplifier OP. The capacitor CC1 is the first noise canceling capacitor, and the switch SC1 is the first noise canceling switch. It should be noted that it is also possible to implement a modification such as providing circuit elements other than the capacitors CF1, CC1, and the switches SF1, SC1, SR1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP.

[0018] FIG. 2 is an operation explanatory diagram of the present embodiment, and FIGS. 3, 4, and 5 are operation explanatory diagrams showing the states of the switches of the programmable gain amplifier 50 during the sampling period, the noise canceling period, and the amplification period, respectively. The amplification period can also be referred to as the gain period or the gain operation period. In FIG. 2, it is shown that each switch is on when the control signal input to each of the switches SI1, SI2, SR1, SC1, and SF1 is at a high level, and each switch is off when the control signal is at a low level. The control signal is output by a control circuit (not shown), and thereby the on and off of each of the switches SI1, SI2, SR1, SC1, and SF1 are controlled. For example, the control signal is input to the gate of the transistor constituting each switch.

[0019] As shown in FIGS. 2 and 3, during the sampling period of the programmable gain amplifier 50, the switch SI1 which is the first input switch is turned on, and the switch SI2 which is the second input switch is turned off. Also, the switch SR1 which is the first reset switch and the switch SC1 which is the first noise cancellation switch are turned on. Also, the switch SF1 which is the first feedback switch is turned on. When the sampling switch SI1 is turned on, a charge corresponding to the input signal VI1 which is the first input signal is accumulated in the sampling capacitor CS1. For example, the input terminal T2 of the operational amplifier OP is set to the common voltage VCM, and due to the virtual ground of the operational amplifier OP, the node N3 of the input terminal T1 is also set to the common voltage VCM. Therefore, when the voltage of the input signal VI1 is V1, the capacitance value of the capacitor CS1 is C1, and VCM = 0V, a charge corresponding to C1×V1 is accumulated in the sampling capacitor CS1. Also, when the reset switch SR1 is turned on and the switches SC1 and SF1 are turned on, the charges accumulated in the capacitors CC1 and CF1 are reset to zero. At this time, kT / C noise caused by the on-resistance of the transistor of the switch SR1 is generated, and the potential of the node N3 of the input terminal T1 of the operational amplifier OP fluctuates due to this noise.

[0020] As shown in FIGS. 2 and 4, during the noise cancellation period after the sampling period, the reset switch SR1 is turned off. At this time, the feedback switch SF1 is also turned off. In this case, the kT / C noise at the timing when the switch SR1 is turned from on to off remains at the node N3. When this noise is represented as VN, a charge QN = C1×VN due to the noise is accumulated in the noise cancellation capacitor CC1.

[0021] As shown in FIGS. 2 and 5, in the amplification period after the noise cancellation period, the switch SI1 for input of the input signal VI1 is turned off, and the switch SI2 for input of the input signal VI2 is turned on. Also, the switch SC1 for noise cancellation is turned off. Further, the switch SF1 for feedback is turned on. In this amplification period, when the capacitance values of the capacitors CS1 and CF1 are C1 and C2, respectively, an amplification operation with a gain represented by G = C1 / C2 is performed. That is, when the voltages of the input signals VI1 and VI2 are V1 and V2, respectively, an amplification operation represented by G×(V1 - V2)=(C1 / C2)×(V1 - V2) is performed, and an output signal VQ1 of a voltage obtained by amplifying the voltage difference V1 - V2 between the input signals VI1 and VI2 by the gain G is output. That is, when the voltage of the output signal VQ1 is VQ, an output signal VQ1 of VQ=(C1 / C2)×(V1 - V2) is output.

[0022] In this case, if the noise cancellation circuit 52 as in the present embodiment is not provided, kT / C noise is superimposed on the output signal VQ1. However, in the present embodiment, this kT / C noise can be canceled and reduced by the noise cancellation circuit 52. Specifically, in the noise cancellation period of FIG. 3, by accumulating a charge QN = C1×VN in the noise cancellation capacitor CC1, cancellation of the kT / C noise is realized.

[0023] Next, the noise cancellation operation of the present embodiment will be described in more detail. In the sampling period of FIG. 3, due to the virtual ground of the operational amplifier OP, the node N3 of the input terminal T1 is set to the common voltage VCM = 0V. And since the switch SI1 is turned on in FIG. 3, a charge QS = C1×V1 is accumulated in the capacitor CS1. In this case, since the kt / C noise of the switch SR1 is generated, the charge accumulated in the node N3 can be expressed as -C1×V1 - C1×VN. The charge C1×VN due to this noise varies according to the temperature and the like.

[0024] During the noise cancellation period in FIG. 4, switch SR1 turns from on to off, and a charge of -C1×V1 - C1×VN is accumulated at node N3. In this case, C1×VN is the charge due to noise at the timing when switch SR1 turns off. Since a charge of -C1×V1 is accumulated on the node N3 side of capacitor CS1, according to the charge conservation law, a charge of -C1×VN is accumulated on the node N3 side of capacitor CC1 for noise cancellation. Note that a charge of C1×VN is accumulated on the node N5 side of capacitor CC1. Node N5 is the node to which the output terminal TQ1 of operational amplifier OP is connected. That is, out of the charge of -C1×V1 - C1×VN at node N3, a charge of -C1×V1 is accumulated on the node N3 side of capacitor CS1, and a charge of -C1×VN is accumulated on the node N3 side of capacitor CC1. Thus, in this embodiment, during the noise cancellation period in FIG. 4, the charge C1×VN corresponding to the noise is accumulated in capacitor CC1 for noise cancellation.

[0025] During the amplification period in FIG. 5, switch SI1 of input signal VI1 turns off, and switch SI2 of input signal VI2 turns on. As a result, when the voltage of input signal VI2 is V2, the charge on the node N1 side of capacitor CS1 becomes C1×V2, and the charge on the node N3 side becomes -C1×V2.

[0026] Also, during the amplification period in FIG. 5, when the noise cancellation switch SC1 turns from on to off, a charge of -C1×VN is fixed on the node N3 side of capacitor CC1 for noise cancellation, and a charge of C1×VN is fixed on the node N5 side.

[0027] That is, during the noise cancellation period in FIG. 4, since the voltage V1 of input signal VI1 is applied to one end of sampling capacitor CS1, the charge on the node N3 side of capacitor CS1 is -C1×V1. Also, the charge on the node N3 side of capacitor CC1 for noise cancellation is -C1×VN. Therefore, the charge at node N3 during the noise cancellation period is expressed as in the following formula (1).

[0028] -C1×V1 - C1×VN (1)

[0029] On the other hand, during the amplification period in FIG. 5, since the voltage V2 of the input signal VI2 is applied to one end of the sampling capacitor CS1, the charge on the node N3 side of the capacitor CS1 is -C1×V2. Also, the charge on the node N3 side of the capacitor CC1 is -C1×VN. Further, assuming the voltage of the output signal VQ1 is VQ, the charge on the node N3 side of the capacitor CF1 is -C2×VQ. Therefore, the charge of the node N3 during the amplification period is expressed as the following formula (2).

[0030] -C1×V2 - C1×VN - C2×VQ (2)

[0031] And according to the charge conservation law, since the above formula (1) and the above formula (2) are equal, the following formula (3) holds.

[0032] -C1×V1 - C1×VN = -C1×V2 - C1×VN - C2×VQ (3)

[0033] Therefore, the charge C1×VN due to noise, which is present on both sides of the above formula (3), is canceled out, and the voltage VQ of the output signal VQ1 is expressed as the following formula (4).

[0034] VQ = (C1 / C2)×(V1 - V2) (4)

[0035] As described above, the programmable gain amplifier 50 of the present embodiment includes input switches SI1 and SI2 for input signals VI1 and VI2, an operational amplifier OP, a sampling capacitor CS1, a feedback capacitor CF1, a reset switch SR1, and a noise canceling circuit 52. The input switches SI1 and SI2 are provided between the input nodes NI1 and NI2 of the input signals VI1 and VI2 and the node N1. The sampling capacitor CS1 is provided between the node N1 and the input terminal T1 of the operational amplifier OP. The feedback capacitor CF1 is provided between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP and is a capacitor whose capacitance value is variable according to the gain G. The reset switch SR1 is provided in parallel with the feedback capacitor CF1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. The noise canceling circuit 52 is provided in parallel with the feedback capacitor CF1 and the reset switch SR1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP and includes a noise canceling capacitor CC1 and a switch SC1 connected in series.

[0036] According to the programmable gain amplifier 50 of the present embodiment configured as described above, an output signal VQ1 of a voltage VQ obtained by amplifying the voltage difference (V1 - V2) between the input signals VI1 and VI2 with a variable gain G = C1 / C2 can be output. And in this embodiment, during the noise cancellation period in FIG. 4, the charge C1×VN due to kt / C noise can be accumulated and held in the noise cancellation capacitor CC1 of the noise cancellation circuit 52. Then, during the amplification period in FIG. 5, since the charge due to noise is accumulated in the noise cancellation capacitor CC1, noise can be canceled during the amplification operation of the programmable gain amplifier 50. As a result, noise can be reduced and the high-precision of the programmable gain amplifier 50 can be realized. That is, it becomes possible to realize a programmable gain amplifier 50 that can perform an amplification operation with a variable gain and reduce noise. Also, kT / C noise can be reduced by increasing the capacitance value of the sampling capacitor CS1, but this causes an increase in the circuit area. In this regard, in this embodiment, since the kT / C noise is canceled by providing the noise cancellation circuit 52, it becomes possible to reduce noise without increasing the capacitance value of the sampling capacitor CS1. As an example, the capacitance value of the capacitor CS1, which has been 10 to 20 pF until now, can be reduced to about 1 to 5 pF, thereby realizing a reduction in the circuit area. Therefore, it becomes possible to reduce noise while reducing the circuit area and to realize a programmable gain amplifier 50 that can amplify the voltage difference between the input signals VI1 and VI2 with a variable gain.

[0037] Also, as described with reference to FIGS. 2 to 5, in this embodiment, during the sampling period, the input switch SI1 is on, the input switch SI2 is off, the reset switch SR1 and the noise cancellation switch SC1 are on. And during the noise cancellation period, the reset switch SR1 is off, and during the amplification period, the input switch SI1 is off, the input switch SI2 is on, and the noise cancellation switch SC1 is off. In this way, during the sampling period, when the input switch SI1 is on, the charge based on the input signal VI1 is accumulated in the sampling capacitor CS1. Also, during the noise cancellation period, when the reset switch SR1 is off, the charge based on the sampling noise can be accumulated in the noise cancellation capacitor CC1. And during the amplification period, when the input switch SI2 is on, the charge based on the input signal VI2 is accumulated in the sampling capacitor CS1. As a result, the charge corresponding to the voltage difference between the input signals VI1 and VI2 is accumulated in the feedback capacitor CF1, and the output signal VQ1 of the voltage based on this voltage difference can be output. And during the amplification period, since the charge due to noise is accumulated in the noise cancellation capacitor CC1, the noise can be cancelled during the amplification operation of the programmable gain amplifier 50.

[0038] Also, the programmable gain amplifier 50 of this embodiment includes a feedback switch SF1 provided in series with the feedback capacitor CF1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP. In this way, when the feedback switch SF1 is on, a feedback loop can be formed between the output terminal TQ1 and the input terminal T1 of the operational amplifier OP, or when the feedback switch SF1 is off, the feedback loop between the output terminal TQ1 and the input terminal T1 of the operational amplifier OP can be cut off.

[0039] Also, as described with reference to FIGS. 2 to 5, in this embodiment, during the sampling period, the input switch SI1 is on, the input switch SI2 is off, the reset switch SR1 and the noise cancellation switch SC1 are on, and the feedback switch SF1 is on. During the noise cancellation period, the reset switch SR1 is off and the feedback switch SF1 is off. During the amplification period, the input switch SI1 is off, the input switch SI2 is on, the noise cancellation switch SC1 is off, and the feedback switch SF1 is on. In this way, during the noise cancellation period in FIG. 4, when the feedback switch SF1 is turned off, the feedback loop between the output terminal TQ1 and the input terminal T1 of the operational amplifier OP is interrupted, and the charge based on the sampling noise can be accumulated and held in the noise cancellation capacitor CC1. Then, during the amplification period in FIG. 5, when the feedback switch SF1 is turned on, a feedback loop is formed, and an amplification operation based on the capacitance ratio of the sampling capacitor CS1 and the feedback capacitor CF1 can be realized.

[0040] 2. Differential Programmable Gain Amplifier FIG. 6 shows a configuration example of a differential programmable gain amplifier 50. The differential programmable gain amplifier 50 in FIG. 6 further includes input switches SI3 and SI4, a sampling capacitor CS2, a feedback capacitor CF2, a reset switch SR2, and a noise cancellation circuit 54 in addition to the configuration in FIG. 1.

[0041] The switch SI3, which is the third input switch, is provided between the input node NI1 of the input signal VI1 and the node N2. The switch SI4, which is the fourth input switch, is provided between the input node NI2 of the input signal VI2 and the node N2. The input nodes NI1 and NI2 are the first input node and the second input node, respectively, and the node N2 is the second input node.

[0042] A capacitor CF2 for the second feedback, which is a capacitor, is provided between an input terminal T2 and an output terminal TQ2 of an operational amplifier OP, and is a capacitor whose capacitance value is variable according to the gain. The gain can be expressed as G = C1 / C2. The input terminal T2 is the second input terminal, and the output terminal TQ2 is the second output terminal. In FIG. 6, the input terminals T1 and T2 are the inverting input terminal and the non-inverting input terminal of the operational amplifier OP, respectively, and the output terminals TQ1 and TQ2 are the non-inverting output terminal and the inverting output terminal of the operational amplifier OP, respectively, but it is not limited thereto.

[0043] A switch SR2, which is a second reset switch, is provided in parallel with a feedback capacitor CF2 between an input terminal T2 and an output terminal TQ2 of an operational amplifier OP.

[0044] A noise canceling circuit 54, which is a second noise canceling circuit, is provided in parallel with a feedback capacitor CF2 and a reset switch SR2 between an input terminal T2 and an output terminal TQ2 of an operational amplifier OP. The noise canceling circuit 54 includes a noise canceling capacitor CC2 and a switch SC2 connected in series. The capacitor CC2 is a second noise canceling capacitor, and the switch SC2 is a second noise canceling switch.

[0045] According to the differential-configured programmable gain amplifier 50 of FIG. 6, the voltage difference between the input signals VI1 and VI2 is amplified with a variable gain, and the output signal VQ1 is output from the node N5 of the output terminal TQ1 of the operational amplifier OP, and the output signal VQ2 is output from the node N6 of the output terminal TQ2. For example, let the voltages of the output signals VQ1 and VQ2 be VP and VM. In this case, as will be described later, according to the programmable gain amplifier 50 of FIG. 6, the voltage difference V1-V2 between the input signals VI1 and VI2 can be amplified by the gain G = 2×(C1 / C2) to output the output signals VQ1 and VQ2 with a voltage difference VP-VM = 2×(C1 / C2)×(V1-V2). By adopting such a differential input and differential output configuration, compared with the differential input and single output programmable gain amplifier 50 of FIG. 1, further noise reduction and the like can be achieved.

[0046] FIG. 7 is an operation explanatory diagram of the differential-configured programmable gain amplifier 50, and FIGS. 8, 9, and 10 are operation explanatory diagrams showing the states of the switches during the sampling period, the noise cancellation period, and the amplification period, respectively.

[0047] As shown in FIGS. 7 and 8, during the sampling period, the first input switch SI1 and the fourth input switch SI4 are turned on, and the second input switch SI2 and the third input switch SI3 are turned off. Also, the first reset switch SR1, the second reset switch SR2, the first noise cancellation switch SC1, and the second noise cancellation switch SC2 are turned on. Also, the first feedback switch SF1 and the second feedback switch SF2 are turned on. When the switch SI1 is turned on, a charge corresponding to the input signal VI1 is accumulated in the capacitor CS1, and when the switch SI4 is turned on, a charge corresponding to the input signal VI2 is accumulated in the capacitor CS2. Therefore, when the voltages of the input signals VI1 and VI2 are V1 and V2, the capacitance values of the capacitors CS1 and CS2 are C1, and VCM = 0V, a charge corresponding to C1×V1 is accumulated in the capacitor CS1, and a charge corresponding to C1×V2 is accumulated in the capacitor CS2. Also, when the switches SR1 and SR2 are turned on and the switches SC1, SC2, SF1, and SF2 are turned on, the charges accumulated in the capacitors CC1, CC2, CF1, and CF2 are reset to zero. At this time, kT / C noise caused by the on-resistance of the transistors of the switches SR1 and SR2 is generated, and due to this noise, the potentials of the nodes N3 and N4 at the input terminals T1 and T2 of the operational amplifier OP fluctuate.

[0048] As shown in FIGS. 7 and 9, during the noise cancellation period, the reset switches SR1 and SR2 are turned off. At this time, the feedback switches SF1 and SF2 are also turned off. In this case, the kT / C noise at the timing when the switches SR1 and SR2 turn from on to off remains at nodes N3 and N4. Representing this noise as VN, when the capacitance values of the capacitors CS1 and CS2 are C1, a charge QN = C1×VN due to the noise is accumulated in the noise cancellation capacitors CC1 and CC2. For example, due to the virtual ground of the operational amplifier OP or the like, the nodes N3 and N4 of the input terminals T1 and T2 are set to a common voltage VCM = 0V.

[0049] As shown in FIGS. 7 and 10, during the amplification period, the switches SI1 and SI4 are turned off, and the switches SI2 and SI3 are turned on. Also, the noise cancellation switches SC1 and SC2 are turned off. The feedback switches SF1 and SF2 are turned on. During this amplification period, an amplification operation with a variable gain G is performed. For example, when the voltages of the input signals VI1 and VI2 are V1 and V2, the programmable gain amplifier 50 can output output signal voltage differences VQ1 and VQ2 that are the voltage differences obtained by amplifying the voltage difference V1 - V2 of the input signals VI1 and VI2 with the gain G.

[0050] In this case, if noise cancellation circuits 52 and 54 like those of this embodiment are not provided, kT / C noise will be superimposed on the output signals VQ1 and VQ2. However, in this embodiment, the kT / C noise can be canceled and reduced by the noise cancellation circuits 52 and 54. Specifically, in the noise cancellation period of FIG. 9, the charge QN = C1×VN is accumulated in the noise cancellation capacitors CC1 and CC2, thereby realizing the cancellation of the kT / C noise.

[0051] For example, FIG. 11 shows the configuration of a programmable gain amplifier of a comparative example of the present embodiment. In the comparative example of FIG. 11, noise canceling circuits 52 and 54 as in the present embodiment are not provided. Also, switches SS1, SS2, SM1, SM2, and SS3 are provided. During the sampling period, switches SM1, SM2, and SS3 are turned on, and switches SS1 and SS2 are turned off. Further, in FIG. 11, voltage follower-connected operational amplifiers OP1 and OP2 to which output signals VQ1 and VQ2 are input, and an A / D conversion circuit 60 for A / D converting the output signals of the operational amplifiers OP1 and OP2 are provided. Also in the present embodiment of FIGS. 1 and 6, such operational amplifiers OP1 and OP2 and A / D conversion circuit 60 can be provided. In the comparative example of FIG. 11, kT / C noise occurs from switches SM1 and SM2 to which a common voltage VCM is input at one end, and there is a problem that this noise cannot be canceled. In this regard, according to the present embodiment, by providing noise canceling circuits 52 and 54, charges corresponding to the kT / C noise are accumulated in capacitors CC1 and CC2, and noise cancellation can be realized during the amplification period using the accumulated charges.

[0052] For example, B1 in FIG. 12 is an example of the noise characteristics of the programmable gain amplifier in the comparative example of FIG. 11, and B2 is an example of the noise characteristics in the present embodiment. As shown in B2 of FIG. 12, according to the present embodiment, it is possible to significantly reduce noise compared to the comparative example. For example, in the comparative example of FIG. 11, in order to reduce the kT / C noise, it is necessary to increase the capacitance values of the sampling capacitors CS1 and CS2, which causes a problem of an increase in the circuit scale. On the other hand, in the present embodiment, since the noise can be canceled by the noise canceling circuits 52 and 54, it is not necessary to increase the capacitance values of the sampling capacitors CS1 and CS2, and there is an advantage that the circuit area can be reduced compared to the comparative example.

[0053] In the comparative example of FIG. 11, during the sampling period, switches SS1 and SS2 that turn off during the sampling period are provided so that the charge due to the noise of the operational amplifier OP is not transmitted to and accumulated in the sampling capacitors CS1 and CS2. In this regard, in the present embodiment, since noise cancellation can be achieved including the noise of such an operational amplifier OP, there is an advantage that such switches SS1 and SS2 do not need to be provided.

[0054] As described above, in the present embodiment, as described with reference to FIGS. 7 to 10, during the sampling period, the input switches SI1 and SI4 are on, the input switches SI2 and SI3 are off, and the reset switches SR1 and SR2 and the noise cancellation switches SC1 and SC2 are on. Then, during the noise cancellation period, the reset switches SR1 and SR2 are turned off, and during the amplification period, the input switches SI1 and SI4 are off, the input switches SI2 and SI3 are on, and the noise cancellation switches SC1 and SC2 are off. In this way, during the sampling period, when the input switches SI1 and SI4 are turned on, the charge based on the input signal VI1 is accumulated in the sampling capacitor CS1, and the charge based on the input signal VI2 is accumulated in the sampling capacitor CS2. Also, during the noise cancellation period, when the reset switches SR1 and SR2 are turned off, the charge based on the sampling noise can be accumulated in the noise cancellation capacitors CC1 and CC2. Then, during the amplification period, when the input switches SI2 and SI3 are turned on, the charge based on the input signal VI2 is accumulated in the sampling capacitor CS1, and the charge based on the input signal VI1 is accumulated in the sampling capacitor CS2. As a result, the charge corresponding to the voltage difference between the input signal VI1 and the input signal VI2 is accumulated in the feedback capacitors CF1 and CF2, and the output signals VQ1 and VQ2 of the voltage based on this voltage difference can be output.

[0055] For example, let the voltages of the output signals VQ1 and VQ2 be VP and VM, respectively. In this case, the charge of node N3 during the noise cancellation period in FIG. 9 is expressed as in the following equation (5), and the charge of node N3 during the amplification period in FIG. 10 is expressed as in the following equation (6).

[0056] -C1×V1 - C1×VN (5)

[0057] -C1×V2 - C1×VN - C2×VP (6)

[0058] Then, according to the charge conservation law at node N3, since the above equation (5) and equation (6) are equal, the following equation (7) holds, and the voltage VP of the output signal VQ1 is expressed as in the following equation (8).

[0059] -C1×V1 - C1×VN = -C1×V2 - C1×VN - C2×VP (7)

[0060] VP = (C1 / C2)×(V1 - V2) (8)

[0061] Also, the charge of node N4 during the noise cancellation period in FIG. 9 is expressed as in the following equation (9), and the charge of node N4 during the amplification period in FIG. 10 is expressed as in the following equation (10).

[0062] -C1×V2 - C1×VN (9)

[0063] -C1×V1 - C1×VN - C2×VM (10)

[0064] Then, according to the charge conservation law at node N4, since the above equation (9) and equation (10) are equal, the following equation (11) holds, and the voltage VM of the output signal VQ2 is expressed as in the following equation (12).

[0065] -C1×V2 - C1×VN = -C1×V1 - C1×VN - C2×VM (11)

[0066] VM = -(C1 / C2)×(V1 - V2) (12)

[0067] Therefore, from the above equations (8) and (12), the voltage difference (VP - VM) between the output signals VQ1 and VQ2 is expressed as the following equation (13).

[0068] VP - VM = 2×(C1 / C2)×(V1 - V2) (13)

[0069] Therefore, according to the differential programmable gain amplifier 50 in FIG. 6, the voltage difference (V1 - V2) between the input signals VI1 and VI2 can be amplified to the voltage difference VP - VM = 2×(C1 / C2)×(V1 - V2). For example, in the case of the configuration in FIG. 1, the gain is G = C1 / C2, whereas in the differential configuration in FIG. 6, the gain can be doubled to G = 2×(C1 / C2), enabling low noise and the like to be achieved.

[0070] For example, in the case of the comparative example in FIG. 11, the voltage VP of the output signal VQ1 is expressed as the following equation (14), and the voltage VM of the output signal VQ2 is expressed as the following equation (15). Therefore, the voltage difference (VP - VM) between the output signals VQ1 and VQ2 is expressed as the following equation (16).

[0071] VP = (C1 / C2)×(V1 - V2)+(C1 / C2)×VN (14)

[0072] VM = -(C1 / C2)×(V1 - V2)-(C1 / C2)×VN (15)

[0073] VP - VM = 2×(C1 / C2)×(V1 - V2) +2×(C1 / C2)×VN (16)

[0074] In the comparative example without the noise canceling circuits 52 and 54 in this way, there was a problem that the noise was multiplied by the capacitance ratio such as 2×(C1 / C2)×VN. For example, when the gain is changed, the noise also fluctuates accordingly. On the other hand, according to the programmable gain amplifier 50 of the present embodiment, since the noise is canceled as shown in the above equation (13), the occurrence of such problems can be prevented.

[0075] Also, the programmable gain amplifier 50 of the present embodiment includes a feedback switch SF1 provided in series with a feedback capacitor CF1 between the input terminal T1 and the output terminal TQ1 of the operational amplifier OP, and a feedback switch SF2 provided in series with a feedback capacitor CF2 between the input terminal T2 and the output terminal TQ2 of the operational amplifier OP. In this way, when the feedback switches SF1 and SF2 are turned on, a feedback loop is formed between the output terminal TQ1 and the input terminal T1 of the operational amplifier OP and between the output terminal TQ2 and the input terminal T2, and when the feedback switches SF1 and SF2 are turned off, the feedback loop can be cut off.

[0076] Also, as described with reference to FIGS. 7 to 10, in the present embodiment, during the sampling period, the input switches SI1 and SI4 are on, the input switches SI2 and SI3 are off, the reset switches SR1 and SR2 and the noise canceling switches SC1 and SC2 are on, and the feedback switches SF1 and SF2 are on. During the noise canceling period, the reset switches SR1 and SR2 are off and the feedback switches SF1 and SF2 are off. During the amplification period, the input switches SI1 and SI4 are off, the input switches SI2 and SI3 are on, the noise canceling switches SC1 and SC2 are off, and the feedback switches SF1 and SF2 are on. In this way, during the noise canceling period in FIG. 9, by turning off the feedback switches SF1 and SF2, the feedback loop between the output terminals TQ1 and TQ2 and the input terminals T1 and T2 of the operational amplifier OP is cut off, and the charge based on the sampling noise can be accumulated and held in the noise canceling capacitors CC1 and CC2. Then, during the amplification period in FIG. 10, by turning on the feedback switches SF1 and SF2, a feedback loop is formed, and an amplification operation based on the capacitance ratio of the sampling capacitors CS1 and CS2 and the feedback capacitors CF1 and CF2 can be realized.

[0077] 3. Circuit device Fig. 13 shows a configuration example of a circuit device 20 including the programmable gain amplifier 50 of the present embodiment. The circuit device 20 includes a programmable gain amplifier 50 and an A / D conversion circuit 60 that A / D-converts the output signal of the programmable gain amplifier 50. Also in Fig. 13, the circuit device 20 further includes a D / A conversion circuit 40 and a control circuit 70. The circuit device 20 in Fig. 13 realizes an A / D converter 30 that A / D-converts an input signal VIN and outputs ADC result data DQ. Note that the circuit device 20 of the present embodiment is not limited to the configuration of Fig. 13, and various modifications such as omitting some of its components, adding other components, or changing its components to other types of components are possible. For example, a configuration without the D / A conversion circuit 40 or the control circuit 70 may be adopted. Also hereinafter, the circuit device 20 will be described as the A / D converter 30 as appropriate.

[0078] The D / A conversion circuit 40 D / A-converts the DAC input digital value n and outputs a DAC output signal Vn. As the D / A conversion circuit 40, for example, a resistor ladder type D / A conversion circuit can be used.

[0079] The programmable gain amplifier 50 differentially amplifies the input signal VIN, which is the input voltage, and the DAC output signal Vn, which is the DAC output voltage. In FIG. 13, the programmable gain amplifier 50 differentially amplifies the input signal VIN and the DAC output signal Vn with a gain G and outputs a differential signal DS, which is a differential voltage signal, to the A / D conversion circuit 60. By providing such a programmable gain amplifier 50, the differential between the input signal VIN and the DAC output signal Vn, which is amplified by the programmable gain amplifier 50 as the differential signal DS, can be input to the A / D conversion circuit 60. Therefore, the A / D conversion circuit 60 can perform A / D conversion, for example, at full scale, on the differential signal DS with a wide amplitude range amplified by the programmable gain amplifier 50, and high-precision A / D conversion can be realized. For example, by performing A / D conversion on the signal amplified by the programmable gain amplifier 50 using the A / D conversion circuit 60, an A / D converter 30 with a resolution higher than the resolution of the A / D conversion circuit 60 can be realized. Note that the gain G of the programmable gain amplifier 50 can be, for example, about 10 to 20 times.

[0080] The A / D conversion circuit 60 performs A / D conversion on the differential signal DS and outputs an ADC output digital value d. For example, in the A / D conversion circuit 60, the first differential signal of the differential signal DS is input to the first input terminal of the differential input, the second differential signal of the differential signal DS is input to the second input terminal of the differential input, and the ADC output digital value d obtained by performing A / D conversion on the difference between the first differential signal and the second differential signal is output. The first differential signal and the second differential signal are, for example, the output signals VQ1 and VQ2 in FIG. 6, or the signals obtained by buffering the output signals VQ1 and VQ2 with the operational amplifiers OP1 and OP2 connected in a voltage follower configuration as shown in FIG. 11. As the A / D conversion circuit 60, for example, a successive approximation type A / D conversion circuit can be used. However, in this embodiment, as the A / D conversion circuit 60, it is also possible to use other types of A / D conversion circuits such as a pipeline type or a delta-sigma type other than the successive approximation type.

[0081] The control circuit 70 outputs the DAC input digital value n. For example, the control circuit 70 outputs the DAC input digital value n based on the ADC output digital value d from the A / D conversion circuit 60. For example, the control circuit 70 performs arithmetic processing based on the ADC output digital value d and outputs the DAC input digital value n to the D / A conversion circuit 40. The control circuit 70 also outputs the final ADC result data DQ. That is, it outputs the digital value of the ADC result data DQ. The control circuit 70 can be realized by a logic circuit.

[0082] Specifically, the control circuit 70 outputs, as the DAC input digital value n, the DAC input digital value n1 and the DAC input digital value n2 different from the DAC input digital value n1. The DAC input digital value n1 is the first DAC input digital value, and the DAC input digital value n2 is the second DAC input digital value. Then, the control circuit 70 obtains the ADC result data DQ based on the ADC output digital value d1, which is the ADC output digital value d obtained corresponding to the DAC input digital value n1, the ADC output digital value d2, which is the ADC output digital value d obtained corresponding to the DAC input digital value n2, and the DAC input digital value n. For example, when the value of one of the DAC input digital values n1 and n2 is obtained from the other, the control circuit 70 obtains the ADC result data DQ from the ADC output digital value d1, the ADC output digital value d2, and the DAC input digital value n1 or the DAC input digital value n2. The ADC output digital value d1 is the first ADC output digital value, and the ADC output digital value d2 is the second ADC output digital value.

[0083] For example, when the control circuit 70 outputs a DAC input digital value n1, the D / A conversion circuit 40 performs D / A conversion on the DAC input digital value n1 and outputs a DAC output signal Vn = Vn1. Then, the programmable gain amplifier 50 outputs a differential signal DS based on the difference between the input signal VIN and the DAC output signal Vn1, and the A / D conversion circuit 60 performs A / D conversion on the differential signal DS to output an ADC output digital value d = d1 to the control circuit 70. Also, when the control circuit 70 outputs a DAC input digital value n2, the D / A conversion circuit 40 performs D / A conversion on the DAC input digital value n2 and outputs a DAC output signal Vn = Vn2. Then, the programmable gain amplifier 50 outputs a differential signal DS based on the difference between the input signal VIN and the DAC output signal Vn2, and the A / D conversion circuit 60 performs A / D conversion on the differential signal DS to output an ADC output digital value d = d2 to the control circuit 70. Then, the control circuit 70 obtains ADC result data DQ based on the ADC output digital values d1, d2 and the DAC input digital value n. For example, the control circuit 70 obtains ADC result data DQ based on the ADC output digital values d1, d2 and the DAC input digital value n1 or the DAC input digital value n1, and outputs it as the digital value of the final ADC result.

[0084] As described above, the A / D converter 30 in FIG. 13 performs, for example, two A / D conversions such as an A / D conversion based on the DAC input digital value n1 and an A / D conversion based on the DAC input digital value n2. Then, based on the ADC output digital value d1 which is the A / D conversion result based on the DAC input digital value n1 and the ADC output digital value d2 which is the A / D conversion result based on the DAC input digital value n2, the final ADC result data DQ is calculated. For the ADC output digital value d1, it is obtained by performing an A / D conversion on the difference between the input signal VIN and the DAC output signal Vn1 obtained by D / A converting the DAC input digital value n1 by the D / A conversion circuit 40 using the A / D conversion circuit 60. For the ADC output digital value d2, it is obtained by performing an A / D conversion on the difference between the input signal VIN and the DAC output signal Vn2 obtained by D / A converting the DAC input digital value n2 by the D / A conversion circuit 40 using the A / D conversion circuit 60. In this way, by using the A / D conversion circuit 60 and the D / A conversion circuit 40, it becomes possible to realize the A / D converter 30 capable of performing A / D conversion with higher accuracy than the resolution of the A / D conversion circuit 60. As an example, when the resolution of the A / D conversion circuit 60 is, for example, 15 to 16 bits, the resolution can be improved by about 2 bits, and for example, an A / D converter 30 with a resolution of 17 to 18 bits can be realized.

[0085] FIG. 14 is an operation explanatory diagram of the A / D converter 30. A1 in FIG. 14 shows the relationship between the input voltage and the DAC output voltage. The input voltage is the voltage of the input signal VIN, and the DAC output voltage is the voltage of the DAC output signal Vn. The DAC input digital value n on the horizontal axis of A1 in FIG. 14 is the digital value input to the D / A conversion circuit 40, and the digital value is also called a digital code. As shown in A1 of FIG. 14, when the DAC input digital value n1 is input, the D / A conversion circuit 40 outputs the DAC output voltage of Vn1 to the programmable gain amplifier 50, and when the DAC input digital value n2 is input, it outputs the DAC output voltage of Vn2 to the programmable gain amplifier 50. In A1 of FIG. 14, VIN, which is the input voltage of the A / D converter 30, is, for example, a voltage between Vn1 and Vn2, which are the DAC output voltages. In this embodiment, the input signal VIN is appropriately described as the input voltage, the D / A conversion circuit 40 is appropriately described as the DAC, and the A / D conversion circuit 60 is appropriately described as the ADC.

[0086] A2 in FIG. 14 shows the relationship between the input voltage after amplification by the programmable gain amplifier 50 and the ADC input voltage. The ADC input voltage is a differential voltage that is the voltage of the differential signal DS. In A2 of FIG. 14, the programmable gain amplifier 50 amplifies the signal by G times (G>1).

[0087] As shown in A1 of FIG. 14, when the DAC input digital value n1 is input to the D / A conversion circuit 40, the D / A conversion circuit 40 outputs an output voltage of Vn1. Then, as shown in A2 of FIG. 14, the programmable gain amplifier 50 amplifies the differential voltage VIN - Vn1, which is the difference between the input voltage VIN and the DAC output voltage Vn1, by G times and outputs it to the A / D conversion circuit 60. The A / D conversion circuit 60 A / D-converts the voltage of (VIN - Vn1)×G and outputs an ADC output digital value d1 to the control circuit 70. Also, as shown in A1 of FIG. 14, when the DAC input digital value n2 is input to the D / A conversion circuit 40, the D / A conversion circuit 40 outputs an output voltage of Vn2. Then, as shown in A2 of FIG. 14, the programmable gain amplifier 50 amplifies the differential voltage VIN - Vn2, which is the difference between the input voltage VIN and the output voltage Vn2, by G times and outputs it to the A / D conversion circuit 60. The A / D conversion circuit 60 A / D-converts the voltage of (VIN - Vn2)×G and outputs an ADC output digital value d2 to the control circuit 70.

[0088] Then, based on the ADC output digital value d1 input from the A / D conversion circuit 60 when the DAC input digital value n1 is output to the D / A conversion circuit 40, and the ADC output digital value d2 input from the A / D conversion circuit 60 when the DAC input digital value n2 is output to the D / A conversion circuit 40, the control circuit 70 obtains ADC result data DQ. For example, the differential voltage shown in A3 of FIG. 14 is expressed as (VIN - Vn1)×G, which corresponds to the ADC output digital value d1. The differential voltage shown in A4 is expressed as (VIN - Vn2)×G, which corresponds to the ADC output digital value d2. Also, the differential voltage shown in A5 is expressed as (Vn2 - Vn1)×G = (VIN - Vn1)×G - (VIN - Vn2)×G, which corresponds to d1 - d2, the difference between the ADC output digital values d1 and d2. Therefore, the input voltage VIN of the A / D converter 30 can be specified from the ratio of the differential voltage in A3 to the differential voltages in A4 and A5 for the differential voltage in A5. Specifically, VIN can be specified as shown in the following formula (17).

[0089] VIN = Vn1+(Vn2 - Vn1)×{d1 / (d1 - d2)} (17)

[0090] Here, d1 = G×(VIN - Vn1) and d2 = G×(VIN - Vn2).

[0091] Therefore, the control circuit 70 can perform the operation on the ADC result data DQ as shown in the following equation (18) and output it.

[0092] DQ = n1+(n2 - n1)×{d1 / (d1 - d2)} (18)

[0093] For example, when VIN is the voltage between Vn1 and Vn2, VIN is the voltage represented by the ratio of d1 / (d1 - d2) between Vn1 and Vn2. For example, when d1 / (d1 - d2) is 0.5, VIN = Vn1+(Vn2 - Vn1)×0.5, and VIN is the voltage at the center between Vn1 and Vn2. When d1 / (d1 - d2) is 0.6, VIN = Vn1+(Vn2 - Vn1)×0.6, and VIN is the voltage represented by a 60% ratio between Vn2 and Vn1. Even when VIN is not the voltage between Vn1 and Vn2, VIN can be specified by the above equation (17), and the control circuit 70 can obtain and output the ADC result data DQ as shown in the above equation (18).

[0094] According to the present embodiment, even when a programmable gain amplifier 50 is provided in front of the A / D conversion circuit 60 to improve the resolution of A / D conversion, for example, the circuit characteristics of the programmable gain amplifier 50, which is an amplifier circuit, are less likely to affect the result of A / D conversion. For example, as shown in the above equations (17) and (18), theoretically, the gain G of the programmable gain amplifier 50 does not affect the result of A / D conversion. Also, in the present embodiment, the control circuit 70 generates a DAC input digital value n based on the ADC output digital value d from the A / D conversion circuit 60. For example, the control circuit 70 generates the DAC input digital value n by feedback control. By performing such feedback control, it becomes possible to bring the DAC output voltage VN of the D / A conversion circuit 40 closer to the input voltage VIN. For example, if VN and VIN are too far apart, it becomes difficult to obtain an accurate A / D conversion result, but by bringing VN closer to VIN, it becomes possible to improve the accuracy of the A / D conversion result.

[0095] 4. Power supply noise Fig. 15 shows a configuration example of the circuit device 20 of the present embodiment including the sensor circuit 90. The circuit device 20 includes a programmable gain amplifier 50, an A / D conversion circuit 60 that A / D-converts the output signal of the programmable gain amplifier 50, and a sensor circuit 90 that outputs a detection signal as an input signal VI1 or an input signal VI2 to the programmable gain amplifier 50. The input signals VI1 and VI2 are a first input signal and a second input signal, respectively. Taking Fig. 13 as an example, the detection signal of the sensor circuit 90 is input to the programmable gain amplifier 50 as VIN, which is the input signal VI1 or the input signal VI2. According to the circuit device 20 having such a configuration, the signal obtained by amplifying the detection signal of the sensor circuit 90 by the programmable gain amplifier 50 can be A / D-converted by the A / D conversion circuit 60, and a digital A / D conversion result can be output.

[0096] The sensor circuit 90 is a circuit that detects a physical quantity and outputs a detection signal. When the physical quantity to be detected is temperature, the sensor circuit 90, which is a temperature sensor circuit, detects the temperature and outputs a detection signal of the temperature. For example, the sensor circuit 90 outputs a temperature-dependent voltage that changes according to the temperature of the environment as a detection signal. For example, the temperature sensor circuit 90 generates a detection signal using a circuit element having temperature dependence. Specifically, the temperature sensor circuit 90 outputs, as a detection signal, a temperature detection voltage whose voltage value changes depending on the temperature by using the temperature dependence of the forward voltage of the PN junction. The programmable gain amplifier 50 amplifies the detection signal, which is this temperature detection voltage, and the A / D conversion circuit 60 performs A / D conversion on the amplified signal, thereby realizing a temperature sensor with digital output. For example, in the circuit device 20 of the present embodiment, since A / D conversion with higher accuracy than the resolution of the A / D conversion circuit 60 is possible, it is possible to meet the demand for output of a highly accurate temperature detection result. Also, in a temperature sensor with digital output, it is necessary to output a highly accurate temperature detection result in a wide band. However, in the circuit device 20 of the present embodiment, since it is easy to widen the band, it is also possible to meet the demand for output of a highly accurate temperature detection result in a wide band. Note that the physical quantity detected by the sensor circuit 90 is not limited to temperature, and may be a physical quantity such as acceleration, angular velocity, distance, or pressure.

[0097] In FIG. 15, a power supply voltage based on a common power supply VDD is supplied to the A / D conversion circuit 60 and the sensor circuit 90. For example, in the circuit device 20 of the present embodiment, a power supply circuit (not shown) is provided. This power supply circuit generates a power supply voltage based on VDD and supplies it to the A / D conversion circuit 60 and the sensor circuit 90. The power supply circuit also supplies a power supply voltage to the programmable gain amplifier 50. In this case, the power supply voltage supplied to the A / D conversion circuit 60, the sensor circuit 90, and the programmable gain amplifier 50 may be a power supply voltage obtained by regulating VDD by a regulator included in the power supply circuit. For example, the power supply voltages supplied to the A / D conversion circuit 60, the sensor circuit 90, etc. may be power supply voltages of different voltages. For example, a first regulator for the A / D conversion circuit 60 and a second regulator for the sensor circuit 90 are provided in the power supply circuit, and the power supply voltages regulated by these first regulator and second regulator are supplied to the A / D conversion circuit 60 and the sensor circuit 90.

[0098] In the case of the configuration of FIG. 15, noise generated during the A / D conversion operation of the A / D conversion circuit 60 is transmitted to the sensor circuit 90 via the common power supply VDD, causing problems such as a decrease in the detection accuracy of the sensor circuit 90.

[0099] Therefore, in the present embodiment, as shown in FIG. 16, during the period in which the programmable gain amplifier 50 performs the sampling operation, the A / D conversion circuit 60 is caused to perform the conversion operation. For example, during the sampling period of the programmable gain amplifier 50, the A / D conversion circuit 60 performs an A / D conversion operation such as a successive A / D conversion. Note that the A / D conversion circuit 60 may perform the A / D conversion operation during the noise cancellation period of the programmable gain amplifier 50. Then, during the period in which the programmable gain amplifier 50 performs the amplification operation, the A / D conversion circuit 60 performs the sampling operation. For example, during the amplification period of the programmable gain amplifier 50, the A / D conversion circuit 60 performs a sampling operation of a signal based on the output signal of the programmable gain amplifier 50. For example, the A / D conversion circuit 60 has a sampling capacitor, and performs an operation of sampling a signal based on the output signal of the programmable gain amplifier 50 with respect to this sampling capacitor. The signal based on the output signal is the output signal or a signal obtained by buffering the output signal by an operational amplifier or the like in a voltage follower connection. Then, the A / D conversion circuit 60 performs an A / D conversion operation based on the sampled voltage and outputs the A / D converted digital data. By doing so, it becomes possible to end the sampling period of the programmable gain amplifier 50 earlier and reduce the adverse effect of the noise generated in the A / D conversion circuit 60 after the end timing of the sampling period on the final A / D conversion result. For example, it becomes possible to change the sampling period to an arbitrary period and reduce the adverse effect caused by the fluctuation of the power supply VDD. For example, as described above, in the present embodiment, since the kT / C noise cancellation is performed, the capacitance values of the sampling capacitors CS1 and CS2 can be reduced. Therefore, the programmable gain amplifier 50 has an advantage that it can sample the detection signal of the sensor circuit 90 in a short sampling period. Therefore, the sampling period of the programmable gain amplifier 50 can be ended in a short time, and it becomes possible to suppress the noise generated in the A / D conversion operation after the end of this sampling period from affecting the final A / D conversion result.

[0100] For example, FIG. 17 shows an example of the final noise characteristics in the circuit device 20 of FIG. 15. D1 in FIG. 17 is an example of the noise characteristics in the case of the comparative example of FIG. 11, and D2 is an example of the noise characteristics in the case of the present embodiment. According to the present embodiment as shown in D2 of FIG. 17, for example, it is possible to significantly reduce the noise in the final result such as temperature detection data as compared with the comparative example.

[0101] As the A / D conversion circuit 60, for example, a successive approximation type A / D conversion circuit can be used. In the case of the successive approximation type, the A / D conversion circuit 60 can include a SAR circuit, a D / A conversion circuit, a sample hold circuit, and a comparator. The SAR circuit has a successive approximation register in which the register value is set by the comparison result signal from the comparator, and outputs the successive approximation data to the D / A conversion circuit. The D / A conversion circuit performs D / A conversion of the successive approximation data and outputs a DAC output signal corresponding to the successive approximation data to the comparator. The comparator, which is a comparison circuit, compares the input signal sample-held by the sample hold circuit with the DAC output signal from the D / A conversion circuit, and outputs a comparison result signal to the SAR circuit. When the comparator performs successive comparison processing from the MSB bit to the LSB bit, the result of the comparison processing at each bit is stored as each register value of the successive approximation register included in the SAR circuit. Then, the SAR circuit outputs the result signal of the final A / D conversion by successive comparison. As the D / A conversion circuit of the successive approximation type A / D conversion circuit 60, for example, a charge redistribution type D / A conversion circuit of a capacitive array type can be used. In this case, the function of the sample hold circuit is actually realized by the D / A conversion circuit. The charge redistribution type D / A conversion circuit is realized by, for example, a comparator whose non-inverting input terminal is set to a common voltage, a capacitor array and a switch array connected in series to the inverting input terminal of the comparator, and a control circuit that controls on and off of a plurality of switches of the switch array. In this way, if a successive approximation type A / D conversion circuit is used as the A / D conversion circuit 60, wide-band A / D conversion becomes possible.

[0102] Moreover, the circuit device 20 of this embodiment can be used as an oscillator circuit device. The oscillator includes a vibrator and the circuit device 20. The vibrator is electrically connected to the circuit device 20. For example, the vibrator and the circuit device 20 are electrically connected using internal wiring, bonding wires, or metal bumps inside a package that houses the vibrator and the circuit device 20. The vibrator is an element that generates mechanical vibration by an electrical signal. It can be realized by a vibrating piece such as a crystal vibrating piece. The circuit device 20 is, for example, an IC (Integrated Circuit) manufactured by a semiconductor process, and is a semiconductor chip on which circuit elements are formed on a semiconductor substrate. The circuit device 20 in this case includes an oscillation circuit and an output circuit. The oscillation circuit is a circuit that oscillates the vibrator. The output circuit outputs a clock signal based on the oscillation signal of the oscillation circuit. For example, the output circuit buffers the oscillation signal and outputs it as a clock signal. And the circuit device 20 having the sensor circuit 90 described in FIG. 15 detects the ambient temperature of the vibrator and outputs the ADC result data as temperature detection data. In this way, a circuit device 20 that can detect the ambient temperature of the vibrator and output it as temperature detection data can be realized. In this case, for example, an external system may form a PLL loop or the like to perform temperature compensation of the oscillation frequency of the vibrator based on the temperature detection data to realize temperature compensation of the clock signal.

[0103] As described above, the programmable gain amplifier according to the present embodiment that amplifies the voltage difference between the first input signal and the second input signal with a variable gain includes a first input switch provided between the first input node of the first input signal and the first node, a second input switch provided between the second input node of the second input signal and the first node, and an operational amplifier. The programmable gain amplifier also includes a first sampling capacitor provided between the first node and the first input terminal of the operational amplifier, a first feedback capacitor provided between the first input terminal and the first output terminal of the operational amplifier and having a capacitance value variable according to the gain, and a first reset switch provided in parallel with the first feedback capacitor between the first input terminal and the first output terminal. The programmable gain amplifier further includes a first noise cancellation circuit including a first noise cancellation capacitor and a first noise cancellation switch connected in series and provided in parallel with the first feedback capacitor and the first reset switch between the first input terminal and the first output terminal.

[0104] According to the present embodiment, an output signal of a voltage obtained by amplifying the voltage difference between the first input signal and the second input signal with a variable gain can be output. In the present embodiment, for example, charges due to sampling noise can be accumulated and held in the first noise cancellation capacitor of the first noise cancellation circuit. Then, since charges due to noise are accumulated in the first noise cancellation capacitor, noise can be canceled during the amplification operation of the programmable gain amplifier. As a result, noise can be reduced and high-precision of the programmable gain amplifier can be realized.

[0105] Also, in the present embodiment, during the sampling period, the first input switch is turned on, the second input switch is turned off, the first reset switch and the first noise cancellation switch are turned on, and during the noise cancellation period after the sampling period, the first reset switch may be turned off. Also, during the amplification period after the noise cancellation period, the first input switch may be turned off, the second input switch may be turned on, and the first noise cancellation switch may be turned off.

[0106] In this way, during the sampling period, the charge based on the first input signal is accumulated in the first sampling capacitor. Also, during the noise cancellation period, the charge based on the sampling noise can be accumulated in the first noise cancellation capacitor. And during the amplification period, the charge corresponding to the voltage difference between the first input signal and the second input signal is accumulated in the first feedback capacitor, and the output signal of the voltage based on this voltage difference can be output.

[0107] The present embodiment may also include a first feedback switch provided in series with the first feedback capacitor between the first input terminal and the first output terminal.

[0108] In this way, by turning on the first feedback switch, a feedback loop can be formed between the first output terminal and the first input terminal of the operational amplifier, or by turning off the first feedback switch, the feedback loop can be interrupted.

[0109] Also, in this embodiment, during the sampling period, the first input switch is turned on, the second input switch is turned off, the first reset switch, the first noise cancellation switch, and the first feedback switch are turned on. During the noise cancellation period after the sampling period, the first reset switch and the first feedback switch may be turned off. Also, during the amplification period after the noise cancellation period, the first input switch may be turned off, the second input switch may be turned on, the first noise cancellation switch may be turned off, and the first feedback switch may be turned on.

[0110] In this way, during the noise cancellation period, by turning off the first feedback switch, the feedback loop between the first output terminal and the first input terminal of the operational amplifier is cut off, and the first noise cancellation capacitor can accumulate and hold the charge based on the sampling noise. Then, during the amplification period, by turning on the first feedback switch, the above feedback loop is formed, and the amplification operation based on the capacitance ratio of the first sampling capacitor and the first feedback capacitor can be realized.

[0111] This embodiment may also include a third input switch provided between the first input node and the second node, a fourth input switch provided between the second input node and the second node, a second sampling capacitor provided between the second node and the second input terminal of the operational amplifier, and a second feedback capacitor provided between the second input terminal and the second output terminal of the operational amplifier and having a variable capacitance value according to the gain. Also, a second reset switch provided in parallel with the second feedback capacitor between the second input terminal and the second output terminal, and a second noise cancellation circuit including a second noise cancellation capacitor and a second noise cancellation switch connected in series and provided in parallel with the second feedback capacitor and the second reset switch between the second input terminal and the second output terminal may be included.

[0112] In this way, the voltage difference between the first input signal and the second input signal is amplified with a variable gain, and a first output signal is output from the first output terminal of the operational amplifier, and a second output signal is output from the second output terminal. And according to such a programmable gain amplifier having a differential configuration, compared with a programmable gain amplifier not having a differential configuration, for example, a first output signal and a second output signal in which the voltage difference is amplified with a gain of 2 times can be output, and further reduction of noise and the like becomes possible.

[0113] Also, in the present embodiment, during the sampling period, the first input switch and the fourth input switch may be turned on, the second input switch and the third input switch may be turned off, and the first reset switch, the second reset switch, the first noise canceling switch, and the second noise canceling switch may be turned on. Also, during the noise canceling period after the sampling period, the first reset switch and the second reset switch may be turned off. Also, during the amplification period after the noise canceling period, the first input switch and the fourth input switch may be turned off, the second input switch and the third input switch may be turned on, and the first noise canceling switch and the second noise canceling switch may be turned off.

[0114] In this way, during the sampling period, the charge based on the first input signal is accumulated in the first sampling capacitor, and the charge based on the second input signal is accumulated in the second sampling capacitor. Also, during the noise canceling period, the charge based on the sampling noise can be accumulated in the first noise canceling capacitor and the second noise canceling capacitor. And during the amplification period, the charge corresponding to the voltage difference between the first input signal and the second input signal is accumulated in the first feedback capacitor and the second feedback capacitor, and the first output signal and the second output signal of the voltage based on this voltage difference can be output.

[0115] In this embodiment, a first feedback switch provided in series with a first feedback capacitor between the first input terminal and the first output terminal, and a second feedback switch provided in series with a second feedback capacitor between the second input terminal and the second output terminal may be included.

[0116] In this way, when the first feedback switch and the second feedback switch are turned on, a feedback loop is formed between the first output terminal and the first input terminal and between the second output terminal and the second input terminal of the operational amplifier, and when the first feedback switch and the second feedback switch are turned off, the feedback loop can be cut off.

[0117] In this embodiment, during the sampling period, the first input switch and the fourth input switch are turned on, the second input switch and the third input switch are turned off, and the first reset switch, the second reset switch, the first noise canceling switch, the second noise canceling switch, the first feedback switch, and the second feedback switch may be turned on. Also, during the noise canceling period after the sampling period, the first reset switch, the second reset switch, the first feedback switch, and the second feedback switch may be turned off. Also, during the amplification period after the noise canceling period, the first input switch and the fourth input switch are turned off, the second input switch and the third input switch are turned on, the first noise canceling switch and the second noise canceling switch are turned off, and the first feedback switch and the second feedback switch may be turned on.

[0118] In this way, during the noise cancellation period, by turning off the first feedback switch and the second feedback switch, the feedback loops between the first output terminal and the first input terminal of the operational amplifier and between the second output terminal and the second input terminal are cut off, so that the first noise cancellation capacitor and the second noise cancellation capacitor can accumulate and hold charges based on sampling noise. Then, during the amplification period, by turning on the first feedback switch and the second feedback switch, the above feedback loop is formed, and an amplification operation based on the capacitance ratio of the first sampling capacitor to the first feedback capacitor and the capacitance ratio of the second sampling capacitor to the second feedback capacitor can be realized.

[0119] Further, the circuit device of this embodiment may include the above programmable gain amplifier and an A / D conversion circuit that A / D-converts the output signal of the programmable gain amplifier.

[0120] In this way, the A / D conversion circuit can perform A / D conversion on signals in a wide amplitude range amplified by the programmable gain amplifier, and high-precision A / D conversion can be realized.

[0121] Also, in this embodiment, a sensor circuit that outputs a detection signal as the first input signal or the second input signal to the programmable gain amplifier may be included.

[0122] In this way, it becomes possible to A / D-convert the signal amplified by the programmable gain amplifier from the detection signal of the sensor circuit by the A / D conversion circuit to obtain a digital A / D conversion result.

[0123] In this embodiment, a power supply voltage based on a common power supply may be supplied to the A / D conversion circuit and the sensor circuit. During the period when the programmable gain amplifier performs a sampling operation, the A / D conversion circuit may perform a conversion operation, and during the period when the programmable gain amplifier performs an amplification operation, the A / D conversion circuit may perform a sampling operation.

[0124] In this way, it is possible to, for example, end the sampling period of the programmable gain amplifier earlier and reduce the adverse effect of the noise generated in the A / D conversion circuit after the end timing of the sampling period on the final A / D conversion result.

[0125] Although the present embodiment has been described in detail as above, those skilled in the art will easily understand that many modifications can be made without substantially departing from the novel matters and effects of the present disclosure. Therefore, all such modified examples are included in the scope of the present disclosure. For example, in the specification or drawings, a term described at least once together with a broader or synonymous different term can be replaced with the different term at any place in the specification or drawings. Also, all combinations of the present embodiment and the modified examples are included in the scope of the present disclosure. Further, the configuration and operation of the programmable gain amplifier and the circuit device are not limited to those described in the present embodiment, and various modified implementations are possible.

Explanation of Reference Numerals

[0126] 20... Circuit device, 30... A / D converter, 40... D / A conversion circuit, 50... Programmable gain amplifier, 52... Noise cancellation circuit, 54... Noise cancellation circuit, 60... A / D conversion circuit, 70... Control circuit, 90... Sensor circuit, CC1, CC2... Capacitors for noise cancellation, CF1, CF2... Capacitors for feedback, CS1, CS2... Capacitors for sampling, N1, N2, N3, N4, N5, N6... Nodes, NI1, NI2... Input nodes, OP, OP1, OP2... Operational amplifiers, SC1, SC2... Switches for noise cancellation, SF1, SF2... Switches for feedback, SI1, SI2, SI3, SI4... Input switches, SR1, SR2... Reset switches, T1, T2... Input terminals, TQ1... Output end, TQ2... Output terminals, V1, V2, VP, VM, VQ... Voltages, VDD... Power supply, VI1, VI2... Input signals, VQ1, VQ2... Output signals

Claims

1. A programmable gain amplifier that amplifies the voltage difference between a first input signal and a second input signal with a variable gain, comprising: a first input switch provided between a first input node of the first input signal and the first node; a second input switch provided between a second input node of the second input signal and the first node; an operational amplifier; a first sampling capacitor provided between the first node and a first input terminal of the operational amplifier; a first feedback capacitor provided between the first input terminal and a first output terminal of the operational amplifier, the capacitance value of which is variable according to the gain; a first reset switch provided in parallel with the first feedback capacitor between the first input terminal and the first output terminal; a first noise cancellation circuit including a first noise cancellation capacitor and a first noise cancellation switch, which are provided in parallel with the first feedback capacitor and the first reset switch between the first input terminal and the first output terminal and are connected in series; A programmable gain amplifier characterized by including the above.

2. In the programmable gain amplifier according to Claim 1, during a sampling period, the first input switch is turned on, the second input switch is turned off, the first reset switch and the first noise cancellation switch are turned on; during a noise cancellation period after the sampling period, the first reset switch is turned off; during an amplification period after the noise cancellation period, the first input switch is turned off, the second input switch is turned on, and the first noise cancellation switch is turned off. A programmable gain amplifier characterized by this.

3. In the programmable gain amplifier according to Claim 1, characterized by including a first feedback switch provided in series with the first feedback capacitor between the first input terminal and the first output terminal.

4. In the programmable gain amplifier according to Claim 3, during a sampling period, the first input switch is turned on, the second input switch is turned off, the first reset switch, the first noise cancellation switch, and the first feedback switch are turned on; In the noise cancellation period after the sampling period, the first reset switch and the first feedback switch are turned off, In the amplification period after the noise cancellation period, the first input switch is turned off, the second input switch is turned on, the first noise cancellation switch is turned off, and the first feedback switch is turned on. A programmable gain amplifier characterized by this.

5. In the programmable gain amplifier according to claim 1, A third input switch provided between the first input node and the second node, A fourth input switch provided between the second input node and the second node, A second sampling capacitor provided between the second node and the second input terminal of the operational amplifier, A second feedback capacitor provided between the second input terminal and the second output terminal of the operational amplifier, and having a capacitance value variable according to the gain, A second reset switch provided in parallel with the second feedback capacitor between the second input terminal and the second output terminal, A second noise cancellation circuit including a second noise cancellation capacitor and a second noise cancellation switch, which are provided in parallel with the second feedback capacitor and the second reset switch between the second input terminal and the second output terminal and are connected in series, A programmable gain amplifier characterized by including.

6. In the programmable gain amplifier according to claim 5, In the sampling period, the first input switch and the fourth input switch are turned on, the second input switch and the third input switch are turned off, the first reset switch, the second reset switch, the first noise cancellation switch, and the second noise cancellation switch are turned on, In the noise cancellation period after the sampling period, the first reset switch and the second reset switch are turned off, In the amplification period after the noise cancellation period, the first input switch and the fourth input switch are turned off, the second input switch and the third input switch are turned on, and the first noise cancellation switch and the second noise cancellation switch are turned off. A programmable gain amplifier characterized by this.

7. In the programmable gain amplifier according to claim 5, A first feedback switch provided in series with the first feedback capacitor between the first input terminal and the first output terminal; A programmable gain amplifier characterized by including a second feedback switch provided in series with the second feedback capacitor between the second input terminal and the second output terminal.

8. In the programmable gain amplifier according to claim 7, During the sampling period, the first input switch and the fourth input switch are turned on, the second input switch and the third input switch are turned off, the first reset switch, the second reset switch, the first noise cancellation switch, the second noise cancellation switch, the first feedback switch, and the second feedback switch are turned on, During the noise cancellation period after the sampling period, the first reset switch, the second reset switch, the first feedback switch, and the second feedback switch are turned off, In the amplification period after the noise cancellation period, the first input switch and the fourth input switch are turned off, the second input switch and the third input switch are turned on, the first noise cancellation switch and the second noise cancellation switch are turned off, and the first feedback switch and the second feedback switch are turned on. A programmable gain amplifier characterized by this.

9. The programmable gain amplifier according to any one of claims 1 to 8, An A / D conversion circuit for A / D converting the output signal of the programmable gain amplifier, A circuit device characterized by including.

10. In the circuit device according to claim 9, A circuit device characterized by including a sensor circuit that outputs a detection signal as the first input signal or the second input signal to the programmable gain amplifier. **Claim 11** In the circuit device according to claim 10, a power supply voltage based on a common power supply is supplied to the A / D conversion circuit and the sensor circuit, and the A / D conversion circuit performs a conversion operation during a period in which the programmable gain amplifier performs a sampling operation, and the A / D conversion circuit performs a sampling operation during a period in which the programmable gain amplifier performs an amplification operation.

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