Wiring board and manufacturing method thereof

Abstract

To provide a technology that can suppress short circuits that occur between thin via conductors.SOLUTION: A method for manufacturing a wiring board includes the steps of alternately stacking internal insulating layers and internal conductive layers, arranging electronic components on or in the internal insulating layers, forming an outermost insulating layer that covers the internal conductive layers and the electronic components, forming first through holes in the outermost insulating layer to expose the internal conductive layers, desmearing the first through holes, filling the first through holes with first conductive parts and forming an outermost conductive layer on the outermost insulating layer, stacking a solder resist layer that covers the outermost conductive layer, forming second through holes in the solder resist layer and the outermost insulating layer to expose pads of the electronic components, desmearing the second through holes, and filling the second through holes with second conductive parts.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to a wiring board in which electronic components are embedded and a method for manufacturing the same.

Background Art

[0002] Conventionally, as a method for manufacturing this type of wiring board, a method is known in which via conductors connected to electronic components are made thinner than via conductors connected to an internal conductive layer (see, for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

[0020] , FIG. 12)

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the above-described conventional method for manufacturing a wiring board, a short circuit may occur between thin via conductors, and improvement thereof is demanded.

Means for Solving the Problems

[0005] One aspect of the invention is that an internal insulating layer and an internal conductive layer are alternately laminated, an electronic component is disposed on or within the internal insulating layer, an outermost insulating layer covering the internal conductive layer and the electronic component is formed, a first through-hole exposing the internal conductive layer is formed in the outermost insulating layer, the inside of the first through-hole is subjected to desmear treatment, a first conductive part is filled in the first through-hole, an outermost conductive layer is formed on the outermost insulating layer, a solder resist layer covering the outermost conductive layer is laminated, a second through-hole exposing the pad of the electronic component is formed in the solder resist layer and the outermost insulating layer, the inside of the second through-hole is subjected to desmear treatment, and a second conductive part is filled in the second through-hole, which is a method for manufacturing a wiring board including the above steps in sequence.

[0006] One aspect of the invention is a wiring board having an internal conductive layer and an internal insulating layer laminated alternately, an electronic component disposed on or within the internal insulating layer, an outermost insulating layer covering the internal conductive layer and the electronic component, an outermost conductive layer laminated on the outermost insulating layer, a solder resist layer covering the outermost conductive layer, a first through-hole formed in the outermost insulating layer to expose the internal conductive layer, a first conductive part filled in the first through-hole, a second through-hole having an inner surface continuous from the upper surface of the solder resist layer to the upper surface of the electronic component and exposing the pad of the electronic component, and a second conductive part filled in the second through-hole.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

[0008] [First Embodiment] Hereinafter, with reference to FIGS. 1 to 10, the wiring board 10 of the first embodiment will be described. The wiring board 10 shown in FIG. 1 includes a core substrate 11, build-up portions 100 laminated on both the front and back surfaces of the core substrate 11, and a solder resist layer 29 covering the build-up portions 100.

[0009] The core substrate 11 has a core base material 11K. The core base material 11K is made of an epoxy resin or a BT (bismaleimide triazine) resin and a reinforcing material such as a glass cloth. Core conductive layers 12 are laminated on both the front and back surfaces of the core base material 11K. The core conductive layer 12 on the front side and the core conductive layer 12 on the back side are connected by a through-hole conductor 13 passing through the core substrate 11. The through-hole conductor 13 is formed, for example, by forming a copper plating on the wall surface of a through-hole 13A (see FIG. 3B) passing through the core substrate 11.

[0010] The build-up portion 100 has a laminated structure in which an insulating layer 21 and a conductive layer 22 are alternately laminated on the core substrate 11. The insulating layer 21 is made of an insulating material such as a resin film or prepreg. The conductive layer 22 is made of a metal such as copper.

[0011] Between adjacent conductive layers 22 in the lamination direction and between the conductive layer 22 and the core conductive layer 12, they are connected by via conductors 17. The via conductor 17 is formed by filling a plating metal inside a via formation hole 17A that penetrates the insulating layer 21 between adjacent conductive layers 22. Also, the via conductor 17 has a tapered shape that tapers down in diameter from the front side to the back side of the core substrate 11.

[0012] Also, as shown in FIG. 2, among the conductive layers 22, a solid plane layer 31A is formed in the third layer from the outermost. Also, in the insulating layers 21 that overlap the plane layer 31A in the lamination direction, a cavity 31 that penetrates the second and third layers from the outermost is formed in the second and third insulating layers 21. The cavity 31 exposes the plane layer 31A as the bottom surface. Also, the inner peripheral surface of the cavity 31 is inclined so as to reduce the cross-section of the cavity 31 toward the bottom surface side (plane layer 31A side). Note that the inner peripheral surface of the cavity 31 may rise up so as to be substantially perpendicular to the plane layer 31A.

[0013] An electronic component 80 is housed in the cavity 31. Specifically, the electronic component 80 is mounted on an adhesive layer 33 formed on the plane layer 31A. The electronic component 80 is, for example, a semiconductor component (capacitor, inductor), and has a component body 80A and a pad 81 provided on the upper surface of the component body 80A.

[0014] The upper surfaces of the cavity 31 and the electronic component 80 are covered by the outermost insulating layer 21A. Also, the space between the inner peripheral surface of the cavity 31 and the outer peripheral surface of the electronic component 80 is filled by the outermost insulating layer 21A.

[0015] Of the second and third insulating layers 21 from the outermost where the cavity 31 is formed, a conductive layer 22 is formed on the third insulating layer 21, and no conductive layer 22 is formed on the second insulating layer 21. The conductive layer 22 on the third insulating layer 21 and the outermost conductive layer 22A are connected by a first conductive portion 24 as a via conductor 17. The first conductive portion 24 is formed by filling a plating metal inside a first through hole 23 that penetrates the outermost insulating layer 21A.

[0016] The outermost conductive layer 22A and the outermost insulating layer 21A are covered by a solder resist layer 29. A plurality of third through holes 27 are formed in the solder resist layer 29, and a part of the outermost conductive layer 22A is exposed as a pad 21B. A metal post 28A is formed on the pad 21B. The metal post 28A has a first pad 34 arranged on the solder resist layer 29 and a third conductive portion 28. The third conductive portion 28 is formed by filling a plating metal in the third through hole 27 and connects the outermost conductive layer 22A and the first pad 34. Note that the metal post 28A includes a solder bump 36 with a dome-shaped upper surface formed on the first pad 34.

[0017] Now, in addition to the first pad 34, a second pad 35 is provided on the solder resist layer 29. The second pad 35 is arranged above the electronic component 80 and is connected to the pad 81 of the electronic component 80 via a second conductive portion 26. The second conductive portion 26 is formed by filling a plating metal in a second through hole 25 that penetrates both the solder resist layer 29 and the outermost insulating layer 21A and is integrally formed with the second pad 35. The inner surface of the second through hole 25 is a tapered surface that continuously reduces in diameter from the upper surface of the solder resist layer 29 to the pad 81 of the electronic component 80. Note that a solder bump 36 is also formed on the second pad 35.

[0018] The second conductive part 26 is thinner than the first conductive part 24, and the diameter of the lower end is about 40 nm. Also, in this embodiment, while the distance between the first conductive parts 24 is 100 μm or more, the distance between the second conductive parts 26 is about 40 to 80 μm, which is smaller than the distance between the first conductive parts 24.

[0019] The description of the structure of the wiring board 10 is as above. Next, a manufacturing method of the wiring board 10 will be described.

[0020] (1) As shown in FIG. 3A, through holes 13A are formed in a core base material 11K with copper foils (not shown) laminated on the front and back surfaces by, for example, drilling.

[0021] (2) By electroless plating treatment, plating resist treatment, and electrolytic plating treatment, core conductive layers 12 are formed on both the front and back surfaces of the core base material 11K, and through hole conductors 13 are formed on the inner surfaces of the through holes 13A (FIG. 3B). Thereby, the core board 11 is completed.

[0022] (3) As shown in FIG. 3C, an insulating layer 21 and a conductive layer 22 are laminated on the core conductive layer 12. Specifically, resin films as the insulating layer 21 are overlapped on both surfaces of the core conductive layer 12 and heated and pressed, and then irradiated with a CO2 laser to form via formation holes 17A penetrating the insulating layer 21. Then, electroless plating treatment, plating resist treatment, and electrolytic plating treatment are performed, and electrolytic plating is filled into the via formation holes to form via conductors 17. Then, when the plating resist and the electroless plating film and copper foil in the portion where the plating resist overlapped are removed, a conductive layer 22 having a predetermined pattern is formed on the insulating layer 21.

[0023] Note that as the insulating layer 21, a prepreg (a B-stage resin sheet obtained by impregnating a core material with resin) may be used instead of a resin film. In this case, a copper foil is laminated together with the prepreg.

[0024] (4) In the same manner as in the process of (3) above, an insulating layer 21 and a conductive layer 22 are alternately laminated on the front side and the back side of the core substrate 11 (FIG. 4A). At this time, via conductors 17 penetrating the insulating layer 21 are formed, and the conductive layers 22 adjacent to each other in the lamination direction are connected by the via conductors 17. Note that only the front side is shown in FIG. 4. Hereinafter, the same shall apply to FIGS. 5 to 10.

[0025] (5) As shown in FIG. 4B, for example, a solid planar layer 31A is formed on the fourth conductive layer 22 from the core substrate 11 side.

[0026] (6) As shown in FIG. 5A, an insulating layer 21 and a conductive layer 22 are laminated on the conductive layer 22 including the planar layer 31A. Next, as shown in FIG. 5B, an insulating layer 21 is further laminated on the conductive layer 22.

[0027] (7) As shown in FIG. 6A, a cavity 31 is formed by irradiating with a CO2 laser, which penetrates through two layers of the insulating layer 21 and reaches the upper surface of the planar layer 31A. Here, the area of the range irradiated with the laser, that is, the opening area of the cavity 31, is smaller than the area of the planar layer 31A, and the entire bottom surface of the cavity 31 is formed only by the planar layer 31A.

[0028] (8) As shown in FIG. 6B, an adhesive layer 33 is laminated on the planar layer 31A exposed as the bottom surface of the cavity 31, and an electronic component 80 is placed on the adhesive layer 33, and a thermosetting process is performed.

[0029] (9) As shown in FIG. 7A, the outermost insulating layer 21A is laminated so as to cover the insulating layer 21 and the cavity 31. Specifically, a resin film as the outermost insulating layer 21A is overlapped so as to cover the insulating layer 21 and the cavity 31, and heat-pressed. At this time, a part of the melted resin film fills the space between the inner peripheral surface of the cavity 31 and the outer peripheral surface of the electronic component 80.

[0030] Before the resin film is stacked on the cavity 31, a filling resin may be filled between the inner peripheral surface of the cavity 31 and the outer peripheral surface of the electronic component 80. With this configuration, voids are less likely to occur.

[0031] (10) As shown in FIG. 7B, a first through hole 23 that reaches the internal conductive layer 22 is formed from the outermost insulating layer 21A. The first through hole 23 is formed by a CO2 laser, and the laser wavelength is 1000 to 15000 nm. Note that the first through hole 23 may be formed by a UV laser or other processing methods.

[0032] (11) Next, the inside of the first through hole 23 is subjected to desmear treatment. Specifically, after swelling the resin residue inside the first through hole 23 by conditioner treatment and then treating it with alkaline permanganate, the resin residue dissolves and the internal conductive layer 22 is exposed as a clean surface.

[0033] In this embodiment, alkaline permanganate is used as the desmear liquid, but desmear treatment may be performed by a plasma method.

[0034] (12) As shown in FIG. 8A, the outermost conductive layer 22A is formed, and the first conductive portion 24 is filled inside the first through hole 23.

[0035] (13) As shown in FIG. 8B, a solder resist layer 29 is laminated so as to cover the outermost conductive layer 22A. Note that as the solder resist layer 29, a film type may be laminated, or an ink type may be applied.

[0036] (14) As shown in FIG. 9A, a third through hole 27 is formed by photolithography. Note that the third through hole 27 may be formed by a UV laser in the same manner as the second through hole 25 described later.

[0037] (15) As shown in FIG. 9B, a second through-hole 25 is formed from the upper surface of the solder resist layer 29 to the upper surface of the pad 81 of the electronic component 80. Specifically, a UV laser irradiates the solder resist layer 29, and the solder resist layer 29 and the outermost insulating layer 21A are penetrated together. The wavelength of the UV laser is 100 - 500 nm.

[0038] (16) Next, the inside of the second through-hole 25 is subjected to desmear treatment. The treatment time at this time is shorter than the desmear treatment time of the first through-hole 23.

[0039] (17) An electroless plating film and a plating resist (not shown) are formed on the solder resist layer 29. Next, by electrolytic plating, an electrolytic plating layer is formed on the portion exposed from the plating resist, the first pad 34 and the second pad 35 are formed, and the second conductive part 26 and the third conductive part 28 are formed inside the second through-hole 25 and the third through-hole 27.

[0040] As shown in FIG. 10, solder bumps 36 are formed by electrolytic plating on the first pad 34 and the second pad 35, the plating resist and the electroless plating film are removed, and the wiring board 10 is completed.

[0041] Now, in a conventional wiring board in which the pads of the electronic component are connected to the outermost conductive layer, there has been a problem that a short circuit easily occurs between the via conductors connected to the electronic component. This is presumably because the via holes of the via conductors connected to the electronic component and the via holes of the via conductors connected to the internal conductive layer are subjected to desmear treatment under the same conditions.

[0042] Specifically, the via conductors connected to the electronic components are required to have fine wiring for the conductor patterns. They are thinner and have a narrower pitch compared to the via conductors connected to the internal conductive layers. Therefore, when desmearing the thin via holes on the electronic components under the condition of matching them with the thick via holes on the internal conductive layers, the resin on the inner surface of the via holes on the electronic components is removed more than necessary, and plating is applied even to the removed portions, resulting in a short circuit inside the via holes on the electronic components.

[0043] On the other hand, in the wiring board 10 of the present embodiment, after the inside of the first through hole 23 is desmeared and the first conductive portion 24 is formed, the second through hole 25 is formed, and the inside of the second through hole 25 is desmeared. According to this, since the desmearing process for the first through hole 23 and the second through hole 25 that is thinner than the first through hole 23 is performed under appropriate conditions for each, the occurrence of a short circuit can be prevented.

[0044] Also, by forming the second through hole 25 so as to penetrate through the solder resist layer 29 and the outermost insulating layer 21A together, it is possible to reduce the deviation between the through holes and resin residues compared to the case where the solder resist layer 29 and the outermost insulating layer 21A are provided separately.

[0045] Furthermore, while the first through hole 23 and the second through hole 25 are formed by a laser, the third through hole 27 is formed by a photolithography process. According to this, the third through hole 27 that is thicker than the second through hole 25 can be formed in a batch, and the second through hole 25 can be accurately formed by a laser.

[0046] Also, for the minute second through hole 25, by using a UV laser with less thermal influence, it is possible to form the highly accurate second through hole 25 while reducing resin residues. For the relatively large-diameter first through hole 23, by using a CO2 laser, it is possible to efficiently form the large-diameter first through hole 23.

[0047] Also, by forming the first through-hole 23 with a laser having a wavelength of 1000 to 15000 nm and forming the second through-hole 25 with a laser having a wavelength smaller than that, i.e., 100 to 500 nm, the large-diameter first through-hole 23 can be efficiently formed, and the minute second through-hole 25 can be formed with high precision. Further, since the interval between the second through-holes 25 is narrower than the interval between the first through-holes 23, it is preferable to use a UV laser having a wavelength of 355 nm.

[0048] Also, in order to prevent short circuits due to excessive oxidation, it is preferable to make the time of the desmear treatment performed on the second through-hole 25 shorter than the time of the desmear treatment performed on the first through-hole 23.

[0049] [Other Embodiments] The third through-hole 27 may be formed by photolithography or may be formed by laser processing such as a CO2 laser. In this case, after the third through-hole 27 is formed, the desmear treatment is performed, and then the second through-hole 25 is formed.

[0050] The electronic component 80 may not be embedded in the build-up portion 100, and may be accommodated, for example, inside a cavity formed through the core substrate 11.

[0051] The second conductive portion 26 may not be connected to the electronic component 80, and may be connected to the internal conductive layer 22.

[0052] In the first embodiment, the second through-hole 25 is formed after the third through-hole 27 is formed, but the third through-hole 27 may be formed after the second through-hole 25 is formed. In this case, after the second through-hole 25 is formed and the desmear treatment is performed, the third through-hole 27 is formed.

[0053] The first through-hole 23 and the third through-hole 27 may have the same diameter or may not have the same diameter.

[0054] [Description of Reference Numerals] 10 Wiring Substrate 11 Core substrate 13 Through-hole conductor 13A Through-hole 21 Insulating layer 21A Insulating layer 22 Conductive layer 22A Conductive layer 23 First through-hole 24 First conductive part 25 Second through-hole 26 Second conductive part 27 Third through-hole 28 Third conductive part 29 Solder resist layer 80 Electronic component

Claims

1. An internal insulating layer and an internal conductive layer are alternately laminated; electronic components are disposed on or within the internal insulating layer; an outermost insulating layer covering the internal conductive layer and the electronic components is formed; a first through-hole for exposing the internal conductive layer is formed in the outermost insulating layer; the inside of the first through-hole is subjected to desmear treatment; a first conductive portion is filled in the first through-hole, and an outermost conductive layer is formed on the outermost insulating layer; a solder resist layer covering the outermost conductive layer is laminated; a second through-hole for exposing pads of the electronic components is formed in the solder resist layer and the outermost insulating layer; the inside of the second through-hole is subjected to desmear treatment; a second conductive portion is filled in the second through-hole, in this order, in a method for manufacturing a wiring board.

2. A method for manufacturing a wiring board according to Claim 1, wherein a diameter of the second through-hole is smaller than a diameter of the first through-hole.

3. A method for manufacturing a wiring board according to Claim 1, wherein a third through-hole for exposing the outermost conductive layer is formed in the solder resist layer; and a third conductive portion is filled in the third through-hole.

4. A method for manufacturing a wiring board according to Claim 3, wherein the third through-hole is formed by photolithography.

5. A method for manufacturing a wiring board according to Claim 4, wherein a diameter of the third through-hole is larger than a diameter of the second through-hole.

6. A method for manufacturing a wiring board according to any one of Claims 1 to 5, wherein the first through-hole and the second through-hole are formed by a laser.

7. A method for manufacturing a wiring board according to Claim 6, wherein the first through-hole is formed by an infrared laser, and the second through-hole is formed by an ultraviolet laser.

8. A method for manufacturing a wiring board according to Claim 7, The formation of the first through hole is performed by a CO ２ laser, and the formation of the second through hole is performed by a UV laser.

9. A method for manufacturing a wiring board according to any one of Claims 1 to 5, wherein a plurality of the first conductive portions and a plurality of the second conductive portions are provided; and a distance between the second conductive portions is narrower than a distance between the first conductive portions.

10. A method for manufacturing a wiring board according to Claim 9, wherein the distance between the second conductive portions is 80 microns or less.

11. A method for manufacturing a wiring board according to any one of claims 1 to 5, wherein the processing time of the desmear treatment in the second through hole is shorter than the processing time of the desmear treatment in the first through hole.

12. alternately laminated internal conductive layers and internal insulating layers, electronic components disposed on or within the internal insulating layer, an outermost insulating layer covering the internal conductive layer and the electronic components, an outermost conductive layer laminated on the outermost insulating layer, a solder resist layer covering the outermost conductive layer, a first through hole formed in the outermost insulating layer to expose the internal conductive layer, a first conductive portion filled in the first through hole, a second through hole having an inner surface continuous from the upper surface of the solder resist layer to the upper surface of the electronic component and exposing the pads of the electronic component, and a second conductive portion filled in the second through hole. A wiring board having

13. A wiring board according to claim 12, wherein the aperture diameter of the second through hole is smaller than the aperture diameter of the first through hole.

14. A wiring board according to claim 12, wherein a third through hole is provided in the solder resist layer to expose the outermost conductive layer, and a third conductive portion is formed in the third through hole.

15. A wiring board according to claim 14, wherein the aperture diameter of the third through hole is larger than the aperture diameter of the second through hole.

16. A wiring board according to any one of claims 12 to 15, wherein a plurality of the first conductive portions and a plurality of the second conductive portions are provided, and the interval between the second conductive portions is narrower than the interval between the first conductive portions.

17. A wiring board according to claim 16, wherein the interval between the second conductive portions is 80 microns or less.

Images