Semiconductor light-emitting element and method of manufacturing semiconductor light-emitting element

Abstract

To provide a semiconductor light-emitting element capable of uniformizing a current density injected to an active layer which is formed on a side face of a nanowire, and a method of manufacturing a semiconductor light-emitting element.SOLUTION: A semiconductor light-emitting element (100) comprises a growth substrate (10), a mask (30) formed on the growth substrate (10), and a columnar semiconductor layer (40) grown from an opening which is provided in the mask (30). In the semiconductor light-emitting element (100), an n-type nanowire layer (41) is formed in a center of the columnar semiconductor layer (40), an active layer (42) is formed in an outer periphery of the n-type nanowire layer (41), and a p-type semiconductor layer (43) is formed in an outer periphery of the active layer (42). An n-type impurity concentration of the n-type nanowire layer (41) is larger at the side of the growth substrate (10) than that at a tip side.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor light-emitting element and a method for manufacturing the semiconductor light-emitting element.

Background Art

[0002] In recent years, the crystal growth method of nitride semiconductors has advanced rapidly, and high-brightness light-emitting elements using this material have been put into practical use. In a semiconductor light-emitting element using such a nitride semiconductor, it is desirable to achieve high energy conversion efficiency and high light output in a high current density region, and it is desirable that the light distribution characteristics of the emitted light are stable. In order to solve these problems, Patent Document 1 proposes a semiconductor light-emitting element in which an n-type nanowire core, an active layer, and a p-type layer are grown on a semiconductor substrate.

[0003] In a semiconductor light-emitting element in which an active layer is formed on the outer periphery of the nanowire core disclosed in Patent Document 1, there are fewer crystal defects and threading dislocations than in a case where the active layer is formed on the entire surface of a sapphire substrate, and a high-quality crystal can be obtained. Also, since m-plane growth is possible, the external quantum efficiency at high current density can be improved. Further, in the semiconductor light-emitting element using the nanowire core of Patent Document 1, since the active layer can be formed of a high-quality crystal, it is expected to increase the In composition of the active layer to achieve a longer wavelength.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In conventional semiconductor light-emitting devices, nanowires with a high aspect ratio in the height direction are used, and current is injected from the p-type layer into the active layer formed on the side surface of the nanowire. Therefore, the current density is high at the upper part of the nanowire and tends to be low at the lower part. For this reason, it is difficult to perform uniform current injection into the active layer, and it is difficult to improve the light-emitting efficiency of the entire nanowire.

[0006] Therefore, the present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device capable of equalizing the current density injected into the active layer formed on the side surface of the nanowire.

Means for Solving the Problems

[0007] In order to solve the above problems, a semiconductor light-emitting device of the present invention is a semiconductor light-emitting device including a growth substrate, a mask formed on the growth substrate, and a columnar semiconductor layer grown from an opening provided in the mask, wherein the columnar semiconductor layer has an n-type nanowire layer formed at the center, an active layer formed on the outer periphery of the n-type nanowire layer, a p-type semiconductor layer formed on the outer periphery of the active layer, and the n-type impurity concentration of the n-type nanowire layer is larger on the growth substrate side than on the tip side.

[0008] In such a semiconductor light-emitting device of the present invention, since the n-type impurity concentration of the n-type nanowire layer is larger on the growth substrate side than on the tip side, the electrical conductivity of the n-type nanowire layer on the growth substrate side is increased, and it becomes possible to equalize the current density injected into the active layer formed on the side surface of the nanowire.

[0009] In one aspect of the present invention, the n-type impurity concentration of the n-type nanowire layer gradually decreases from the growth substrate side toward the tip side.

[0010] In one aspect of the present invention, the n-type nanowire layer includes a first region on the growth substrate side and a second region on the tip side, and the gradient of the n-type impurity concentration is larger in the first region than in the second region.

[0011] Also, in one aspect of the present invention, the n-type impurity concentration in the second region has a maximum value that is 1.2 times or more the minimum value.

[0012] Also, in one aspect of the present invention, the n-type impurity concentration in the second region has a maximum value of 3×10 20 / cm 3 or less.

[0013] Also, in one aspect of the present invention, the p-type impurity concentration of the p-type semiconductor layer is higher around the tip side than around the periphery on the growth substrate side.

[0014] In order to solve the above problems, a method for manufacturing a semiconductor light-emitting device according to the present invention includes a mask step of forming a mask layer having an opening on a growth substrate, and a growth step of forming a columnar semiconductor layer in the opening using selective growth. The growth step includes a nanowire growth step of forming an n-type nanowire layer, an active layer growth step of forming an active layer outside the n-type nanowire layer, and a p-type layer growth step of forming a p-type semiconductor layer outside the active layer. The nanowire growth step is characterized by increasing the n-type impurity concentration on the growth substrate side rather than on the tip side.

[0015] Also, in one aspect of the present invention, in the nanowire growth step, the supply amount of n-type impurities is decreased on the tip side rather than on the growth substrate side.

[0016] Also, in one aspect of the present invention, in the nanowire growth step, the growth temperature is decreased on the tip side rather than on the growth substrate side.

Advantages of the Invention

[0017] The present invention can provide a semiconductor light-emitting device and a method for manufacturing a semiconductor light-emitting device capable of equalizing the current density injected into the active layer formed on the side surface of the nanowire.

Brief Description of the Drawings

[0018]

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[0019] (First Embodiment) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. FIG. 1 is a schematic diagram showing a semiconductor light-emitting element 100 according to the present embodiment.

[0020] As shown in FIG. 1, the semiconductor light-emitting element 100 includes a growth substrate 10, an underlying layer 20, a mask 30, an n-type nanowire layer 41, an active layer 42, a p-type semiconductor layer 43, a tunnel junction layer 44, an embedded semiconductor layer 50, a protective film 60, an anode electrode 70, and a cathode electrode 80. Here, the n-type nanowire layer 41, the active layer 42, the p-type semiconductor layer 43, and the tunnel junction layer 44 are selectively grown in a direction perpendicular to the growth substrate 10 to form a columnar shape, and constitute a columnar semiconductor layer 40 in the present invention.

[0021] The growth substrate 10 is a substantially flat member made of a material capable of crystal-growing a semiconductor material, and a mask 30 is formed on the main surface side. The growth substrate 10 may be made of a single material, or a material obtained by growing a plurality of semiconductor layers such as a buffer layer on a single crystal substrate may be used. The growth substrate 10 may be a single crystal substrate made of a material for growing a semiconductor single crystal layer via a buffer layer. When the semiconductor light-emitting element 100 is made of a nitride-based semiconductor, a c-plane sapphire substrate is preferable, but other heterogeneous substrates such as Si may also be used. Further, in order to cause laser oscillation, a c-plane GaN substrate whose resonator surface is easily formed by cleavage may be used. The buffer layer is a layer formed between the single crystal substrate and the underlying layer 20 to relax the lattice mismatch between the two. When a c-plane sapphire substrate is used as the single crystal substrate, it is preferable to use GaN as the material, but AlN, AlGaN, or the like may also be used.

[0022] The underlying layer 20 is a single-crystalline semiconductor layer formed on the growth substrate 10 or the buffer layer, and it is preferably composed of a plurality of layers in which undoped GaN is formed with a thickness of several micrometers, and an n-type semiconductor layer such as an n-type contact layer is provided thereon. The n-type contact layer is a semiconductor layer doped with an n-type impurity, for example, n-type Al doped with Si 0.05 Ga 0.95 N and the like can be mentioned. As shown in FIG. 1, a cathode electrode 80 is formed in a part of the underlying layer 20.

[0023] The mask 30 is a layer made of a dielectric material formed on the surface of the underlying layer 20. As the material constituting the mask 30, a material that is difficult for semiconductor crystal growth is selected. For example, SiO2, SiN x or Al2O3 and the like are suitable. A plurality of openings described later are formed in the mask 30, and a semiconductor layer can grow from the underlying layer 20 within the openings.

[0024] The columnar semiconductor layer 40 is a semiconductor layer grown by crystal growth in the openings provided in the mask 30, and a substantially columnar semiconductor layer is formed upright with respect to the main surface of the growth substrate 10. Such a columnar semiconductor layer 40 can be obtained by setting appropriate growth conditions according to the semiconductor material constituting it and performing selective growth in which a specific crystal plane orientation grows. In the example shown in FIG. 1, since a plurality of openings are formed two-dimensionally and periodically in the mask 30, the columnar semiconductor layer 40 is also formed two-dimensionally and periodically on the growth substrate 10.

[0025] The n-type nanowire layer 41 is a columnar semiconductor layer selectively grown on the underlying layer 20 exposed from the opening of the mask 30, and is composed of, for example, GaN doped with n-type impurities. When GaN is used as the n-type nanowire layer 41, the n-type nanowire layer 41 selectively grown on the c-plane of the underlying layer 20 has a substantially hexagonal column shape with six m-planes formed as facets. In FIG. 1, it appears that the n-type nanowire layer 41 grows only in the region where the opening is formed, but actually, crystal growth also proceeds on the mask 30 due to lateral growth, so that an enlarged hexagonal column is formed around the opening. For example, when the opening is formed as a circle with a diameter of about 150 nm, an n-type nanowire layer 41 having a hexagonal column shape with a height of about 1 to 2 μm and a hexagonal shape inscribed in a circle with a diameter of about 240 nm as the bottom surface can be formed.

[0026] The active layer 42 is a semiconductor layer grown on the outer periphery of the n-type nanowire layer 41. Examples thereof include a multiple quantum well active layer in which a GaInN quantum well layer with a thickness of 5 nm and a GaN barrier layer with a thickness of 10 nm are stacked 5 times. Here, a multiple quantum well active layer is exemplified, but a single quantum well structure or a bulk active layer may also be used. Since the active layer 42 is formed on the side surface and the upper surface of the n-type nanowire layer 41, the area of the active layer 42 can be ensured. The higher the ratio of In incorporated into the active layer, the longer the emission wavelength of the semiconductor light-emitting device 100. By setting the In composition ratio to 0.1 or more, the emission wavelength can be set to 480 nm or more. Further, by setting the In composition ratio to 0.12 or more, the emission wavelength can be set to 500 nm or more.

[0027] The p-type semiconductor layer 43 is a semiconductor layer grown on the outer periphery of the active layer 42, and is composed of, for example, GaN doped with p-type impurities. Since the p-type semiconductor layer 43 is formed on the side surface and the upper surface of the active layer 42, a double heterostructure is formed by the n-type nanowire layer 41, the active layer 42, and the p-type semiconductor layer 43, and carriers can be well confined in the active layer 42 to improve the probability of emission recombination.

[0028] The tunnel junction layer 44 is a semiconductor layer grown on the outer periphery of the p-type semiconductor layer 43. For example, it has a two-layer structure in which a p+ layer highly doped with p-type impurities on the inner side and an n+ layer highly doped with n-type impurities on the outer side are grown in sequence. The p+ layer is a semiconductor layer highly doped with p-type impurities. For example, GaN with a thickness of 5 nm and a Mg concentration of 2×10 20 cm -3 can be used. The n+ layer can be, for example, GaN with a thickness of 10 nm and a Si concentration of 2×10 20 cm -3 Since a tunnel junction is formed by the p+ layer and the n+ layer, the two layers of the p+ layer and the n+ layer constitute the tunnel junction layer 44 in the present invention.

[0029] The embedded semiconductor layer 50 is a semiconductor layer formed to cover the upper surface and the side surface of the columnar semiconductor layer 40 and to cover up to the mask 30. As shown in FIG. 1, above the columnar semiconductor layer, the embedded semiconductor layer 50 also covers the tunnel junction layer 44. The embedded semiconductor layer 50 is an n-type semiconductor layer in order to make an ohmic contact with the anode electrode 70 and inject carriers through the tunnel junction layer 44. Here, the embedded semiconductor layer 50 is shown as a single layer, but it may be composed of a plurality of semiconductor layers having different materials, compositions, and impurity concentrations.

[0030] The anode electrode 70 is an electrode formed on a part of the embedded semiconductor layer 50, and is composed of a laminated structure of a metal material that makes an ohmic contact with the outermost surface of the embedded semiconductor layer 50 and a pad electrode. The cathode electrode 80 is an electrode formed in a region where the underlying layer 20 is exposed, and is composed of a laminated structure of a metal material that makes an ohmic contact with the outermost surface of the underlying layer 20 and a pad electrode. Also, a known structure such as covering the surface of the semiconductor light-emitting element 100 with a protective film 60 may be applied as necessary. Further, a transparent electrode extending from the anode electrode 70 may be formed over the entire upper surface of the embedded semiconductor layer 50.

[0031] When increasing the emission wavelength of the semiconductor light-emitting element 100, it is necessary to increase the InN molar fraction of the active layer 42. For example, when the outer circumscribed circle diameter of the n-type nanowire layer 41 is 300 nm, it is necessary to use red active layer composition Ga 0.6 In 0.4 N. However, as the InN molar fraction increases, the compressive stress increases, and misfit dislocations may occur. To avoid this, it is also possible to reduce the film thickness of the Ga 0.6 In 0.4 N well layer or use GaInN as the material constituting the n-type nanowire layer 41. Similarly, when shortening the wavelength of the semiconductor light-emitting element 100, it is also possible to use AlGaN as the n-type nanowire layer 41 or change the well layer and barrier layer of the active layer 42 to AlGaN with different compositions, respectively.

[0032] FIG. 2 is a diagram schematically showing the structure and impurity concentration of the columnar semiconductor layer 40 according to the present embodiment. In the figure, the gradations applied to the n-type nanowire layer 41, the p-type semiconductor layer 43, and the tunnel junction layer 44 visually represent the gradient of the impurity concentration in each layer. In the present embodiment, as shown in FIG. 2, in the n-type nanowire layer 41, the concentration of the n-type impurity is larger on the growth substrate 10 side than on the tip side and gradually decreases from the growth substrate 10 side toward the tip side. The method of forming and measuring the concentration gradient of the n-type impurity in the n-type nanowire layer 41 will be described later.

[0033] Also, in the p-type semiconductor layer 43 and the p+ layer of the tunnel junction layer 44, the concentration of the p-type impurity is larger on the tip side than on the growth substrate 10 side and gradually decreases from the tip side toward the growth substrate side. The concentration gradient of the p-type impurity in the p-type semiconductor layer 43 may be naturally formed because the aspect ratio of the n-type nanowire layer 41 is large and the raw material of the p-type impurity is not sufficiently supplied to the growth substrate 10 side.

[0034] FIG. 3 is a schematic diagram showing a method for manufacturing the semiconductor light-emitting device 100 according to the present embodiment. FIG. 3(a) shows a mask formation step, FIG. 3(b) shows a nanowire growth step and an active layer growth step, FIG. 3(c) shows a p-type layer growth step and a tunnel junction layer growth step, FIG. 3(d) shows an embedding step, and FIG. 3(e) shows an electrode formation step.

[0035] First, in the mask formation step shown in FIG. 3(a), a buffer layer made of GaN and a base layer 20 made of GaN and AlGaN are grown on a growth substrate 10 made of a sapphire single crystal using metal-organic chemical vapor deposition (MOCVD). Next, a mask 30 made of SiO2 is deposited on the base layer 20 by sputtering to a thickness of about 30 nm, and a plurality of openings 31 having a diameter of about 150 nm are formed using a fine pattern formation method such as nanoimprint lithography. As the growth conditions of the buffer layer, for example, TMA (TriMethylAlminium), TMG (TriMethylGallium), and ammonia are used as source gases, the growth temperature is 1100°C, the V / III ratio is 1000, and hydrogen is used as a carrier gas at a pressure of 10 hPa. As the growth conditions of the base layer 20 and the n-type semiconductor layer, for example, the growth temperature is 1050°C, the V / III ratio is 1000, and hydrogen is used as a carrier gas at a pressure of 500 hPa.

[0036] Next, in the nanowire growth step shown in FIG. 3(b), an n-type nanowire layer 41 made of GaN is grown on the base layer 20 exposed from the openings 31 by selective growth using the MOCVD method. As the growth conditions of the n-type nanowire layer 41, for example, TMG and ammonia are used as source gases, the growth temperature is 1050°C, the V / III ratio is 10, and hydrogen is used as a carrier gas at a pressure of 100 hPa. In the height direction of the n-type nanowire layer 41, the concentration of the n-type impurity gradually decreases from the growth substrate 10 side toward the tip side as described above. The method for forming the concentration gradient and the measurement method will be described later.

[0037] In the active layer growth process, an active layer 42 is grown on the side and top surfaces of the n-type nanowire layer 41 by using the MOCVD method, with 5 cycles of a 5-nm-thick GaInN quantum well layer and a 10-nm-thick GaN barrier layer stacked. As the growth conditions for the active layer 42, for example, the growth temperature is 800 °C, the V / III ratio is 3000, nitrogen is used as the carrier gas at a pressure of 1000 hPa, and TMG, TMI (TriMethylIndium), and ammonia are used as the source gases.

[0038] Next, in the p-type layer growth process shown in Fig. 3(c), a p-type semiconductor layer 43 made of GaN doped with p-type impurities is grown. As the growth conditions for the p-type semiconductor layer 43, for example, the growth temperature is 950 °C, the V / III ratio is 1000, hydrogen is used as the carrier gas at a pressure of 300 hPa, and TMG, Cp2Mg (bisCycropentadienylMagnesium), and ammonia are used as the source gases.

[0039] Also, in the tunnel junction layer growth process, a tunnel junction layer 44 including a p+-type layer made of GaN with a thickness of 5 nm and an Mg concentration of 2×10 20 cm -3 and an n+-type layer made of GaN with a thickness of 10 nm and an Si concentration of 2×10 20 cm -3 is grown. As the growth conditions for the tunnel junction layer 44, for example, the growth temperature is 800 °C, the V / III ratio is 3000, and nitrogen is used as the carrier gas at a pressure of 500 hPa. Thereby, a columnar semiconductor layer 40 is formed by the n-type nanowire layer 41, the active layer 42, the p-type semiconductor layer 43, and the tunnel junction layer 44.

[0040] Next, in the embedding process shown in FIG. 3(d), an embedded semiconductor layer 50 made of n-type GaN is grown, and the outer periphery and upper surface of the tunnel junction layer 44 are filled with the embedded semiconductor layer 50. The embedded semiconductor layer 50 needs to be grown on the mask 30 provided between the columnar semiconductor layers 40, and voids may occur at the lower part of the columnar semiconductor layer 40 when the embedded semiconductor layer 50 is grown. Therefore, in the growth of the embedded semiconductor layer 50, it is preferable to use TMG, silane, and ammonia as source gases and grow at a low temperature and a low V / III ratio that promotes the growth of the m-plane, which is lateral growth, in the initial stage. As an example of a low temperature and a low V / III ratio, a growth at 800°C or lower with a V / III ratio of 100 or lower and a pressure of 200 hPa using hydrogen as a carrier gas can be mentioned. After the upper part of the mask 30 is filled without gaps at the lower part of the columnar semiconductor layer 40 by the lateral growth of the embedded semiconductor layer 50, it is preferable to grow at a high temperature and a high V / III ratio that promotes the growth of the c-plane, which is vertical growth. As an example of a high temperature and a high V / III ratio, a growth at 1000°C or higher with a V / III ratio of 2000 or higher and a pressure of 500 hPa using hydrogen as a carrier gas can be mentioned.

[0041] Next, in the electrode formation process shown in FIG. 3(e), the element isolation region and the region for forming the cathode electrode 80 are selectively dry-etched, and the embedded semiconductor layer 50 and the columnar semiconductor layer 40 are removed up to the mask 30 to expose the upper surface of the underlying layer 20. Then, annealing is performed at 600°C in an air atmosphere to remove the hydrogen incorporated into the p-type semiconductor layer 43 and the p-type semiconductor layer in the tunnel junction layer 44, and activate the p-type semiconductor layer 43 and the tunnel junction layer 44. Although annealing in an air atmosphere is shown here, an atmosphere without atomic hydrogen that can activate the p-type semiconductor layer 43 and the tunnel junction layer 44 may be used.

[0042] Finally, an anode electrode 70 is formed on the embedded semiconductor layer 50, and a cathode electrode 80 is formed on the surface of the underlying layer 20. Further, if necessary, annealing after electrode formation, formation of a protective film 60, and element division are performed to obtain the semiconductor light-emitting element 100.

[0043] FIG. 4 is a graph showing changes in temperature and the supply amount of n-type impurities during the nanowire growth process. FIG. 4(a) shows an example in which the supply amount of n-type impurities is changed, and FIG. 4(b) shows an example in which the temperature is changed. In FIGS. 4(a) and 4(b), the horizontal axis represents the passage of time, and the vertical axis in the figure represents the relative changes in temperature and the supply amount of n-type impurities. In the example shown in FIG. 4(a), while keeping the growth temperature of the n-type nanowire layer 41 constant, the flow rate of the Si raw material, which is the supply amount of n-type impurities, is gradually decreased step by step. As a result, the concentration of n-type impurities is high below the n-type nanowire layer 41 (on the side of the growth substrate 10), and the concentration of n-type impurities becomes low toward the upper side (tip side), and the impurity concentration gradient shown in FIG. 2 can be realized.

[0044] In the example shown in FIG. 4(b), while keeping the flow rate of the Si raw material, which is the supply amount of n-type impurities, constant, the growth temperature of the n-type nanowire layer 41 is gradually decreased step by step. As a result, the amount of n-type impurities incorporated is large below the n-type nanowire layer 41 (on the side of the growth substrate 10), and the amount of n-type impurities incorporated becomes small toward the upper side (tip side), so that the impurity concentration gradient shown in FIG. 2 can be realized.

[0045] In FIG. 4, an example is shown in which either the temperature or the supply amount of n-type impurities is kept constant and the other is changed, but both may be changed together. Further, the changes in temperature and the supply amount of n-type impurities are not limited to the stepwise ones shown in FIG. 4, and may be gradually decreased. Also, the amount of change in temperature and the supply amount of n-type impurities is not limited to a fixed value, and the amount of change at each step may be changed. Further, since the nitride semiconductor tends to have n-type conductivity without intentionally doping with n-type impurities, when growing near the tip of the n-type nanowire layer 41, the supply amount of n-type impurities may be set to zero. Also, during the growth of the n-type nanowire layer 41, the supply amount of n-type impurities may be set to zero, and the n-type impurities remaining in the MOCVD apparatus may be incorporated into the semiconductor layer.

[0046] In the semiconductor light-emitting device 100 of the present embodiment, when a voltage is applied between the anode electrode 70 and the cathode electrode 80, current flows in the order of the embedded semiconductor layer 50, the tunnel junction layer 44, the p-type semiconductor layer 43, the active layer 42, the n-type nanowire layer 41, and the base layer 20, and light is generated by emission recombination in the active layer 42. The light emitted from the active layer 42 is extracted to the outside of the semiconductor light-emitting device 100.

[0047] Also, in the semiconductor light-emitting device 100 of the present embodiment, the active layer 42 is formed on the outer periphery rather than the n-type nanowire layer 41, and further, the tunnel junction layer 44 is formed on the outer periphery thereof and is embedded in the embedded semiconductor layer 50. Therefore, the current injected from the anode electrode 70 is injected into the active layer 42 from the side wall of the p-type semiconductor layer 43 as a tunnel current via the tunnel junction layer 44 from the embedded semiconductor layer 50. Current injection by the tunnel current through the tunnel junction layer 44 has low resistance and can perform current injection well. In addition, since the embedded semiconductor layer 50, which is an n-type semiconductor layer, diffuses current more easily than the p-type semiconductor layer, current can be diffused well from the side surface of the columnar semiconductor layer 40 to the vicinity of the bottom surface, and current injection can be performed from the entire tunnel junction layer 44.

[0048] As a result, the current injected from the anode electrode 70 is injected well into the p-type semiconductor layer 43 from the entire side surface rather than the upper surface of the columnar semiconductor layer 40, and current injection is performed well on the active layer 42 to realize a high current density, and at the same time, it is possible to improve the external quantum efficiency.

[0049] In addition, since the side surface of the n-type nanowire layer 41 is an m-plane formed by selective growth, the active layer 42 and the p-type semiconductor layer 43 formed on the outer periphery thereof are also in contact with each other on the m-plane. Since the m-plane is a non-polar plane and no polarization occurs, the light emission efficiency in the active layer 42 is also high, and moreover, since all the side surfaces of the hexagonal column are m-planes, the light emission efficiency of the semiconductor light-emitting device 100 can be improved. Furthermore, since the film thickness of the active layer 42 can be increased, the volume of the active layer 42 can be increased by about 3 to 10 times compared with the conventional semiconductor light-emitting device, and the injection carrier density can be reduced to significantly reduce the efficiency droop.

[0050] Also, in the present embodiment, in the n-type nanowire layer 41, the concentration of n-type impurities is higher on the growth substrate 10 side than on the tip side, and gradually decreases from the growth substrate 10 side toward the tip side. Thereby, an increase in the current density at the tip of the columnar semiconductor layer 40 is suppressed, and the current is diffused to below the n-type nanowire layer 41 far from the anode electrode 70 (the side close to the growth substrate 10), so that the current density injected into the active layer 42 can be made uniform.

[0051] Also, in the present embodiment, in the p-type semiconductor layer 43 and the p+ layer of the tunnel junction layer 44, the concentration of p-type impurities is higher on the tip side than on the growth substrate 10 side, and gradually decreases from the tip side toward the growth substrate side. Thereby, by combining the concentration gradient of n-type impurities in the n-type nanowire layer 41 and the concentration gradient of p-type impurities in the p-type semiconductor layer 43, the current density injected into the active layer 42 can be made uniform.

[0052] In the present embodiment, after the columnar semiconductor layer 40 including the n-type nanowire layer 41 is grown vertically on the growth substrate 10, the embedded semiconductor layer 50 is grown between the n-type nanowire layers 41. Therefore, in a normal SIMS (Secondary Ion Mass Spectrometry) analysis, n-type impurities contained in both the n-type nanowire layer 41 and the embedded semiconductor layer 50 are detected, and a depth profile of only the n-type nanowire layer 41 cannot be obtained. Therefore, in order to obtain a depth profile of only the n-type nanowire layer 41, SIMS analysis is performed using the columnar semiconductor layer 40 for measurement.

[0053] FIG. 5 is a schematic diagram for explaining a method for measuring the impurity concentration of the n-type nanowire layer 41. FIG. 5(a) shows the formation of the columnar semiconductor layer 40, FIG. 5(b) shows the formation of the p-type GaN layer 90, FIG. 5(c) is a schematic cross-sectional view of the SIMS analysis, and FIG. 5(d) is a schematic plan view of the SIMS analysis. In FIG. 5, the growth substrate 10 and the mask 30 are not shown.

[0054] First, as shown in FIG. 5(a), a columnar semiconductor layer 40 is selectively grown on the base layer 20. At this time, the growth conditions of the columnar semiconductor layer 40 are the same as those of the nanowire growth process shown in FIG. 2. The columnar semiconductor layer 40 includes an n-type nanowire layer 41, but the active layer 42 and the p-type semiconductor layer 43 may not be included in this measurement. Since the tunnel junction layer 44 includes an n+ layer, it is preferable not to include the tunnel junction layer 44 in the columnar semiconductor layer 40 for measurement so as not to detect the n-type impurities in the n+ layer.

[0055] Next, as shown in FIG. 5(b), a p-type GaN layer 90 is grown between and on top of the columnar semiconductor layers 40 to planarize the surface. The growth conditions of the p-type GaN layer 90 may be the same as or different from those of the p-type semiconductor layer 43. Here, an example is shown in which the space between the columnar semiconductor layers 40 for measurement is filled with the p-type GaN layer 90, but any semiconductor layer that does not contain n-type impurities may be non-doped or may be filled with AlGaN or the like. The p-type impurities contained in the p-type GaN layer 90 are not limited, but Mg can be used.

[0056] Next, as shown in FIGS. 5(c) and (d), SIMS analysis is performed by irradiating an ion beam B from the surface side of the p-type GaN layer 90. The simple graph shown on the right side of FIG. 5(c) schematically represents the concentration distribution of n-type impurities obtained by SIMS analysis. As shown in FIGS. 5(c) and (d), since the ion beam B used in the SIMS analysis is irradiated over a range wider than the diameter of the columnar semiconductor layer 40, the detected depth profile includes the columnar semiconductor layer 40 and the p-type GaN layer 90.

[0057] FIG. 6 is a diagram for explaining the shape and density of the n-type nanowire layer 41. FIG. 6(a) is a cross-sectional SEM image of the sample, and FIG. 6(b) is a schematic plan view showing the arrangement of the n-type nanowire layer 41 in the plane of the growth substrate 10. As shown in FIG. 6(a), the n-type nanowire layer 41 (n-GaN core shown in the figure) included in the columnar semiconductor layer 40 has a height of 1070 nm, and the p-type GaN layer 90 formed on the columnar semiconductor layer 40 is 230 nm, with a total thickness of 1300 nm. Also, as shown in FIG. 6(b), the columnar semiconductor layers 40 are arranged in a triangular lattice, and two columnar semiconductor layers 40 are included in the unit area surrounded by a rectangle in the figure. Therefore, the concentration of the depth profile obtained by SIMS analysis can be corrected from the ratio of the cross-sectional area of the columnar semiconductor layer 40 to the area of the unit area. As an example, when the width of the opposing m-plane of the columnar semiconductor layer 40 is 340 nm and the pitch of the columnar semiconductor layer 40 is 1200 nm, the ratio occupied by the columnar semiconductor layer 40 in the area is 8%.

[0058] FIG. 7 is a diagram showing the results of SIMS analysis. FIG. 7(a) is a schematic diagram showing the positions in the n-type nanowire layer 41, and FIG. 7(b) is a graph showing the SIMS depth profile of the Si concentration and the corrected value. The position a shown in FIG. 7(a) is the surface of the p-type GaN layer 90, corresponding to a depth of 0 nm in FIG. 7(b). The position b is the tip of the columnar semiconductor layer 40, corresponding to a depth of 230 nm in FIG. 7(b). The position c corresponds to the position where the concentration gradient changes in FIG. 7(b). The position d is the root of the columnar semiconductor layer 40 (the opening of the mask 30), corresponding to a depth of 1260 - 1300 nm in FIG. 7(b). The horizontal axis in FIG. 7(b) indicates the depth from the surface of the p-type GaN layer 90, and the vertical axis indicates the Si concentration in logarithm. Also, the dashed-line graph shown in FIG. 7(b) indicates the detected value of Si obtained by SIMS analysis, and the solid-line graph indicates the concentration of Si corrected by the area ratio of the columnar semiconductor layer 40.

[0059] As shown in Fig. 7, in the columnar semiconductor layer 40 for measurement formed in the same process as the semiconductor light-emitting element 100, the concentration of Si, which is an n-type impurity, gradually decreases from position d to position b. Also, the gradient of the Si concentration is large from position d to position c, while the gradient of the Si concentration becomes small from position c to position b. Here, the region where the gradient of the Si concentration is large corresponds to the first region in the present invention, and the region where the gradient is small corresponds to the second region in the present invention.

[0060] The reason why the gradient of the Si concentration is large from position d to position c, which is the first region, is unclear, but in the initial stage of the growth of the n-type nanowire layer 41, Si contained in the SiO2 constituting the mask 30 may have an influence. However, in the present embodiment, there is also a gradient in the Si concentration in the second region grown after the first region, and the Si concentration gradually decreases toward the tip.

[0061] In the example shown in Fig. 7, in the second region, the n-type impurity concentration reaches the maximum value at position c, which is the boundary between the first region and the second region, and reaches the maximum value at position b, which is the tip of the second region. Here, the n-type impurity concentration in the second region preferably has a maximum value that is 1.2 times or more, more preferably 2 times or more, the minimum value. If the maximum value is smaller than this range, the gradient of the Si concentration may be insufficient, and current diffusion in the height direction of the columnar semiconductor layer 40 may become insufficient. Also, the n-type impurity concentration in the second region preferably has a maximum value of 3×10 20 / cm 3 or less, more preferably a maximum value of 5×10 19 / cm 3 or less. If the maximum value is greater than this concentration, the crystal quality of the n-type nanowire layer 41 may deteriorate, which is not preferable.

[0062] As described above, in the semiconductor light-emitting device 100 and the method for manufacturing the same according to the present embodiment, since the n-type impurity concentration of the n-type nanowire layer 41 is higher on the growth substrate 10 side than on the tip side, the electrical conductivity of the n-type nanowire layer 41 on the growth substrate 10 side is increased, and the current density injected into the active layer 42 formed on the side surface of the n-type nanowire layer 41 can be made uniform.

[0063] (Second Embodiment) Next, a second embodiment of the present invention will be described with reference to FIGS. 8 to 10. Descriptions of the contents overlapping with those of the first embodiment will be omitted. FIG. 8 is a schematic diagram showing a semiconductor light-emitting device 100 according to the present embodiment. In the present embodiment, the columnar semiconductor layer 40 does not include a p-type semiconductor layer 43 and a tunnel junction layer 44, and is different from the first embodiment in that the columnar semiconductor layer 40 is filled with the p-type semiconductor layer 43 instead of the embedded semiconductor layer 50.

[0064] As shown in FIG. 8, the semiconductor light-emitting device 100 includes a growth substrate 10, an underlying layer 20, a mask 30, an n-type nanowire layer 41, an active layer 42, a p-type semiconductor layer 43, a protective film 60, an anode electrode 70, and a cathode electrode 80. Here, the n-type nanowire layer 41 and the active layer 42 are selectively grown in a direction perpendicular to the growth substrate 10 to form a column shape, and constitute the columnar semiconductor layer 40 in the present invention.

[0065] In the present embodiment, the p-type semiconductor layer 43 functions as an embedded layer, and the anode electrode 70 is formed on the surface of the p-type semiconductor layer 43. FIG. 8 shows an example in which the p-type semiconductor layer 43 is formed of a single layer, but it may be formed of a plurality of semiconductor layers having different materials, compositions, and impurity concentrations. As an example, a p-type contact layer may be added by increasing the p-type impurity concentration on the surface where the anode electrode 70 is formed.

[0066] FIG. 9 is a diagram schematically showing the structure and impurity concentration of the columnar semiconductor layer 40 according to the present embodiment. In the figure, the gradations applied to the n-type nanowire layer 41 and the p-type semiconductor layer 43 visually represent the gradients of the impurity concentrations in the respective layers. Also in the present embodiment, as shown in FIG. 9, in the n-type nanowire layer 41, the concentration of the n-type impurity is larger on the growth substrate 10 side than on the tip side, and gradually decreases from the growth substrate 10 side toward the tip side.

[0067] FIG. 10 is a schematic diagram showing a method for manufacturing the semiconductor light-emitting device 100 according to the present embodiment. FIG. 10(a) shows a mask formation step, FIG. 10(b) shows a nanowire growth step and an active layer growth step, FIG. 10(c) shows a p-type layer growth step, and FIG. 10(d) shows an electrode formation step.

[0068] First, in the mask formation step shown in FIG. 10(a), a buffer layer made of GaN and an underlayer 20 made of GaN and AlGaN are grown on the growth substrate 10 using the MOCVD method. Next, a mask 30 is deposited on the underlayer 20, and a plurality of openings 31 are formed using nanoimprint lithography or the like.

[0069] Next, in the nanowire growth step shown in FIG. 10(b), an n-type nanowire layer 41 made of GaN is grown on the underlayer 20 exposed from the openings 31 by selective growth using the MOCVD method. Also in the active layer growth step, an active layer 42 is grown on the side surfaces and the upper surface of the n-type nanowire layer 41 using the MOCVD method. Thereby, the columnar semiconductor layer 40 is formed by the n-type nanowire layer 41 and the active layer 42.

[0070] Next, in the p-type layer growth step shown in FIG. 10(c), the outer periphery and the upper surface of the columnar semiconductor layer 40 are filled with a p-type semiconductor layer 43. Next, in the electrode formation step shown in FIG. 10(d), the p-type semiconductor layer 43 and the columnar semiconductor layer 40 are removed up to the mask 30 to expose the upper surface of the underlayer 20. Then, annealing is performed to activate the p-type semiconductor layer 43 and the tunnel junction layer 44. Finally, an anode electrode 70 is formed on the p-type semiconductor layer 43, and a cathode electrode 80 is formed on the surface of the underlayer 20.

[0071] Even in the semiconductor light-emitting device 100 and its manufacturing method of the present embodiment, since the n-type impurity concentration of the n-type nanowire layer 41 is higher on the growth substrate 10 side than on the tip side, the electrical conductivity of the n-type nanowire layer 41 on the growth substrate 10 side can be increased, and the current density injected into the active layer 42 formed on the side surface of the n-type nanowire layer 41 can be made uniform.

[0072] The present invention is not limited to the above-described embodiments, and various modifications are possible within the scope indicated in the claims. Embodiments obtained by appropriately combining the technical means disclosed in different embodiments are also included in the technical scope of the present invention.

Explanation of Reference Numerals

[0073] 100... Semiconductor light-emitting device 10... Growth substrate 20... Underlayer 30... Mask 31... Opening 40... Columnar semiconductor layer 41... n-type nanowire layer 42... Active layer 43... p-type semiconductor layer 44... Tunnel junction layer 50... Embedded semiconductor layer 60... Protective film 70... Anode electrode 80... Cathode electrode 90... p-type GaN layer

Claims

1. A semiconductor light-emitting device comprising a growth substrate, a mask formed on the growth substrate, and a columnar semiconductor layer grown from an opening provided in the mask, wherein the columnar semiconductor layer has an n-type nanowire layer formed at the center, and an active layer formed on the outer periphery of the n-type nanowire layer, a p-type semiconductor layer is formed on the outer periphery of the active layer, and the n-type impurity concentration of the n-type nanowire layer is higher on the growth substrate side than on the tip side. A semiconductor light-emitting device characterized by this.

2. The semiconductor light-emitting device according to claim 1, wherein the n-type impurity concentration of the n-type nanowire layer gradually decreases from the growth substrate side toward the tip side. A semiconductor light-emitting device characterized by this.

3. The semiconductor light-emitting device according to claim 2, wherein the n-type nanowire layer includes a first region on the growth substrate side and a second region on the tip side, and the gradient of the n-type impurity concentration is such that the first region is larger than the second region. A semiconductor light-emitting device characterized by this.

4. The semiconductor light-emitting device according to claim 3, wherein the n-type impurity concentration in the second region has a maximum value that is 1.2 times or more the minimum value. A semiconductor light-emitting device characterized by this.

5. The semiconductor light-emitting device according to claim 3, The n-type impurity concentration in the second region has a maximum value of 3×10 ２０ / cm ３ or less, and the semiconductor light-emitting device is characterized by this.

6. The semiconductor light-emitting device according to claim 1, wherein the p-type impurity concentration of the p-type semiconductor layer is higher on the tip side periphery than on the growth substrate side periphery. A semiconductor light-emitting device characterized by this.

7. A method for manufacturing a semiconductor light-emitting device, comprising a mask step of forming a mask layer having an opening on a growth substrate, and a growth step of forming a columnar semiconductor layer in the opening using selective growth, wherein the growth step includes a nanowire growth step of forming an n-type nanowire layer, and an active layer growth step of forming an active layer outside the n-type nanowire layer, and has a p-type layer growth step of forming a p-type semiconductor layer outside the active layer, wherein the nanowire growth step increases the n-type impurity concentration on the growth substrate side than on the tip side. A method for manufacturing a semiconductor light-emitting device characterized by this.

8. The method for manufacturing a semiconductor light-emitting device according to claim 7, wherein the nanowire growth step reduces the supply amount of n-type impurities on the tip side than on the growth substrate side. A method for manufacturing a semiconductor light-emitting device characterized by this.

9. The method for manufacturing a semiconductor light-emitting device according to claim 7, The method for manufacturing a semiconductor light-emitting device is characterized in that the growth temperature is decreased on the tip side rather than on the growth substrate side in the nanowire growth step.

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