Display device

Abstract

To provide a method of fabricating a semiconductor device that reduces characteristic defects due to a crack of the semiconductor device.SOLUTION: A crack suppression layer is provided at a circumference where a semiconductor element is formed, and then cracking from a substrate outer peripheral part is suppressed to reduce damage to the semiconductor element. Further, even if physical force is applied from the outer peripheral part to the semiconductor device when the semiconductor device is peeled and displaced, the crack suppression layer can prevent cracking from extending (growing) to the semiconductor device.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor device.

[0002] In this specification, a semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. It generally refers to a substrate on which semiconductor elements such as thin film transistors (TFTs) are formed, a liquid crystal display device driven by using a TFT, an electroluminescence (EL) display device driven by using a TFT, and all semiconductor circuits and electronic devices are semiconductor devices.

Background Art

[0003] In recent years, the development of semiconductor device manufacturing technology has been remarkable. In addition to the miniaturization and weight reduction of devices, the adoption of flexible substrates has been considered because flexibility and

[0004] impact resistance can be achieved. As a method for manufacturing a flexible semiconductor device, after manufacturing semiconductor elements such as thin film transistors on a substrate such as a glass substrate or a quartz substrate, a technology for transposing the semiconductor elements from the substrate to another base material (for example, a flexible base material) has been developed. In order to transpose the semiconductor elements to another base material, a step of separating the semiconductor elements from the base material used when manufacturing the semiconductor elements is necessary.

[0005] For example, Patent Document 1 describes the following separation technique using laser ablation. On a substrate, a separation layer made of amorphous silicon or the like is provided, and a layer to be peeled off made of a thin film element is provided on the separation layer. The layer to be peeled off is adhered to a transfer body by an adhesive layer. By irradiating the separation layer with laser light to ablate the separation layer, separation is caused in the separation layer.

[0006] ​​​​​​​​In addition, Patent Document 2 describes a technique for peeling using a physical force such as a human hand. Patent Document 2 forms a metal layer between a substrate and an oxide layer, and utilizes the fact that the bond at the interface between the oxide layer and the metal layer is weak to cause peeling at the interface between the oxide layer and the metal layer, thereby separating the layer to be peeled from the substrate.

[0007] When peeling is performed by a physical force such as a human hand, it is necessary to bend the layer to be peeled in order to peel the layer to be peeled from the base material starting from the peeling layer The layer to be peeled formed in contact with the peeling layer is a thin film in which semiconductor elements including thin film transistors (TFTs), wirings, interlayer films, etc. are formed and is a very brittle one with a thickness of about 10 μm. When bending stress is applied to the semiconductor element cracks (hereinafter referred to as cracks) are likely to occur in the layer to be peeled, and this causes a problem that the semiconductor device is destroyed .

[0008] Cracks generated in the peeling process often occur from the periphery of the substrate, and when cracks occur the cracks progress ( grow) from the periphery of the substrate to the inside over time due to stress from resins, films, etc.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0010] The present invention relates to a method for manufacturing a semiconductor device with reduced characteristic defects caused by cracks in the semiconductor device. One of the objectives is to provide such a method.

[0011] The present invention aims to provide a method for manufacturing a semiconductor device with reduced characteristic defects caused by cracks generated when separating a semiconductor element from a substrate (i.e., during the peeling process) and cracks generated when transferring a semiconductor element to a flexible substrate. One of the objectives is to provide such a method. One of the objectives is to provide a method for manufacturing a semiconductor device with reduced characteristic defects caused by cracks generated when separating a semiconductor element from a substrate (i.e., during the peeling process) and cracks generated when transferring a semiconductor element to a flexible substrate.

Means for Solving the Problems

[0012] One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element.

[0013] One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element.

[0014] One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. One form of the configuration of the invention disclosed in this specification is a method for manufacturing a semiconductor device, which includes forming a release layer on a first substrate, forming a buffer layer on the release layer, forming a semiconductor element composed of transistors on the buffer layer, and forming a crack suppression layer around the formed semiconductor element. , a crack suppression layer of a metal film is formed around the semiconductor element to be formed, and the transistor includes a gate electrode layer, a source electrode layer, and a drain electrode layer. The crack suppression layer of the metal film is formed by the same process as at least one of the gate electrode layer, the source electrode layer, and the drain electrode layer, and the first substrate and the semiconductor element are peeled or separated with the peeling layer as a trigger. This is a method for manufacturing a semiconductor device.

[0015] One form of the configuration of the invention disclosed in this specification is to form a peeling layer on a first substrate, form a buffer layer on the peeling layer, and form a semiconductor element composed of transistors on the buffer layer. A crack suppression layer of a resin film is formed around the semiconductor element to be formed. The transistor includes a gate electrode layer, a source electrode layer, a drain electrode layer, an insulating layer, a protective insulating layer, a partition wall, and the crack suppression layer of the resin film is formed of the same material as at least one of the insulating layer, the protective insulating layer, and the partition wall. The first substrate and the semiconductor element are peeled or separated with the peeling layer as a trigger. This is a method for manufacturing a semiconductor device.

[0016] In the above configuration, the crack suppression layer of the metal film is a film mainly composed of an element selected from aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, or a laminated film thereof, or an alloy film thereof, or a laminated film combining a film mainly composed of these metals and the alloy film. This is a method for manufacturing a semiconductor device.

[0017] In the above configuration, the crack suppression layer of the resin film is polyimide, acrylic, polyamide, e ​​​​​​A method for manufacturing a semiconductor device formed of a material selected from an organic resin film such as epoxy, an inorganic insulating film, or a siloxane-based resin, or a laminated film thereof. A method for manufacturing a semiconductor device formed thereof.

[0018] In the above configuration, the crack suppression layer of the metal film is formed with a thickness of 300 nm or more and 5000 nm or less. A method for manufacturing a semiconductor device formed thereof.

[0019] In the above configuration, the crack suppression layer of the resin film is formed with a thickness of 700 nm or more and 20000 nm or less. A method for manufacturing a semiconductor device formed thereof.

[0020] In the above configuration, the crack suppression layer of the metal film and the crack suppression layer of the resin film are characterized by having a width of 100 μm or more and 10000 μm or less. A method for manufacturing a semiconductor device.

[0021] In the above configuration, the crack suppression layer of the metal film is electrically connected to the transistor. A method for manufacturing a semiconductor device characterized thereby.

[0022] The peripheral region where the desired semiconductor element is formed becomes a blank region when the semiconductor elements are later separated individually, and cracks generated in this region do not affect the yield. Also, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for the transistors in the pixel portion on the same substrate. The protection circuit is preferably configured using a non-linear element using an oxide semiconductor layer.

[0023] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the lamination order. Also, the names specific to the matters for specifying the invention in this specification do not indicate anything.

[0024] The ordinal numbers attached as the first and second are for convenience and do not indicate the process order or the lamination order. Also, the specific names in this specification for identifying the invention do not indicate anything. Effect of the Invention

[0025] According to the present invention, a crack prevention layer made of a metal film and a crack prevention layer made of a resin film are formed. When the semiconductor element is separated from the substrate, the semiconductor element itself is prevented from cracking. This makes it possible to improve the manufacturing yield of semiconductor devices.

[0026] According to the present invention, the metal film crack prevention layer is a gate electrode layer and a source electrode layer of a semiconductor element. Since the same material as at least one of the drain electrode layer can be used, It can be easily formed without increasing the manufacturing process.

[0027] According to the present invention, the crack prevention layer of the resin film is used for the insulating layer of the semiconductor element, the protective insulating layer, and the partition wall. The same materials can be used as at least one other, which increases the manufacturing process. It is possible to easily form the same without causing any trouble.

[0028] According to the present invention, cracks that occur during the peeling process often occur around the periphery of the substrate. In addition, this is likely to occur in resin films, which are layers with weak mechanical strength. This makes it possible to prevent cracks. Even if the film is made of resin, it can be connected on a flat surface. If the resin film is continuous, the cracks will grow. If the mechanical strength of the resin film is higher than that of the crack, it is possible to prevent the crack from occurring. .

[0029] Therefore, even in a situation where cracks occurring during the peeling process are unavoidable, the desired semiconductor element can be obtained. By forming a metal film crack prevention layer or a resin film crack prevention layer around the element, The crack suppression layer can suppress cracks that progress (grow) and improve the manufacturing yield of semiconductor devices.

Brief Description of the Drawings

[0030]

Figure 1

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Figure 16

Embodiments for Carrying Out the Invention

[0031] Embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description and can be variously modified in its form and details without departing from the spirit and scope of the present invention, which can be easily understood by those skilled in the art. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below.

[0032] (Embodiment 1) In this embodiment, the manufacturing process of the semiconductor device will be described with reference to FIGS. 1 to 9.

[0033] FIG. 1(A) is a plan view of the semiconductor device, and FIG. 1(B) is a cross-sectional view taken along the dash-dotted line A-B in FIG. 1(A). Note that FIG. 1 shows a plan view and a cross-sectional view before the semiconductor element forming process is completed and the semiconductor element is separated from the first substrate.

[0034] In the semiconductor device 200 shown in FIG. 1, a release layer 101 is formed on the first substrate 100, a first insulating layer 111 is formed on the release layer 101, a transistor 134 included in the pixel circuit portion 202 and a transistor 133 included in the drive circuit portion 201 are formed on the first insulating layer 111, and a crack suppression region 205 having a crack suppression layer 124 formed of a metal film is disposed outside the drive circuit portion 201 and the pixel circuit portion 202. Further, an insulating layer 125 is formed on the transistors 134 and 133, and a protective insulating layer 132 is formed on the insulating layer 125. Note that a semiconductor element 203 is formed by the drive circuit portion 201 and the pixel circuit portion 202.

[0035] In the pixel circuit portion 202, a color filter layer 136 is formed on the protective insulating layer 132. ​​​​​​​​​​​, the color filter layer 136 is covered with an overcoat layer 137 and a protective insulating layer 138. The first electrode layer 143 is electrically connected to the source electrode layer 120a or the drain electrode layer 120b through the contact hole 140. Also, a partition wall 145 that separates between the light-emitting elements is formed on the transistor 134. Further, a capacitor 135 composed of a capacitance wiring layer 105 and a gate insulating layer 107 is formed in the pixel circuit section 202. Also, a second terminal 123 and a terminal electrode 144 are electrically connected.

[0036] In the drive circuit section 201, a transistor 133 has a source electrode layer 119a and a drain electrode layer 119b formed thereon. Also, the drain electrode layer 119b is electrically connected to the conductive layer 104. A first terminal 102 formed in the same process as the gate electrode layer 103 is electrically connected to the terminal electrode 142 through a connection electrode 122 formed in the same process as the source electrode layer 119a and the drain electrode layer 119b.

[0037] The transistors shown in this embodiment (that is, the transistor 133 in the drive circuit section and the transistor 134 in the pixel circuit section) use an inverted staggered type of bottom gate structure. Also, the transistor 133 in the drive circuit section and the transistor 134 in the pixel circuit section are channel etch type transistors in which an oxide semiconductor layer exposed between the source electrode layer and the drain electrode layer is formed.

[0038] Note that the structure of the transistors (that is, the transistor 133 in the drive circuit section and the transistor 134 in the pixel circuit section) is not particularly limited, and for example, a top gate structure or a bottom gate ​An inverted staggered type, a planar type, etc. of the T structure can be used. Also, the transistor is a single gate structure in which one channel formation region is formed, a double gate structure in which two are formed, or a triple gate structure in which three are formed may be used. Also, a dual gate type having two gate electrode layers arranged via a gate insulating layer above and below the channel region may be used.

[0039] Also, in the present embodiment, a channel etch type transistor is described, but it is not limited to this, and a structure such as a channel protection type (also referred to as a channel stopper type) may be appropriately used.

[0040] In the crack suppression region 205 shown in FIG. 1(B), the crack suppression layer 124 is formed in the same process as the source electrode layer 119a, the drain electrode layer 119b of the transistor 133, and the source electrode layer 120a, the drain electrode layer 120b of the transistor 134. Also, in the present embodiment, the crack suppression layer 124 has a single layer structure, but when forming the gate electrode layer 103 and the gate electrode layer 106, that is, in the gate electrode process, a metal film may be provided in the crack suppression region 205 to form a laminated structure of metal films fabricated in different processes. Also, a gate insulating layer 107 or the like may be interposed between the laminated structures of the metal films.

[0041] Note that in the cross-sectional view shown in FIG. 1(B), the transistors 134 and 133 have a width of about 10 to 100 μm, while the width of the crack suppression layer is about 100 to 10000 μm, with a difference of 10 times or more, but it is shown differently from the actual scale.

[0042] ​​​​​​​​​Here, an example of a method for manufacturing the semiconductor device 200 shown in FIG. 1B will be described with reference to FIGS. The following description will be given in detail. Note that the same reference numerals are used in common between different drawings for the parts described below. Therefore, the repeated explanation will be omitted.

[0043] A release layer 101 is formed on a first substrate 100, and a first insulating layer 111 is formed on the release layer 101. Preferably, the first insulating layer 11 is formed without exposing the formed release layer 101 to the air. By forming them successively, the release layer 101 and the first insulating layer 11 This prevents the intrusion of dust and impurities between the electrodes 1 (see Figure 2(A)).

[0044] The first substrate 100 may be a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, A metal substrate or the like can be used. The substrate to be fabricated can be appropriately selected in accordance with the requirements.

[0045] In addition, for glass substrates, if the temperature of the subsequent heat treatment is high, the distortion point is 730°C or higher. For the glass substrate, for example, aluminosilicate glass, alumina Glass materials such as lumino borosilicate glass and barium borosilicate glass are used. In addition, by adding more barium oxide (BaO), a more practical heat-resistant glass can be obtained. Alternatively, crystallized glass or the like can be used.

[0046] In this process, the peeling layer 101 is provided on the entire surface of the first substrate 100. If necessary, a peeling layer 101 is provided on the entire surface of the first substrate 100, and then the peeling layer 101 is removed. The release layer may be selectively removed to provide a release layer only in desired areas.

[0047] In addition, in FIG. 2, the release layer 101 is formed in contact with the first substrate 100. When a glass substrate is used as the first substrate 100, a silicon oxide film is formed between the first substrate 100 and the peeling layer 101. By forming an insulating layer such as a silicon oxynitride film, a silicon nitride film, or a silicon nitride oxide film, This is more preferable since it can prevent contamination from the substrate.

[0048] The release layer 101 may be made of tungsten, molybdenum, titanium, tantalum, niobium, nickel, or copper. Baltic, Zirconium, Ruthenium, Rhodium, Palladium, Osmium, Iridium, An element selected from silicon, an alloy material containing the element, or a compound material containing the element The silicon-containing layer may have a crystal structure of amorphous, microcrystalline, Either the crystal or polycrystal may be used.

[0049] The peeling layer 101 can be formed by a sputtering method, a plasma CVD method, a coating method, a printing method, or the like. The coating method includes a spin coating method, a droplet discharge method, and a dispense method.

[0050] When the release layer 101 has a single-layer structure, it is preferably a tungsten layer, a molybdenum layer, or a tungsten layer. A layer containing a mixture of tungsten and molybdenum is formed. Alternatively, a layer containing tungsten oxide or a layer containing an oxynitride, a layer containing an oxide or oxynitride of molybdenum, or a layer containing tungsten A layer containing an oxide or oxynitride of a mixture of tungsten and molybdenum is formed. A mixture of tungsten and molybdenum corresponds, for example, to an alloy of tungsten and molybdenum. do.

[0051] When the release layer 101 has a laminated structure, it is preferable that the first layer from the first substrate 100 side is a tantalum. Form a layer containing a tungsten layer, a molybdenum layer, or a mixture of tungsten and molybdenum. As the second layer, form an oxide, nitride, oxynitride, or nitroxide of tungsten, molybdenum, or a mixture of tungsten and molybdenum.

[0052] When forming a laminated structure of a layer containing tungsten and a layer containing an oxide of tungsten as the release layer 101, form a layer containing tungsten, and form an insulating layer formed of an oxide on the upper layer thereof. By doing so, it may be utilized that a layer containing an oxide of tungsten is formed at the interface between the tungsten layer and the insulating layer.

[0053] Also, when forming an oxide semiconductor layer as a semiconductor element after forming the release layer, the release layer is also heated by heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer, and peeling at the release layer interface becomes easy when peeling from the production substrate in a later process.

[0054] Also, the surface of the layer containing tungsten may be treated by thermal oxidation treatment, oxygen plasma treatment, treatment with a solution having a strong oxidizing power such as ozone water, etc. to form a layer containing an oxide of tungsten. Also, plasma treatment and heat treatment may be performed in an atmosphere of oxygen, nitrogen, nitrous oxide alone, or a mixed gas atmosphere of the gas and other gases. This is the same when forming a layer containing a nitride, oxynitride, and nitroxide of tungsten. After forming a layer containing tungsten, it is preferable to form a silicon nitride layer, a silicon oxynitride layer, or a silicon nitroxide layer on the upper layer thereof. Next, form a first insulating layer 111 on the release layer 101. The first insulating layer 111 is formed of a single layer or multiple layers of an insulating film containing nitrogen and silicon, such as silicon nitride, silicon oxynitride, or silicon nitroxide.

[0055] ​​​​​​​is preferably formed.

[0056] The first insulating layer 111 can be formed by using a sputtering method, a plasma CVD method, a coating method, a printing method, etc. For example, by forming the film at a film formation temperature of 250°C or higher and 400°C or lower by the plasma CVD method, a dense and very low water permeability film can be obtained. The thickness of the first insulating layer 111 is preferably 10 nm or more and 3000 nm or less, and more preferably 200 nm or more and 1500 nm or less. By providing the first insulating layer 111, peeling at the interface with the peeling layer 101 in the subsequent peeling process becomes easy. Further, the first insulating layer 111 functions as a protective layer for the layer to be peeled 300 after separating the layer to be peeled 300 from the first substrate 100.

[0057]

[0058] Next, the gate electrode layer 103, the conductive layer 104, the capacitor wiring layer 105, the gate electrode layer 106, and the first terminal 102 are formed. The materials of the gate electrode layer 103, the conductive layer 104, the capacitor wiring layer 105, the gate electrode layer 106, and the first terminal 102 can be formed as a single layer or laminated using a metal material such as aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, etc. or an alloy material mainly composed of these.

[0059] For example, as the laminated structure of the gate electrode layer 103, the conductive layer 104, the capacitor wiring layer 105, the gate electrode layer 106, and the first terminal 102, a two-layer laminated structure in which a molybdenum layer is laminated on an aluminum layer, or a two-layer structure in which a molybdenum layer is laminated on a copper layer, or a two-layer structure in which a titanium nitride layer or a tantalum nitride layer is laminated on a copper layer, a titanium nitride layer and a molybdenum layer It is preferable to form a laminated two-layer structure. As for the three-layer laminated structure, it is preferable to form a laminate in which a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated. That is, a tungsten layer or a tungsten nitride layer, an alloy of aluminum and silicon or an alloy of aluminum and titanium, and a titanium nitride layer or a titanium layer are laminated.

[0060] Next, a gate insulating layer 107 is formed on the gate electrode layer 103, the conductive layer 104, the capacitive wiring layer 105, the gate electrode layer 106, and the first terminal 102 (see Fig. 2(A)).

[0061] The gate insulating layer 107 can be formed as a single layer or laminated with a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer by using a plasma CVD method, a sputtering method, or the like. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. That is, a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer can be formed as a single layer or laminated. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. For example, a silicon oxynitride layer can be formed by the plasma CVD method using SiH4, oxygen, and nitrogen as the film-forming gas. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer. The film thickness of the gate insulating layer 107 is 100 nm or more and 500 nm or less. In the case of lamination, for example, a first gate insulating layer with a film thickness of 50 nm or more and 200 nm or less and a second gate insulating layer with a film thickness of 5 nm or more and 300 nm or less are laminated on the first gate insulating layer.

[0062] In this embodiment, a silicon oxide layer with a film thickness of 100 nm is formed as the gate insulating layer 107 by the plasma CVD method. That is, a silicon oxide layer with a film thickness of 100 nm is formed as the gate insulating layer 107 by the plasma CVD method.

[0063] Next, an oxide semiconductor layer 108 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 107 (see Fig. 2(B)). That is, an oxide semiconductor layer 108 with a film thickness of 2 nm or more and 200 nm or less is formed on the gate insulating layer 107 (see Fig. 2(B)).

[0064] Before forming the oxide semiconductor layer 108 by the sputtering method, reverse sputtering is performed by introducing argon gas to generate plasma, and the surface of the gate insulating layer 107 is adhered to. Before forming the oxide semiconductor layer 108 by the sputtering method, reverse sputtering is performed by introducing argon gas to generate plasma, and the surface of the gate insulating layer 107 is adhered to. It is preferable to remove dust and the like. Reverse sputtering is a method in which a voltage is applied using an RF power supply to the substrate side in an argon atmosphere, and the substrate is exposed to plasma to modify the surface. There is. Note that nitrogen, helium, etc. may be used instead of the argon atmosphere. Also, it may be performed in an atmosphere in which oxygen, N2O, etc. are added to the argon atmosphere. Also, it may be performed in an atmosphere in which Cl2, CF4, etc. are added to the argon atmosphere.

[0065] The oxide semiconductor layer 108 is an In-Ga-Zn-O-based non-single crystal film, an In-Sn-Zn-O-based , In-Al-Zn-O-based, Sn-Ga-Zn-O-based, Al-Ga-Zn-O-based, Sn- Al-Zn-O-based, In-Ga-O-based, In-Zn-O-based, Sn-Zn-O-based, Al-Z n-O-based, In-O-based, Sn-O-based, Zn-O-based oxide semiconductor film is used. Also, the oxide The semiconductor layer 108 is formed by sputtering in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. When using the sputtering method, a target containing 2 wt% or more and 10 wt% or less of SiO2 is used for film formation, and SiOx (x>0) that inhibits crystallization is included in the oxide semiconductor layer 108, and during the heat treatment for dehydration or dehydrogenation performed in a later step It is preferable to suppress crystallization.

[0066] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO = 1:1:1 [mol%], In:Ga:Zn = 1:1:0.5 [atom% ) is used, the distance between the substrate and the target is 90 mm, the substrate temperature is 200 °C, and the pressure is 0. ​​​​​​6 Pa, DC power supply of 5 kW, argon and oxygen (argon: oxygen = 30 sccm: 20 sccm, oxygen flow rate ratio 40%) in an atmosphere. Note that when using a pulsed DC power supply, dust can be reduced and the film thickness distribution becomes uniform, which is preferred. The film thickness of the In-Ga-Zn-O-based non-single crystal film is set to be 5 nm or more and 200 nm or less. In this embodiment, as the oxide semiconductor film, an In-Ga-Zn-O-based metal oxide target is used to form an In-Ga-Zn-O-based non-single crystal film with a film thickness of 30 nm by sputtering. Also, as the metal oxide target containing In, Ga, and Zn, a target having a composition ratio of In:Ga:Zn = 1:1:1 [atom%] or In:Ga:Zn = 1:1:2 [atom%] can be used.

[0067] In the sputtering method, there are an RF sputtering method using a high-frequency power supply for the sputtering power supply and a DC sputtering method, and there is also a pulsed DC sputtering method that applies a bias pulse. The RF sputtering method is mainly used when forming an insulating film, and the DC sputtering method is mainly used when forming a metal film.

[0068] There is also a multi-source sputtering apparatus that can install a plurality of targets made of different materials. The multi-source sputtering apparatus can stack and form different material films in the same chamber, or can simultaneously form a plurality of types of materials in the same chamber.

[0069] Also, there are sputtering apparatuses using the magnetron sputtering method equipped with a magnet mechanism inside the chamber, and ECR sputtering apparatuses using plasma generated by using ​There is a sputtering apparatus using the CR sputtering method.

[0070] Also, as a film formation method using the sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation. Also, as a film formation method using the sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation. Also, as a film formation method using the sputtering method, there are a reactive sputtering method in which a target substance and a sputtering gas component are chemically reacted during film formation to form a compound thin film thereof, and a bias sputtering method in which a voltage is also applied to a substrate during film formation.

[0071] Next, a photolithography process is performed on the oxide semiconductor layer 108 to form resist masks 110a, 110b, and 110c, and unnecessary portions of the oxide semiconductor layer 108 and the gate insulating layer 107 are removed by etching to form a contact hole 109a reaching the first terminal 102 and a contact hole 109b reaching the conductive layer 104 (see FIG. 2(C)). Next, a photolithography process is performed on the oxide semiconductor layer 108 to form resist masks 110a, 110b, and 110c, and unnecessary portions of the oxide semiconductor layer 108 and the gate insulating layer 107 are removed by etching to form a contact hole 109a reaching the first terminal 102 and a contact hole 109b reaching the conductive layer 104 (see FIG. 2(C)). Next, a photolithography process is performed on the oxide semiconductor layer 108 to form resist masks 110a, 110b, and 110c, and unnecessary portions of the oxide semiconductor layer 108 and the gate insulating layer 107 are removed by etching to form a contact hole 109a reaching the first terminal 102 and a contact hole 109b reaching the conductive layer 104 (see FIG. 2(C)). Next, a photolithography process is performed on the oxide semiconductor layer 108 to form resist masks 110a, 110b, and 110c, and unnecessary portions of the oxide semiconductor layer 108 and the gate insulating layer 107 are removed by etching to form a contact hole 109a reaching the first terminal 102 and a contact hole 109b reaching the conductive layer 104 (see FIG. 2(C)).

[0072] In this way, when the step of forming a contact hole in the gate insulating layer 107 is performed in a state where the oxide semiconductor layer 108 is laminated on the entire surface of the gate insulating layer 107, since the resist mask does not directly contact the surface of the gate insulating layer 107, contamination (such as adhesion of impurities, etc.) of the surface of the gate insulating layer 107 can be prevented. Therefore, the interface state between the gate insulating layer 107 and the oxide semiconductor layer 108 can be made good, leading to an improvement in reliability. In this way, when the step of forming a contact hole in the gate insulating layer 107 is performed in a state where the oxide semiconductor layer 108 is laminated on the entire surface of the gate insulating layer 107, since the resist mask does not directly contact the surface of the gate insulating layer 107, contamination (such as adhesion of impurities, etc.) of the surface of the gate insulating layer 107 can be prevented. Therefore, the interface state between the gate insulating layer 107 and the oxide semiconductor layer 108 can be made good, leading to an improvement in reliability. In this way, when the step of forming a contact hole in the gate insulating layer 107 is performed in a state where the oxide semiconductor layer 108 is laminated on the entire surface of the gate insulating layer 107, since the resist mask does not directly contact the surface of the gate insulating layer 107, contamination (such as adhesion of impurities, etc.) of the surface of the gate insulating layer 107 can be prevented. Therefore, the interface state between the gate insulating layer 107 and the oxide semiconductor layer 108 can be made good, leading to an improvement in reliability. In this way, when the step of forming a contact hole in the gate insulating layer 107 is performed in a state where the oxide semiconductor layer 108 is laminated on the entire surface of the gate insulating layer 107, since the resist mask does not directly contact the surface of the gate insulating layer 107, contamination (such as adhesion of impurities, etc.) of the surface of the gate insulating layer 107 can be prevented. Therefore, the interface state between the gate insulating layer 107 and the oxide semiconductor layer 108 can be made good, leading to an improvement in reliability. In this way, when the step of forming a contact hole in the gate insulating layer 107 is performed in a state where the oxide semiconductor layer 108 is laminated on the entire surface of the gate insulating layer 107, since the resist mask does not directly contact the surface of the gate insulating layer 107, contamination (such as adhesion of impurities, etc.) of the surface of the gate insulating layer 107 can be prevented. Therefore, the interface state between the gate insulating layer 107 and the oxide semiconductor layer 108 can be made good, leading to an improvement in reliability.

[0073] It is also possible to directly form a resist pattern on the gate insulating layer 107 to open the contact hole. In that case, after peeling off the resist, it is preferable to perform a heat treatment to perform a dehydration and dehydrogenation treatment on the surface of the gate insulating layer. For example, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), a heat treatment (400°C or higher and 75 It is also possible to directly form a resist pattern on the gate insulating layer 107 to open the contact hole. In that case, after peeling off the resist, it is preferable to perform a heat treatment to perform a dehydration and dehydrogenation treatment on the surface of the gate insulating layer. For example, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), a heat treatment (400°C or higher and 75 It is also possible to directly form a resist pattern on the gate insulating layer 107 to open the contact hole. In that case, after peeling off the resist, it is preferable to perform a heat treatment to perform a dehydration and dehydrogenation treatment on the surface of the gate insulating layer. For example, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), a heat treatment (400°C or higher and 75 It is also possible to directly form a resist pattern on the gate insulating layer 107 to open the contact hole. In that case, after peeling off the resist, it is preferable to perform a heat treatment to perform a dehydration and dehydrogenation treatment on the surface of the gate insulating layer. For example, under an inert gas atmosphere (nitrogen, or helium, neon, argon, etc.), a heat treatment (400°C or higher and 75 Perform at a temperature below 0°C to remove impurities such as hydrogen and water contained in the gate insulating layer 107. That's all right.

[0074] Next, remove the resist masks 110a, 110b, and 110c, and perform etching using the resist masks 112 and 113 formed by the photolithography process to form the island-shaped oxide semiconductor layers 114 and 115 (see Fig. 3(A)). Also, the resist masks 112 and 113 for forming the island-shaped oxide semiconductor layer may be formed by the inkjet method. Since no photomask is used when forming the resist mask by the inkjet method, the manufacturing cost can be reduced.

[0075] Next, perform dehydration or dehydrogenation of the oxide semiconductor layer 114 and the oxide semiconductor layer 115 to form the dehydrated or dehydrogenated oxide semiconductor layers 116 and 117 (see Fig. 3(B)). The temperature of the first heat treatment for dehydration or dehydrogenation is 400°C or higher and 750°C or lower, preferably 425°C or higher and 750°C or lower. Note that if it is 425°C or higher, the heat treatment time may be 1 hour or less, but if it is less than 425°C, the heat treatment time will be longer than 1 hour. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment apparatuses, and heat treatment is performed on the oxide semiconductor layer 114 and the oxide semiconductor layer 115 in a nitrogen atmosphere, and then, without being exposed to the atmosphere, re-mixing of water and hydrogen into the oxide semiconductor layer is prevented to obtain the oxide semiconductor layers 116 and 117. In this embodiment, from the heating temperature T for dehydration or dehydrogenation of the oxide semiconductor layer, water is not allowed to enter again. Using the same furnace until the temperature drops to a sufficient level, specifically, until it drops by 100 °C or more from the heating temperature T slowly cool in a nitrogen atmosphere. Also, it is not limited to a nitrogen atmosphere, and dehydrogenation or dehydration is carried out in an inert gas atmosphere such as helium, neon, or argon.

[0076] By heating the oxide semiconductor layer 114 and the oxide semiconductor layer 115 at a temperature of 400 °C to 700 °C dehydration and dehydrogenation of the oxide semiconductor layer 114 and the oxide semiconductor layer 115 are achieved, and subsequent re-entry of water (H2O) can be prevented.

[0077] Note that the heat treatment apparatus is not limited to an electric furnace. For example, RTA (Rapid Thermal Anneal) apparatuses such as GRTA (Gas Rapid Thermal Anneal) apparatuses and LRTA (Lamp Rapid Thermal Anneal) apparatuses can be used. An LRTA apparatus is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. Also, an LRTA apparatus may be equipped with a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element in addition to the lamp. GRTA is a method of performing a heat treatment using a high-temperature gas. As the gas, an inert gas such as argon or a gas that does not react with the object to be processed by heat treatment, such as nitrogen, is used. Using the RTA method, a heat treatment may be performed at 600 °C to 750 °C for several minutes.

[0078] Note that in the first heat treatment, nitrogen or an inert gas such as helium, neon, or argon is used. ​​​​​​​​​​​It is preferably free of water, hydrogen, etc. In particular, for the oxide semiconductor layer 114 and the oxide heat treatment for dehydration and dehydrogenation performed at 400°C to 750°C on the semiconductor layer 115 is preferably carried out in a nitrogen atmosphere with H2O of 20 ppm or less. Alternatively, the purity of the nitrogen introduced into the heat treatment apparatus, or rare gases such as helium, neon, and argon, is 6N (99.9 999%) or more, preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1p pm or less, preferably 0.1 ppm or less).

[0079] Also, depending on the conditions of the first heat treatment or the materials of the oxide semiconductor layer 114 and the oxide semiconductor layer 115, crystallization may occur, resulting in a microcrystalline film or a polycrystalline film. For example, the oxide semiconductor layer 116 and the oxide semiconductor layer 11 may become a microcrystalline with a crystallization rate of 90% or more, or 80% or more. Also, depending on the conditions of the first heat treatment or the materials of the oxide semiconductor layer 114 and the oxide semiconductor layer 115, an amorphous oxide semiconductor layer 116 that does not contain a crystalline component, an oxide semiconductor layer 117 may result. Also, in the amorphous oxide semiconductor, a microcrystalline part (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) may be mixed to form the oxide semiconductor layer 116 and the oxide semiconductor layer 11 7. Also, when performing high-temperature heat treatment using RTA (GRTA, L RTA), needle-like crystals in the longitudinal direction (film thickness direction) may occur on the surface side of the oxide semiconductor layer 116 and the oxide semiconductor layer 11 (particle size of 1 nm or more and 20 nm or less (typically 2 nm or more and 4 nm or less)) may be mixed to form the oxide semiconductor layer 116 and the oxide semiconductor layer 11 7. Also, when performing high-temperature heat treatment using RTA (GRTA, L RTA), needle-like crystals in the longitudinal direction (film thickness direction) may occur on the surface side of the oxide semiconductor layer 116 and the oxide semiconductor layer 11 7.

[0080] Also, the first heat treatment performed on the oxide semiconductor layer 114 and the oxide semiconductor layer 115 is for the island-shaped oxide semiconductor layer 114 and the oxide semiconductor layer 108 before processing the oxide semiconductor layer 115 This can also be done. In that case, after the first heat treatment, the substrate is taken out of the heating device, a photolithography process is performed.

[0081] The heat treatment for dehydration and dehydrogenation of the oxide semiconductor layer 114 and the oxide semiconductor layer 115 can be performed either after forming the oxide semiconductor layer and laminating the source electrode and the drain electrode on the oxide semiconductor layer or after forming a passivation film on the source electrode and the drain electrode. Either way is acceptable.

[0082] Note that the etching of the oxide semiconductor layer 114 and the oxide semiconductor layer 115 here is not limited to wet etching, and dry etching may also be used. As the etching gas used for dry etching, a gas containing chlorine (chlorine-based gas, for example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride

[0083] CCl4), etc.) is preferable. For example, chlorine (Cl2), boron trichloride (BCl3), silicon tetrachloride (SiCl4), carbon tetrachloride CCl4), etc.) is preferable.

[0084] In addition, as other etching gases used for dry etching, a gas containing fluorine (fluorine-based gas, for example, carbon tetrafluoride (CF4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3 ), trifluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used. )、trifluoromethane (CHF3), etc.), hydrogen bromide (HBr), oxygen (O2), a gas obtained by adding a noble gas such as helium (He) or argon (Ar) to these gases, etc. can be used. As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching can be performed into a desired processed shape. As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma) etching method can be used. Etching can be performed into a desired processed shape.

[0085] As the dry etching method, a parallel plate type RIE (Reactive Ion Etching) method or an ICP (Inductively Coupled Plasma: inductively coupled plasma) etching method can be used. Etching can be performed into a desired processed shape. coupled plasma) etching method can be used. Etching can be performed into a desired processed shape. As such, appropriately adjust the etching conditions (the amount of electric power applied to the coil-shaped electrode, the amount of electric power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.).

[0086] As the etching solution used for wet etching, a solution obtained by mixing phosphoric acid, acetic acid, and nitric acid, etc. can be used. Also, ITO07N (manufactured by Kanto Chemical Co., Inc.) may be used. In the present embodiment, ITO07N (manufactured by Kanto Chemical Co., Inc.) is used as the etching solution.

[0087] Also, the etching solution after wet etching is removed together with the etched material by washing. The waste liquid of the etching solution containing the removed material may be purified and the contained material may be reused. By recovering and reusing the materials such as indium contained in the oxide semiconductor layer from the waste liquid after the etching, resources can be effectively utilized and the cost can be reduced.

[0088] Also, appropriately adjust the etching conditions (etching solution, etching time, temperature, etc.) according to the material so that etching can be performed into a desired processed shape.

[0089] Next, a metal conductive film made of a metal material is formed on the oxide semiconductor layers 116 and 117 by sputtering or vacuum deposition.

[0090] As the material of the metal conductive film, elements selected from aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, or alloys containing the above-described elements as components, or alloy films formed by combining the above-described elements, etc. can be mentioned. Also, the metal conductive film may have a single-layer structure or a laminated structure of two or more layers. For example, containing silicon ​​​​​​​​​​​​A single-layer structure of an aluminum film, a two-layer structure in which a titanium film is laminated on the aluminum film, titanium film, an aluminum film is laminated on the titanium film, and a titanium film is further formed thereon A three-layer structure and the like can be mentioned.

[0091] When performing heat treatment after forming the metal conductive film, it is preferable to endow the metal conductive film with heat resistance to withstand this heat treatment. It is preferable to have it.

[0092] Next, a photolithography process is performed to form resist masks 118a, 118 b, resist mask 118c, resist mask 118d, resist mask 118e, resist mask 118f, resist mask 118g, resist mask 118h, resist mask 118i, and unnecessary portions of the metal conductive film are removed by etching to form a source electrode layer 119a, drain electrode layer 119b, source electrode layer 120a, drain electrode layer 120b, capacitor electrode layer 121, connection electrode 122, second terminal 123, and crack suppression layer 1 of the metal film 24 is formed (see Fig. 3(C)).

[0093] In this embodiment, 300 nm of aluminum is formed as the metal conductive film, and 100 nm of titanium is provided on both the top and bottom of the aluminum. Note that as the thickness of the metal conductive film, Since it also serves as the crack suppression layer of the metal film for the source electrode layer, drain electrode layer, capacitor electrode layer, and connection electrode of the transistor, a film thickness that can maintain low resistance and mechanical strength is selected It is necessary to do so. Specifically, as the metal conductive film, it is formed with a thickness of 300 nm or more and 5000 nm or less and more preferably formed with a thickness of 500 nm or more and 1500 nm or less.

[0094] ​In addition, as the crack suppression layer 124 of the metal film, a width capable of suppressing the progress (growth) of cracks is required. However, increasing the width of the crack suppression layer may reduce the number of desired semiconductor devices that can be obtained from a single substrate (also referred to as the take-up number). Therefore, the crack suppression layer of the metal film is formed with a width of 100 μm or more and 10,000 μm or less, and more preferably with a width of 1,000 μm or more and 5,000 μm or less.

[0095] In this photolithography process, the connection electrode 122 and the second terminal 123 are formed at the end portions, respectively. Note that the second terminal 123 is electrically connected to the source electrode layer (that is, the source electrode layer including the source electrode layer 119a and the source electrode layer 120a).

[0096] In addition, the crack suppression layer 124 of the metal film may be formed in a separate process from the source electrode layer (that is, the source electrode layer including the source electrode layer 119a and the source electrode layer 120a). For example, it may be formed in the same process as the gate electrode layer (that is, the gate electrode layer including the gate electrode layer 103 and the gate electrode layer 106). Forming it in the same process as the gate electrode layer or the source electrode layer is preferable because the crack suppression layer of the metal film can be formed without increasing the manufacturing process.

[0097] Note that the shape of the crack suppression layer 124 of the metal film on the plane may be any shape such as a square, a rectangle, a circle, or an ellipse, and it is formed around the semiconductor element. In addition, the crack suppression layer forms the periphery of the semiconductor element continuously, in an island shape (island-like), or by combining a continuously formed crack suppression layer and an island-shaped crack suppression layer, or continuously forms A plurality of formed crack suppression layers may be formed. Note that it is preferable to form them continuously because the probability of suppressing cracks advancing to the semiconductor element increases.

[0098] In the present embodiment, as shown in FIG. 1(A), the crack suppression layer 124 is continuously formed in a rectangular shape with a width of 1200 μm around the semiconductor element 203.

[0099] Further, the source electrode layer 119a, the source electrode layer 120a, the drain electrode layer 119b, the drain electrode layer 120b, the connection electrode 122, the second terminal 123, and the crack suppression layer 124 are formed by the resist masks 118a, 118b, 118 c, the resist mask 118d, the resist mask 118e, the resist mask 118f, the resist mask 118g, the resist mask 118h, and the resist mask 118i by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0100] Next, the resist masks 118a, 118b, 118c, the resist masks 118d, 118e, 118f, the resist masks 118g, 118h, and 118i are removed, and an insulating layer 125 serving as a protective insulating film in contact with the oxide semiconductor layer 116 and the oxide semiconductor layer 117 is formed ( see FIG. 4(A)).

[0101] At this stage, regions where the oxide semiconductor layer 116 and the oxide semiconductor layer 117 are in contact with the insulating layer 125 are formed, and among these regions, the region overlapping the gate electrode layer and the gate insulating layer is the channel shape. It becomes the formation region 126 and the channel formation region 128.

[0102] The insulating layer 125 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method that does not mix impurities such as water and hydrogen into the insulating layer 12 5. In this embodiment In this form, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 125 using a sputtering method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and is set to room temperature in this embodiment. The film formation of the silicon oxide film by the sputtering method can be carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and oxygen atmosphere. In addition, a silicon oxide target or a silicon target can be used as the target. For example, a silicon oxide film can be formed by the sputtering method in an oxygen atmosphere using a silicon target. The insulating layer 125 formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH and uses an inorganic insulating film that blocks these from entering from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. Next, a second heat treatment (preferably 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or a nitrogen gas atmosphere. - For example, a second heat treatment of 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer 116 and the oxide semiconductor layer 117 that overlap with the insulating layer 12 5 is heated in a state of being in contact with the insulating layer 125.

[0103]

[0104] By the second heat treatment, oxygen is introduced and diffused into the oxide semiconductor layer from the exposed portions of the oxide semiconductor layer (the channel formation regions 126 and 128) between the source region and the drain region. By forming a silicon oxide film by sputtering, excess oxygen can be contained in the silicon oxide film, and the oxygen can be further introduced and diffused into the oxide semiconductor layer by the second heat treatment. By introducing and diffusing oxygen into the oxide semiconductor layer, the channel region can be made highly resistive (type I). Thereby, a normally-off transistor can be obtained. Therefore, the reliability of the semiconductor device can be improved. Specifically, the channel formation region 126 overlapping the gate electrode layer 103 of the oxide semiconductor layer 116 becomes type I, and a high-resistance source region 127a overlapping the source electrode layer 119a and a high-resistance drain region 127b overlapping the drain electrode layer 119b are self-alignedly formed. Similarly, in the oxide semiconductor layer 117, the channel formation region 128 overlapping the gate electrode layer 106 becomes type I, and a high-resistance source region 129a overlapping the source electrode layer 120a and a high-resistance drain region 129b overlapping the drain electrode layer 120b are self-alignedly formed (see Fig. 4(A)). In the oxide semiconductor layers 116 and 117 overlapping the drain electrode layer 119b and the drain electrode layer 120b (and the source electrode layer 119a and the source electrode layer 120a), by forming the high-resistance drain regions 127b and 129b (or the high-resistance source regions 127a and 129a), the reliability when forming a circuit can be improved.

[0105]

[0106] ​​​​​​​​​​​​​​can be improved. Specifically, by forming the high-resistance drain regions 127b and the high-resistance drain regions 129b, a structure can be achieved in which the conductivity changes stepwise from the drain electrode layers 119b and 120b to the high-resistance drain regions 127b, the high-resistance drain regions 129b, the channel formation regions 126, and the channel formation regions 128. Therefore, when operating by connecting to a wiring that supplies a high power supply potential V DD to the drain electrode layers 119b and 120b, even if a high electric field is applied between the gate electrode layers 103 and 10 6 and the drain electrode layers 119b and 120b, the high-resistance drain region serves as a buffer and no local high electric field is applied, and a configuration can be achieved in which the breakdown voltage of the transistor is improved.

[0107] Also, in the oxide semiconductor layer overlapping with the drain electrode layers 119b and 120b (and the source electrode layers 119a and 120a), by forming the high-resistance drain regions 127b and the high-resistance drain regions 129b (or the high-resistance source regions 127a and 12 9a), it is possible to reduce the leakage current in the channel formation regions 126 and 128 when forming a circuit.

[0108] Also, the high-resistance source region or high-resistance drain region in the oxide semiconductor layer is formed over the entire film thickness direction when the film thickness of the oxide semiconductor layer is as thin as 15 nm or less. However, when the film thickness of the oxide semiconductor layer is thicker, at 30 nm or more and 50 nm or less, a part of the oxide semiconductor layer, the region in contact with the source electrode layer or the drain electrode layer, and its vicinity have reduced resistance, and the high-resistance source region ​​​​​​​Alternatively, a high-resistance drain region is formed, and the region in the oxide semiconductor layer close to the gate insulating layer can be type I.

[0109] A protective insulating layer 132 may be further formed on the insulating layer 125. For example, a silicon nitride film is formed using the RF sputtering method. Since the RF sputtering method has good mass productivity, it is preferable as a film-forming method for the protective insulating layer. The protective insulating layer uses an inorganic insulating film that does not contain moisture, hydrogen ions, OH - and the like and blocks these from entering from the outside, and uses a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, or the like. In this embodiment, it is formed using a silicon nitride film as the protective insulating layer 132 (see Fig. 4(A)). In this embodiment, it is formed using a silicon nitride film as the protective insulating layer 132 (see Fig. 4(A)). reference).

[0110] Through the above steps, on the same substrate, the transistor 133 in the drive circuit section, the pixel circuit section the transistor 134, and the capacitor 135 can be fabricated. The transistors 133 The transistor 134 is a bottom gate type transistor including an oxide semiconductor layer including a high-resistance source region, a high-resistance drain region, and a channel formation region. Therefore, the transistors 133 The transistor 134 has a configuration in which the high-resistance drain region or the high-resistance source region serves as a buffer even when a high electric field is applied, so that a local high electric field is not applied, and the breakdown voltage of the transistor is improved. In addition, by forming the drive circuit section and the pixel circuit section on the same substrate, the connection wiring can be shortened, and the semiconductor device (light-emitting device) can be miniaturized and cost-reduced. Yes.

[0111] In addition, the capacitor 135 uses the gate insulating layer 107 in the capacitor section as a dielectric, and the capacitor wiring layer 1 It is formed by 05 and the capacitive electrode layer 121.

[0112] Next, a color filter layer 136 is formed on the protective insulating layer 132. The color filter layer 13 6 can be a green color filter layer, a blue color filter layer, a red color filter layer and the like can be used, and a green color filter layer, a blue color filter layer, and a red color filter layer are sequentially formed. Each color filter layer is formed by a printing method, an inkjet method, an etching method using a photolithography technique, etc. respectively. By providing the color filter layer 136, the alignment between the color filter layer 136 and the light-emitting region of the light-emitting element can be performed without depending on the bonding accuracy of the sealing substrate. In this embodiment a green color filter layer, a blue color filter layer, and a red color filter layer are formed in the photolithography process (see FIG. 4(B)).

[0113] Next, an overcoat layer 137 that covers the color filter layer (green color filter layer, blue color filter layer, and red color filter layer) is formed. The overcoat layer 13 7 uses a resin having translucency.

[0114] Here, an example of full-color display using three colors of RGB is shown, but it is not particularly limited and full-color display may be performed using four colors of RGBW.

[0115] Next, a protective insulating layer 138 that covers the overcoat layer 137 and the protective insulating layer 132 is formed (see FIG. 4(B)). The protective insulating layer 138 uses an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, an aluminum oxynitride film, etc. The protective insulating layer 138 and If an insulating film having the same composition as the protective insulating layer 132 is used, etching can be performed in a single step when forming the contact hole later, which is preferable. This is preferable because etching can be performed in one step.

[0116] Next, a resist mask is formed by a photolithography process, and the protective insulating layer 138, the protective insulating layer 132, and the insulating layer 125 are etched to form a contact hole 140 reaching the drain electrode layer 120b, and the resist mask is removed (see Fig. 5(A)). Also, at this time, a contact hole 141 reaching the second terminal 123 and a contact hole 139 reaching the connection electrode 122 are also formed by this etching. Further, a resist mask for forming the contact hole may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photomask is not used, the manufacturing cost can be reduced.

[0117] Next, a conductive film having translucency is formed. As materials for the conductive film having translucency, indium oxide (In2O3), indium oxide - tin oxide alloy (In2O3 - SnO2, abbreviated as ITO), etc. are formed using a sputtering method, a vacuum evaporation method, or the like. As other materials for the conductive film having translucency, an Al - Zn - O - based non - single - crystal film containing nitrogen, a Zn - O - based non - single - crystal film containing nitrogen, or a Sn - Zn - O - based non - single - crystal film containing nitrogen may be used. Note that the composition ratio (atomic %) of zinc in the Al - Zn - O - based non - single - crystal film containing nitrogen is 47 atomic % or less, greater than the composition ratio (atomic %) of aluminum in the non - single - crystal film, and the composition ratio (atomic %) of aluminum in the non - single - crystal film is greater than the composition ratio (atomic %) of nitrogen in the non - single - crystal film. The etching treatment of such materials is performed using a hydrochloric acid - based solution. However, especially for IT Etching of O tends to generate residues. Therefore, indium zinc oxide alloy (In2O3―ZnO) may be used to improve the etching processability.

[0118] Note that the unit of the composition ratio of the conductive film having translucency is atomic %, and it shall be evaluated by analysis using an electron probe X-ray microanalyzer (EPMA:Electron Probe X-ray MicroAnalyzer ).

[0119] Next, a resist mask is formed in the photolithography process, and unnecessary portions of the conductive film having translucency are removed by etching to form the first electrode layer 143, the terminal electrodes 142, 144, and the resist mask is removed (see Fig. 5(B)).

[0120] Note that a capacitor 135 formed by the capacitor wiring layer 105 and the capacitor electrode layer 121 with the gate insulating layer 107 as a dielectric can also be formed on the same substrate. Also, in the semiconductor device 200, the capacitor electrode layer 121 is part of the power supply line, and the capacitor wiring layer 105 also functions as part of the gate electrode layer of the driving TFT.

[0121] Also, the terminal electrodes 142 and 144 formed at the terminal portion serve as electrodes or wirings for connection to the FPC. The terminal electrode 142 formed on the first terminal 102 via the connection electrode 122 serves as a terminal electrode for connection that functions as an input terminal of the gate wiring. The terminal electrode 144 formed on the second terminal 123 is a terminal electrode for connection that functions as an input terminal of the source wiring.

[0122] Next, a partition wall 145 is formed so as to cover the peripheral portion of the first electrode layer 143. The partition wall 145 ​​​​​​​Organic resin films such as polyimide, acrylic, polyamide, and epoxy, inorganic insulating films, or siloxane are formed using a siloxane-based resin.

[0123] Note that the siloxane-based resin corresponds to a resin containing Si-O-Si bonds formed using a siloxane-based material as a starting material. The siloxane-based resin may use an organic group (e.g., an alkyl group, an aryl group, and a fluoro group) as a substituent.

[0124] As the partition wall 145, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the partition wall 145 may be formed by laminating a plurality of insulating films formed of these materials.

[0125] The method for forming the partition wall 145 is not particularly limited, and depending on the material, a sputtering method, a SOG method, spin coating, dipping, spray coating, a droplet discharge method (inkjet method, screen printing, offset printing, etc.), a doctor knife, a roll coater, a curtain coater, a knife coater, etc. can be used. Also, the above materials and methods shown as examples of the partition wall 145 can be used as other insulating layers used in a semiconductor device (light-emitting device).

[0126] The partition wall 145 is preferably formed using a photosensitive resin material, forming an opening on the first electrode layer 143, and forming an inclined surface such that the side wall of the opening has a continuous curvature. When a photosensitive resin material is used as the partition wall 145, the process of forming a resist mask can be omitted.

[0127] Through the above steps, a semiconductor element forming process including a crack suppression layer of the metal film shown in Fig. 1(A) is obtained. ​​​​​​​​​​The semiconductor device 200 with the process completed can be fabricated.

[0128] Here, a method for separating the semiconductor device 200 from the first substrate 100 will be described in detail with reference to FIGS. 6 to 9. of which will be described in detail.

[0129] First, using a removable adhesive layer 301, the second substrate 302 is temporarily bonded to the layer 300 to be peeled off. By bonding the second substrate 302 to the layer 300 to be peeled off, the layer 300 to be peeled off can be easily peeled from the peeling layer 101. Also, by using the removable adhesive layer 301, the stress applied to the layer 300 to be peeled off is relaxed, and the transistor can be protected. Further, since the removable adhesive layer 301 is used, if the second substrate 302 becomes unnecessary, it can be easily removed (see FIG. 6). As the removable adhesive layer 301, for example, a water-soluble resin can be cited as an example. The applied water-soluble resin

[0130] relaxes the unevenness of the layer 300 to be peeled off and facilitates bonding with the second substrate 302. Also, as the removable adhesive layer 301, an adhesive that can be peeled off by light or heat laminated on the water-soluble resin may be used. As the second substrate 302, it is preferable to use a material with high mechanical strength so that it can be peeled off without causing physical damage to the layer 300 to be peeled off. In the present embodiment,

[0131] a quartz substrate is used as the second substrate 302. Next, the layer 300 to be peeled off is peeled (separated) from the first substrate 100 (see FIG. 6). Various methods can be used for the peeling method.

[0132]

[0133] When the first insulating layer 111 is formed on the release layer 101, the release layer 101 and the first insulating layer 111 are 11 is heated during the semiconductor element formation process, and a metal oxide is formed at the interface between the peeling layer 101 and the insulating layer 111. A metal oxide film is formed on the peeling layer 101, and the metal oxide film is formed on the peeling layer 101. The peeling layer 101 becomes weak and peeling occurs at the interface between the release layer 101 and the first insulating layer 111 .

[0134] The peeling method can be, for example, applying mechanical force (peel-off process using human hands or a jig). Separation can be performed by using a method such as rolling a roller or a method of separating the particles while rotating the roller. The liquid is dropped onto the interface between the release layer 101 and the first insulating layer 111, so that the liquid penetrates the interface between the release layer 101 and the first insulating layer 111. The layer to be peeled 300 may be peeled off from the groove. A gas is introduced, and the peeling layer 101 is etched and removed with a fluoride gas to form a second insulating layer. A method of peeling the layer 300 from the substrate 100 may be used. Alternatively, a liquid such as water may be added between the peeling layer 101 and the layer to be peeled 300 to effect the peeling.

[0135] As another peeling method, when the peeling layer 101 is formed of tungsten, ammonia The peeling can be performed while etching the peeling layer 101 with a mixed solution of water and hydrogen peroxide. can.

[0136] The peeling layer 101 may be a film containing nitrogen, oxygen, hydrogen, or the like (for example, amorphous silicon containing hydrogen). The first substrate 100 is made of a transparent material such as a bare film, a hydrogen-containing alloy film, or an oxygen-containing alloy film. In the case of using a substrate having a first substrate 100, the peeling layer 101 is irradiated with laser light from the first substrate 100. The nitrogen, oxygen, and hydrogen contained in the peeling layer are evaporated to separate the first substrate 100 and the peeling layer 10. A method of peeling between the substrate 1 and the substrate 2 can be used.

[0137] Next, a thin, light-weight third substrate 1100 having translucency is attached to the peeled layer 300. 101 is used for bonding (see FIG. 7(A)).

[0138] The third substrate 1100 is thin and lightweight and has optical transparency. A substrate having optical transparency can be used, for example, polyethylene terephthalate (PET). Polyester resins such as polyethylene naphthalate (PEN), polyacrylonitrile resins Grease, polyimide resin, polymethyl methacrylate resin, polycarbonate resin (PC), Polyethersulfone resin (PES), polyamide resin, cycloolefin resin, poly Styrene resin, polyamide-imide resin, polyvinyl chloride resin, etc. can be preferably used. The third substrate 1100 may be made of a material containing nitrogen and silicon, such as silicon nitride or silicon oxynitride. A protective film with low water permeability, such as a film containing aluminum and nitrogen, or aluminum nitride, is used. The third substrate 1100 may be a substrate having a structure in which a fiber is contained in an organic resin. A structure (so-called prepreg) may also be used.

[0139] The semiconductor device shown in this embodiment mode is a bottom emission type in which light is extracted from the surface on the third substrate 1100 side. Since the light-emitting device is a hologram type light-emitting device, a light-transmitting substrate is used as the third substrate 1100. In the case of a top emission type in which light is emitted from the surface opposite to the third substrate 1100, the third substrate As the 1100, a metal substrate that is thin enough to have a non-transparent flexibility may be used. The metal substrate is provided on the side from which light is not extracted. There are no particular limitations on the material that constitutes the metal substrate. Although not fixed, alloys of metals such as aluminum, copper, nickel, aluminum alloys, or stainless steel can be preferably used.

[0140] When the fibrous body is included in the material of the third substrate 1100, high-strength fibers of organic compounds or inorganic compounds are used for the fibrous body. High-strength fibers specifically refer to fibers with a high tensile elastic modulus or Young's modulus. Representative examples include polyvinyl alcohol-based fibers, polyester-based fibers, polyamide-based fibers, polyethylene-based fibers, aramid-based fibers, polyparaphenylene benzobisoxazole fibers, glass fibers, or carbon fibers. Examples of glass fibers include glass fibers using E glass, S glass, D glass, Q glass, etc. These are used in the state of woven fabric or non-woven fabric, the fibrous body is included in the organic resin, and a structure obtained by curing this organic resin may be used as the third substrate 1100. When a structure composed of a fibrous body and an organic resin is used as the third substrate 1100, it is a preferable configuration because the reliability against breakage due to bending or local pressing is improved.

[0141] When the fibrous body as described above is included in the third substrate 1100, in order to reduce the prevention of light from the light-emitting element from exiting to the outside, it is preferable that the fibrous body be a nanofiber bar of 100 nm or less. Also, it is preferable to match the refractive indices of the fibrous body, the organic resin, and the adhesive.

[0142] As the resin layer 1101, various curable adhesives such as photocurable adhesives such as ultraviolet curable adhesives, reaction curable adhesives, thermosetting adhesives, or anaerobic adhesives can be used. As the materials of these adhesives, epoxy resins, acrylic resins, silicone resins, phenols ​​​​​​​​​​​​​​ Resins and the like can be used.

[0143] When a prepreg is used as the third substrate 1100, the substrate is directly peeled off without using an adhesive. The release layer 300 and the third substrate 1100 are bonded together by pressure bonding. Resins are available in a variety of types, including reactive curing, heat curing, and UV curing, which can be hardened by additional processing. It is advisable to use one that undergoes chemical conversion.

[0144] After providing the third substrate 1100, the second substrate 302 and the removable adhesive layer 301 are removed. Thus, the first electrode layer 143 is exposed (see FIG. 7B).

[0145] In this embodiment, a removable adhesive layer is used as the adhesive layer 301. However, when a prepreg is used as the third substrate 1100, it is not necessary to remove it. That's fine.

[0146] Through the above steps, the driver circuit portion 201, the transistor 134, and the A peeled layer 300 on which up to the first electrode layer 143 of the light emitting element is formed can be formed.

[0147] Next, the EL layer 193 is formed over the first electrode layer 143 and the partition wall 145. The EL layer 193 can be made of either a low molecular weight material or a high molecular weight material. The materials that form the material include not only those that are made of organic compounds only, but also those that contain inorganic compounds in part. The EL layer 193 includes at least a light-emitting layer. The layer structure may be a single layer structure or a laminate structure having layers each having a different function. For example, in addition to the light-emitting layer, a hole injection layer, a hole transport layer, a carrier blocking layer, an electron transport layer, , a functional layer having each function such as an electron injection layer is appropriately combined and configured. Note that a layer having two or more functions of these layers may be included (see Fig. 8(A)). It may include a layer having two or more functions of these layers at the same time (see Fig. 8(A)).

[0148] In addition, for the formation of the EL layer 193, a vapor deposition method, an inkjet method, a spin coating method, a dip coating method, a nozzle printing method, etc., can be used regardless of wet or dry.

[0149] Next, a second electrode layer 194 is formed on the EL layer 193. Note that when the first electrode layer 143 is used as an anode, the second electrode layer 194 becomes a cathode, and when the first electrode layer 143 is used as a cathode , the second electrode layer 194 becomes an anode. Therefore, preferably, materials having work functions corresponding to the polarities of the first electrode layer 143 and the second electrode layer 194 are selected and formed.

[0150] In this embodiment, the first electrode layer 143 is used as an anode, and the EL layer 193 has a structure in which a hole injection layer, a hole transport layer, a light emitting layer, and an electron injection layer are laminated in this order from the side of the first electrode layer 143. Various materials can be used as the light emitting layer. For example, a fluorescent compound that emits fluorescence or a phosphorescent compound that emits phosphorescence can be used. In addition, the second electrode layer 194 uses a material with a small work function. In addition, in order to extract light emission from the side of the first electrode layer 143 , the second electrode layer 194 selects a material with a high reflectance. In order to extract light emission from the side of the first electrode layer 143, the second electrode layer 194 selects a material with a high reflectance.

[0151] A protective layer may also be provided on the second electrode layer 194. For example, as the protective layer, by a sputtering method, a plasma CVD method, a coating method, a printing method, etc., for example, a material containing nitrogen and silicon such as silicon nitride, silicon oxynitride , silicon nitride oxide, etc., or aluminum oxide, etc., is used to form a single layer or It is formed in multiple layers. Alternatively, the above-mentioned inorganic insulating film and an organic insulating film such as a resin film may be laminated to form a protective layer. By providing the protective layer, it is possible to prevent moisture and gases such as oxygen from entering the element portion thereby. The thickness of the protective layer is preferably 10 nm or more and 1000 nm or less, more preferably 1 00 nm or more and 700 nm or less.

[0152] Next, the fourth substrate 1200 is bonded using the resin layer 1201 so as to cover the drive circuit portion 201, the pixel circuit portion 202, and the crack suppression region 205 (see FIG. 8(B)).

[0153] It is preferable to use a material with good adhesion for the resin layer 1201. For example, acrylic resin, po lyimide resin, melamine resin, polyester resin, polycarbonate resin, phenol resin resin, epoxy resin, polyacetal, polyether, polyurethane, polyamide (nylon ), organic compounds such as furan resin and diallyl phthalate resin, and compounds composed of silicon, oxygen, and hydrogen formed from siloxane polymer-based materials represented by silica glass among which inorganic siloxane polymers containing Si-O-Si bonds, or alkylsiloxane poly mers, alkylsilsesquioxane polymers, hydrogenated silsesquioxane polymers, and hydrogen ated alkylsilsesquioxane polymers, which are organic siloxane polymers in which hydrogen bonded to silicon is substituted by an organic group such as methyl or phenyl can be used. Further, the resin layer 1201 may contain a fibrous body in these materials.

[0154] The resin layer 1201 can be formed, for example, by applying a composition using a coating method and drying and heating it. Further, a structure in which a fibrous body is included in an organic resin can be used as the resin layer 1201. It is also possible.

[0155] As the fourth substrate 1200, a thin and low water-permeability substrate is used. For example, a metal substrate can be used. There is no particular limitation on the material constituting the metal substrate, but alloys of metals such as aluminum, copper, nickel, aluminum alloys, or stainless steel can be preferably used. Before adhering the fourth substrate 1200, it is preferable to remove the water adhering to the surface of the metal substrate by performing baking or plasma treatment in a vacuum. It is also possible to provide a resin film on the surface of the fourth substrate 1200 to protect the fourth substrate 1200.

[0156] The adhesion of the fourth substrate 1200 can also be performed using a laminator. For example, a sheet-like adhesive is bonded to the metal substrate using a laminator, and then it can be further adhered onto the pixel circuit portion 202 and the drive circuit portion 201 using a laminator. Also, a resin layer 1201 can be printed on the fourth substrate 1200 by screen printing or the like, and then it can be adhered onto the light-emitting element using a laminator. When this process is performed under reduced pressure, it is preferable because air bubbles are less likely to enter.

[0157] Through the above steps, the drive circuit portion 201, the pixel circuit portion 202, and the crack suppression region 205 are sandwiched between the third substrate 1100, which is a flexible substrate, and the fourth substrate 1200, which is a flexible substrate.

[0158] As described above, the peeling layer 300 is separated from the first substrate 100, and the peeling layer 30 is placed between the third substrate 1100, which is a flexible substrate, and the fourth substrate 1200, which is a flexible substrate. It has a plurality of steps until 0 is clamped. Therefore, by providing a crack suppression region 205 around the semiconductor device 200, the semiconductor device 200 can be separated with high yield without being damaged by the crack generated from the outer peripheral portion of the substrate, and can be transferred to a flexible substrate. Next, the crack suppression region 205 is removed, and a semiconductor element including the drive circuit portion 201 and the pixel circuit portion 202 is fabricated on the flexible substrate (see FIG. 9). As a method for removing the crack suppression region 205, it can be appropriately selected according to the materials of the third substrate 1100 and the fourth substrate 1200. Typically, it can be removed using a cutter knife or a laser. In this embodiment, the separation by irradiation of laser light is applied.

[0159] The conditions such as the wavelength, intensity, and beam size of the laser light used in the above separation process are not particularly limited. At least, any conditions that can separate the semiconductor device are acceptable. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser.

[0160] The conditions such as the wavelength, intensity, and beam size of the laser light used in the above separation process are not particularly limited. At least, any conditions that can separate the semiconductor device are acceptable. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser. The conditions such as the wavelength, intensity, and beam size of the laser light used in the above separation process are not particularly limited. At least, any conditions that can separate the semiconductor device are acceptable. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser.

[0161] The conditions such as the wavelength, intensity, and beam size of the laser light used in the above separation process are not particularly limited. At least, any conditions that can separate the semiconductor device are acceptable. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser. As the laser oscillator, for example, continuous oscillation lasers such as Ar laser, Kr laser, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser, helium cadmium laser, etc., and excimer (ArF, KrF, XeCl) lasers, CO2 laser, YAG laser, YVO4 laser, YLF laser, YAlO3 laser, GdVO4 laser, Y2O3 laser, ruby laser, alexandrite laser, Ti:sapphire laser.​​​​​​​​ Pulsed lasers such as copper vapor lasers and gold vapor lasers can be used.

[0162] In this embodiment, the case of removing the crack suppression region 205 is illustrated, but the present invention is not limited to this, and the crack suppression region may be left as it is and function as a part of the semiconductor device. It is also possible.

[0163] In this embodiment, a method of providing the transistor 133, the transistor 134, and the first electrode layer 143 of the light emitting element up to the peelable layer 300 is illustrated. However, the invention disclosed in this specification is not limited to this, and after forming up to the light emitting element (that is, after forming the second electrode layer 194 of the light emitting element), peeling and transfer may be performed. Further, the peelable layer 300 formed with the first insulating layer 111 and the first electrode layer 143 may be peeled and transferred, and transistors and light emitting elements may be manufactured after the transfer. Further, only the first insulating layer 111 may be formed on the manufacturing substrate, peeled and transferred to the substrate, and then transistors and light emitting elements may be manufactured.

[0164] In this embodiment, an active matrix light emitting device has been described as one of semiconductor devices. However, it can also be applied to a method for manufacturing a passive matrix light emitting device.

[0165] Further, in this embodiment, a light emitting device has been described as one of semiconductor devices. However, the present invention can be applied to a liquid crystal display device, a semiconductor circuit, an electronic device, etc., a semiconductor device that can function by utilizing semiconductor characteristics, and a manufacturing method of all semiconductor devices.

[0166] According to this embodiment, a transistor manufactured using a substrate with high heat resistance is made thin and It can be transferred onto a lightweight third substrate having translucency. Therefore, without being restricted by the heat resistance of the third substrate, a transistor with high reliability and good electrical characteristics can be formed. A semiconductor device in which such a transistor is incorporated in a pixel portion and a drive circuit portion on the same substrate is excellent in reliability and has excellent operating characteristics. As described above, by providing a crack suppression layer of a metal film around the formed semiconductor element, cracks from the outer peripheral portion of the substrate can be suppressed and damage to the semiconductor element can be reduced. Further, even if a physical force is applied to the semiconductor device from the outer peripheral portion during peeling and transfer, the crack suppression layer can prevent the crack from proceeding (growing) to the semiconductor device. (Embodiment 2) In the present embodiment, unlike the crack suppression layer of the metal film shown in Embodiment 1, an example of forming a crack suppression layer of a resin layer will be described with reference to FIGS. 14 to 16. Therefore, other operations can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having the same functions and the repetition of the steps in Embodiment 1 will be omitted. Further, FIGS. 14 to 16 are the same as FIGS. 1 to 9 except that the steps are partially different, so the same reference numerals are used for the same parts, and the detailed description of the same parts will be omitted. First, according to Embodiment 1, a release layer 101, a first insulating layer 111, a gate electrode layer 103, a conductive layer 104, a capacitor wiring layer 105, a gate electrode layer 106, a first terminal 102, a gate insulating layer 107, contact holes 109a, contact holes 109b, an oxide semiconductor layer 116, and an oxide semiconductor layer 117 are formed on a substrate 100 (see FIG. 14(A)).

[0167] As described above, by providing a crack suppression layer of a metal film around the formed semiconductor element, cracks from the outer peripheral portion of the substrate can be suppressed and damage to the semiconductor element can be reduced. Further, even if a physical force is applied to the semiconductor device from the outer peripheral portion during peeling and transfer, the crack suppression layer can prevent the crack from proceeding (growing) to the semiconductor device. It can be transferred onto a lightweight third substrate having translucency. Therefore, without being restricted by the heat resistance of the third substrate, a transistor with high reliability and good electrical characteristics can be formed. A semiconductor device in which such a transistor is incorporated in a pixel portion and a drive circuit portion on the same substrate is excellent in reliability and has excellent operating characteristics. As described above, by providing a crack suppression layer of a metal film around the formed semiconductor element, cracks from the outer peripheral portion of the substrate can be suppressed and damage to the semiconductor element can be reduced.

[0168] (Embodiment 2) In this embodiment, unlike the crack suppression layer of the metal film shown in Embodiment 1, an example of forming a crack suppression layer of a resin layer will be described with reference to FIGS. 14 to 16. Therefore, other operations can be performed in the same manner as in Embodiment 1, and the description of the same parts or parts having the same functions and the repetition of the steps in Embodiment 1 will be omitted. Further, FIGS. 14 to 16 are the same as FIGS. 1 to 9 except that the steps are partially different, so the same reference numerals are used for the same parts, and the detailed description of the same parts will be omitted. First, according to Embodiment 1, a release layer 101, a first insulating layer 111, a gate electrode layer 103, a conductive layer 104, a capacitor wiring layer 105, a gate electrode layer 106, a first terminal 102, a gate insulating layer 107, contact holes 109a, contact holes 109b, an oxide semiconductor layer 116, and an oxide semiconductor layer 117 are formed on a substrate 100 (see FIG. 14(A)). As described above, by providing a crack suppression layer of a metal film around the formed semiconductor element, cracks from the outer peripheral portion of the substrate can be suppressed and damage to the semiconductor element can be reduced. Further, even if a physical force is applied to the semiconductor device from the outer peripheral portion during peeling and transfer, the crack suppression layer can prevent the crack from proceeding (growing) to the semiconductor device.

[0169] First, according to Embodiment 1, a release layer 101, a first insulating layer 111, a gate electrode layer 103, a conductive layer 104, a capacitor wiring layer 105, a gate electrode layer 106, a first terminal 102, a gate insulating layer 107, contact holes 109a, contact holes 109b, an oxide semiconductor layer 116, and an oxide semiconductor layer 117 are formed on a substrate 100 (see FIG. 14(A)). It can be transferred onto a lightweight third substrate having translucency. Therefore, without being restricted by the heat resistance of the third substrate, a transistor with high reliability and good electrical characteristics can be formed. A semiconductor device in which such a transistor is incorporated in a pixel portion and a drive circuit portion on the same substrate is excellent in reliability and has excellent operating characteristics. As described above, by providing a crack suppression layer of a metal film around the formed semiconductor element, cracks from the outer peripheral portion of the substrate can be suppressed and damage to the semiconductor element can be reduced.

[0170] Next, a metal film was formed over the oxide semiconductor layer 116, the oxide semiconductor layer 117, and the gate insulating layer 107. A metal conductive film made of the material is formed by sputtering or vacuum deposition.

[0171] The materials for the metal conductive film include aluminum, chromium, tantalum, titanium, molybdenum, and tantalum. an element selected from the group consisting of tin, silver, copper, gold, platinum, nickel, and palladium, or Examples of the alloy include an alloy film containing the above elements as a component, and an alloy film made up of a combination of the above elements. The metal conductive film may have a single layer structure or a laminated structure of two or more layers. A single-layer structure of an aluminum film containing titanium, a two-layer structure of a titanium film on an aluminum film, A titanium film is then formed on top of the aluminum film. Examples include a three-layer structure.

[0172] When a heat treatment is performed after the formation of the metal conductive film, the metal conductive film is required to have heat resistance sufficient to withstand the heat treatment. It is preferable to have the

[0173] Next, a photolithography process is performed to form a resist mask 150a and a resist mask 150 b, resist mask 150c, resist mask 150d, resist mask 150e, A mask 150f and a resist mask 150g are formed, and the metal conductive film is etched. The unnecessary portions are removed to form the source electrode layer 119a, the drain electrode layer 119b, and the source electrode layer 1 20a, drain electrode layer 120b, capacitance electrode layer 121, connection electrode 122, second terminal 12 3 is formed (see FIG. 14(B)).

[0174] In this embodiment, the metal conductive film is formed of aluminum having a thickness of 300 nm. It is configured such that titanium is provided in an amount of 100 nm each above and below.

[0175] Note that the resist masks 150a, 150b, 150c, 150d, 150e, 150f, and 150g for forming the source electrode layer 119a, the source electrode layer 120a, the drain electrode layer 119b, the drain electrode layer 120b, the connection electrode 122, and the second terminal 123 may be formed by an inkjet method. When the resist mask is formed by the inkjet method, since a photo mask is not used, the manufacturing cost can be reduced. mask 150a, the resist mask 150b, the resist mask 150c, the resist Next, the resist masks 150a, 150b, 150c, 150d, 150e, 150f, and 150g are removed, and an insulating layer 125 serving as a protective insulating layer in contact with the oxide semiconductor layer 116 and the oxide semiconductor layer 117 is formed (FIG. 15(A)).

[0176] At this stage, regions in contact with the insulating layer 125 are formed in the oxide semiconductor layer 116 and the oxide semiconductor layer 117, and among these regions, the regions overlapping with the gate electrode layer and the gate insulating layer become the channel formation regions 126 and 128. The insulating layer 125 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as a sputtering method that does not mix impurities such as water and hydrogen into the insulating layer 12 5. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 125 using a sputtering method. The substrate temperature during film formation may be set to be equal to or higher than room temperature and equal to or lower than 300 °C. In this embodiment

[0177] At this stage, regions in contact with the insulating layer 125 are formed in the oxide semiconductor layer 116 and the oxide semiconductor layer 117, and among these regions, the regions overlapping with the gate electrode layer and the gate insulating layer become the channel formation regions 126 and 128. regions 126 and 128.

[0178] The insulating layer 125 has a film thickness of at least 1 nm or more, and can be formed by appropriately using a method such as a sputtering method that does not mix impurities such as water and hydrogen into the insulating layer 12 5. In this embodiment, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 125 using a sputtering method. The substrate temperature during film formation may be set to be equal to or higher than room temperature and equal to or lower than 300 °C. In this embodiment form, a silicon oxide film with a film thickness of 300 nm is formed as the insulating layer 125 using a sputtering method. The substrate temperature during film formation may be set to be equal to or higher than room temperature and equal to or lower than 300 °C. In this embodiment the substrate temperature during film formation is set to be equal to or higher than room temperature and equal to or lower than 300 °C. Set the temperature to room temperature. The formation of the silicon oxide film by sputtering can be carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or an atmosphere of a rare gas (typically argon) and oxygen. It can also be carried out in an oxygen atmosphere or an atmosphere of a rare gas (typically argon) and oxygen. Also, a silicon oxide target or a silicon target can be used as the target. For example, silicon oxide can be formed by sputtering in an oxygen atmosphere using a silicon target. The insulating layer 125 formed in contact with the low-resistance oxide semiconductor layer does not contain impurities such as moisture, hydrogen ions, and OH, and an inorganic insulating film that blocks these from entering from the outside is used. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or an aluminum oxynitride film is used. Then, a second heat treatment (preferably 200°C or higher and 400°C or lower, for example, 250°C or higher and 350°C or lower) is carried out in an inert gas atmosphere or a nitrogen gas atmosphere. For example, a second heat treatment at 250°C for 1 hour is carried out in a nitrogen atmosphere. When the second heat treatment is carried out, a part of the oxide semiconductor layers 116 and 117 that overlap with the insulating layer 125 is heated in a state of being in contact with the insulating layer 125. By the second heat treatment, oxygen is introduced and diffused into the exposed portions (the channel formation regions 126 and 128) of the oxide semiconductor layer between the source region and the drain region. By producing a silicon oxide film by sputtering, excess oxygen can be contained in the silicon oxide film, and that oxygen can be further introduced and diffused into the oxide semiconductor layer by the second heat treatment. By the introduction and diffusion of oxygen into the oxide semiconductor layer, the channel formation region 12 - - -

[0179]

[0180] 6. The channel formation regions 128 can be made highly resistive (type I), thereby obtaining a normally-off transistor. Therefore, the reliability of the semiconductor device can be improved.

[0181] Specifically, the channel formation region 12 6 overlapping with the gate electrode layer 103 of the oxide semiconductor layer 116 becomes type I, and a highly resistive source region 127a overlapping with the source electrode layer 119a and a highly resistive drain region 127b overlapping with the drain electrode layer 119b are self-alignedly formed. Similarly, the channel formation region 128 overlapping with the gate electrode layer 106 of the oxide semiconductor layer 117 becomes type I, and a highly resistive source region 129a overlapping with the source electrode layer 120a and a highly resistive drain region 129b overlapping with the drain electrode layer 120b are self-alignedly formed (see Fig. 15( A)).

[0182] Note that in the oxide semiconductor layers 116 and 117 overlapping with the drain electrode layer 119b and the drain electrode layer 120b (and the source electrode layer 119a, source electrode layer 120a), by forming the highly resistive drain regions 127b and 129b (or the highly resistive source regions 1 27a and 129a), the reliability when forming a circuit can be improved. Specifically, by forming the highly resistive drain regions 127b and 129b, a structure can be obtained in which the conductivity can be changed stepwise from the drain electrode layer 119b and the drain electrode layer 120b to the highly resistive drain regions 127b and 129b, the channel formation region 126, and the channel formation region 1 28. Therefore, a wiring for supplying a high power supply potential VDD to the drain electrode layer 119b and the drain electrode layer 120b can be made. ​​​When connected and operated, even if a high electric field is applied between the gate electrode layer 103, the gate electrode layer 106 and the drain electrode layer 119b, and the drain electrode layer 120b, the high-resistance drain region serves as a buffer and a local high electric field is not applied, and the breakdown voltage of the transistor can be improved. This can be achieved with a configuration.

[0183] Also, in the oxide semiconductor layer overlapping with the drain electrode layer 119b, the drain electrode layer 120b (and the source electrode layer 119a, the source electrode layer 120a), by forming the high-resistance drain region 127b and the high-resistance drain region 129b (or the high-resistance source region 127a, the high-resistance source region 12 9a), it is possible to reduce the leakage current in the channel formation region 126 and the channel formation region 128 when forming a circuit.

[0184] Also, the high-resistance source region or the high-resistance drain region in the oxide semiconductor layer is formed over the entire film thickness direction when the film thickness of the oxide semiconductor layer is as thin as 15 nm or less. However, when the film thickness of the oxide semiconductor layer is thicker, between 30 nm and 50 nm, a part of the oxide semiconductor layer, the region in contact with the source electrode layer or the drain electrode layer, and its vicinity are made to have a lower resistance, and the high-resistance source region or the high-resistance drain region is formed, and the region near the gate insulating layer in the oxide semiconductor layer can also be made into type I.

[0185] A protective insulating layer 132 may be further formed on the insulating layer 125. For example, a silicon nitride film is formed using the RF sputtering method. The RF sputtering method is preferable as a method for forming the protective insulating layer because of its good mass productivity. The protective insulating layer blocks moisture, hydrogen ions, OH and the like. - ​​​​​​​It uses an inorganic insulating film that does not contain impurities and blocks them from entering from the outside, and nitrides A silicon film, an aluminum nitride film, a silicon nitride oxide film, an aluminum oxynitride film, or the like is used. In this embodiment, the protective insulating layer 132 is formed using a silicon nitride film as the protective insulating layer. See Figure 15(A).

[0186] Through the above steps, the transistor 133 is formed in the driver circuit section and the pixel circuit section is formed on the same substrate. The transistor 133 and the capacitor 135 can be fabricated in the same manner. The transistor 134 includes a high-resistance source region, a high-resistance drain region, and a channel forming region. The transistor 13 is a bottom-gate transistor including an oxide semiconductor layer. 3. The transistor 134 has a high resistance drain region or a high resistance source region even when a high electric field is applied. The buffer region prevents localized high electric fields from being applied, improving the breakdown voltage of the transistor. In addition, by forming the driving circuit section and the pixel circuit section on the same substrate, This allows the wiring between the driver circuit and external signals to be shortened, making it possible to miniaturize semiconductor devices (light-emitting devices) and reduce costs. It is possible to store it.

[0187] The capacitor 135 is formed by connecting the gate insulating layer 107 in the capacitor section to the capacitor wiring layer 1 05 and the capacitive electrode layer 121.

[0188] Next, a color filter layer 136 is formed on the protective insulating layer 132. 6 includes a green color filter layer, a blue color filter layer, and a red color filter layer. A green color filter layer, a blue color filter layer, a red color filter layer, etc. can be used. Each color filter layer is formed by a printing method, an inkjet method, a filter layer, and a filter layer. Each is formed by an etching method using photolithography technology or the like. Color filter By providing the color filter layer 136, the alignment between the color filter layer 136 and the light-emitting region of the light-emitting element can be performed without depending on the bonding accuracy of the sealing substrate. In this embodiment In the photolithography process, a green color filter layer, a blue color filter layer, and a red color filter layer are formed (see FIG. 15(B)).

[0189] Next, an overcoat layer 137 that covers the color filter layer (the green color filter layer, the blue color filter layer, and the red color filter layer) is formed. The overcoat layer 13 7 uses a resin having translucency.

[0190] Here, an example of full-color display using three colors of RGB is shown, but it is not particularly limited and full-color display may be performed using four colors of RGBW.

[0191] Next, a protective insulating layer 138 that covers the overcoat layer 137 and the protective insulating layer 132 is formed (see FIG. 15(B)). The protective insulating layer 138 uses an inorganic insulating film, such as a silicon nitride film, an aluminum nitride film, a silicon oxynitride film, or an aluminum oxynitride. As for the protective insulating layer 138 it is preferable to use an insulating film having the same composition as the protective insulating layer 132 because it can be etched in one step when forming the contact hole later .

[0192] Next, a resist mask is formed by a photolithography process, and the protective insulating layer 138, the protective insulating layer 132, and the insulating layer 125 are etched to form a contact hole 140 that reaches the drain electrode layer 120b, and the resist mask is removed (see FIG. 16(A)). Also, here Etching is performed to form a contact hole 141 reaching the second terminal 123 and a connection electrode 12 2, and a contact hole 139 reaching the connection electrode 12 is also formed. Further, a resist mask for forming the contact hole may be formed by an inkjet method. Since the resist mask is formed by the inkjet method, a photomask is not used, and the manufacturing cost can be reduced. Next, a conductive film having translucency is formed. As the material of the conductive film having translucency, indium oxide (In2O3), indium oxide-tin oxide alloy (In2O3 - SnO2, abbreviated as ITO ) is formed by a sputtering method, a vacuum deposition method, or the like. As another material of the conductive film having translucency, an Al-Zn-O-based non-single crystal film containing nitrogen, a Zn-O-based non-single crystal film containing nitrogen, or a Sn-Zn-O-based non-single crystal film containing nitrogen may be used. The composition ratio (atomic%) of zinc in the Al-Zn-O-based non-single crystal film containing nitrogen is 47

[0193] atomic% or less, greater than the composition ratio (atomic%) of aluminum in the non-single crystal film, and the composition ratio (atomic%) of aluminum in the non-single crystal film is greater than the composition ratio (atomic%) of nitrogen in the non-single crystal film. The etching treatment of such a material is performed with a hydrochloric acid-based solution. However, especially for the etching of ITO, residues are likely to occur, so an indium oxide-zinc oxide alloy (In2O3 - ZnO) may be used to improve the etching processability.

[0194]

[0195] Note that the unit of the composition ratio of the conductive film having translucency is atomic%, and it is evaluated by analysis using an electron probe X-ray microanalyzer (EPMA: Electron Probe X-ray MicroAnalyzer

[0194]

[0195] )

[0195]

[0195] Next, a resist mask is formed in the photolithography process, and unnecessary portions of the conductive film having translucency are removed by etching to form the first electrode layer 143, the terminal electrodes 142, and the terminal electrode 1 44, and the resist mask is removed (see FIG. 16(B)).

[0196] The gate insulating layer 107 can be formed as a dielectric capacitor 135 formed by the capacitor wiring layer 105 and the capacitor electrode layer 121 on the same substrate. Also, in the semiconductor device 400, the capacitor electrode layer 121 is a part of the power supply line, and the capacitor wiring layer 105 also functions as a part of the gate electrode layer of the driving TFT.

[0197] The terminal electrodes 142 and 144 formed at the terminal portion serve as electrodes or wires for connection to the FPC. The terminal electrode 142 formed via the connection electrode 122 on the first terminal 102 is a terminal electrode for connection that functions as an input terminal of the gate wiring. The terminal electrode 144 formed on the second terminal 123 is a terminal electrode for connection that functions as an input terminal of the source wiring.

[0198] Next, a partition wall 145 is formed so as to cover the peripheral portion of the first electrode layer 143. At the same time as the partition wall 14 5, a crack suppression layer 151 of a resin film is formed in the crack suppression region 205. The partition wall 1 45 and the crack suppression layer 151 of the resin film are formed using an organic resin film such as polyimide, acrylic, polyamide, or epoxy xy, an inorganic insulating film, or a siloxane-based resin.

[0199] The siloxane-based resin corresponds to a resin containing an Si-O-Si bond formed using a siloxane-based material as a starting material. The siloxane-based resin has an organic group as a substituent (for example, an alkyl ​​​​​​An Ru group, an aryl group, and a fluoro group may be used.

[0200] As the partition wall 145 and the crack suppression layer 151 of the resin layer, PSG (phosphosilicate glass), BPSG (borophosphosilicate glass), etc. can also be used. Note that the insulating film formed of these materials may be formed into a plurality of laminated layers to form the partition wall 145.

[0201] The method for forming the partition wall 145 and the crack suppression layer 151 of the resin layer is not particularly limited, and depending on the material used, a sputtering method, a SOG method, spin coating, dipping, spray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife coater, etc. can be used. Also, as other insulating layers used in a semiconductor device (light-emitting device), the above materials and methods shown as examples of the partition wall 145 can be used.

[0202] The partition wall 145 and the crack suppression layer 151 of the resin layer use a photosensitive resin material in particular, and an opening is formed on the first electrode layer 143, and the side wall of the opening is formed so as to be an inclined surface having a continuous curvature. It is preferably formed. When a photosensitive resin material is used as the partition wall 145 and the crack suppression layer 151 of the resin layer, the step of forming a resist mask can be omitted.

[0203] The crack suppression layer 151 of the resin layer requires a film thickness and a width that can suppress the progress (growth) of cracks. Also, by increasing the width of the crack suppression layer of the resin layer, the number of desired semiconductor devices that can be taken from one substrate (also referred to as the take number) may decrease. Therefore, as the crack suppression layer of the resin layer, the thickness is 700 nm or more and 20000 nm or less, and the width is 100 μm or more ​​​​​​It is formed at 10,000 μm or less.

[0204] Through the above steps, a semiconductor element including a crack prevention layer of the resin layer shown in FIG. 16(B) is formed. When the process is completed, a semiconductor device 400 can be manufactured.

[0205] This embodiment mode can be implemented in appropriate combination with the configurations described in other embodiments. It is.

[0206] (Embodiment 3) Regarding another example of a method for manufacturing a semiconductor device different from the above embodiment mode, reference is made to FIGS. In the first and second embodiments, a driving circuit section and a pixel circuit section are configured. A method for manufacturing a display device, which is one type of semiconductor device having a transistor, will be described. However, in this embodiment, a semiconductor integrated circuit chip (also called an IC chip) is used. We will explain how to make the above.

[0207] FIG. 10(A) is a plan view of the semiconductor device, and FIG. 10(B) is a schematic diagram of the semiconductor device of FIG. FIG. 10(C) shows an enlarged plan view of a part of a semiconductor integrated circuit chip. FIG. 10(B) shows an enlarged plan view of a part of a semiconductor integrated circuit chip. 10 is a cross-sectional view taken along dashed line CD of FIG. 10 after the semiconductor device forming process is completed. 1A and 1B are a plan view and a cross-sectional view of the semiconductor device before it is separated from the substrate.

[0208] FIG. 10(A) shows a semiconductor integrated circuit chip (also called an IC chip, hereafter IC A metal film cladding is placed around the periphery of multiple semiconductor integrated circuits. A lock-suppressing layer 750 is formed.

[0209] In this embodiment mode, a plurality of semiconductor devices, that is, IC chips, are shown in FIG. It can be stopped and peeled off.

[0210] As in this embodiment, a crack suppression layer of a metal film can also be formed on a plurality of semiconductor devices. That is, the size of the crack suppression layer on the plane is not particularly limited, and can be appropriately changed according to the size for separating the semiconductor device from the substrate.

[0211] The semiconductor device according to this embodiment shown in FIG. 10 has a release layer 702 on a substrate 701, has a first insulating layer 703 on the release layer 702, and has an integrated circuit 751 on the first insulating layer 703. The integrated circuit 751 is formed by transistors 730a and 730b. Also, an antenna 720 is provided above the transistors 730a and 730b, and the transistor 730a is electrically connected to the antenna 720.

[0212] Here, an example of a method for manufacturing the semiconductor device 700 shown in FIG. 10(C) will be described in detail with reference to FIGS. 11 to 14. In addition, the same reference numerals are used in the parts described below in common among different drawings, and the repeated description thereof will be omitted.

[0213] First, a release layer 702 is formed on the surface of the substrate 701, and subsequently, a first insulating layer 703 and a semiconductor layer 704 (for example, a film containing amorphous silicon) are formed (see FIG. 11(A)). The release layer 7 02, the first insulating layer 703, and the semiconductor layer 704 can be formed continuously. By forming continuously, the release layer 702 or the first insulating layer 703 is not exposed to the atmosphere, so that the mixing of impurities can be prevented.

[0214] Note that the release layer 702 is the same as the release layer 101 shown in Embodiment 1, and the first insulating layer 703 can be formed by the same method as the first insulating layer 111 shown in Embodiment 1. It can be formed by the same method as the first insulating layer 111 shown in Embodiment 1.

[0215] The semiconductor layer 704 can be formed by a sputtering method, an LPCVD method, a plasma CVD method, or the like. In this embodiment, an amorphous silicon film is formed by the plasma CVD method to a thickness of 66 nm. When an amorphous silicon film is used as the semiconductor layer, it is formed to a thickness of 25 nm or more and 300 nm or less, preferably 50 nm or more and 70 nm or less. When an amorphous silicon film is used as the semiconductor layer, it is formed to a thickness of 25 nm or more and 300 nm or less, preferably 50 nm or more and 70 nm or less. When an amorphous silicon film is used as the semiconductor layer, it is formed to a thickness of 25 nm or more and 300 nm or less, preferably 50 nm or more and 70 nm or less.

[0216] Next, the semiconductor layer 704 is irradiated with laser light for crystallization. Note that the crystallization of the semiconductor layer 704 may be performed by a method combining laser light irradiation with a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Next, the semiconductor layer 704 is irradiated with laser light for crystallization. Note that the crystallization of the semiconductor layer 704 may be performed by a method combining laser light irradiation with a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Next, the semiconductor layer 704 is irradiated with laser light for crystallization. Note that the crystallization of the semiconductor layer 704 may be performed by a method combining laser light irradiation with a thermal crystallization method using an RTA or a furnace annealing furnace, or a thermal crystallization method using a metal element that promotes crystallization. Thereafter, the obtained crystalline semiconductor film is etched into a desired shape to form a semiconductor layer 704a and a semiconductor layer 704b, and a gate insulating layer 705 is formed so as to cover these (see FIG. 11(B)). Thereafter, the obtained crystalline semiconductor film is etched into a desired shape to form a semiconductor layer 704a and a semiconductor layer 704b, and a gate insulating layer 705 is formed so as to cover these (see FIG. 11(B)). Thereafter, the obtained crystalline semiconductor film is etched into a desired shape to form a semiconductor layer 704a and a semiconductor layer 704b, and a gate insulating layer 705 is formed so as to cover these (see FIG. 11(B)).

[0217] An example of the manufacturing process of the semiconductor layer 704a and the semiconductor layer 704b will be briefly described below. First, an amorphous semiconductor film (for example, an amorphous silicon film) is formed using the plasma CVD method. Next, An example of the manufacturing process of the semiconductor layer 704a and the semiconductor layer 704b will be briefly described below. First, an amorphous semiconductor film (for example, an amorphous silicon film) is formed using the plasma CVD method. Next, a solution containing nickel, which is a metal element that promotes crystallization, is held on the amorphous semiconductor film. After that, a dehydrogenation treatment (500 °C, 1 hour) and a thermal crystallization treatment (550 °C, 4 hours) are performed on the amorphous semiconductor film to form a crystalline semiconductor film. Thereafter, depending on the degree of crystallization, laser light is irradiated from a laser oscillator as necessary, and photolithography is used. laser light is irradiated from a laser oscillator as necessary, and photolithography is used. Therefore, semiconductor layers 704a and 704b are formed. Note that crystallization of the amorphous semiconductor film may be performed only by irradiating laser light without performing thermal crystallization using a metal element that promotes crystallization.

[0218] Also, semiconductor layers 704a and 704b can be formed by scanning the semiconductor film in one direction while irradiating it with continuous oscillation laser light or laser light oscillating at a frequency of 10 MHz or more to crystallize it. In such a case of crystallization, crystals have the property of growing in the scanning direction of the laser light. It is preferable to arrange the transistors so that the scanning direction coincides with the channel length direction (the direction in which carriers flow when the channel formation region is formed).

[0219] Next, a gate insulating layer 705 covering the semiconductor layers 704a and 704b is formed. The gate insulating layer 705 is formed of a film containing silicon oxide or silicon nitride in a single-layer structure or a laminated structure by a plasma CVD method, a sputtering method, or the like. Specifically, a silicon oxide film, a silicon oxynitride film, or a silicon nitride oxide film is formed in a single-layer structure or a laminated structure.

[0220] Also, the gate insulating layer 705 may be formed by performing plasma treatment on the semiconductor layers 704a and 704b to oxidize or nitride the surface. For example, it is formed by plasma treatment introducing a mixed gas of a noble gas such as He, Ar, Kr, Xe, etc. and oxygen, nitrogen dioxide (NO2), ammonia, nitrogen, hydrogen, etc. In this case, when the plasma is excited using microwaves, a high-density plasma can be generated at a low electron temperature. Oxygen radicals (which may include OH radicals) or nitrogen radicals (NH radicals) generated by this high-density plasma ​​​​​​​​​​​​​​The surface of the semiconductor layer can be oxidized or nitrided by (which may include CAL).

[0221] By the treatment using such high-density plasma, typically in the range of 1 nm or more and 20 nm or less, an insulating film with a thickness of 5 nm or more and 10 nm or less is formed on the semiconductor layer. In this case, the reaction is a solid-phase reaction, so the interface trap density between the insulating layer and the semiconductor layer can be made extremely low. Such plasma treatment directly oxidizes (or nitrides) the semiconductor layer (crystalline silicon or polycrystalline silicon), so that the variation in the film thickness of the formed insulating layer can be made extremely small. In addition, oxidation does not proceed even at the grain boundaries of crystalline silicon, resulting in a very favorable state. That is, by solid-phase oxidizing the surface of the semiconductor layer with the high-density plasma treatment shown here, an insulating layer with good uniformity and low interface trap density can be formed without causing an abnormal oxidation reaction at the grain boundaries.

[0222] The gate insulating layer 705 may use only the insulating layer formed by plasma treatment, or in addition, an insulating film such as silicon oxide, silicon oxynitride, or silicon nitride may be deposited and laminated by a CVD method using plasma or thermal reaction. In any case, a transistor formed by including the insulating film formed by plasma treatment in part or all of the gate insulating film can reduce the variation in characteristics, which is preferable.

[0223] Also, when forming the semiconductor layer 704a and the semiconductor layer 704b obtained by crystallizing while scanning in one direction while irradiating the semiconductor film with continuous-wave laser light or laser light oscillating at a frequency of 10 MHz or more, the above-mentioned gate insulating layer subjected to plasma treatment is combined. ​​​​ Thus, a transistor with small characteristic variations and high field-effect mobility can be obtained.

[0224] Next, a conductive layer is formed on the gate insulating layer 705. In this embodiment, a conductive layer with a thickness of 100 nm or more and 500 nm or less is formed. As the material to be used, materials containing elements selected from aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, etc., alloy materials mainly composed of these elements, or compound materials mainly composed of these elements can be used. When forming the conductive layer in a laminated structure, for example, a laminated structure of a tantalum nitride film and a tungsten film, a laminated structure of a tungsten nitride film and a tungsten film, or a laminated structure of a molybdenum nitride film and a molybdenum film can be used. For example, a laminated structure of 30 nm of tantalum nitride and 150 nm of tungsten can be used. Since tungsten and tantalum nitride have high heat resistance, heat treatment for the purpose of thermal activation can be performed after forming the conductive layer. Also, the conductive layer may have a laminated structure of three or more layers. For example, a laminated structure of a molybdenum film, an aluminum film, and a molybdenum film can be adopted.

[0225] Next, a mask made of resist is formed on the above conductive layer using photolithography, and an etching process for forming the gate electrode and the gate wiring is performed to form the gate electrode layer 707 above the semiconductor layer 704a and the semiconductor layer 704b (see Fig. 11(C)).

[0226] Next, a mask made of resist is formed by photolithography, and the semiconductor layer 70 ​​​​​​​​​​​​​​4a, the semiconductor layer 704b is doped with n-type or p-type ions by ion doping or ion implantation. The impurity element is added at a low concentration. The semiconductor layer 704b is doped with a low concentration of an impurity element that imparts n-type conductivity. Pure elements can be any element in group 15, such as phosphorus (P) or arsenic (As). In addition, as the impurity element for imparting p-type, an element belonging to group 13 is used. For example, boron (B) can be used.

[0227] In this embodiment, only an n-type TFT is shown, but the present invention is not limited to this. It is not to be construed as being limited thereto. A configuration using only p-type TFTs is also possible. A p-type TFT may be formed at the same time. When an n-type TFT and a p-type TFT are formed at the same time, A mask is formed to cover the semiconductor layer that will become the p-type TFT, and an impurity element that gives the n-type is added. Then, a mask is formed to cover the semiconductor layer that will later become an n-type TFT, and an impurity element that gives the p-type is added. By adding impurity elements, n-type and p-type impurity elements can be selectively added. It is possible.

[0228] Next, an insulating layer is formed to cover the gate insulating layer 705 and the gate electrode layer 707. The insulating layer is formed by depositing silicon, silicon oxide, or silicon by plasma CVD or sputtering. A film containing an inorganic material such as an inorganic nitride, or a film containing an organic material such as an organic resin, is formed as a single layer or a laminate. The insulating layer is selectively etched by anisotropic etching mainly in the vertical direction. Then, an insulating layer 708 (also called a sidewall) is formed in contact with the side surface of the gate electrode layer 707. The insulating layer 708 will later be used as a lightly doped drain (LDD). It is used as a mask for adding impurity elements when forming a region.

[0229] Next, using a mask made of a resist formed by photolithography, and the gate electrode layer 7 07 and the insulating layer 708 as masks, impurity elements for imparting an n-type are added to the semiconductor layer 704a and the semiconductor layer 704b. Thereby, a channel formation region 706a, a first impurity region 706b, and a second impurity region 706c are formed (see FIG. 11(C)). The first impurity region 706b functions as a source region or a drain region of the transistor, and the second impurity region 706c functions as an LDD region. The concentration of the impurity elements included in the second impurity region 706c is lower than the concentration of the impurity elements included in the first impurity region 706b.

[0230] Subsequently, an insulating layer is formed in a single-layer structure or a stacked structure so as to cover the gate electrode layer 707, the insulating layer 708, etc. In the present embodiment, the case where the insulating layer 709, the insulating layer 710, and the insulating layer 711 are in a three-layer structure is exemplified (see FIG. 12(A)). These insulating layers can be formed by plasma CVD method, and the insulating layer 709 can be formed as a silicon oxynitride film with a thickness of 50 nm, the insulating layer 710 can be formed as a silicon nitride oxide film with a thickness of 200 nm, and the insulating layer 711 can be formed as a silicon oxynitride film with a thickness of 400 nm. The surface of these insulating films is formed along the surface shape of the layer provided in the lower layer, although it also depends on the film thickness. That is, since the insulating layer 709 has a thin film thickness, its surface largely follows the surface shape of the gate electrode layer 7 07 and the insulating layer 708. As the film thickness increases, the surface shape approaches flatness. Therefore, the surface shape of the insulating layer 711, which has the thickest film thickness among the three-layer structure, is nearly flat. However, since it is different from an organic material, it is different from a flat surface shape. That is, However, since it is different from an organic material, it has a different flat surface shape. That is, If you want to flatten the surface shape, organic materials such as polyimide, polyamide, benzocyclobutene , acrylic, epoxy, etc., or siloxane materials can be used. In addition to the plasma CVD method, the manufacturing method of these insulating layers can adopt sputtering method, SOG method, droplet discharge method, screen printing method, etc.

[0231] Then, using photolithography, insulating layers 709, 710, 711, etc. are etched to form contact holes reaching the first impurity region 706b, and then a conductive layer 731a, a conductive layer 731 b, a conductive layer 731c, a conductive layer 731d that function as the source electrode or drain electrode of the transistor, a conductive layer 731e that functions as a connection wiring, and a crack suppression layer 750 of the metal film are formed. The conductive layers 731a, 731b, 73 1c, 731d form a conductive layer so as to fill the contact holes, and can be formed by selectively etching the conductive layer. Note that before forming the conductive layer, on the surfaces of the semiconductor layers 704a and 704b exposed in the contact holes, a sil icide side can be formed to lower the resistance.

[0232] The conductive layers 731a, 731b, 731c, and 731d are preferably formed using a low-resistance material so as not to cause signal delay. Since many low-resistance materials have low heat resistance, it is advisable to provide materials with high heat resistance above and below the low-resistance material. For example, a configuration in which 300 nm of aluminum is formed as the low-resistance material and 100 n m of titanium is provided above and below the aluminum is good. Also, although the conductive layer 731e functions as a connection wiring, the conductive By forming it with the same laminated structure as the layer 731a, the low resistance of the connection wiring and the heat resistance can be improved. This can be achieved.

[0233] Also, for the crack suppression layer 750 of the metal film, it is necessary to select a film thickness that can maintain mechanical strength. Specifically, as the metal conductive film, it is formed with a thickness of 300 nm or more and 5000 nm or less, more preferably, it is formed with a thickness of 500 nm or more and 1500 nm or less.

[0234] Also, for the crack suppression layer 750 of the metal film, a width that can suppress the progress (growth) of cracks is required. However, by increasing the width of the crack suppression layer, the number of desired semiconductor devices that can be taken from one substrate (also referred to as the take number) may decrease. Therefore, the crack suppression layer is formed with a width of 100 μm or more and 10000 μm or less, and more preferably with a width of 1000 μ m or more and 5000 μm or less. This can be achieved.

[0235] Also, the conductive layer 731a, the conductive layer 731b, the conductive layer 731c, the conductive layer 731d, the conductive layer 73 1e, and the crack suppression layer 750 can be formed in a single-layer structure or a laminated structure using other conductive materials, for example, materials containing elements selected from aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, materials containing elements selected from these elements, alloy materials having these elements as the main component, and compound materials having these elements as the main component. Also, the conductive layer 731a, the conductive layer 731b, the conductive layer 731c, the conductive layer 731d, the conductive layer 7 31e, and the crack suppression layer 750 can be formed by a sputtering method or the like. This can be achieved. This can be achieved.

[0236] As described above, the transistor 730a, the transistor 730b, and the crack suppression layer 750 An element layer 749 including the above-mentioned elements is obtained (see FIG. 12A).

[0237] Before forming the insulating layer 709, the insulating layer 710, and the insulating layer 711, or after forming the insulating layer 709, After forming the insulating layer 709 and the insulating layer 710, the semiconductor layer 704a and the semiconductor layer 704b are formed. The crystallinity of the semiconductor layer 704b is restored, and impurities added to the semiconductor layers 704a and 704b are removed. Heat treatment is performed for the purpose of activating the elements and hydrogenating the semiconductor layers 704a and 704b. Heat treatment can be performed using thermal annealing, laser annealing, RTA, etc. It is good.

[0238] Next, the conductive layer 731a, the conductive layer 731b, the conductive layer 731c, the conductive layer 731d, and the conductive layer 73 1e and the insulating layer 712 and the insulating layer 713 are formed so as to cover the crack prevention layer 750. (See FIG. 12B.) In this embodiment, the insulating layer 712 has a thickness of 100 nm. A silicon nitride film is formed, and a polyimide film having a thickness of 1500 nm is used for the insulating layer 713. The insulating layer 713 preferably has a highly flat surface. In addition to the characteristics of a certain organic material, the composition of the thick film, for example, 750 nm to 3000 nm The thickness of the insulating layer 713 enhances the flatness of the planar shape of the insulating layer 713. 2. An opening is formed in the insulating layer 713. In this embodiment, the conductive layer 731e In this example, an opening 714 is formed so that the exposed portion 714 is formed. In the region 715 surrounded by the dotted line, the end of the insulating layer 712 is covered with an insulating layer 713. The upper insulating layer 713 covers the end of the lower insulating layer 712, and the opening is then It is possible to prevent disconnection of the wiring formed in the section 714. In the present embodiment, since the insulating layer 713 uses polyimide which is an organic material, in the opening 714, the insulating layer 7 13 can have a gentle taper and can efficiently prevent disconnection. Materials for the insulating layer 713 that can obtain such a disconnection prevention effect include, in addition to polyimide, organic materials such as polyamide, benzocyclobutene, acrylic, and epoxy, and siloxane materials and the like. Further, for the insulating layer 712, instead of the silicon nitride film, a silicon oxynitride film or a silicon oxynitride film may be used. Also, for the manufacturing methods of the insulating layer 712 and the insulating layer 713, plasma C VD method, sputtering method, SOG method, droplet discharge method, screen printing method, or the like can be used .

[0239] Next, a conductive layer 717 is formed on the insulating layer 712, the insulating layer 713, and the conductive layer 731e, and an insulating layer 718 is formed on the conductive layer 717 (see FIG. 12(C)). The conductive layer 717 can be formed of the same material as the conductive layer 731a, the conductive layer 731b, the conductive layer 731c, the conductive layer 731d, and the conductive layer 731e. For example, a laminated structure of 100 nm of titanium, 200 nm of aluminum, and 100 nm of titanium can be adopted. Since the conductive layer 717 is connected to the conductive layer 731e at the opening 714, contact resistance can be suppressed by the contact of titaniums with each other . Also, since the conductive layer 717 is electrically joined to the transistor and the antenna (formed thereby), it is preferable that the wiring resistance is low. Therefore, it is advisable to use a low-resistance material such as aluminum . Since the insulating layer 718 is required to have flatness in its surface shape, it is preferably formed of an organic material . Taking the case of using 2000 nm of polyimide as an example. The insulating layer 718 is formed using, for example, 2000 nm of polyimide. The insulating layer 718 ​An opening 714 in an insulating layer 713 formed to a thickness of 1500 nm and a thin film formed in the opening 714 The surface of the conductive layer 717 formed on the insulating layer 713 must be smoothed to have a uniform thickness. The insulating layer 718 is formed to a thickness of 2000 nm. The thickness of the insulating layer 713 is preferably 1.1 to 2 times or more, and more preferably 1.2 to 1.5 times. If the film thickness is 750 nm or more and 3000 nm or less, it is 900 nm or more and 4500 nm or less. The insulating layer 718 is preferably formed to have a thickness of 1 μm or less. A material with high planarity is preferably used for the insulating layer 718. In addition to polyimides, organic materials such as polyamides, benzocyclobutene, acrylics, and epoxy are also used. When an antenna is formed on the insulating layer 718, the insulating layer 718 is formed of a siloxane material. The flatness of the surface shape of the insulating layer 718 must be taken into consideration.

[0240] Next, an antenna 720 is formed on the insulating layer 718 (see FIG. 13). 20 and the conductive layer 717 are connected through an opening. The opening is provided below the antenna 720. The antenna 720 may be directly connected to the conductive layer 731a. By providing the conductive layer 717 as in this embodiment mode, This is preferable because it allows a margin to be provided in the formation of the opening, and therefore allows for high integration. Therefore, an additional conductive layer may be provided on the conductive layer 717 to connect the antenna 720. That is, the antenna 720 is electrically connected to the conductive layer 731a which constitutes a transistor. A high degree of integration can be achieved by a connection structure via multiple conductive layers. A plurality of conductive layers including the conductive layer 717, etc., are preferably thin because when the film thickness increases, the semiconductor device will also have a thickness. Therefore, compared with the conductive layer 731a, the conductive layer 717, etc. preferably have a smaller film thickness.

[0241] The antenna 720 can adopt a stacked structure of a first conductive layer 721 and a second conductive layer 722. In this embodiment, as an example, the case of a stacked structure with 100 nm of titanium as the first conductive layer 721 and 2000 nm of aluminum as the second conductive layer 722 is illustrated. Titanium used as the first conductive layer 721 can enhance the moisture resistance of the antenna and also enhance the adhesion between the insulating layer 718 and the antenna 720. Furthermore, titanium can reduce the contact resistance with the conductive layer 717. This is because titanium is formed on the uppermost layer of the conductive layer 717, so the same materials of titanium in the antenna are in contact with each other. Such titanium is formed using dry etching, so the end portions are often in a standing state. Aluminum used as the second conductive layer 722 is a low-resistance material, so it is suitable for the antenna. By thickening the aluminum film, the resistance can be made lower. When the resistance of the antenna becomes lower, the communication distance can be extended, which is preferable. Such aluminum is formed using wet etching, so a taper is often attached to the side surface at the end portion. In the taper in this embodiment, a convex portion is formed on the aluminum side, that is, it is formed in a shape concave inward. The protrusion of the titanium end portion beyond the aluminum end portion can prevent the step break of the insulating layer formed thereafter and enhance the resistance of the antenna.

[0242] In addition to titanium and aluminum, the antenna can use materials containing metal elements such as aluminum, chromium, tantalum, titanium, molybdenum, tungsten, silver, copper, gold, platinum, nickel, palladium, etc., alloy materials containing the metal elements, and compound materials containing the metal elements as conductive materials, and can be formed by using sputtering methods, printing methods such as screen printing and gravure printing, droplet ejection methods, dispenser methods, plating methods, etc. In this embodiment, although a laminated structure is exemplified, it may be formed of a single-layer structure of any of the above-described materials.

[0243] An insulating layer 723 is formed to cover the antenna 720. In this embodiment, the insulating layer 723 is formed of a 200-nm silicon nitride film. The insulating layer 723 can further enhance the moisture resistance of the antenna, which is preferable. Since the titanium end of the insulating layer 723 protrudes more than the aluminum end, it can be formed without steps. Such an insulating layer 723 can be formed of a silicon oxynitride film, a silicon nitride oxide film, or other inorganic materials in addition to the silicon nitride film.

[0244] Also, as a peripheral portion of the semiconductor device, a peripheral portion 752 is exemplified. The insulating layer 718 preferably covers the end of the insulating layer 713 outside the antenna in the circuit portion (specifically, the region 740). When covering the insulating layer 713, the insulating layer 718 preferably covers from a position more than twice the outside (distance d) from the sum of the film thickness of the insulating layer 713 and the film thickness of the insulating layer 718. In this embodiment, since the insulating layer 713 is formed to be 1500 nm and the insulating layer 718 is formed to be 2000 nm, the insulating layer 718 covers the end of the insulating layer 713 from the outside at a distance d = 7000 nm from the end of the insulating layer 713. With such a configuration, a process margin can be ensured, and moisture and oxygen can be​​​​​​​​​​​​​​ Invasion can be prevented.

[0245] Further, the insulating layer 723 and the insulating layer 712 are preferably in contact with each other outside the insulating layer 718, that is, outside the antenna in the circuit portion (specifically, in the region 741). In the present embodiment, since both the insulating layers 712 and 723 are formed of a silicon nitride film, the same materials are in close contact with each other, resulting in high adhesion and preventing the intrusion of moisture and oxygen. Further, since the silicon nitride film has higher density than the silicon oxide film, it can effectively prevent the intrusion of moisture and oxygen.

[0246] In the present embodiment, the crack suppression region 753 is formed in the same process as the conductive layers 731a, 731b, 731c, 731d that function as the source electrode or drain electrode of the transistor and the conductive layer 731e that functions as a connection wiring, but is not limited thereto, and can also be formed in the process of forming the antenna 720 or in the same process as the conductive layer 717 that functions as a connection electrode.

[0247] Through the above processes, a semiconductor device 700 including the crack suppression layer shown in FIG. 10(C) and having completed the semiconductor element formation process can be manufactured.

[0248] The present embodiment can be implemented in appropriate combination with the configurations described in other embodiments.

[0249] (Embodiment 4) In the above-described Embodiments 1 to 3, examples of other materials that can be used for the semiconductor layer of the transistor will be described.

[0250] ​​​​​​​​The semiconductor layers of semiconductor elements are made of semiconductor materials such as silane and germanium. Amorphous semiconductors are made by vapor deposition or sputtering using a source gas. and polycrystalline semiconductors obtained by crystallizing the amorphous semiconductors using light energy or thermal energy. The semiconductor layer can be formed by sputtering, LPC, or the like. The film can be formed by the VD method, the plasma CVD method, or the like.

[0251] The microcrystalline semiconductor film is formed by a high-frequency plasma CVD method with a frequency of several tens to several hundreds of MHz, or It can be formed by a microwave plasma CVD device with a frequency of 1 GHz or more. Generally speaking, SiH4, Si2H6, SiH2Cl2, SiHCl3, SiCl4, and SiF 4 can be formed by diluting these silicon compounds with hydrogen. and one or more rare earth elements selected from the group consisting of hydrogen, helium, argon, krypton, and neon. A microcrystalline semiconductor film can be formed by diluting the silicon compound with a gas element. The flow rate ratio of hydrogen to the gas is set to 5 times or more and 200 times or less, preferably 50 times or more and 150 times or less, and Preferably, the concentration is 100 times.

[0252] Representative examples of amorphous semiconductors include hydrogenated amorphous silicon and crystalline semiconductors. A typical example is polysilicon. Polysilicon (polycrystalline silicon) has the following features: The so-called "polysilicon-based" semiconductor is formed at a process temperature of 800°C or higher. The main materials are high-temperature polysilicon and polysilicon formed at process temperatures below 600°C. The so-called low-temperature polysilicon is used as a material for the crystallization of amorphous silicon. It contains polysilicon obtained by crystallizing con. Of course, as described above, microcrystals It is also possible to use a semiconductor containing a crystal phase in part of the semiconductor or semiconductor layer.

[0253] When a crystalline semiconductor film is used for the semiconductor layer, the method for producing the crystalline semiconductor film can be various methods (laser crystallization method, thermal crystallization method, or thermal crystallization method using an element that promotes crystallization such as nickel, etc.). Also, a microcrystalline semiconductor that is SAS (Semi Amorphous Se miconductor) can be crystallized by laser irradiation to increase its crystallinity. When an element that promotes crystallization is not introduced, before irradiating the amorphous silicon film with laser light, the amorphous silicon film is heated at 500 °C for 1 hour in a nitrogen atmosphere to reduce the hydrogen concentration contained in the amorphous silicon film to 1×10 atoms / cm or less. This is because when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light, the amorphous silicon film will be destroyed. 20 atoms / cm 3 This is because when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light, the amorphous silicon film will be destroyed. This is because when the amorphous silicon film containing a large amount of hydrogen is irradiated with laser light, the amorphous silicon film will be destroyed. There is.

[0254] As a method for introducing a metal element into the amorphous semiconductor layer, there is no particular limitation as long as it is a method that can cause the metal element to exist on the surface or inside of the amorphous semiconductor film. For example, sputtering method, CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals CVD method, plasma treatment method (including plasma CVD method), adsorption method, and a method of applying a solution of a metal salt can be used. Among these, the method using a solution is simple and useful in that it is easy to adjust the concentration of the metal element. Also, at this time, in order to improve the wettability of the surface of the amorphous semiconductor film and allow the aqueous solution to spread over the entire surface of the amorphous semiconductor film, irradiation with UV light in an oxygen atmosphere, thermal oxidation method, treatment with ozone water or hydrogen peroxide containing hydroxyl radicals It is desirable to form an oxide film by, etc.

[0255] Also, in the crystallization step of crystallizing an amorphous semiconductor film to form a crystalline semiconductor film, an element that promotes crystallization (also referred to as a catalyst element or a metal element) is added to the amorphous semiconductor film, and crystallization may be performed by heat treatment (at 550 °C to 750 °C for 3 minutes to 24 hours). As the element that promotes (facilitates) crystallization, one or more selected from iron (Fe), nickel (Ni), cobalt (Co), ruthenium (Ru), rhodium (Rh), palladium (Pd), osmium (Os), iridium (Ir), platinum (Pt), copper (Cu), and gold (Au) can be used.

[0256]

[0257] To remove or reduce the element that promotes crystallization from the crystalline semiconductor film, a semiconductor film containing an impurity element is formed in contact with the crystalline semiconductor film to function as a gettering sink. As the impurity element, an impurity element that imparts an n-type, an impurity element that imparts a p-type, a noble gas element, etc. can be used. For example, one or more selected from phosphorus (P), nitrogen (N), arsenic (As), antimony (Sb), bismuth (Bi), boron (B), helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) can be used. A semiconductor film containing a noble gas element is formed on the crystalline semiconductor film containing the element that promotes crystallization, and heat treatment (at 550 °C to 750 °C for 3 minutes to 24 hours) is performed. The element that promotes crystallization contained in the crystalline semiconductor film moves into the semiconductor film containing the noble gas element, and the element that promotes crystallization in the crystalline semiconductor film is removed or reduced. Thereafter, the semiconductor film containing the noble gas element that has become a gettering sink is removed.

[0257] The crystallization of the amorphous semiconductor film may combine heat treatment and crystallization by laser light irradiation. Moreover, heat treatment or laser light irradiation may be performed alone or multiple times.

[0258] Also, the crystalline semiconductor film may be directly formed on the substrate by a plasma method. Further, a crystalline semiconductor film may be selectively formed on the substrate using the plasma method.

[0259] This embodiment can be implemented in appropriate combination with the configurations described in other embodiments. It is.

Explanation of Reference Numerals

[0260] 100 Substrate 101 Release layer 102 Terminal 103 Gate electrode layer 104 Conductive layer 105 Capacitor wiring layer 106 Gate electrode layer 107 Gate insulating layer 108 Oxide semiconductor layer 109a Contact hole 109b Contact hole 110a Resist mask 110b Resist mask 110c Resist mask 111 Insulating layer 112 Resist mask 113 Resist mask 114 Oxide semiconductor layer 115 Oxide semiconductor layer 116 Oxide semiconductor layer 117 Oxide semiconductor layer 118a Resist mask 118b Resist mask 118c Resist mask 118d Resist mask 118e Resist mask 118f Resist mask 118g resist mask 118h resist mask 118i resist mask 119a source electrode layer 119b drain electrode layer 120a source electrode layer 120b drain electrode layer 121 capacitor electrode layer 122 connection electrode 123 terminal 124 crack suppression layer 125 insulating layer 126 channel formation region 127a high-resistance source region 127b high-resistance drain region 128 channel formation region 129a high-resistance source region 129b high-resistance drain region 132 protective insulating layer 133 transistor 134 transistor 135 capacitor 136 color filter layer 137 overcoat layer 138 protective insulating layer 139 contact hole 140 contact hole 141 contact hole 142 terminal electrode 143 electrode layer 144 terminal electrode 145 partition wall 150a resist mask 150b resist mask 150c resist mask 150d resist mask 150e resist mask 150f resist mask 150g resist mask 151 crack suppression layer 193 EL layer 194 electrode layer 200 Semiconductor device 201 Drive circuit section 202 Pixel circuit section 203 Semiconductor element 205 Crack suppression region 300 Layer to be peeled off 301 Adhesive layer 302 Substrate 400 Semiconductor device 700 Semiconductor device 701 Substrate 702 Release layer 703 Insulating layer 704 Semiconductor layer 704a Semiconductor layer 704b Semiconductor layer 705 Gate insulating layer 706a Channel formation region 706b Impurity region 706c Impurity region 707 Gate electrode layer 708 Insulating layer 709 Insulating layer 710 Insulating layer 711 Insulating layer 712 Insulating layer 713 Insulating layer 714 Opening 715 Region 717 Conductive layer 718 Insulating layer 720 Antenna 721 Conductive layer 722 Conductive layer 723 Insulating layer 730a Transistor 730b Transistor 731a Conductive layer 731b Conductive layer 731c Conductive layer 731d Conductive layer 731e Conductive layer 740 Region 741 Region 749 Element layer 750 Crack suppression layer 751 Integrated circuit 752 Peripheral part 753 Crack suppression region 1100 Substrate 1101 Resin layer 1200 Substrate 1201 Resin layer

Claims

【Claim 1】 A display device having a pixel circuit portion, a driving circuit portion, and a conductive layer provided outside the pixel circuit portion and the driving circuit portion, in a plan view, the conductive layer has a shape surrounding the pixel circuit portion and the driving circuit portion, the driving circuit portion has an electrode used for connection with an FPC, the conductive layer does not overlap with the semiconductor layer, the display device in which the conductive layer does not overlap with the electrode used for connection with the FPC.

Images