Semiconductor device

Abstract

To provide a semiconductor device having a structure capable of suppressing warpage of a wafer while configuring a semiconductor layer constituting a deep layer by an ion implantation layer.SOLUTION: A p-type deep layer 5, a p-type deep layer 30, and a p-type guard ring 21 are formed by an ion implantation. Then, not only the p-type deep layer 5 and the p-type guard ring 21 but also the p-type deep layer 30 is linearly configured. In this way, linearly configuring the p-type deep layer 30 makes a total value TV of occupancy of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in a chip 40% or lower. This makes it possible to suppress warpage of a wafer while configuring the p-type deep layer 30 by the ion implantation.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and is particularly suitable for application to a silicon carbide (hereinafter referred to as SiC) semiconductor device.

Background Art

[0002] Conventionally, in order to reduce the on-resistance of a semiconductor switching element such as a MOSFET by adopting a trench gate structure, it is necessary to relieve the electric field at the bottom of the trench in the trench gate structure in order to suppress the application of a high electric field to the gate insulating film. For this reason, for example, in Patent Document 1, in order to relieve the electric field at the bottom of the trench, deep deep layers are formed on both sides of the trench gate structure by high-acceleration ion implantation. Due to this deep deep layer, the rise of the equipotential line is suppressed, and the electric field at the bottom of the trench is relieved, thereby suppressing the application of a high electric field to the gate insulating film. In addition, an outer peripheral region surrounding the cell region is provided with a guard ring portion, and a deep layer is provided over the entire area of the connecting portion located between the cell region and the guard ring portion. As a result, the equipotential line extends from the cell region to the connecting portion and further to the guard ring portion and is terminated at the guard ring portion, so that a high breakdown voltage can be achieved.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when forming a deep deep layer by high-acceleration ion implantation as in Patent Document 1, warping of the wafer depending on the dose amount and acceleration occurs during the process, causing problems associated with wafer warping such as conveyance errors, substrate adsorption errors, and reduction in photoresolution.

[0005] On the other hand, when ion implantation is performed, the wafer warp can be mitigated by performing activation annealing or the like each time. However, stacking defects occur in the ion implantation region along with the mitigation process, leading to an increase in drain leakage, an increase in the number of processes, that is, an increase in manufacturing cost.

[0006] In addition, as a countermeasure against the wafer warp, there are also measures such as ion implantation on the back surface of the wafer. However, an increase in the number of processes and unexpected particle adhesion due to surface adsorption occur, resulting in a decrease in yield due to pattern collapse.

[0007] Furthermore, a deep layer can be formed by embedding a p-type epitaxial layer in the trench, but it is difficult to control the concentration of the deep layer and perform planarization processing on the surface.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device having a structure capable of suppressing wafer warp while configuring a semiconductor layer constituting a deep layer with an ion implantation layer.

Means for Solving the Problems

[0009] To achieve the above object, the invention according to claim 1 is a semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed in a chip (Ch), a guard ring portion (RG) surrounding the outer periphery of the cell region, and an outer peripheral region (RO) including a connecting portion (RJ) located between the guard ring portion and the cell region, comprising a substrate (1, 101) of a first or second conductivity type, and a first conductivity type drift layer (2, 50, 60, 102) formed on the surface side of the substrate having a front surface and a back surface and having a lower impurity concentration than the substrate. In the cell region, there are provided a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, and a second electrode (11, 107) formed on the back surface side of the substrate, and a vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided. The connecting portion is also provided with a second conductivity type layer (31, 33 - 35, 71) formed in a line shape in the drift layer. Further, the guard ring portion or the guard ring portion and the connecting portion are provided with a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constitutes a guard ring (21, 104). The second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less.

[0010] Thus, the second conductivity type layer and the second conductivity type ring are formed by ion implantation. Not only the second conductivity type layer in the cell region and the second conductivity type ring in the guard ring portion, but also the second conductivity type layer in the connecting portion is configured in a line shape. By configuring the second conductivity type layer in the connecting portion in a line shape in this way, the total value of the occupation ratio of the second conductivity type layer and the second conductivity type ring in the chip is made 40% or less. Thereby, while configuring the semiconductor layer constituting the second conductivity type layer in the connecting portion, that is, the deep layer, by ion implantation, it becomes possible to suppress wafer warping.

[0011] Specifically, in the invention according to claim 1, the second conductivity type layer provided in the connecting portion includes a linear portion (31) having the same longitudinal direction as that of the second conductivity type layer provided in the cell region, The second conductivity type ring is disposed in the guard ring portion and the connecting portion, A mesa portion (RM) is formed in which the cell region and the connecting portion protrude more than the guard ring portion, In the guard ring, the distance (DA3, DB3) between the guard rings increases from the inner peripheral side to the outer peripheral side, Taking the distance between the guard rings as the third distance (DA3, DB3), The relationship is such that the distance (DA3out, DB3out) of the widest portion located on the outermost periphery among the third distances > the distance (DA3in, DB3in) of the portion located within a predetermined range from the boundary position of the mesa portion among the third distances.

[0012] By setting the third distance in this way, the total value of the occupation ratios of the second conductivity type layer and the second conductivity type ring in the chip is 40% or less.

[0013] Note that the reference numerals in parentheses for each of the above means indicate an example of the correspondence relationship with the specific means described in the embodiments described later.

Brief Description of the Drawings

[0014]

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Mode for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other are denoted by the same reference numerals for description.

[0016] (First Embodiment) The first embodiment will be described. Here, a SiC semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed as a semiconductor element will be described as an example.

[0017] FIG. 1 shows the top layout of a chip CH of a SiC semiconductor device in which a MOSFET 100 having a trench gate structure is formed. The SiC semiconductor device shown in FIG. 1 has a configuration including a cell region RC in which the MOSFET 100 is formed and an outer peripheral region RO surrounding the cell region RC. The outer peripheral region RO has a guard ring portion RG and a connecting portion RJ disposed inside the guard ring portion RG, that is, between the cell region RC and the guard ring portion RG. Although FIG. 1 is not a cross-sectional view, hatching is partially shown for easy viewing of the figure.

[0018] As shown in FIG. 2, the SiC semiconductor device is formed using an n + -type substrate 1 made of SiC. On the main surface of the n + -type substrate 1, an n -The n-type layer 2 and the p-type base region 3 are formed by epitaxial growth or the like. Further, an n + -type source region 4 is formed in the surface layer portion of the p-type base region 3.

[0019] The n + -type substrate 1 has, for example, an n-type impurity concentration of 1.0×10 19 / cm 3 , a surface of (0001)Si plane, and is an off-substrate with an off-direction of <11-20> direction. The n - -type layer 2 has a lower impurity concentration than the n + -type substrate 1, and has, for example, an n-type impurity concentration of 5.0×10 15 ~2.0×10 16 / cm 3 . In the case of this embodiment, this n - -type layer 2 constitutes a drift layer.

[0020] Further, the p-type base region 3 is a portion where a channel region is formed, and has a p-type impurity concentration of, for example, 2.0×10 17 / cm 3 and a thickness of 300 nm. In the surface layer portion of the p-type base region 3, that is, in the place sandwiched by the n + -type source regions 4 of adjacent cells in the MOSFET 100, a p-type contact region 3a and a p-type hole extraction layer 3b with a high concentration of p-type impurities are partially formed. The n + -type source region 4 has a higher impurity concentration than the n - -type layer 2, and has an n-type impurity concentration in the surface layer portion of, for example, 2.5×10 18 ~1.0×10 19 / cm 3 and a thickness of about 0.5 μm.

[0021] In the cell region RC, the p-type base region 3 and the n + -type source region 4 are left on the surface side of the n + -type substrate 1. In the connection portion RJ, the p-type base region 3 including the p-type hole extraction layer 3b is left on the surface side of the n + -type substrate 1. Further, in the guard ring portion RG, it penetrates the p-type base region 3 and n- A recess 20 is formed so as to reach the type layer 2. With such a structure, a mesa portion RM in which the cell region RC and the connecting portion RJ protrude more than the guard ring portion RG is formed. Note that the portion surrounded by the broken line in FIG. 1 indicates the mesa portion RM, and the portion with the broken line hatching inside thereof is the connecting portion RJ.

[0022] Also, in the cell region RC, n - A p-type deep layer 5 having a p-type impurity concentration higher than that of the p-type base region 3 is formed in the surface layer portion of the n-type layer 2. The p-type deep layer 5 constitutes at least a part of the second conductivity type layer. The p-type deep layer 5 is - formed from a position at a predetermined depth of the n-type layer 2 to the surface, and is formed by ion-implanting p-type impurities into the n-type layer 2. -

[0023] The p-type deep layer 5 has a plurality of straight portions 5a arranged at equal intervals in the n-type layer 2, and as shown in FIG. 1, has straight portions 5a arranged in a stripe shape separated from each other without intersections. Further, in the case of the present embodiment, the p-type deep layer 5 also has an intersection portion 5b extending in a direction intersecting the straight portion 5a, and the intersection portions 5b are arranged at both ends of each straight portion 5a so that the two are connected. In other words, the p-type deep layer 5 forms a rectangular shape surrounding the outer periphery of the cell region RC by the outermost portion among the plurality of straight portions 5a and the intersection portion 5b, and inside thereof, the remaining straight portions 5a are arranged in a plurality of stripes. The above-described p-type base region 3 and n - type source region 4 are formed on the p-type deep layer 5. +

[0024] In the present embodiment, the p-type deep layer 5 is formed with the same impurity concentration, the same width, and the same depth. For example, the p-type impurity concentration is 1.0×10 17 ~1.0×10 19 / cm 3, it is configured with a width of 0.4 to 1.0 μm and a depth of about 2.0 μm. Also, the interval DA1 between the linear portions 5a of the p-type deep layer 5 is set to 0.6 to 1.5 μm. And at the intersection 5b of the p-type deep layer 5, the linear portion 31 of the p-type deep layer 30 of the connecting portion RJ described later is connected.

[0025] The extending direction of the p-type deep layer 5 is arbitrary, but in this embodiment, it is the <11-20> direction same as the off direction.

[0026] Note that the intersection 5b of the p-type deep layer 5 is not essential, and the linear portions 5a of the p-type deep layer 5 and the p-type deep layer 30 of the connecting portion RJ do not have to be connected. Here, the interval DA1 between the linear portions 5a of the p-type deep layer 5 is made different from the interval DA2 of the linear portion 31 of the p-type deep layer 30, but the interval DA1 and the interval DA2 may be the same, and a structure may be adopted in which each linear portion 5a and each linear portion 31 are connected.

[0027] Also, the p-type base region 3 and n + type source region 4 penetrate through to reach the n - type layer 2, and a plurality of gate trenches 6 with a width of 0.8 μm and a depth of 1.0 μm, for example, are formed so as to be shallower than the p-type deep layer 5. The above-described p-type base region 3 and n + type source region 4 are arranged so as to be in contact with the side surfaces of each of the plurality of gate trenches 6. Each gate trench 6 is formed in a linear layout with the horizontal direction of the paper of FIG. 2 as the width direction, the vertical direction of the paper as the longitudinal direction, and the up-down direction of the paper as the depth direction. Also, as shown in FIG. 1, the plurality of gate trenches 6 are arranged so as to be sandwiched between the linear portions 5a of the p-type deep layer 5, and are formed in a stripe shape by being arranged in parallel at equal intervals.

[0028] Furthermore, the portion of the p-type base region 3 located on the side surface of the gate trench 6 is n + type source region 4 and n -As a channel region connecting to the p-type layer 2, a gate insulating film 7 is formed on the inner wall surface of the gate trench 6 including the channel region. A gate electrode 8 made of doped Poly-Si is formed on the surface of the gate insulating film 7, and the gate trench 6 is filled with these gate insulating film 7 and gate electrode 8. Thereby, a trench gate structure with one direction as the longitudinal direction is formed. The above-described p-type deep layer 5 is formed on both sides of this trench gate structure along the same direction as the longitudinal direction of the trench gate structure. In FIG. 1, for ease of viewing, the number of trench gate structures and p-type deep layers 5 is reduced, but actually, many similar structures are arranged.

[0029] Also, an n + type substrate 1 with an n - type layer 2 sandwiched therebetween, specifically, on the opposite side of the n + type source region 4, p-type base region 3, and the surface of the gate electrode 8, a source electrode 9 corresponding to the first electrode and a gate wiring layer (not shown) are formed via an interlayer insulating film 10. The source electrode 9 and the gate wiring layer are composed of a plurality of metals, for example, Ni / Al, etc. And among the plurality of metals, at least the part in contact with the n-type SiC, specifically, the n + type source region 4 is composed of a metal capable of ohmic contact with n-type SiC. Also, among the plurality of metals, at least the part in contact with the p-type SiC, specifically, the p-type contact region 3a and the p-type hole extraction layer 3b is composed of a metal capable of ohmic contact with p-type SiC. Note that these source electrode 9 and gate wiring layer are electrically insulated by being separated on the interlayer insulating film 10. And through the contact hole formed in the interlayer insulating film 10, the source electrode 9 is electrically contacted with the n + type source region 4 and the p-type contact region 3a, etc., and the gate wiring layer is electrically contacted with the gate electrode 8.

[0030] Furthermore, on the back side of the n + type substrate 1, there is an n +A drain electrode 11 corresponding to a second electrode electrically connected to the type substrate 1 is formed. With such a structure, an MOSFET 100 having an n-channel type inverted trench gate structure is configured. And a cell region RC is configured by arranging a plurality of such MOSFETs 100.

[0031] On the other hand, in the guard ring portion RG, as described above, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the n - type layer 2. Therefore, at a position away from the cell region RC, the n + type source region 4 and the p-type base region 3 are removed, and the n - type layer 2 is exposed. And in the thickness direction of the n + type substrate 1, a cell region RC and a part of the connecting portion RJ located inside the recess 20 are formed into a mesa portion RM protruding in an island shape.

[0032] Also, on the surface layer portion of the n - type layer 2 located below the recess 20, a plurality of p-type guard rings 21 are provided so as to surround the cell region RC and the connecting portion RJ. The p-type guard ring 21 constitutes at least a part of the second conductivity type ring. In the case of this embodiment, as shown in FIG. 1, the p-type guard ring 21 is formed in a rectangular shape with rounded corners, but it may be formed in other frame shapes such as a circular shape. The p-type guard ring 21 is formed from the surface of the n - type layer 2 to a position at a predetermined depth, but it may be formed away from the surface of the n - type layer 2. The p-type guard ring 21 is formed by ion implanting p-type impurities into the n - type layer 2.

[0033] In this embodiment, the p-type guard ring 21 has the same configuration as the above-described p-type deep layer 5. The p-type guard ring 21 is different from the linearly formed p-type deep layer 5 in that the upper surface shape is a line shape in a frame shape surrounding the cell region RC and the connection part RJ, but the others are the same. That is, the p-type guard ring 21 has the same impurity concentration and the same width as the p-type deep layer 5. Regarding the interval DA3 between the p-type guard rings 21, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, the interval DA3 of the p-type guard ring 21 is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DA3in of the portion of the interval DA3 of the p-type guard ring 21 located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DA1 of the linear portion 5a of the p-type deep layer 5 and the interval DA2 of the linear portion 31 of the p-type deep layer 30 described later. Also, the widest portion located at the outermost periphery of the interval DA3, that is, the interval DA3out between the outermost p-type guard ring 21 and the one inside it is made wider than the interval DA1 and the interval DA2.

[0034] Although not shown in the figure, if necessary, an EQR structure is provided on the outer periphery of the p-type guard ring 21, so that a guard ring portion RG having an outer peripheral breakdown voltage structure surrounding the cell region RC is configured.

[0035] Furthermore, the connection part RJ is provided between the cell region RC and the guard ring part RG. In the connection part RJ, a p-type deep layer 30 is formed in the surface layer portion of the n - type layer 2. The p-type deep layer 30 is brought into contact with the p-type base region 3 and is fixed to the source potential. In the case of this embodiment, as shown by the broken line hatching in FIG. 1, the connection part RJ is formed so as to surround the cell region RC, and further, a plurality of p-type guard rings 21 having a square shape with rounded corners are formed so as to surround the outside of the connection part RJ.

[0036] The p-type deep layer 30 is configured to have a linear portion 31 arranged in a stripe shape with a plurality of them arranged in parallel to the p-type deep layer 5 formed in the cell region RC, and a frame portion 32 formed by arranging one or a plurality of them so as to surround the p-type deep layer 5 and the linear portion 31. The linear portion 31 of the p-type deep layer 30 constitutes a part of the second conductivity type layer, and the frame portion 32 constitutes a part of the second conductivity type ring.

[0037] The linear portion 31 is formed in the region between the cell region RC and the frame portion 32. In this region, if a p-type layer is not formed in the n - type layer 2, a place where equipotential lines rise excessively will occur, so it is formed so that such a place does not occur. In the direction perpendicular to the longitudinal direction of the linear portion 5a of the p-type deep layer 5, a plurality of linear portions 31 are arranged in parallel to the linear portion 5a between the cell region RC and the frame portion 32. Also, in the longitudinal direction of the linear portion 5a, a plurality of linear portions 31 are extended and formed in the same direction as the linear portion 5a between the cell region RC and the frame portion 32. And the tip of each linear portion 5a is connected to the intersection portion 5b of the p-type deep layer 5 or the portion located on the innermost peripheral side of the frame portion 32. In this way, the linear portion 31 is arranged between the cell region RC and the frame portion 32. The tip of the linear portion 31 may be separated without being connected to the intersection portion 5b or the frame portion 32, but in that case, it is preferable that the distance between them is the same as or smaller than the interval DA1 between the linear portions 5a of the p-type deep layer 5.

[0038] The frame portion 32 is in a rectangular shape with rounded corners and surrounds the cell region RC and the periphery of the linear portion 31. Specifically, the frame portion 32 is arranged concentrically with the p-type guard ring 21. In this embodiment, a plurality of frame portions 32 are provided.

[0039] Each p-type deep layer 30 constituted by these linear portions 31 and the frame portion 32 is formed by ion implantation from the surface of the n - type layer 2 to a position at a predetermined depth below the p-type base region 3.

[0040] In the case of this embodiment, the width of the linear portion 31 in the p-type deep layer 30 is set to 0.4 to 1.0 μm, which is the same as the width of the p-type deep layer 5. The interval DA2 between the linear portions 31 may be the same as the interval DA1 between the linear portions 5a of the p-type deep layer 5, but here it is made narrower than the interval DA1.

[0041] The frame-shaped portion 32 is formed from the inner peripheral side to the outer peripheral side of the mesa portion RM and has the same width as the p-type deep layer 5. Also, the intervals DA4 of the frame-shaped portion 32 may all have the same width or may be different. Preferably, the interval DA4 of the frame-shaped portion 32 is set to be equal to or less than the interval DA1 between the linear portions 5a of the p-type deep layer 5 in the cell region RC. More preferably, the interval DA4out of the portion of the interval DA4 of the frame-shaped portion 32 located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DA2 between the linear portions 31 in the p-type deep layer 30.

[0042] Here, the interval DA3in between the p-type guard rings 21 located within a predetermined range from the boundary position of the mesa portion RM and the interval DA4out of the frame-shaped portion 32 are made narrower than the interval DA2 between the linear portions 31 in the p-type deep layer 30. This is to cope with mask misalignment when forming the concave portion 20 for forming the mesa portion RM.

[0043] When mask misalignment occurs, the formation position of the inner peripheral end of the recess 20 is shifted. For example, in the structure of FIG. 1, it is assumed that mask misalignment occurs and the formation position of the inner peripheral end of the recess 20 is shifted to the right side of the paper surface. In this case, a part of the frame-shaped portion 32 is formed in the recess 20 outside the mesa portion RM on the left side of the paper surface, and a part of the p-type guard ring 21 is formed not in the recess 20 but in the mesa portion RM on the right side of the paper surface. With such a structure, since a part of the frame-shaped portion 32 has the same structure as the guard ring, it is preferable that the width and interval are the same as those on the inner peripheral side of the p-type guard ring 21. Therefore, as in the present embodiment, for the portion located within a predetermined range from the boundary position of the mesa portion RM, the interval DA4out of the frame-shaped portion 32 and the interval DA3in of the p-type guard ring 21 are made narrower than the interval DA1. Preferably, the frame-shaped portion 32 and the p-type guard ring 21 have the same width and interval. By doing so, it is possible to cope with mask misalignment.

[0044] Here, the frame-shaped portion 32 has been described separately from the p-type guard ring 21, but it can be said that the frame-shaped portion 32 and the p-type guard ring 21 constitute a plurality of concentric frame-shaped p-type rings. That is, it can be said that the portion of the p-type ring arranged on the inner peripheral side of the recess 20 constitutes the frame-shaped portion 32, and the portion formed in the recess 20 constitutes the p-type guard ring 21.

[0045] Also, in the connection part RJ, the p-type base region 3 is formed. And on the p-type base region 3, a p-type hole extraction layer 3b is formed. The source electrode 9 is formed up to the top of the p-type hole extraction layer 3b, and the p-type base region 3 and the p-type deep layer 30 are connected through the p-type hole extraction layer 3b. The p-type hole extraction layer 3b is formed so as to surround the cell region RC in the connection part RJ. Here, the p-type hole extraction layer 3b is formed so as to surround the entire circumference of the cell region RC once, but it may be formed by dividing it into a plurality of parts and arranging them at equal intervals around the entire circumference. By providing this p-type hole extraction layer 3b, when avalanche breakdown occurs in the cell region RC, or when avalanche breakdown occurs in the guard ring part RG or the connection part RJ, holes generated in the outer peripheral region can be extracted to the source electrode 9. Therefore, the flow of holes into the cell region RC side can be restricted, and element breakdown can be suppressed.

[0046] Also, an interlayer insulating film 10 is formed on the surface of the p-type hole extraction layer 3b. Although not shown, the gate pad connected to the gate wiring layer is formed at a location different from the location where the source electrode 9 is disposed in the interlayer insulating film 10 in the connection part RJ.

[0047] With the above structure, the SiC semiconductor device according to this embodiment is configured. When the SiC semiconductor device configured in this way turns on the MOSFET 100, a channel region is formed on the surface portion of the p-type base region 3 located on the side surface of the gate trench 6 by controlling the voltage applied to the gate electrode 8. Thereby, a current flows between the source electrode 9 and the drain electrode 11 through the n + -type source region 4, the channel region, and the n - -type layer 2.

[0048] Also, when the MOSFET 100 is off, even if a high voltage is applied, the p-type deep layer 5 and the p-type deep layer 30 formed to a position deeper than the trench gate structure suppress the intrusion of the electric field to the bottom of the gate trench. Therefore, the electric field concentration at the bottom of the gate trench is alleviated. Thereby, the breakdown of the gate insulating film 7 is prevented.

[0049] Furthermore, at the connection portion RJ, the rise of the equipotential line is suppressed, and the equipotential line is directed toward the guard ring portion RG. Then, in the guard ring portion RG, the equipotential line is gradually terminated in the outer peripheral direction by the p-type guard ring 21, and a desired breakdown voltage can be obtained also in the guard ring portion RG.

[0050] Here, regarding the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, the widths and intervals DA1 to DA4 of each part are as described above. Thereby, the ratio of the p-type layer deeply implanted by ion implantation to the entire area of the chip constituting the SiC semiconductor device, that is, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21, is made 40% or less.

[0051] When the p-type layer is formed by ion implantation, warpage occurs in the wafer for forming the SiC semiconductor device depending on the dose amount and acceleration during the process, so problems associated with wafer warpage such as transfer errors, substrate adsorption errors, and reduction in photo resolution occur.

[0052] Therefore, while achieving the effect of suppressing the intrusion of the electric field to the bottom of the gate trench and the effect of obtaining a desired breakdown voltage in the guard ring portion RG, it is required to minimize the wafer warpage.

[0053] Specifically, the relationship between the acceleration voltage of ion implantation and the wafer warp is shown as in FIG. 3. Also, the relationship between the integrated dose amount of ion implantation and the wafer warp is shown as in FIG. 4. Regarding the relationship between the acceleration voltage of ion implantation and the warp of the wafer, when using a 350-μm thick substrate, forming a p-type layer with the same depth as the p-type deep layer 5 using Al as a p-type impurity, and performing ion implantation on the front surface side and the back surface side of the SiC substrate respectively, the dose amount at this time was made constant at 8×10 14 cm -2 . Also, regarding the relationship between the dose amount of ion implantation and the wafer warp, with a constant acceleration voltage of 150 keV, forming a p-type layer with the same depth as the p-type deep layer 5 on the surface of the SiC substrate using Al as a p-type impurity, the height difference between the outer edge part and the center part of the substrate was measured as the warp amount.

[0054] As can be seen from FIG. 3, the wafer warp is proportional to the acceleration voltage of ion implantation, and the larger the acceleration voltage, the larger the wafer warp. Also, as can be seen from FIG. 4, the wafer warp is also proportional to the dose amount of ion implantation, and the larger the dose amount, the larger the wafer warp.

[0055] Therefore, if the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are to be formed to a deep position with a high acceleration voltage, it is required to reduce the dose amount during ion implantation. To achieve this, it is not preferable to have a structure with deep layers throughout the joint part as in Patent Document 1, and it is necessary to limit the formation ranges of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 as in this embodiment.

[0056] Therefore, in the present embodiment, the p-type deep layer 30 formed in the connection portion RJ is configured by a linear straight portion 31 and a frame portion 32, and is not formed over the entire area of the connection portion RJ. However, when the p-type deep layer 30 is not formed over the entire area of the connection portion RJ, if the interval DA2 between the linear portions 31 is wide, as shown in FIG. 5A, the equipotential lines will bulge, which may reduce the breakdown voltage. Specifically, when the p-type layers are arranged in stripes and the relationship between the interval DA2 and the breakdown voltage is examined, the results are shown in FIG. 5B. It is confirmed that in order to obtain a breakdown voltage with an interval DA2 of about 1800 [V], the interval DA2 is preferably 1.5 μm or less. For this reason, the interval DA2 between the linear portions 31 in the p-type deep layer 30 is set to 1.5 μm or less.

[0057] On the other hand, from the perspective of the breakdown voltage, it is sufficient if the interval DA2 is 1.5 μm or less. However, if the interval DA2 is too narrow, the remaining width of the photomask used when ion-implanting the p-type deep layer 30 will be narrow, and there is a possibility that patterning cannot be performed well. For this reason, the interval DA2 is set to 0.6 μm or more.

[0058] Here, the interval DA2 between the linear portions 31 in the p-type deep layer 30 has been described. The same applies to the interval DA1 between the p-type deep layers 5 in the cell region RC. It is preferable that the interval DA1 is 0.6 to 1.5 μm. Also, it is preferable that the intervals DA3in and DA4out are also 0.6 to 1.5 μm, and it is more preferable to make them smaller than the intervals DA1 and DA2 so as to cope with mask misalignment.

[0059] Also, the closer the intervals DA1 and DA2 are, the higher the withstand voltage can be improved. However, accordingly, the formation ratios of the p-type deep layer 5 and the p-type deep layer 30 increase, and the dose amount during ion implantation increases. Therefore, while reducing the intervals DA1 and DA2, it is necessary to ensure that the dose amount during ion implantation does not become excessive. Furthermore, not only the intervals DA1 and DA2 but also the widths of the p-type deep layer 5 and the p-type deep layer 30 affect the dose amount of ion implantation. And since the widths of the p-type deep layer 5 and the p-type deep layer 30 are factors contributing to a decrease in withstand voltage and an increase in the feedback capacitance Crss, it is necessary to set the dose amount of ion implantation so that the feedback capacitance Crss can be suppressed while ensuring the withstand voltage and the wafer warpage can be suppressed.

[0060] FIG. 6A shows the change in the electric field strength applied near the bottom of the gate trench 6 when the width of the linear portion 31 in the p-type deep layer 5 is changed in the cell region RC. The same result was obtained when the interval between the linear portions 31 was widened while keeping the width of the linear portion 31 constant. Although the electric field in the cell region RC is shown here, the same applies to the connecting portion RJ. As shown in this figure, when the widths of the p-type deep layer 5 and the p-type deep layer 30 become narrow, equipotential lines tend to enter the p-type deep layer 5 and the p-type deep layer 30 in the same manner as described above. For this reason, the rise of the equipotential lines between the p-type deep layer 5 and the p-type deep layer 30 becomes large, leading to a decrease in withstand voltage. In particular, in the cell region RC, a high electric field is applied to the bottom of the gate trench 6, and the gate insulating film 7 may be broken down.

[0061] FIG. 6B shows the change in the feedback capacitance Crss when the interval between the linear portions 31 in the p-type deep layer 30 is kept constant and the width of the linear portion 31 is changed. Specifically, with the measured value n = 3, the width of the linear portion 31 was changed, and the feedback capacitance Crss when 450 [V] was applied to the drain side was measured, and the result of curve fitting the average value is shown. The same result was obtained when the interval between the linear portions 31 was widened while keeping the width of the linear portion 31 constant.

[0062] When the reverse recovery capacitance Crss increases, the switching loss increases, so it is necessary to limit the width of the p-type deep layer 30 to a certain extent. When the width of the p-type deep layer 30 is narrow, a depletion layer is generated at the PN junction between the p-type deep layer 30 and the n - type layer 2, and equipotential lines enter the p-type deep layer 30. Therefore, if the width of the p-type deep layer 30 is too narrow, the reverse recovery capacitance Crss will be further increased.

[0063] Considering the switching loss, it is preferable that the reverse recovery capacitance Crss is 60 [pF] or less, and considering the breakdown voltage, it is preferable that the electric field strength applied between the p-type deep layer 5 and the p-type deep layer 30 is 4 [MV / cm] or less. In order to satisfy these conditions, in the present embodiment, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 μm or more.

[0064] Also, for the p-type deep layer 5 and the p-type deep layer 30, the above conditions can be satisfied if the width is increased. However, when the width exceeds a certain level, even if the width is increased, the effect of suppressing the reverse recovery capacitance Crss and ensuring the breakdown voltage does not improve much. On the contrary, increasing the width of the p-type deep layer 5 and the p-type deep layer 30 means that the dose amount of ion implantation of p-type impurities increases accordingly, which affects the wafer warpage. Therefore, it is better to limit the widths of the p-type deep layer 5 and the p-type deep layer 30 to 1.5 μm or less, preferably 1.0 μm or less, at which the effect of suppressing the reverse recovery capacitance Crss and ensuring the breakdown voltage almost levels off.

[0065] When the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 to 1.5 μm, it is necessary to set the intervals between the p-type deep layer 5 and the p-type deep layer 30 so that the dose amount during ion implantation can suppress the wafer warpage to a predetermined value or less. For this reason, based on the results shown in Fig. 4, the intervals DA1 and DA2 are set to 0.6 to 1.5 μm. As described above, the interval DA1 and the interval DA2 can be made the same. However, unlike the interval DA1 where the trench gate structure is sandwiched, since the trench gate structure is not sandwiched in the interval DA2, it is more preferable to make it smaller than the interval DA1.

[0066] Here, the intervals DA1 and DA2 have been described. However, the same can be said for the intervals DA4, DA4out of the frame-shaped portion 32 and the interval DA3in of the portion located within a predetermined range from the boundary position of the mesa portion RM of the p-type guard ring 21. Also, the same can be said for the width of the p-type guard ring 21 as for the p-type deep layer 5 and the p-type deep layer 30. Furthermore, due to the concentration of equipotential lines in the vicinity of the mesa portion RM in terms of structure, in order to suppress the rise of the equipotential lines in the mesa portion RM, it is better to make the intervals DA4out and DA3in within a predetermined range from the boundary portion of the mesa portion RM smaller than the intervals DA1 and DA2.

[0067] In this way, the intervals DA1 to DA4 and the widths of the p-type deep layers 5 and 30 are defined. FIG. 7 shows the area ratios occupied by the cell region RC, the connection part RJ, and the guard ring part RG in a 5 mm□ chip in which the SiC semiconductor device is formed, and the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 among them. Here, as an example, a case is cited where the cell region RC occupies 60%, the connection part RJ occupies 30%, and the guard ring part RG occupies 10% with respect to the chip area. As a comparative example, a case where the p-type deep layer 30 is formed over the entire area of the connection part RJ and a case where the p-type deep layer 30 is composed of the linear part 31 and the frame-shaped part 32 as in the present embodiment are examined. Also, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.0 μm, the intervals DA1 to DA3 are set to 0.6 μm, the width of the p-type guard ring 21 is set to 1.0 μm, and the interval DA4 is set to 0.6 to 1.5 μm so as to become wider as it is farther from the cell region RC.

[0068] As shown in this figure, in the comparative example where the p-type deep layer 30 is formed over the entire area of the connection part RJ, the occupancy ratio of the p-type deep layer 30 in the connection part RJ becomes 100%. Therefore, the occupancy ratio of the p-type deep layer 30 in the chip becomes 30%, which is the same as the area ratio occupied by the connection part RJ in the chip. And in the cell region RC, the occupancy ratio of the p-type deep layer 5 in the chip was 24%, and in the guard ring part RG, the occupancy ratio of the p-type guard ring 21 in the chip was 3%. Therefore, the total value of the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip became 57%.

[0069] In contrast, when the p-type deep layer 30 is configured by the linear portion 31 and the frame-shaped portion 32 as in the present embodiment, the ratio occupied by the p-type deep layer 30 in the connecting portion RJ becomes 40%. Therefore, the ratio occupied by the p-type deep layer 30 in the chip becomes 12%. Also, in the cell region RC, the ratio occupied by the p-type deep layer 5 in the chip remains 24%, and in the guard ring portion RG, the ratio occupied by the p-type guard ring 21 in the chip remains 3%. Therefore, the total value TV of the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip becomes 39%.

[0070] In this way, by making the p-type deep layer 30 linear like the linear portion 31 and the frame-shaped portion 32, the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip can be decreased. Here, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 1.0 μm, and the intervals DA1 to DA3 are set to 0.6 μm. Therefore, compared with the case of making the widths narrower and the intervals DA1 to DA3 wider than this, the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip are at high values. If the width of the p-type deep layer 30 is made smaller than 1.0 μm or the intervals DA1 to DA3 are made larger than 0.6 μm, the total value TV can be made smaller and can be at least 40% or less. Thereby, it becomes possible to suppress the total value TV of the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip, that is, to reduce the dose amount at the time of ion implantation, and it becomes possible to suppress wafer warping.

[0071] As described above, in the present embodiment, by configuring the p-type deep layer 30 in a linear shape, the total value TV of the occupancy ratios of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is made 40% or less. Thereby, it becomes possible to suppress wafer warping while forming the p-type deep layer 30 by ion implantation.

[0072] In addition, in the present embodiment, the following effects can also be achieved.

[0073] (1) As described above, the widths of the p-type deep layer 5 and the p-type deep layer 30 are set to 0.4 to 1.0 μm, and the intervals DA1 between the p-type deep layers 5, the interval DA2 of the linear portion 31, and the interval DA4 of the frame portion 32 are set to 0.6 to 1.5 μm. Therefore, an increase in the feedback capacitance Crss can be suppressed. In addition, it is possible to suppress the rise of equipotential lines between the p-type deep layer 5 and the p-type deep layer 30, suppress the application of a high electric field to the bottom of the gate trench 6, and ensure the breakdown voltage of the SiC semiconductor device. Further, by setting the widths of the p-type deep layer 5 and the p-type deep layer 30 and the intervals DA1, DA2, and DA4 in this way, the occupied area of the p-type deep layer 5 and the p-type deep layer 30 in the chip can be reduced, and the dose amount during ion implantation can be further reduced. Therefore, it is possible to further reduce the wafer warp.

[0074] Also, in this case, it is preferable that the intervals DA1 to DA4 are equal to or greater than the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. By doing so, without degrading functions such as the breakdown voltage, the occupancy area ratio of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip, where the total value TV is 40% or less, can be achieved.

[0075] (2) Further, regarding the magnitudes of the respective intervals, when the interval DA3out > interval DA1 > interval DA2 > interval DA3in and interval DA4out, a breakdown can be caused in the entire cell region RC. Thereby, even if a high voltage due to a load surge or the like is applied to the SiC semiconductor device, element breakdown can be prevented.

[0076] (3) Furthermore, in the present embodiment, the p-type deep layer 5 in the cell region RC is provided with an intersection portion 5b, and is connected to the linear portion 31 in the p-type deep layer 30 of the linear portion 5a and the connecting portion RJ. Also, the portion located on the innermost peripheral side of the frame portion 32 is connected to the linear portion 31.

[0077] By adopting such a structure, in the top view shown in FIG. 1, the gap between the p-type deep layer 5 and the p-type deep layer 30, that is, the area of the portion where the p-type deep layer 5 and the p-type deep layer 30 are not arranged can be reduced. Therefore, it is possible to further suppress the rise of the equipotential line and ensure a high breakdown voltage.

[0078] Note that instead of forming the p-type deep layer 5 and the p-type deep layer 30 by an ion implantation layer, it is also conceivable to form trenches on the surface of the n-type layer 2 and fill the trenches with a p-type layer. However, in addition to the difficulty of filling the trenches with a p-type layer itself, at the positions where the linear portions intersect or are connected, dents will occur in the p-type layer. On the other hand, when the p-type deep layer 5 and the p-type deep layer 30 are formed by an ion implantation layer, no dents will occur in the p-type layer even at the positions where the linear portions intersect or are connected. Therefore, the flatness of the wafer surface can be ensured. - -

[0079] Subsequently, a method for manufacturing the SiC semiconductor device according to the present embodiment will be described with reference to FIGS. 8A to 8H.

[0080] 〔Step shown in FIG. 8A〕 First, as a semiconductor substrate, a semiconductor substrate in which an n-type layer 2 made of SiC is epitaxially grown on the main surface of an n-type substrate 1 is prepared. At this time, the semiconductor substrate may be prepared by epitaxially growing the n-type layer 2 on the main surface of the n-type substrate 1, or a so-called epi-substrate in which the n-type layer 2 has been epitaxially grown on the main surface of the n-type substrate 1 in advance may be prepared as the semiconductor substrate. + + - - + + - - + + - -

[0081] 〔Step shown in FIG. 8B〕 Next, n -Place a mask (not shown) on top of the n-type layer 2 and open the mask in the planned formation areas of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. Then, ion-implant p-type impurities using the mask. At this time, adjust the range of the ion implantation so that the p-type impurities are implanted to a position at a predetermined depth from the surface of the n - type layer 2. Thereby, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed. Then, remove the mask.

[0082] Here, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed at once, but they may be formed in multiple parts. In that case, for example, the p-type deep layer 5 and the p-type deep layer 30 may be formed separately into upper and lower parts, and the lower part may have a different width, such as being wider than the upper part.

[0083] 〔Step shown in FIG. 8C〕 Epitaxially grow the p-type base region 3 and the n - type source region 4 in sequence on top of the n-type layer 2, including on top of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21. +

[0084] 〔Step shown in FIG. 8D〕 n + After placing a mask (not shown) on top of the n-type source region 4, open the mask in the planned formation areas of the p-type contact region 3a and the p-type hole extraction layer 3b. Then, form the p-type contact region 3a and the p-type hole extraction layer 3b by ion-implanting p-type impurities using the mask. Then, remove the mask.

[0085] Here, the n + type source region 4 is epitaxially grown and the p-type contact region 3a and the p-type hole extraction layer 3b are formed by ion implantation, but it is not limited to this. For example, the n +The type source region 4, the p-type contact region 3a, and the p-type hole extraction layer 3b may all be formed by ion implanting them into the p-type base region 3. Further, epitaxial growth is performed so that the impurity concentration in the surface layer portion of the p-type base region 3 becomes high to form the p-type contact region 3a and the p-type hole extraction layer 3b, and n-type impurities are ion implanted into the p-type base region 3 to form an n + type source region 4.

[0086] [Process shown in FIG. 8E] n + After forming a mask (not shown) on the n-type source region 4, the p-type base region 3, etc., the planned formation regions of the gate trench 6 and the recess 20 in the mask are opened. Then, anisotropic etching such as RIE (Reactive Ion Etching) is performed using the mask to simultaneously form the gate trench 6 and the recess 20 having a depth deeper than the upper surface of the n - type layer 2.

[0087] Here, the gate trench 6 and the recess 20 are formed simultaneously, but they can also be formed separately. In that case, since the gate trench 6 and the recess 20 can have different depths, it is possible to design each of them to an optimal depth.

[0088] [Process shown in FIG. 8F] After removing the mask, for example, by depositing an oxide film, a gate insulating film 7 is formed, and the inner wall surface of the gate trench 6 and the surface of the n + type source region 4 are covered by the gate insulating film 7. Then, after depositing Poly-Si doped with p-type impurities or n-type impurities and etching it back, the gate electrode 8 is formed by leaving Poly-Si in at least the gate trench 6. Thereby, a trench gate structure is formed.

[0089] [Process shown in FIG. 8G] A interlayer insulating film 10 made of, for example, an oxide film is formed so as to cover the surfaces of the gate electrode 8 and the gate insulating film 7. Then, after forming a mask (not shown) on the surface of the interlayer insulating film 10, portions of the mask located between the respective gate electrodes 8, that is, portions corresponding to the p-type contact regions 3a and the vicinity thereof are opened. At the same time, portions of the mask corresponding to the p-type hole extraction layer 3b are also opened. After that, by patterning the interlayer insulating film 10 using the mask, contact holes for exposing the p-type contact regions 3a and the n + type source regions 4 and contact holes for exposing the p-type hole extraction layer 3b are formed.

[0090] 〔Step shown in FIG. 8H〕 An electrode material composed of, for example, a stacked structure of a plurality of metals is formed on the surface of the interlayer insulating film 10. Then, by patterning the electrode material, a source electrode 9, a gate wiring (not shown), and the like are formed.

[0091] Although the subsequent steps are not shown, steps such as forming a drain electrode 11 on the back side of the n + type substrate 1 are performed, whereby the SiC semiconductor device according to the present embodiment is completed.

[0092] As described above, the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are formed by ion implantation. However, not only the p-type deep layer 5 and the p-type guard ring 21 but also the p-type deep layer 30 are formed in a line shape. By forming the p-type deep layer 30 in a line shape, the total occupancy value TV of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 in the chip is set to 40% or less. Thereby, it becomes possible to suppress wafer warpage while forming the p-type deep layer 30 by ion implantation.

[0093] (Modification of the First Embodiment) The layout of the p-type deep layer 5 and the p-type deep layer 30 may be changed with respect to the first embodiment.

[0094] For example, as shown in FIG. 9, the p-type deep layer 5 may be composed only of a stripe-shaped portion formed by the linear portion 5a. Further, as shown in FIG. 10, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a lattice-shaped portion 33 formed by the intersection of stripes extending in two directions. Specifically, the lattice-shaped portion 33 can be configured with a structure in which one stripe is parallel to the linear portion 5a in the p-type deep layer 5 and the other stripe is orthogonal to the linear portion 5a. Further, as shown in FIG. 11, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a mesh-shaped portion 34 in which stripes extending in different two directions intersect each other and are inclined with respect to the linear portion 5a. Furthermore, as shown in FIG. 12, the inner portion of the frame-shaped portion 32 of the p-type deep layer 30 may be a dot-shaped portion 35 in which a plurality of dots are arranged linearly with the same direction as the linear portion 5a in the p-type deep layer 5 as the longitudinal direction. Here, the case where oval dots are arranged in a dot line shape with the longitudinal direction being the same direction as the direction in which the dot-shaped portion 35 is arranged linearly is illustrated, but each dot may be formed in other shapes such as a circular shape or a square shape. In the case of the structures shown in FIGS. 10 to 12, the lattice-shaped portion 33, the mesh-shaped portion 34, and the dot-shaped portion 35 each constitute a part of the second conductivity type layer.

[0095] Also in these cases, it is preferable to set the interval DA2 of the p-type deep layer 30 at the connection portion RJ so that the relationship of interval DA3out > interval DA1 > interval DA2 > interval DA3in, DA4out holds. In the case of the structures of FIGS. 10 and 11, the interval between each stripe extending in two directions constituting the lattice-shaped portion 33 and the mesh-shaped portion 34 corresponds to the interval DA2. In the case of the structure of FIG. 12, the interval between adjacent dot lines and the interval between adjacent dots on the same dot line correspond to the interval DA2.

[0096] (Second Embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the breakdown voltage structure using the p-type layer is changed, and other aspects are the same as those of the first embodiment, so the differences from the first embodiment will be mainly described.

[0097] 13, in this embodiment, in the cell region RC, an n-type first current spreading layer 50 and a p-type deep layer 51 are provided below the p-type deep layer 5, and a second current spreading layer 60 is provided between the p-type deep layers 5. The p-type deep layer 51 corresponds to the first deep layer and constitutes at least a part of the second conductive type layer. In addition, the p-type deep layer 5 disposed on the p-type deep layer 51 corresponds to the second deep layer.

[0098] Specifically, n - A first current spreading layer 50 and a p-type deep layer 51 are formed on the n-type layer 2. The first current spreading layer 50 has a depth of 0.3 to 1.5 μm. The p-type deep layer 51 is shallower than the first current spreading layer 50, but has a depth of approximately the same 0.3 to 1.4 μm. In other words, the p-type deep layer 51 is formed so that its bottom is located within the first current spreading layer 50, and - The first current spreading layer 50 is formed at a depth such that it is located between the first and second layers 2. Note that, although a part of the first current spreading layer 50 is arranged at the bottom of the p-type deep layer 51 here, the first current spreading layer 50 and the p-type deep layer 51 may be at the same depth.

[0099] The first current spreading layer 50 and the p-type deep layer 51 are each extended in one direction so as to form a stripe shape in which a plurality of lines are alternately arranged, and are arranged at equal intervals along the perpendicular direction. In the present embodiment, the stripe-shaped portion of the first current spreading layer 50 and the p-type deep layer 51 are extended in a direction intersecting the longitudinal direction of the trench gate structure.

[0100] The spacing between the lines of the striped portion of the first current spreading layer 50 is, for example, 0.6 to 1.5 μm, and the n-type impurity concentration is, for example, 5.0×1016 ~2.0×10 18 / cm 3 It is set like this. The width of each p-type deep layer 51 is, for example, 0.4 to 1.0 μm, and the p-type impurity concentration is, for example, 3.0×10 17 ~1.0×10 18 / cm 3 It is set like this. Regarding the interval DB1 between each p-type deep layer 51, that is, the width of each line of the striped part in the first current dispersion layer 50, it is made different from the interval DB2 of the linear part 71 of the p-type deep layer 70 provided in the joint part RJ described later, but it may be the same. Here, the interval DB1 is set to be equal to or greater than the interval DB2.

[0101] Regarding the first current dispersion layer 50, a concave part is formed in the surface layer part of the n - type layer 2, and after epitaxially growing the n-type layer, it is flattened, or it is formed by ion-implanting n-type impurities into the surface layer part of the n - type layer 2. When the first current dispersion layer 50 is formed by ion implantation, since n-type impurities are implanted into the n - type layer 2, the dose amount becomes sufficiently smaller than when ion-implanting p-type impurities for forming the p-type deep layer 5 or the like. For this reason, wafer warpage hardly occurs. Also, regarding the p-type deep layer 51, it is formed by ion-implanting p-type impurities. For this reason, regarding the p-type deep layer 51, the width and the dose amount are set in consideration of wafer warpage. Also, regarding the p-type deep layer 51, the interval is set to 0.6 μm or more so that the remaining width of the photomask during ion implantation does not become too narrow.

[0102] The second current dispersion layer 60 is formed on the first current dispersion layer 50 and the p-type deep layer 51 together with the p-type deep layer 5. In the first embodiment, the space between the p-type deep layers 5 was the n - type layer 2, but in this embodiment, it is the second current dispersion layer 60. The second current dispersion layer 60 may have the same n-type impurity concentration as the n - type layer 2, but in order to have lower resistance and enable current to be dispersed over a wider range, n -It is preferably higher than the type layer 2. Here, the n-type impurity concentration of the second current dispersion layer 60 is, for example, 1.0×10 16 ~5.0×10 17 / cm 3 and is set as such. Also, the thickness of the second current dispersion layer 60 is, for example, 0.5 to 2 μm. By ion-implanting p-type impurities into this second current dispersion layer 60, a p-type deep layer 5 is formed. And the p-type deep layer 5 is formed at a depth equal to or greater than the depth of the second current dispersion layer 60 and is in a state of being connected to the p-type deep layer 51.

[0103] In addition, in this embodiment, in addition to the n - type layer 2, the first current dispersion layer 50 and the second current dispersion layer 60 form a part that constitutes the drift layer. The second current dispersion layer 60 is formed at a position corresponding to the trench gate structure and extends in a direction orthogonal to the first current dispersion layer 50, that is, in the same direction as the longitudinal direction of the trench gate structure.

[0104] In the guard ring portion RG, the second current dispersion layer 60 formed in the cell region RC remains on the surface of the n - type layer 2. Also, a recess 20 is formed so as to penetrate the p-type base region 3 and reach the second current dispersion layer 60. And a p-type guard ring 21 is formed on the surface layer portion of the n - type layer 2. Here, the p-type guard ring 21 is arranged away from the bottom surface of the recess 20, but it may also be formed in contact with the bottom surface of the recess 20.

[0105] The p-type guard ring 21 is formed so as to surround the cell region RC and the connection part RJ, and a plurality of them are arranged concentrically, having the layout of the first embodiment. The p-type guard ring 21 has the same width and impurity concentration as the above-described p-type deep layer 51. Regarding the interval DB3 between the p-type guard rings 21, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, the interval DB3 of the p-type guard rings 21 is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DB3in of the portion of the interval DB3 located within a predetermined range from the boundary position of the mesa portion RM is made narrower than the interval DB1 between the p-type deep layers 51 in the cell region RC and the interval DB2 of the linear portion 71 of the p-type deep layer 70 in the connection part RJ. Also, the widest portion of the interval DB3, that is, the interval DB3out between the outermost p-type guard ring 21 and the one adjacent to it on the inner side is made wider than the interval DB1 and the interval DB2.

[0106] Also, in the connection part RJ, - a p-type deep layer 5 and a second current dispersion layer 60 are formed on the surface of the n-type layer 2, and further, a p-type base region 3 is also formed thereon. Also, - a p-type deep layer 70 is formed in the surface layer portion of the n-type layer 2.

[0107] Although only a cross-section is shown in Fig. 13, the p-type deep layer 70 is configured to have a linear portion 71 and a frame-shaped portion 72. The linear portion 71 of the p-type deep layer 70 constitutes a part of the second conductivity type layer, and the frame-shaped portion 72 constitutes a part of the second conductivity type ring. When viewing the SiC semiconductor device from above, the linear portion 71 is arranged in parallel with the p-type deep layer 51 and is provided with one or more. When a plurality of linear portions 71 are provided, the layout is such that the interval DB2 between the linear portions 71 is equal to or less than the interval DB1 of the p-type deep layer 51. Also, when viewing the SiC semiconductor device from above, the frame-shaped portion 72 is arranged so as to surround the cell region RC and the linear portion 71, and is configured in a rectangular frame shape with rounded corners. The frame-shaped portion 72 is arranged concentrically with the p-type guard ring 21, and a plurality of them are provided in this embodiment.

[0108] Regarding the width of the p-type deep layer 70, it is the same as the width of the p-type deep layer 51. Regarding the interval DB2 between the linear portions 71, it may be the same as the interval DB1 of the linear portion 5a of the p-type deep layer 5, but here it is made narrower than the interval DB1. Also, regarding the interval DB4 of the frame-shaped portion 72, they may all have the same width, or they may be different. It is preferable that the interval DB4 of the frame-shaped portion 72 is equal to or less than the interval DB1 of the p-type deep layer 51 in the cell region RC. In particular, regarding the interval DB4out of the portion located within a predetermined range from the boundary position of the mesa portion RM of the interval DB4 of the frame-shaped portion 72, it is more preferable to make it narrower than the interval DB2 between the linear portions 71 in the p-type deep layer 70.

[0109] Also, regarding the interval DB3in of the p-type guard ring 21 and the interval DB4out of the frame-shaped portion 72 located within a predetermined range from the boundary position of the mesa portion RM, they are made narrower than the interval DB2 between the linear portions 71 in the p-type deep layer 70. Thereby, similar to the first embodiment, it becomes possible to cope with mask misalignment when forming the recess 20 for forming the mesa portion RM.

[0110] Here, the p-type deep layer 70 is provided with the linear portion 71 and the frame-shaped portion 72, but it may be configured with only one of them. Also, the number of the linear portion 71 and the frame-shaped portion 72 can be arbitrarily set. Further, the inner portion of the frame-shaped portion 72 may have a layout such as the lattice-shaped portion 33, the mesh-shaped portion 34, or the dot-shaped portion 35 as shown in the modification example of the first embodiment.

[0111] As described above, the SiC semiconductor device of this embodiment is configured. In the SiC semiconductor device configured as described above, the ratio of the p-type layer deeply implanted by ion implantation, that is, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 to the total area of the chips constituting the SiC semiconductor device is set to 40% or less. Thereby, it becomes possible to reduce the dose amount during ion implantation, and it becomes possible to suppress wafer warping.

[0112] Also, the width of the p-type deep layer 5 is set to 0.4 to 1.0 μm as in the first embodiment. In this way, also for the p-type deep layer 5 disposed in the upper layer than the p-type deep layer 51, by limiting the injection range, wafer warping can be further suppressed.

[0113] Subsequently, a method for manufacturing the SiC semiconductor device of this embodiment will be described. The method for manufacturing the SiC semiconductor device of this embodiment is generally the same as that of the first embodiment, except for the formation steps of the first current dispersion layer 50, the p-type deep layer 51, the p-type deep layer 70, the p-type guard ring 21, the second current dispersion layer 60, and the p-type deep layer 5. Therefore, except for these manufacturing steps, the respective manufacturing steps described in the first embodiment will be referred to and described.

[0114] First, in the same manner as the process shown in FIG. 8A described in the first embodiment, as a semiconductor substrate, an n + -type substrate 1 having an n - -type layer 2 made of SiC epitaxially grown on the main surface is prepared. Then, the processes shown in FIGS. 14A to 14C are performed.

[0115] [Process shown in Fig. 14A] n - After placing a mask (not shown) with an opening at the planned formation area of the first current dispersion layer 50 on the n-type layer 2, the first current dispersion layer 50 is formed by ion-implanting n-type impurities. Note that the first current dispersion layer 50 may be formed by selective epitaxial growth instead of ion implantation. For example, after partially etching the n - type layer 2 to form a trench at the planned formation position of the first current dispersion layer 50, the n-type layer may be epitaxially grown and then planarized to form the first current dispersion layer 50.

[0116] [Process shown in Fig. 14B] Subsequently, after placing a mask (not shown) with openings at the planned formation positions of the p-type deep layer 51, p-type deep layer 70, and p-type guard ring 21 on the n - type layer 2 including the first current dispersion layer 50, p-type impurities are ion-implanted. Thereby, the p-type deep layer 51, p-type deep layer 70, and p-type guard ring 21 are formed.

[0117] [Process shown in Fig. 14C] Furthermore, the second current dispersion layer 60 is epitaxially grown on the n - type layer 2 including the p-type deep layer 51, p-type deep layer 70, and p-type guard ring 21. Then, after placing a mask (not shown) with an opening at the planned formation position of the p-type deep layer 5, p-type impurities are ion-implanted. Thereby, the p-type deep layer 5 that penetrates the second current dispersion layer 60 and is connected to the p-type deep layer 51 and p-type deep layer 70 is formed.

[0118] Although the subsequent processes are not shown, the SiC semiconductor device of this embodiment can be manufactured by performing the same manufacturing processes as those after Fig. 8D described in the first embodiment.

[0119] Thus, in the case of this embodiment, in the cell region RC, the p-type deep layer 51, in the connection part RJ, the p-type deep layer 70, and in the guard ring part RG, the p-type guard ring 21 are respectively formed on the n -It is provided in the surface layer portion of the p-type layer 2, and these are simultaneously formed by ion implantation. Then, the ratio of the p-type layer, that is, the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 that are deeply implanted by ion implantation with respect to the total area of the chip constituting the SiC semiconductor device is set to 40% or less. As a result, it becomes possible to reduce the dose amount during ion implantation, and it becomes possible to suppress wafer warping.

[0120] (Third Embodiment) The third embodiment will be described. In this embodiment, a junction barrier schottky diode (hereinafter referred to as JBS) is provided as a power element instead of the vertical MOSFET with respect to the first embodiment. Since the other parts are the same as those in the first embodiment, only the parts different from the first embodiment will be described.

[0121] As shown in FIGS. 15 and 16, an n- + type drift layer 102 is formed on the n- - type substrate 101. And in the cell region RC, a p-type deep layer 103 formed in a stripe shape with respect to the n- - type drift layer 102 is formed, and a p-type guard ring 104 is formed in the guard ring portion RG surrounding the periphery thereof. Also, a p-type connecting layer 105 is formed at the connecting portion RJ between the cell region RC and the guard ring portion RG.

[0122] The p-type deep layer 103 constitutes at least a part of the second conductivity type layer, and n- -A plurality of the p-type drift layers 102 are arranged at equal intervals to form a stripe shape. The p-type guard ring 104 constitutes at least a part of the second conductivity type ring, and a plurality of square-shaped ones with rounded corners are arranged concentrically. The p-type connecting layer 105 is configured such that a plurality of frame-shaped ones surrounding the periphery of the p-type deep layer 103 formed in the cell region are arranged side by side. Here, the p-type connecting layer 105 is entirely composed of the frame-shaped portions, but linear portions may be provided inside the frame-shaped portions. The linear portions of the p-type connecting layer 105 constitute a part of the second conductivity type layer, and the frame-shaped portions constitute a part of the second conductivity type ring. These p-type deep layers 103, p-type guard rings 104, and p-type connecting layers 105 are formed by ion-implanting p-type impurities into the n - type drift layer 102.

[0123] Also, in the cell region RC and the connection portion RJ, a Schottky electrode 106 corresponding to the first electrode in contact with the surfaces of the n - type drift layer 102, p-type deep layer 103, and p-type connecting layer 105 is formed. That is, in the case of this embodiment, a plurality of p-type rings made of a linear frame-shaped p-type layer surrounding the cell region RC are provided, and the Schottky electrode 106 is arranged so as to cover a part of the inner peripheral side thereof. Among such a plurality of p-type rings, the one in contact with the Schottky electrode 106 is called the p-type connecting layer 105. Also, among the plurality of p-type layers, the one not in contact with the Schottky electrode 106 and located outside it and where the n - type drift layer 102 is exposed is called the p-type guard ring 104. And the portion where the Schottky electrode 106 is formed becomes the Schottky electrode portion RS composed of the cell region RC and the connection portion RJ.

[0124] Furthermore, on the back surface side of the n + type substrate 101, an ohmic electrode 107 corresponding to the second electrode is formed. In this way, the SiC semiconductor device of this embodiment is configured.

[0125] In such a configuration, the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are, for example, set to have a width of 0.4 to 1 μm. They may be formed with the same width or different widths. Also, they are, for example, set to have a depth of about 2 μm. These depths may be different, but here they are set to the same depth. Further, the intervals DC1 to DC4 between them are, for example, set to 0.6 to 1.5 μm. These intervals DC1 to DC4 may be the same, but here they are made different. Specifically, the interval DC2 of the p-type connecting layer 105 at the connection part RJ is made narrower than the interval DC1 of the p-type deep layer 103 in the cell region RC. In the case of this embodiment, the p-type connecting layer 105 is composed only of the frame portion. If the interval between the portions that are the frame portions among the interval DC2 is set as the interval DC4, then the interval DC4out of the portion located in a predetermined range from the boundary position of the Schottky electrode portion RS among the interval DC4 is made the narrowest. Also, regarding the interval DC3 of the p-type guard ring 104, it may be equally spaced, but in order to relieve the electric field concentration on the cell region RC side and make the equipotential lines go more toward the outer peripheral side, it is made narrower on the cell region RC side and larger toward the outer peripheral side. The interval DC3in of the portion of the interval DC3 of the p-type guard ring 104 located in a predetermined range from the boundary position of the Schottky electrode portion RS is made narrower than the interval DC1 of the p-type deep layer 103 in the cell region RC and is made about the same as the interval DC4out. Also, the widest portion of the interval DC3, that is, the interval DC3out between the outermost p-type guard ring 104 and the one immediately inside it is made wider than the interval DC1 and the interval DC2.

[0126] Thus, also in the SiC semiconductor device including the JBS as a power device, the widths and intervals of the p-type connecting layer 105 and the p-type guard ring 104 are the same as those in the first embodiment.

[0127] That is, the interval DC2 of the p-type connecting layer 105 is basically set to be equal to or less than the interval DC1 of the p-type deep layer 103, and the interval DC2 is further reduced on the outer edge side of the Schottky electrode portion RS. Also, the interval DC3 between the p-type guard rings 104 is gradually increased as it goes toward the outer peripheral side. And on the outermost peripheral side, the interval DC3out between the p-type guard rings 104 is made larger than the interval DC1 between the p-type deep layers 103. As a result, the ratio occupied by the p-type layers that are deeply implanted by ion implantation with respect to the total area of the chip constituting the SiC semiconductor device, that is, the p-type deep layer 103, the p-type connecting layer 105, and the p-type guard ring 104, is made 40% or less.

[0128] The SiC semiconductor device having such a structure is formed, for example, as follows. First, an n + -type drift layer 102 is epitaxially grown on the n - -type substrate 101. After that, a mask (not shown) is disposed on the surface of the n - -type drift layer 102. Then, p-type impurities are ion-implanted from above the mask to form the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105. After that, an electrode material is deposited on the n - -type drift layer 102 including the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105, and then this is patterned to form the Schottky electrode 106. Finally, an ohmic electrode 107 is formed on the back side of the n + -type substrate 101, and thus the SiC semiconductor device of the present embodiment is completed.

[0129] In the manufacture of such a SiC semiconductor device, the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are formed by ion implantation. However, since the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are configured as described above, the SiC semiconductor device of the present embodiment can also obtain the same effects as those of the first embodiment.

[0130] (Other embodiments) The present invention is not limited to the above-described embodiments, and can be appropriately modified within the scope described in the claims.

[0131] For example, in each of the above embodiments, - a p-type deep layer 5 and the like were formed by ion-implanting p-type impurities from the surface of the n-type layer 2. However, p-type impurities may be ion-implanted from the surface of the p-type base region 3 or the surface of the n-type source region 4. However, in that case, ion implantation with a higher acceleration voltage will be performed, and the influence of wafer warping will increase. Therefore, considering the influence of wafer warping, the allowable range of the dose amount and width of the p-type deep layer 5 and the like can be narrower than the case of forming the p-type deep layer 5 and the like by ion-implanting p-type impurities from the surface of the n-type layer 2. + However, in that case, ion implantation with a higher acceleration voltage will be performed, and the influence of wafer warping will increase. Therefore, considering the influence of wafer warping, the allowable range of the dose amount and width of the p-type deep layer 5 and the like can be narrower than the case of forming the p-type deep layer 5 and the like by ion-implanting p-type impurities from the surface of the n-type layer 2. - For example, in each of the above embodiments, a p-type deep layer 5 and the like were formed by ion-implanting p-type impurities from the surface of the n-type layer 2. However, p-type impurities may be ion-implanted from the surface of the p-type base region 3 or the surface of the n-type source region 4. However, in that case, ion implantation with a higher acceleration voltage will be performed, and the influence of wafer warping will increase. Therefore, considering the influence of wafer warping, the allowable range of the dose amount and width of the p-type deep layer 5 and the like can be narrower than the case of forming the p-type deep layer 5 and the like by ion-implanting p-type impurities from the surface of the n-type layer 2.

[0132] Also, in each of the above embodiments, the MOSFET 100 and JBS are cited as examples of semiconductor elements provided in the cell region RC of the SiC semiconductor device. However, even if other semiconductor elements are formed, as long as they include a cell region RC and an outer peripheral region RO and a p-type deep layer is formed at the connection portion RJ of the outer peripheral region RO, it is acceptable. Examples of such semiconductor elements include IGBTs. Also, in each of the above embodiments, the n-channel type MOSFET 100 with the first conductivity type as n-type and the second conductivity type as p-type was cited as an example for explanation. However, it may be a p-channel type MOSFET 100 with the conductivity types of each component inverted. Also, it is not limited to an element with a trench gate structure, and a planar type element may be used. Note that for the IGBT, only the conductivity type of the n-type substrate 1 is changed from n-type to p-type with respect to each of the above embodiments, and the other structures and manufacturing methods are the same as those of each of the above embodiments. + For the IGBT, only the conductivity type of the n-type substrate 1 is changed from n-type to p-type with respect to each of the above embodiments, and the other structures and manufacturing methods are the same as those of each of the above embodiments.

[0133] Also, in the first embodiment, the widths of the p-type deep layer 5, the p-type deep layer 30, and the p-type guard ring 21 are the same, but they may be different widths. In the second embodiment, the widths of the p-type deep layer 51, the p-type deep layer 70, and the p-type guard ring 21 are the same, but they may be different widths. In the third embodiment, the widths of the p-type deep layer 103, the p-type guard ring 104, and the p-type connecting layer 105 are the same, but they may have different widths. Furthermore, in the first to third embodiments, the widths of the respective p-type guard rings 21 and p-type guard rings 104 are the same, but the width of each p-type guard ring 21 may have a structure that becomes wider toward the outer periphery.

[0134] Also, in each of the above embodiments, the case where SiC is used as the semiconductor material has been described, but the present invention can also be applied to semiconductor devices using other semiconductor materials such as Si.

[0135] Note that when indicating the crystal orientation, a bar (-) should originally be attached above the desired number. However, due to the limitations in the expression based on the electronic application, in this specification, a bar is attached in front of the desired number.

Explanation of Reference Numerals

[0136] 1 n + -type substrate 2 n - -type layer 3 p-type base region 4 n + -type source region 5, 30 p-type deep layer 8 gate electrode 9 source electrode 10 interlayer insulating film 21 p-type guard ring

Claims

【Claim 1】 A semiconductor device having a cell region (RC) in which a semiconductor element (100) is formed within a chip (Ch), and an outer peripheral region (RO) including a guard ring portion (RG) surrounding the outer periphery of the cell region and a connection portion (RJ) located between the guard ring portion and the cell region, a substrate (1, 101) of a first or second conductivity type having a front surface and a back surface, and a drift layer (2, 50, 60, 102) of a first conductivity type formed on the front surface side of the substrate and having a lower impurity concentration than the substrate, in the cell region, a second conductivity type layer (5, 5a, 51, 103) formed in the drift layer and including a portion formed in a stripe shape with one direction as the longitudinal direction, a first electrode (9, 106) electrically connected to the second conductivity type layer, a second electrode (11, 107) formed on the back surface side of the substrate, and having, a vertical semiconductor element for flowing a current between the first electrode and the second electrode is provided, also in the connection portion, the drift layer is provided with a second conductivity type layer (31, 33 to 35, 71) formed in a line shape, in the guard ring portion or the guard ring portion and the connection portion, a second conductivity type ring (21, 32, 72, 104, 105) formed in the drift layer and having a plurality of line-shaped frame shapes surrounding the cell region, and at least a part located on the outer peripheral side constituting a guard ring (21, 104) is provided, the second conductivity type layer and the second conductivity type ring are constituted by an ion implantation layer, and the ratio occupied by the second conductivity type layer and the second conductivity type ring with respect to the total area of the chip is 40% or less, the second conductivity type layer provided in the connection portion includes a linear portion (31) having the same longitudinal direction as the longitudinal direction of the second conductivity type layer provided in the cell region, the second conductivity type ring is disposed in the guard ring portion and the connection portion, a mesa portion (RM) in which the cell region and the connection portion protrude more than the guard ring portion is formed, the guard rings have an increased distance (DA3, DB3) between the guard rings as going from the inner peripheral side to the outer peripheral side, the distance between the guard rings is defined as a third distance (DA3, DB3), A semiconductor device having a relationship where the distance (DA3out, DB3out) of the widest portion located at the outermost periphery of the third interval > the distance (DA3in, DB3in) of the portion located within a predetermined range from the boundary position of the mesa portion in the third interval. **Claim 2** Taking the distance between the second conductive type layers disposed in the cell region as a first interval (DA1, DB1), The semiconductor device according to claim 1, having a relationship where the distance of the widest portion located at the outermost periphery of the third interval > the first interval > the distance of the portion located within a predetermined range from the boundary position of the mesa portion in the third interval.

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