Semiconductor device

Abstract

To provide a semiconductor device that can be mass-produced with high reliability using a material suitable for semiconductor applications such as transistors and diodes, and a large substrate such as mother glass, a semiconductor device that has a transistor with a good electronic state at the interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film, and a highly reliable semiconductor device that is imparted with stable electrical characteristics to a transistor that uses an oxide semiconductor film as a channel.SOLUTION: A semiconductor device uses an oxide material containing crystals that are c-axis oriented and have a triangular or hexagonal atomic arrangement when viewed from the ab-plane, surface, or interface direction, and that are rotated around the c-axis.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having a circuit including a semiconductor element such as a transistor and a method of manufacturing the same. For example, it relates to a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, etc. mounted on a power supply circuit, an electro-optical device represented by a liquid crystal display panel, an electronic device having a light-emitting element as a component mounted thereon, etc. Further, it relates to an oxide used in a semiconductor device. For example, a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, etc. mounted on a power supply circuit, an electro-optical device represented by a liquid crystal display panel, an electronic device having a light-emitting element as a component mounted thereon, etc. Further, it relates to an oxide used in a semiconductor device. For example, a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, etc. mounted on a power supply circuit, an electro-optical device represented by a liquid crystal display panel, an electronic device having a light-emitting element as a component mounted thereon, etc. Further, it relates to an oxide used in a semiconductor device. For example, a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, etc. mounted on a power supply circuit, an electro-optical device represented by a liquid crystal display panel, an electronic device having a light-emitting element as a component mounted thereon, etc. Further, it relates to an oxide used in a semiconductor device. For example, a semiconductor integrated circuit including a power device, a memory, a thyristor, a converter, an image sensor, etc. mounted on a power supply circuit, an electro-optical device represented by a liquid crystal display panel, an electronic device having a light-emitting element as a component mounted thereon, etc. Further, it relates to an oxide used in a semiconductor device.

[0002] In the present specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. An electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices. In the present specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. An electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices. In the present specification, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. An electro-optical device, a light-emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

Background Art

[0003] As represented by a liquid crystal display device, many of the transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate. Further, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate. As represented by a liquid crystal display device, many of the transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate. Further, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate. As represented by a liquid crystal display device, many of the transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate. Further, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate. As represented by a liquid crystal display device, many of the transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate. Further, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate. As represented by a liquid crystal display device, many of the transistors formed on a glass substrate or the like are composed of amorphous silicon, polycrystalline silicon, or the like. Although a transistor using amorphous silicon has a low field-effect mobility, it can cope with the enlargement of the area of the glass substrate. Further, a transistor using polycrystalline silicon has a high field-effect mobility but has a drawback that it is not suitable for the enlargement of the area of the glass substrate.

[0004] In addition to transistors using silicon, in recent years, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have attracted attention. For example, as an oxide semiconductor, a transistor is manufactured using zinc oxide, an In-Ga-Zn-O-based oxide, etc., and a technique for using it as a switching element of a pixel of a display device is disclosed in Patent Document 1 and Patent Document 2. In addition to transistors using silicon, in recent years, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have attracted attention. For example, as an oxide semiconductor, a transistor is manufactured using zinc oxide, an In-Ga-Zn-O-based oxide, etc., and a technique for using it as a switching element of a pixel of a display device is disclosed in Patent Document 1 and Patent Document 2. In addition to transistors using silicon, in recent years, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have attracted attention. For example, as an oxide semiconductor, a transistor is manufactured using zinc oxide, an In-Ga-Zn-O-based oxide, etc., and a technique for using it as a switching element of a pixel of a display device is disclosed in Patent Document 1 and Patent Document 2. In addition to transistors using silicon, in recent years, techniques for manufacturing transistors using oxide semiconductors and applying them to electronic devices and optical devices have attracted attention. For example, as an oxide semiconductor, a transistor is manufactured using zinc oxide, an In-Ga-Zn-O-based oxide, etc., and a technique for using it as a switching element of a pixel of a display device is disclosed in Patent Document 1 and Patent Document 2. has been done.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0006] One aspect of the present invention is to provide a material suitable for semiconductor applications such as transistors and diodes. This is one of the problems.

[0007] Another problem is to provide a semiconductor device that can perform highly reliable mass production using a large substrate such as a mother glass. This is one of the problems.

[0008] The electrical characteristics of a transistor are easily affected by the electronic state at the interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film. During or after the fabrication of the transistor, if the interface between the oxide semiconductor film and the gate insulating film is in an amorphous state, the defect density at the interface is large, and the electrical characteristics of the transistor tend to be unstable. Moreover, the electrical characteristics of a transistor using an oxide semiconductor film as a channel change when irradiated with visible light or ultraviolet light.

[0009] In view of such problems, one aspect of the present invention is to provide a semiconductor device having a transistor in which the electronic state at the interface between an oxide semiconductor film and a gate insulating film in contact with the oxide semiconductor film is good. This is one of the problems.

[0010] This is one of the problems. This is one of the problems. This is one of the problems.

[0011] In addition, it is an object to impart stable electrical characteristics to a transistor using an oxide semiconductor film as a channel and to fabricate a highly reliable semiconductor device.

Means for Solving the Problem

[0012] An oxide material is used, which has a c-axis orientation and an atomic arrangement that is triangular or hexagonal when viewed from the direction of the ab-plane, surface, or interface, and includes crystals with different a-axis or b-axis orientations in the ab-plane.

[0013] Note that the aforementioned oxide material may contain zinc. By containing zinc, it becomes easier to form an oxide material that has a c-axis orientation and an atomic arrangement that is triangular or hexagonal when viewed from the direction of the ab-plane, surface, or interface, and includes crystals with different a-axis or b-axis orientations in the ab-plane.

[0014] Alternatively, the aforementioned oxide material is made of a material containing two or more elements selected from indium, gallium, zinc, tin, titanium, and aluminum.

[0015] The aforementioned oxide material can be formed by a sputtering method, a molecular beam epitaxy method, an atomic layer deposition method, or a pulsed laser deposition method.

[0016] The aforementioned oxide material can be formed by crystallizing it by laminating two films with different compositions or by heat-treating it after lamination.

[0017] One aspect of the present invention is an oxide material having a plurality of metal oxide layers, wherein the metal oxide layers are bonded to each other via oxygen atoms with a coordination number of 4 (hereinafter referred to as 4-coordinated O). Also, one metal oxide layer , a central metal atom with a coordination number of 4, a central metal atom with a coordination number of 5, or a central metal atom that has both a coordination number of 5 and a coordination number of 6, and forms a planar layer through a three-coordinate oxygen atom (hereinafter, three-coordinate O) or a four-coordinate O. When the aforementioned oxide material has conductivity, it can be used as the material for the gate electrode of a transistor. Note that the gate electrode may be formed by laminating a film made of the aforementioned oxide material and a metal film.

[0018] When the aforementioned oxide material has conductivity, it can be used as the material for the source electrode and the drain electrode of a transistor. Note that the source electrode and the drain electrode may be formed by laminating a film made of the aforementioned oxide material and a metal film.

[0019] When the aforementioned oxide material has semiconductor properties, a film made of the aforementioned oxide material can be used for the active layer of a transistor. In that case, for example, it is provided in contact with a conductive film that functions as the source electrode and the drain electrode of the transistor, and an insulating film. Note that the aforementioned insulating film functions as the gate insulating film, the underlying insulating film, or the interlayer insulating film of the transistor.

[0020]

Advantages of the Invention

[0021] According to one aspect of the present invention, a semiconductor device having excellent electrical characteristics can be manufactured.

[0022] Also, by using a large substrate such as a mother glass, mass production of highly reliable semiconductor devices can be carried out.

Brief Description of the Drawings

[0023]

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Mode for Carrying Out the Invention

[0024] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and those skilled in the art can easily understand that its form and details can be variously changed. Also, the present invention is not construed as being limited to the description content of the embodiments shown below. In explaining the configuration of the invention with reference to the drawings, the same reference numerals are commonly used between different drawings. When referring to the same things, the hatch pattern is the same, and there may be cases where no reference numerals are particularly assigned. Hereinafter, the present invention will be described, but the terms used in this specification will be briefly explained. First, regarding the source and drain of the transistor, in this specification, when one is called the drain the other is taken as the source. That is, they are not distinguished by the level of potential. Therefore when irradiating the transistor with light.

[0025] Hereinafter, the present invention will be described, but the terms used in this specification will be briefly explained. First, regarding the source and drain of the transistor, in this specification, when one is called the drain the other is taken as the source. That is, they are not distinguished by the level of potential. Therefore when one is called the drain, the other is taken as the source. That is, they are not distinguished by the level of potential. Therefore In this specification, the part regarded as the source can also be read as the drain.

[0026] Also, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively.

[0027] In this specification, even when the expression "connect" is used, in an actual circuit, it may only be the case where there is no physical connection part and the wiring is extending.

[0028] Note that the ordinal numbers attached as the first and second are used for convenience and do not indicate the process order or the stacking order. Also, they do not indicate a unique name as a matter for specifying the invention in this specification.

[0029] (Embodiment 1) In this embodiment, a method for forming an oxide film containing a c-axis oriented crystal having a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and in the c-axis direction, metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers, and in the ab-plane (or surface or interface), crystals with different a-axis or b-axis directions (rotated around the c-axis) (also referred to as CAAC: C Axis Aligned Crystal) will be described.

[0030] CAAC-containing oxide, in a broad sense, is a non-single crystal, and when viewed from a direction perpendicular to its ab-plane, it has an atomic arrangement of a triangle, hexagon, equilateral triangle, or regular hexagon, and when viewed from a direction perpendicular to the c-axis direction, a phase in which metal atoms are arranged in layers or metal atoms and oxygen atoms are arranged in layers. ​​​​​​​​​​refers to a material containing the same. Also, an oxide film containing CAAC may have a new structure with grain boundaries and is not necessarily arranged with respect to the ab plane.

[0031] CAAC is not a single crystal. Also, an oxide film containing CAAC is not formed only from amorphous materials. Further, an oxide film containing CAAC may contain crystallized portions (crystalline portions), but in some cases, the boundaries between one crystalline portion and another cannot be clearly distinguished.

[0032] A part of the oxygen constituting the oxide film containing CAAC may be substituted with nitrogen. Also, the c-axes of the individual crystalline portions constituting CAAC may be aligned in a certain direction (for example, a direction perpendicular to the substrate surface supporting CAAC or the surface of the oxide film containing CAAC). Alternatively, the normal vectors of the ab planes of the individual crystalline portions constituting CAAC may face a certain direction (for example, a direction perpendicular to the substrate surface supporting CAAC or the surface of the oxide film containing CAAC).

[0033] An oxide film containing CAAC may be a conductor, a semiconductor, or an insulator depending on its composition and the like. Also, depending on its composition and the like, it may be transparent or opaque to visible light.

[0034] As an example of such an oxide containing CAAC, a material that is formed in a film shape and, when observed from a direction perpendicular to the film surface, substrate surface, or interface, has a triangular or hexagonal atomic arrangement, and when observing the cross-section of the film, has a layered arrangement of metal atoms or a layered arrangement of metal atoms and oxygen atoms (or nitrogen atoms) can be cited.

[0035] CAAC will be described in detail with reference to FIG. 1. Unless otherwise specified, FIG. 1 is oriented upward. Set the direction as the c-axis direction, and the plane perpendicular to the plane shown in FIG. 1 as the ab-plane. Note that when simply referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary. When referring to the upper half and the lower half, it means the upper half and the lower half with the ab-plane as the boundary.

[0036] FIG. 1(A) shows a structure having one 6-coordinate metal atom M_1 and six 4-coordinate O's adjacent to the metal atom M_1. Such a structure showing only the adjacent oxygen atoms for one such metal atom is herein called a subunit. The structure of FIG. 1(A) takes an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O's each in the upper half and the lower half of FIG. 1(A). The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. Although the subunit typically shows only one metal atom, actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. The structure of FIG. 1(A) takes an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O's each in the upper half and the lower half of FIG. 1(A). The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. The structure of FIG. 1(A) takes an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O's each in the upper half and the lower half of FIG. 1(A). The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. The structure of FIG. 1(A) takes an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O's each in the upper half and the lower half of FIG. 1(A). The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads. The structure of FIG. 1(A) takes an octahedral structure, but is shown in a planar structure for simplicity. Note that there are three 4-coordinate O's each in the upper half and the lower half of FIG. 1(A). The subunit typically shows only one metal atom, but actually, a plurality of subunits are planarized through 3-coordinate O or 4-coordinate O to form a metal oxide layer that spreads.

[0037] FIG. 1(B) shows a structure having one 5-coordinate metal atom M_2, three 3-coordinate O's adjacent to the metal atom M_2, and two 4-coordinate O's adjacent to the metal atom M_2. All the 3-coordinate O's are present on the ab-plane. There is one 4-coordinate O each in the upper half and the lower half of FIG. 1(B). All the 3-coordinate O's are present on the ab-plane. There is one 4-coordinate O each in the upper half and the lower half of FIG. 1(B). All the 3-coordinate O's are present on the ab-plane. There is one 4-coordinate O each in the upper half and the lower half of FIG. 1(B).

[0038] FIG. 1(C) shows a structure consisting of one 4-coordinate metal atom M_3 and four 4-coordinate O's adjacent to the metal atom M_3. There is one 4-coordinate O in the upper half of FIG. 1(C) and three 4-coordinate O's in the lower half. There is one 4-coordinate O in the upper half of FIG. 1(C) and three 4-coordinate O's in the lower half.

[0039] The metal atoms having these coordination numbers are bonded through 4-coordinate O. Specifically, they bond when the number of 4-coordinate O adds up to four. For example, when the 6-coordinate metal atom M_1 has four 4-coordinate O's in the upper half The metal atoms having these coordination numbers are bonded through 4-coordinate O. Specifically, they bond when the number of 4-coordinate O adds up to four. For example, when the 6-coordinate metal atom M_1 has four 4-coordinate O's in the upper half When bonding through the O of the site, since there are three 4-coordinate Os, the 5-coordinate metal atom M_2's upper half of the 4-coordinate O, the lower half of the 4-coordinate O of the 5-coordinate metal atom M_2, or the upper half of the 4-coordinate O of the 4-coordinate metal atom M_3 will bond with any of them.

[0040] Also, in addition to this, the sub-units bond to each other so that the total charge of the layer structure becomes 0 .

[0041] Here, for the 3-coordinate O and 4-coordinate O, the charge per bond can be considered to be -0.6 67 and -0.5 respectively. For example, the charges of In (6-coordinate or 5-coordinate), Zn (4 -coordinate), Ga (5-coordinate), and Sn (5-coordinate or 6-coordinate) are +3, +2, +3, and +4 respectively. Therefore, the sub-units composed of In, the sub-units composed of Zn, and the sub-units composed of G a have a charge of 0. So, for these combinations, the total charge of the layer structure is always 0. On the other hand, the sub-unit composed of Sn has a charge of +1 . Therefore, in order to form a layer structure containing Sn, a charge of -1 that cancels out the charge of +1 is required . As a structure with a charge of -1, a structure in which two Zn sub-units are bonded can be mentioned . For example, if there is one structure in which two Zn sub-units are bonded to one Sn sub-unit , the charges are canceled out, so the total charge of the layer structure can be made 0 .

[0042] Figure 1(D) shows the layer structure of the In-Sn-Zn-O system. For simplicity, the 3-coordinate O is omitted , and only the number of 4-coordinate Os is shown. Assume that In can take both 5-coordinate and 6-coordinate . By using the structure that repeats one period shown in Figure 1(D), In-Sn-Z An n-O-based crystal (In2SnZn3O8) can be obtained. Note that In-Sn-Zn -O-based layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) can be represented by a composition formula. In addition, materials of In-Sn-Ga-Zn-O system, In -Ga-Zn-O system, In-Si-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Z n-O system, In-Zn-O system, Sn-Zn-O system, Al-Zn-O system, Zn-Mg-O system, Sn-Mg-O system, In-Mg-O system , In-Ga-O system, In-O system, Sn-O system, Zn-O system and the like are the same when used.

[0043] Next, a method for forming an oxide film containing CAAC will be described.

[0044] First, a first oxide film is formed on a substrate by sputtering, molecular beam epitaxy, atomic layer deposition or pulsed laser deposition. By heating the substrate during film formation, an oxide film with a higher ratio of crystal region to amorphous region can be obtained. For example, the substrate temperature should be 150 °C or higher and 450 °C or lower. Preferably, the substrate temperature is 200 °C or higher and 35 0 °C or lower.

[0045] By increasing the substrate temperature, the oxide film containing CAAC can be further crystallized .

[0046] Next, a first heat treatment may be performed on the substrate. By performing the first heat treatment, more amorphous An oxide film with a high ratio of the crystalline region to the amorphous region can be obtained. The first heat treatment may be performed, for example, at a temperature of 200 °C or higher and lower than the strain point of the substrate. Preferably, the temperature is 250 °C or higher and 450 °C or lower. The atmosphere is not limited, and the treatment may be performed in an oxidizing atmosphere, an inert atmosphere, or a reduced-pressure atmosphere. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the higher the ratio of the crystalline region to the amorphous region in the oxide film that can be formed. However, heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity. For example, it may be performed at a temperature of 200 °C or higher and lower than the strain point of the substrate. Preferably, the temperature is 250 °C or higher and 450 °C or lower. The atmosphere is not limited, and the treatment may be performed in an oxidizing atmosphere, an inert atmosphere, or a reduced-pressure atmosphere. The treatment time is 3 minutes to 24 hours. The longer the treatment time, the higher the ratio of the crystalline region to the amorphous region in the oxide film that can be formed. However, heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity. The longer the treatment time, the higher the ratio of the crystalline region to the amorphous region in the oxide film that can be formed. However, heat treatment exceeding 24 hours is not preferable because it causes a decrease in productivity.

[0047] An oxidizing atmosphere is an atmosphere containing an oxidizing gas. The oxidizing gas is preferably oxygen, ozone, nitrous oxide, etc., and preferably does not contain water, hydrogen, etc. For example, the purity of oxygen, ozone, or nitrous oxide introduced into the heat treatment apparatus is 8N (99.999999%) or higher, preferably 9N (99.9999999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably less than 0.1 ppm). The oxidizing atmosphere may be used by mixing the oxidizing gas with an inert gas. In that case, the oxidizing gas should contain at least 10 ppm or more. For example, the purity of oxygen, ozone, or nitrous oxide introduced into the heat treatment apparatus is 8N (99.999999%) or higher, preferably 9N (99.9999999%) or higher (i.e., the impurity concentration is 1 ppm or lower, preferably less than 0.1 ppm). The oxidizing atmosphere may be used by mixing the oxidizing gas with an inert gas. In that case, the oxidizing gas should contain at least 10 ppm or more. The oxidizing atmosphere may be used by mixing the oxidizing gas with an inert gas. In that case, the oxidizing gas should contain at least 10 ppm or more. The oxidizing atmosphere may be used by mixing the oxidizing gas with an inert gas. In that case, the oxidizing gas should contain at least 10 ppm or more. The oxidizing atmosphere may be used by mixing the oxidizing gas with an inert gas. In that case, the oxidizing gas should contain at least 10 ppm or more.

[0048] Here, an inert atmosphere is an atmosphere mainly composed of an inert gas such as nitrogen, noble gases (helium, neon, argon, krypton, xenon), etc. Specifically, the reactive gas such as an oxidizing gas should be less than 10 ppm. Here, an inert atmosphere is an atmosphere mainly composed of an inert gas such as nitrogen, noble gases (helium, neon, argon, krypton, xenon), etc. Specifically, the reactive gas such as an oxidizing gas should be less than 10 ppm. Here, an inert atmosphere is an atmosphere mainly composed of an inert gas such as nitrogen, noble gases (helium, neon, argon, krypton, xenon), etc. Specifically, the reactive gas such as an oxidizing gas should be less than 10 ppm.

[0049] The first heat treatment can be performed using an RTA (Rapid Thermal Anneal) apparatus. By using RTA, heat treatment can be performed at a temperature above the strain point of the substrate in a short time. Therefore, an oxide film with a high ratio of the crystalline region to the amorphous region can be formed. By using RTA, heat treatment can be performed at a temperature above the strain point of the substrate in a short time. Therefore, an oxide film with a high ratio of the crystalline region to the amorphous region can be formed. ​​The time required can be shortened.

[0050] As the oxide, a material represented by the chemical formula InMO3(ZnO) m (m>0) may be used. Here, M represents one or more metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co etc. may be used.

[0051] Also, nitrogen at 5×10 19 atoms / cm 3 or more, preferably 1×10 20 atoms / cm 3 or more and less than 7 atomic% of the In-Ga-Zn-O-based material containing nitrogen becomes an oxide containing a c-axis-oriented hexagonal crystal structure, and between the In-O crystal plane (crystal plane containing indium and oxygen) and the In -O crystal plane (crystal plane containing indium and oxygen), there is a layer having a single layer of Ga and Zn. Or, in the In-Ga-Zn-O-based oxide material containing nitrogen within the above range, between the In-O crystal plane and the In-O crystal plane, a layer having a plurality of layers of Ga and Zn may be provided.

[0052] Next, a second oxide film may be formed on the first oxide film to form an oxide laminate. The first oxide film and the second oxide film can be formed by the same method.

[0053] When forming the second oxide film, by forming the film while heating the substrate, the second oxide film can be crystallized with the first oxide film as a seed crystal. At this time, when the first oxide film and the second oxide film are composed of the same elements, it is called homoepitaxial growth. Or, between the first oxide film and the second oxide film The second oxide film is composed of at least one different element, which is called heteroepitaxial growth. It is said.

[0054] Note that after forming the second oxide film, a second heat treatment may be performed. The second heat treatment may be performed in the same manner as the first heat treatment. By performing the second heat treatment, an oxide laminate with a higher proportion of crystal regions compared to the amorphous region can be obtained. Or, by performing the second heat treatment, the second oxide film can be crystallized using the first oxide film as a seed crystal. At this time, it may be homoepitaxial growth in which the first oxide film and the second oxide film are composed of the same element. Or, it may be heteroepitaxial growth in which the first oxide film and the second oxide film are composed of at least one different element. And so on. And so on. And so on. And so on. And so on. And so on.

[0055] An oxide film containing CAAC can be formed by the above method.

[0056] This embodiment can be used in appropriate combination with other embodiments.

[0057] (Embodiment 2) In this embodiment, an example of a transistor using the oxide film containing CAAC shown in Embodiment 1 will be described with reference to FIG. 2. And so on.

[0058] FIG. 2(A) is a top view of the transistor. The dashed-dotted line A-B and the dashed-dotted line C-D shown in FIG. 2(A) correspond to the A-B cross-section shown in FIG. 2(B) and the C-D cross-section shown in FIG. 2(C), respectively. And so on. And so on.

[0059] Here, the A-B cross-section shown in FIG. 2(B) will be described in detail.

[0060] The cross-section A-B includes a substrate 100, a gate electrode 104 on the substrate 100, a gate insulating film 112 covering the substrate 100 and the gate electrode 104, a semiconductor film 106 on the gate insulating film 112, a pair of electrodes 116 on the semiconductor film 106 and in partial contact with the semiconductor film 106, and an interlayer insulating film 118 covering the gate insulating film 112, the semiconductor film 106, and the pair of electrodes 116, and is a cross-section of a transistor. The gate electrode 104 may have a single-layer or laminated structure, and may be selected from one or more of Al, Ti, Cr, Co, Ni, Cu, Y, Zr, Mo, Ag, Ta, and W, their nitrides, oxides, and alloys. Further, the gate electrode 104 may have a configuration including a conductive film (oxide conductive film) made of an oxide film containing CAAC shown in Embodiment 1. The work function can be controlled by the composition of the oxide conductive film.

[0061] When the oxide conductive film is used for the gate electrode 104, since the oxide conductive film has a higher resistance than the metal film, it is preferable to laminate and use it with a low-resistance film selected from the above-described materials so that the sheet resistance becomes 10 Ω / sq or less in order to reduce the resistance of the gate electrode 104. However, a laminated structure is selected so that the oxide conductive film is on the gate insulating film 112 side.

[0062]

[0063] In FIG. 2, the gate electrode 104 is made larger than the semiconductor film 106 in both the vertical and horizontal directions in the top view to suppress deterioration of the semiconductor film 106 due to light and generation of charges, but it is not limited thereto. The semiconductor film 106 may be made larger than the gate electrode 104 in both the vertical and horizontal directions in the top view.

[0064] ​​​​​​​​​​​​​ There is no significant limitation on the substrate 100, but it should at least have heat resistance enough to withstand subsequent heat treatment. For example, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 100. Also, single crystal semiconductor substrates such as silicon and silicon carbide, polycrystalline semiconductor substrates, compound semiconductor substrates such as silicon germanium, SOI ( Silicon On Insulator) substrates, etc. can also be applied, and those with semiconductor elements provided on these substrates may be used as the substrate 100. Moreover, a flexible substrate may be used as the substrate 100. In that case, transistors will be fabricated directly on the flexible substrate. Note that to provide a transistor on a flexible substrate,

[0065] there is also a method of using a non-flexible substrate as the substrate 100, fabricating a transistor thereon, then peeling off the transistor and transferring it to the flexible substrate. In that case, it is advisable to provide a release layer between the substrate 100 and the transistor.

[0066] The semiconductor film 106 may be a silicon film, a germanium film, a silicon germanium film, a silicon carbide film or a gallium nitride film, or a semiconductor film (oxide semiconductor film) made from the oxide film containing CAAC shown in Embodiment 1. Since the oxide semiconductor film is easy to form and has a high field-effect mobility without performing laser beam processing or the like, it is preferable as a material to be used for the semiconductor film 106. Also, a transistor with few interface levels at the interface between the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor film can be obtained.

[0067] The gate insulating film 112 and the interlayer insulating film 118 are, for example, silicon oxide, silicon oxynitride , silicon oxynitride, silicon nitride, aluminum oxide, hafnium oxide, yttrium oxide, or zirconium oxide may be used, and they may be provided in a stacked or single layer. For example, they may be formed by thermal oxidation method, CVD method, sputtering method, etc. The gate insulating film 112 and the interlayer insulating film 118 may be made of a film that releases oxygen upon heating. By using a film that releases oxygen upon heating, defects generated in the semiconductor film 106 can be repaired, and deterioration of the electrical characteristics of the transistor can be suppressed. Here, silicon oxynitride refers to a material in which the oxygen content is higher than the nitrogen content in its composition. For example, oxygen is 50 atomic% or more and 70 atomic% or less, nitrogen is 0.5 atomic% or more and 15 atomic% % or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 0 atomic% or more and 10 atomic% or less. Also, silicon nitride oxide refers to a material in which the nitrogen content is higher than the oxygen content in its composition. For example, oxygen is 5 atomic% or more and 30 atomic% % or less, nitrogen is 20 atomic% or more and 55 atomic% or less, silicon is 25 atomic% or more and 35 atomic% or less, and hydrogen is 10 atomic%

[0068] % or more and 25 atomic% or less. However, the above ranges are for the case measured by Rutherford Backscattering Spectrometry (RBS) or Hydrogen Forward Scattering Spectrometry (HFS). In addition, the content ratio of the constituent elements takes a value whose total does not exceed 100 atomic%. The gate insulating film 112 and the interlayer insulating film 118 are such that the material of the pair of electrodes 116 is the semiconductor film 10 rometry) or Hydrogen Forward Scattering Spectrometry (HFS). rometry) and Hydrogen Forward Scattering Spectrometry (HFS).

[0069] If it diffuses to 6 and may have an adverse effect on transistor characteristics, an insulating film with a small diffusion coefficient of the material of the pair of electrodes 116 may be used. The interlayer insulating film 118 functions as a protective film for the semiconductor film 106. "Releasing oxygen by heating" means that in TDS (Thermal Desorption S pectroscopy: temperature-programmed desorption gas spectroscopy) analysis, the release amount of oxygen in terms of oxygen atoms is

[0070] 1.0×10 or more, preferably 3.0×10 atoms / cm 18 or more. 3 Here, regarding the method for measuring the release amount of oxygen in terms of oxygen atoms in TDS analysis, it will be described below. 20 ato ms / cm 3 or more.

[0071] Here, regarding the method for measuring the release amount of oxygen in terms of oxygen atoms in TDS analysis, it will be described below. to.

[0072] The release amount of gas during TDS analysis is proportional to the integral value of the spectrum. Therefore, the release amount of gas can be calculated by the ratio of the integral value of the measured spectrum to the reference value of the standard sample. The reference value of the standard sample is the ratio of the atomic density to the integral value of the spectrum of a sample containing a predetermined atom. For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating film, the release amount of oxygen molecules (N ) of the insulating film can be obtained by Equation 1. Here, it is assumed that all of the spectra detected at a mass number of 32 obtained by TDS analysis are derived from oxygen molecules. Although there is CH3OH as a substance with a mass number of 32, it is not considered here as it has a low possibility of existence. Also, the isotope of oxygen atom with a mass number of is

[0073] For example, from the TDS analysis results of a silicon wafer containing hydrogen with a predetermined density as a standard sample and the TDS analysis results of the insulating film, the release amount of oxygen molecules (N ) of the insulating film can be obtained by Equation 1. Here, it is assumed that all of the spectra detected at a mass number of 32 obtained by TDS analysis are derived from oxygen molecules. Although there is CH3OH as a substance with a mass number of 32, it is not considered here as it has a low possibility of existence. Also, the isotope of oxygen atom with a mass number of O2 can be obtained by Equation 1. Here, it is assumed that all of the spectra detected at a mass number of 32 obtained by TDS analysis are derived from oxygen molecules. Although there is CH3OH as a substance with a mass number of 32, it is not considered here as it has a low possibility of existence. Also, the isotope of oxygen atom with a mass number of 32 detected by TDS analysis is assumed to be entirely from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as its possibility of existence is low. Also, the isotope of the oxygen atom with a mass number of 32 detected by TDS analysis is assumed to be entirely from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as its possibility of existence is low. Also, the isotope of the oxygen atom with a mass number of 32 detected by TDS analysis is assumed to be entirely from oxygen molecules. Although there is CH3OH with a mass number of 32, it is not considered here as its possibility of existence is low. Also, the isotope of the oxygen atom with a mass number of Oxygen molecules containing oxygen atoms with a mass number of 17 and oxygen atoms with a mass number of 18 are also not considered because their abundance ratios in nature are extremely low. Since the abundance ratio is extremely low, it is not considered.

[0074] N O2 =N H2 / S H2 ×S O2 ×α (Equation 1)

[0075] N H2 is the value obtained by converting the hydrogen molecules desorbed from the standard sample in terms of density. S H2 is the integrated value of the spectrum when the standard sample is analyzed by TDS. Here, let the reference value of the standard sample be N H2 / S H2 Let it be S O2 is the integrated value of the spectrum when the insulating film is analyzed by TDS α is a coefficient that affects the spectrum intensity in TDS analysis. For details of Equation 1, refer to Japanese Patent Laid-Open No. 6-275697. The oxygen release amount of the above insulating film is measured using a temperature-programmed desorption analyzer EMD-WA1000S / W manufactured by Denso Kagaku Co., Ltd. with a silicon wafer containing 1×10 16 atoms / cm 3 of hydrogen atoms as a standard sample.

[0076] In addition, in TDS analysis, part of the oxygen is detected as oxygen atoms. The ratio of oxygen molecules to oxygen atoms can be calculated from the ionization rate of oxygen molecules. Since the above-mentioned α includes the ionization rate of oxygen molecules, by evaluating the release amount of oxygen molecules, the release amount of oxygen atoms can also be estimated.

[0077] Note that N O2 is the release amount of oxygen molecules. The release amount when converted to oxygen atoms is twice the release amount of oxygen molecules. ​

[0078] In the above configuration, the film that releases oxygen by heating may be silicon oxide (SiO X (X>2)) even when oxygen is in excess. Silicon oxide (SiO X (X>2)) means that it contains oxygen atoms more than twice the number of silicon atoms per unit volume. The number of silicon atoms and oxygen atoms per unit volume are values measured by the Rutherford backscattering method.

[0079] By supplying oxygen from the gate insulating film 112 or the interlayer insulating film 118 to the semiconductor film 106 which is an oxide semiconductor film, the interface state density between the semiconductor film 106 and the gate insulating film 112, and also the interface state density between the semiconductor film 106 and the interlayer insulating film 118 can be reduced. As a result, it is possible to suppress carriers from being trapped at the interface between the semiconductor film 106 and the gate insulating film 112, or at the interface between the semiconductor film 106 and the interlayer insulating film 118 due to the operation of the transistor or the like, and a transistor with less deterioration of electrical characteristics can be obtained.

[0080] Furthermore, charges may be generated due to oxygen deficiency in the oxide semiconductor film. Generally, part of the oxygen deficiency in the oxide semiconductor film becomes a donor and releases electrons which are carriers. As a result, the threshold voltage of the transistor shifts in the negative direction. By sufficiently supplying oxygen from the gate insulating film 112 or the interlayer insulating film 118 to the semiconductor film 106 which is an oxide semiconductor film, it is possible to reduce the oxygen deficiency density of the oxide semiconductor film which is a factor for the threshold voltage to shift in the negative direction.

[0081] ​​​​​​​​​​​​That is, a film that releases oxygen by heating is provided on the gate insulating film 112 or the interlayer insulating film 118. By doing so, the interface state density at the interface between the semiconductor film 106 and the gate insulating film 112, or the interface state density at the interface between the semiconductor film 106 and the interlayer insulating film 118, and the oxygen deficiency density of the semiconductor film 106 which is an oxide semiconductor film can be reduced, and the influence of carrier capture at the interface between the semiconductor film 106 which is an oxide semiconductor film and the gate insulating film 112 or the interlayer insulating film 118 can be reduced. This is possible.

[0082] For the pair of electrodes 116, metals, metal nitrides, metal oxides, alloys, etc. shown by the gate electrode 104 may be appropriately used.

[0083] When a film containing Cu is used for the pair of electrodes 116, the resistance of the wiring can be reduced, and the occurrence of wiring delay or the like can be reduced even in a large display device or the like. When Cu is used for the pair of electrodes 116, since the adhesion deteriorates depending on the material of the substrate 100, it is preferable to form a laminate structure with a film having good adhesion to the substrate 100. As the film having good adhesion to the substrate 100, a film containing Ti, Mo, Mn, or Al, etc. may be used. For example, a Cu-Mn-Al alloy may be used.

[0084] As described above, a transistor with controlled threshold voltage and excellent electrical characteristics can be obtained. Therefore, a semiconductor device with low power consumption, good electrical characteristics, and high reliability can be manufactured with high productivity.

[0085] This embodiment can be used in appropriate combination with other embodiments.

[0086] (Embodiment 3) ​​​​​​​In this embodiment, a transistor having a structure different from the transistor shown in Embodiment 2 will be described. will be described.

[0087] FIG. 3 is a top view and a cross-sectional view of a transistor according to one aspect of the present invention. The dashed lines A-B and C-D shown in FIG. 3(A) correspond to the A-B cross-section shown in FIG. 3(B) and the C-D cross-section shown in FIG. 3(C), respectively. respectively.

[0088] Hereinafter, the A-B cross-section shown in FIG. 3(B) will be described in detail.

[0089] The A-B cross-section includes a substrate 100, a gate electrode 104 on the substrate 100, a gate insulating film 112 covering the substrate 100 and the gate electrode 104, a pair of electrodes 116 on the gate insulating film 112, a semiconductor film 106 partially in contact with the pair of electrodes 116 on the gate electrode 104 via the gate insulating film 112, and an interlayer insulating film 118 covering the gate insulating film 112, the pair of electrodes 116, and the semiconductor film 106. is a cross-section of the transistor. In this embodiment as well, the gate electrode 104 and the semiconductor film 106 have the same configuration as in Embodiment 2. By using a gate electrode having an oxide film containing CAAC shown in Embodiment 1, the work function can be controlled, and the threshold voltage of the transistor can be controlled.

[0090] Also, by using the oxide semiconductor film shown in Embodiment 1 for the semiconductor film 106, a transistor with a low interface state density at the interface between the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor film can be obtained. using a gate electrode having an oxide film containing CAAC shown in Embodiment 1, the work function is controlled, and the threshold voltage of the transistor can be controlled. Also, by using the oxide semiconductor film shown in Embodiment 1 for the semiconductor film 106, a transistor with a low interface state density at the interface between the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor film can be obtained. a transistor with a low interface state density at the interface between the oxide semiconductor film and the gate insulating film in contact with the oxide semiconductor film can be obtained.

[0091] FIG. 4 is a top view and a cross-sectional view of a transistor according to one aspect of the present invention. The dashed line shown in FIG. 4(A) The dashed-dotted line A-B and the dashed-dotted line C-D respectively correspond to the A-B cross-section shown in FIG. 4(B) and the C-D cross-section shown in FIG. 4(C).

[0092] The A-B cross-section shown in FIG. 4(B) will be described in detail below.

[0093] The A-B cross-section has a substrate 100, an underlying insulating film 102 on the substrate 100, a semiconductor film 106 on the underlying insulating film 102, a pair of electrodes 116 on the semiconductor film 106 and in partial contact with the semiconductor film 106, a gate insulating film 112 covering the semiconductor film 106 and the pair of electrodes 116, and a gate electrode 104 on the semiconductor film 106 via the gate insulating film 112, and is a cross-section of a transistor.

[0094] The underlying insulating film 102 can have the same configuration as the gate insulating film 112 and the interlayer insulating film 118.

[0095] FIG. 5 is a top view and a cross-sectional view of a transistor according to an aspect of the present invention. The dashed-dotted line A-B and the dashed-dotted line C-D shown in FIG. 5(A) respectively correspond to the A-B cross-section shown in FIG. 5(B) and the C-D cross-section shown in FIG. 5(C).

[0096] The A-B cross-section shown in FIG. 5(B) will be described in detail below.

[0097] The A-B cross-section has a substrate 100, an underlying insulating film 102 on the substrate 100, a pair of electrodes 116 on the underlying insulating film 102, a semiconductor film 106 on the pair of electrodes 116 and in partial contact with the pair of electrodes 116, a gate insulating film 112 covering the semiconductor film 106 and the pair of electrodes 116, and a gate electrode 104 on the semiconductor film 106 via the gate insulating film 112, and is a cross-section of a transistor. ​

[0098] 3 to 5, the gate electrode 104 is larger than the semiconductor film 106 in both length and width. By forming the semiconductor film 106 in this shape, deterioration of the semiconductor film 106 due to light and generation of electric charges are suppressed. The semiconductor film 106 is located vertically and horizontally from the gate electrode 104 in a top view. It is acceptable for the shape to be large both in height and width.

[0099] 6A and 6B are a top view and a cross-sectional view of a transistor according to one embodiment of the present invention. The dashed dotted lines AB and CD indicate the cross sections AB and CD shown in FIG. 6(B), respectively. This corresponds to the CD cross section shown in FIG. 6(C).

[0100] The cross section AB shown in FIG. 6(B) will be described in detail below.

[0101] The AB cross section is a cross section of a substrate 100, an insulating base film 102 on the substrate 100, and a a semiconductor film having the region 126 and the region 121, and a gate insulating film 112 on the region 121; The gate electrode 104 on the gate insulating film 112, the base insulating film 102, the region 126, the gate an interlayer insulating film 118 covering the gate insulating film 112 and the gate electrode 104; a pair of electrodes 116 in contact with the region 126 through an opening exposing the region 126; 1 is a cross section of a transistor having a

[0102] Here, the gate insulating film 112 and the gate electrode 104 may have approximately the same top surface shape. This shape is obtained by processing the gate electrode 104 and the gate insulating film 112 using the same mask. After the gate electrode 104 and the gate insulating film 112 are formed, The width of the gate electrode 104 may be narrowed by a Zuma process or a chemical solution process.

[0103] The region 121 may have substantially the same upper surface shape as the gate insulating film 112 or the gate electrode 104. This shape can be obtained by forming the region 126 of the semiconductor film using the gate insulating film 112 or the gate electrode 104 as a mask. For example, by using the gate insulating film 112 or the gate electrode 1 04 as a mask, impurities (such as boron, phosphorus, hydrogen, rare gas, nitrogen, etc.) are introduced into the semiconductor film and the region with reduced resistance can be used as the region 126. Note that the region 121 is the region of the semiconductor film where the region 12 6 is not formed.

[0104] The region 121 functions as the channel region of the transistor. Also, the region 126 functions as the source region and drain region of the transistor.

[0105] FIG. 7 is a top view and a cross-sectional view of a transistor according to an aspect of the present invention. The dashed lines A-B and C-D shown in FIG. 7(A) correspond to the A-B cross-section shown in FIG. 7(B) and the C-D cross-section shown in FIG. 7(C), respectively.

[0106] Hereinafter, the A-B cross-section shown in FIG. 7(B) will be described in detail.

[0107] The A-B cross-section includes the substrate 100, the gate electrode 104 on the substrate 100, the gate insulating film 112 on the gate electrode 104, the region 1 26 and the semiconductor film having the region 121 on the gate electrode 104 via the gate insulating film 112, the interlayer insulating film 118 covering the semiconductor film and the gate insulating film 112, and the opening exposing the region 126 provided in the interlayer insulating film 118. A cross-section of a transistor having a pair of electrodes 116 in contact with the region 126.

[0108] FIG. 7 shows the gate insulating film 112, the gate electrode 104, and the region 121 having substantially the same upper surface shape as shown, but is not limited thereto. The shapes of the gate insulating film 112, the gate electrode 1 04, and the region 121 may be different.

[0109] As described above, a transistor with controlled threshold voltage and excellent electrical characteristics can be obtained. Therefore, a semiconductor device with low power consumption, good electrical characteristics, and high reliability can be manufactured with high productivity.

[0110] This embodiment can be used in appropriate combination with other embodiments.

[0111] (Embodiment 4) In this embodiment, a liquid crystal display device manufactured using the transistor shown in Embodiment 2 or Embodiment 3 will be described. Note that, in this embodiment, an example in which one form of the present invention is applied to a liquid crystal display device will be described, but the present invention is not limited thereto. For example, applying one form of the present invention to an EL ( Electroluminescence) display device is also easily conceivable by those skilled in the art.

[0112] FIG. 8 shows a circuit diagram of a liquid crystal display device with an active matrix driving method. The liquid crystal display device has source lines SL_1 to SL_a, gate lines GL_1 to GL_b, and a plurality of pixels 200 . Each pixel 200 includes a transistor 230, a capacitor 220, and a liquid crystal element 210 . A plurality of such pixels 200 are arranged to form the pixel portion of the liquid crystal display device. Note , when simply referring to the source line or the gate line, it is described as the source line SL or the gate line GL do.

[0113] The transistor 230 uses the transistor shown in Embodiment 2 or Embodiment 3 . By using the transistor which is one aspect of the present invention, a display device with low power consumption, good electrical characteristics and high reliability can be obtained.

[0114] The gate line GL is connected to the gate of the transistor 230, and the source line SL is connected to the source of the transistor 23 0, and the drain of the transistor 230 is connected to one capacitive electrode of the capacitor 220 and one pixel electrode of the liquid crystal element 210. The other capacitive electrode of the capacitor 220 and the other pixel electrode of the liquid crystal element 210 are connected to the common electrode. Note that the common electrode may be provided in the same layer and made of the same material as the gate line GL.

[0115] Also, the gate line GL is connected to the gate driving circuit. The gate driving circuit may include the transistor shown in Embodiment 2 or Embodiment 3. Since the threshold voltage of the transistor is controlled, the off-current can be reduced and the voltage for turning on can be reduced . Therefore, the power consumption can be reduced.

[0116] Also, the source line SL is connected to the source driving circuit. The source driving circuit may include the transistor shown in Embodiment 2 or Embodiment 3. Since the threshold voltage of the transistor is controlled, the off-current can be reduced and the voltage for turning on can be reduced . Therefore, the power consumption can be reduced.

[0117] Note that either or both of the gate drive circuit and the source drive circuit may be formed on a separately prepared substrate and connected using a method such as COG (Chip On Glass), wire bonding, or TAB (Tape Automated Bonding). Also, since transistors are easily damaged by static electricity or the like, it is preferable to provide a protection circuit. The protection circuit is preferably configured using a non-linear element.

[0118] When a potential is applied to the gate line GL so as to be equal to or higher than the threshold voltage of the transistor 230, the charge supplied from the source line SL becomes the drain current of the transistor 230 and is accumulated in the capacitor 220. After charging for one column, the transistors 230 in that column turn off, and no voltage is applied from the source line SL, but the necessary voltage can be maintained by the charge accumulated in the capacitor 220.

[0119] Then, the charging of the capacitor 220 in the next column is carried out. In this way, the charging for columns 1 to a is performed. Note that since the transistor 230 is a transistor with a controlled threshold voltage, the charge held in the capacitor 220 is difficult to leak, and the capacitance of the capacitor 220 can be reduced, so that the power consumption required for charging can be reduced.

[0120] Also, when a transistor with a small off-current (such as a transistor using an oxide semiconductor film) is used for the transistor 230, the period for maintaining the voltage can be lengthened. Due to this effect, in an image with little movement (including still images), the display rewrite frequency can be reduced.

[0121] ​​​​​​​​, further reduction of power consumption becomes possible. Also, since the capacitance of the capacitor 220 can be made even smaller , it is possible to reduce the power consumption required for charging.

[0122] As described above, according to one aspect of the present invention, a liquid crystal display device with high reliability and low power consumption can be obtained.

[0123] This embodiment can be used in appropriate combination with other embodiments.

[0124] (Embodiment 5) In this embodiment, an example of manufacturing a semiconductor memory device using the transistor shown in Embodiment 2 or Embodiment 3 will be described.

[0125] Typical examples of volatile semiconductor memory devices include DRAM (Dynamic Random Access Memory) that stores information by selecting transistors constituting memory elements and accumulating charges in capacitors, and SRAM (Static Random Access Memory) that holds the stored content using circuits such as flip-flops.

[0126] There is.

[0126] Typical examples of non-volatile semiconductor memory devices include flash memories that have a floating gate between the gate electrode and the channel formation region of a transistor and store information by holding charges in the floating gate.

[0127] The transistor shown in Embodiment 2 or Embodiment 3 can be applied to a part of the transistors included in the semiconductor memory device described above.

[0128] ​​First, a volatile memory applying the transistor shown in Embodiment 2 or Embodiment 3 will be described with reference to FIG. 9.

[0129] A memory cell includes a bit line BL, a word line WL, a sense amplifier SAmp, a transistor Tr, and a capacitor C (see FIG. 9(A)).

[0130] It is known that the voltage held in the capacitor C gradually decreases over time due to the off-current of the transistor Tr as shown in FIG. 9(B). The voltage initially charged from V0 to V1 decreases to VA, which is the limit point for reading data1, as time passes. This period is defined as the retention period T_1. That is, in the case of a binary memory cell, it is necessary to perform a refresh during the retention period T_1.

[0131] Here, when the transistor shown in Embodiment 2 or Embodiment 3 is applied to the transistor Tr, since the threshold voltage is controlled, the retention period T_1 can be extended. That is, since it is possible to reduce the refresh frequency, the power consumption can be reduced.

[0132] When a transistor with a small off-current is used for the transistor Tr, the period for maintaining the voltage can be further extended, so that the power consumption can be further reduced. For example, -21 if a DRAM is configured with a transistor using an oxide semiconductor film with a high purity and an off-current of 1 × 10 -24 A or less, preferably 1 × 10 A or less, it becomes possible to hold data for several days to several decades without power supply.

[0133] ​​​​​​​​​​As described above, according to one aspect of the present invention, a volatile memory with high reliability and low power consumption can be obtained.

[0134] Next, a non-volatile memory to which the transistor shown in Embodiment 2 or Embodiment 3 is applied will be described with reference to FIG. 10.

[0135] FIG. 10(A) is a circuit diagram of the non-volatile memory. The non-volatile memory includes a transistor Tr _1, a word line WL_1 connected to the gate of the transistor Tr_1, a source wiring SL_1 connected to the source of the transistor T r_1, a transistor Tr_2, a source wiring SL_2 connected to the source of the transistor Tr _2, a drain wiring DL_2 connected to the drain of the transistor Tr_2, a capacitor C, a capacitance wiring CL connected to one end of the capacitor C, and a floating gate FG connected to the other end of the capacitor C, the drain of the transistor Tr_1, and the gate of the transistor Tr _2. Note that the non-volatile memory shown in this embodiment utilizes the fact that the threshold voltage of the transistor Tr_2 varies according to the potential of the floating gate FG. For example,

[0136] FIG. 10(B) is a diagram for explaining the relationship between the voltage V CL of the capacitance wiring CL and the drain current I flowing through the transistor Tr_2. CL Here, the floating gate FG can adjust the voltage via the transistor Tr_1. For example, the potential of the source wiring SL_1 is set to VDD. At this time, the potential of the word line WL_1 is set to a potential obtained by adding VDD to the threshold voltage Vth of the transistor Tr_1 or higher D

[0137] Here, the floating gate FG can adjust the voltage via the transistor Tr_1. For example, the potential of the source wiring SL_1 is set to VDD. At this time, the potential of the word line WL_1 is set to a potential obtained by adding VDD to the threshold voltage Vth of the transistor Tr_1 or higher WL_1 is set to a potential obtained by adding VDD to the threshold voltage Vth of the transistor Tr_1 or higher By doing so, the potential of the floating gate FG can be set to HIGH. Also, By setting the potential of the word line WL_1 to be equal to or lower than the threshold voltage Vth of the transistor Tr_1 the potential of the floating gate FG can be set to LOW.

[0138] Therefore, either the V CL -I D _2 curve indicated by FG = LOW or the V CL -I D _2 curve indicated by FG = HIGH can be obtained. That is, when FG = LOW, since the drain current I CL _2 is small at V D = 0V, it represents data 0. Also, when FG = HIGH at V CL = 0V, since the drain current I D _2 is large, it represents data 1. In this way data can be stored.

[0139] Here, if the transistor shown in Embodiment 2 or Embodiment 3 is applied to the transistor Tr_1 the off-current of the transistor can be made extremely small, so that the charge accumulated in the floating gate FG can be prevented from leaking unintentionally between the source and drain of the transistor Tr_1. Therefore, data can be retained for a long period of time. Also, by using one aspect of the present invention, the threshold voltage of the transistor Tr_1 is controlled, so that the voltage required for writing can be reduced, and the power consumption can be reduced compared to flash memories and the like.

[0140] Note that the transistor shown in Embodiment 2 or Embodiment 3 may be applied to the transistor Tr_2. ​

[0141] Next, in the non-volatile memory shown in FIG. 10, a configuration without a capacitor will be described with reference to FIG. 1 1.

[0142] FIG. 11 is a circuit diagram of a non-volatile memory. The non-volatile memory includes a transistor Tr_1 and , a word line WL_1 connected to the gate of the transistor Tr_1, and the transistor Tr_1 's source is connected to a source wiring SL_1, a transistor Tr_2, and a transistor Tr _2's source is connected to a source wiring SL_2, and the drain of the transistor Tr_2 is connected to a drain wiring DL_2, and the drain of the transistor Tr_1 is connected to the gate of the transistor Tr_2.

[0143] When using a transistor with a small off-current for the transistor Tr_1, charge can be held between the drain of Tr_1 and the gate of Tr_2 without providing a capacitor. Since it is a configuration without a capacitor, it is possible to reduce the area, and integration can be achieved compared to the case where a capacitor is provided.

[0144] Also, in this embodiment, a non-volatile memory using four or five wirings is shown, but it is not limited to this. For example, a configuration in which the source wiring SL_1 and the drain wiring DL_2 are common may be adopted.

[0145] As described above, according to one aspect of the present invention, a semiconductor memory device with high long-term reliability and low power consumption can be obtained.

[0146] This embodiment can be used in appropriate combination with other embodiments.

[0147] (Embodiment 6) In this embodiment, an example of an electronic device to which Embodiment 2 or Embodiment 3 is applied will be described.

[0148] FIG. 12(A) shows a mobile information terminal. It includes a housing 300, buttons 301, a microphone 302, a display unit 303, a speaker 304, and a camera 305, and has functions as a mobile phone. One aspect of the present invention can be applied to the display unit 303 and the camera 305. Although not shown, one aspect of the present invention can also be applied to an arithmetic device, a wireless circuit, or a storage circuit inside the main body.

[0149] FIG. 12(B) shows a display. It includes a housing 310 and a display unit 311. One aspect of the present invention can be applied to the display unit 311. By using one aspect of the present invention, it is possible to obtain a display with high display quality even when the size of the display unit 311 is increased.

[0150] FIG. 12(C) shows a digital still camera. It includes a housing 320, buttons 321, a microphone 322, and a display unit 323. One aspect of the present invention can be applied to the display unit 323. Although not shown, one aspect of the present invention can also be applied to a storage circuit or an image sensor.

[0151] By using one aspect of the present invention, the cost of the electronic device can be reduced, and a display device with high display quality can be obtained.

[0152] This embodiment can be used in appropriate combination with other embodiments.

Example

[0153] ​​​​​​​​​​​​ Planar and cross-sectional images obtained by high-angle annular dark-field scanning transmission electron microscopy (HAADF-STEM) of an oxide containing CAAC M:High-Angle Annular Dark Field Scanning Transmission Electron Microscopy) are shown in FIGS. 13(A) and 13(B), respectively. Similarly, planar and cross-sectional images obtained by HAADF-STEM of an amorphous oxide are shown in FIGS. 14(A ) and 14(B), respectively. The sample is an In-Ga-Zn-O-based oxide film formed on a quartz substrate by DC sputtering. Other film-forming conditions were a power of 0.5 kW, a film-forming pressure of 0.4 Pa, 35 sccm of Ar and 15 sccm of O2 as the film-forming

[0154] gases, and a target-substrate distance of 60 m . The target used was an In-Ga-Zn-O target (molar ratio, In2O3: Ga2O3:ZnO = 1:1:2). The thickness was 100 nm. m. The target used was an In-Ga-Zn-O target (molar ratio, In2O3: Ga2O3:ZnO = 1:1:2). The thickness was 100 nm.

[0155] Here, Sample 1 had a substrate temperature of 400°C and Sample 2 had a substrate temperature of room temperature, and no heat treatment was performed after film formation. No heat treatment was performed after film formation.

[0156] From the planar images shown in regions 1001 and 1002 of FIG. 13(A), it was found that the atomic arrangement has a triangular or hexagonal shape when viewed from the direction of the ab plane, the surface, or the interface. Also, from the cross-sectional image shown in FIG. 13(B), it was found that metal atoms are arranged in the direction indicated by the arrow . That is, it was found that metal atoms, or metal atoms and oxygen atoms, are arranged in layers in the c-axis direction. . That is, it was found that metal atoms, or metal atoms and oxygen atoms, are arranged in layers in the c-axis direction. That is, it can be seen that Sample 1 is an oxide film containing CAAC. That is, it can be seen that Sample 1 is an oxide film containing CAAC.

[0157] From the planar image shown in FIG. 14(A), a triangular or hexagonal atomic arrangement could not be confirmed when viewed from the direction of the surface or interface. Also, from the cross-sectional image shown in FIG. 14(B), it was found that metal atoms, or metal atoms and oxygen atoms, were not arranged in layers. That is, it can be seen that Sample 2 is not an oxide film containing CAAC. As described above, an oxide film containing CAAC was obtained.

[0158]

Example

[0159] In this example, an example of evaluating the crystalline state of an oxide film containing CAAC by the X-ray diffraction (XRD: X-Ray Diffraction) method will be described.

[0160] An In-Ga-Zn-O-based oxide film of the sample was formed on a quartz substrate by DC sputtering. Other film formation conditions were a power of 0.5 kW, a film formation pressure of 0.4 Pa, a target-substrate distance of 60 mm, and a substrate temperature of 400 °C. The target used was an In-Ga-Zn-O target (molar ratio, In2O3:Ga2O3:ZnO = 1:1:2). The thickness was 300 nm.

[0161] Here, for Sample 3, the film formation gas was O2 = 40 sccm, and for Sample 4, the film formation gas was N2 = 40 sccm.

[0162] FIGS. 15 and 16 are XRD spectra measured by the out-of-plane method. FIG. 15 shows the as-deposited state after film formation, and FIG. 16 shows the state after heat treatment at 450 °C for 1 hour in an N2 atmosphere after film formation. Here, the solid line 1101 and the solid line 1103 are for Sample 3, and the solid line 110 2 and the solid line 1104 represent the XRD spectrum of Sample 4.

[0163] From FIGS. 15 and 16, it was found that under any conditions, there is a peak corresponding to (009) and it is strongly oriented along the c-axis. That is, it was found that Sample 3 and Sample 4 are c-axis oriented. In particular, a tendency was observed that the peak intensity corresponding to (009) in Sample 4 is large. Also, it was found that in Sample 3, the peak position corresponding to (009) is shifted to the low-angle side.

[0164] FIGS. 17 and 18 are XRD spectra measured by the in-plane method. FIG. 17 shows the as-deposited state, and FIG. 18 shows the state after heat treatment at 450°C for 1 hour in an N2 atmosphere after film formation. Here, the solid lines 1111 and 1113 represent Sample 3, and the solid lines 1112 and 1114 represent the XRD spectra of Sample 4.

[0165] From FIGS. 17 and 18, it was found that under any conditions, there is a peak corresponding to (009) and it is strongly oriented along the c-axis. Also, it was found that there are peaks corresponding to (110) and (119).

[0166] Next, FIGS. 19 and 20 are XRD spectra obtained by fixing the optical system at the peak position (2θ) of (110) obtained by the in-plane method and rotating the sample around the sample surface normal axis. Here, the solid lines 1121 and 1123 represent Sample 3, and the solid lines 1122 and 1124 represent the XRD spectra of Sample 4.

[0167] From FIGS. 19 and 20, no peaks were observed under any conditions.

[0168] ​​​​​​​​​​​ From FIGS. 15 to 20, it was found that the measured sample is non-single crystal and has characteristics of CAAC different from those of polycrystals. Although the oxide film of the In-Ga-Zn- O system is described in this example, it is not particularly limited to this material, and an oxide film containing CAAC can also be obtained in the oxide film of the In-Sn-Zn -O system.

Example

[0169] A transistor was fabricated using an In-Ga-Zn-O-based oxide film (film thickness: 35 nm) containing CAAC on a 600 mm × 720 mm glass substrate, and its initial characteristics are shown in FIG. 21. The channel length L of the fabricated transistor is 3 μm, the channel width W is 50 μm, and it is a bottom gate type transistor having the structure shown in FIG. 2. Also, the film thickness of the gate insulating film of the transistor is 100 nm.

[0170] FIG. 21 shows Vg-Id curve data (Vd = 1 V, Vd = 1 0 V) measured at 20 points in the substrate. Since almost the same values are plotted and overlap, it can be seen from this result that the transistor using the In-Ga-Zn-O-based oxide film containing CAAC has good uniformity. The upper Vg-Id curve in FIG. 21 is the value when Vd = 10 V, and the lower Vg-Id curve in FIG. 21 is the value when Vd = 1 V.

[0171] The average value of the threshold voltage Vth of these transistors is 1.34 V, and the average value of the field effect mobility is 10.7 cm 2 / Vs. The threshold voltage Vth is a value calculated using a curve (hereinafter also referred to as a √ Id curve) obtained by expressing the Id of the Vg-Id curve measured with V 2 d set to 10 V with its square root. d as 10 V and using the curve obtained by expressing the Id of the Vg-Id curve measured with V d as 10 V with its square root (hereinafter also referred to as the √Id curve).

[0172] In addition, in order to evaluate the reliability of the transistor, a new In-Ga-Zn- O-based oxide film (film thickness: 35 nm) was used to fabricate a plurality of transistors on a 5-inch substrate and a BT test was performed on these transistors. The channel length L of the fabricated transistor is 6 μm, the channel width W is 50 μm, and it is a bottom-gate type transistor with the structure shown in FIG. 2. In addition, the film thickness of the gate insulating film of the transistor is 100 nm.

[0173] The BT test is a type of accelerated test, and it can evaluate the characteristic changes of the transistor caused by long-term use in a short time. In particular, the change amount of the threshold voltage Vth of the transistor before and after the BT test is an important index for examining the reliability. The smaller the change amount (ΔVth) of the threshold voltage Vth before and after the BT test, the higher the reliability of the transistor can be said.

[0174] Specifically, the temperature of the substrate on which the transistor is formed (substrate temperature) is kept constant, the source and drain of the transistor are set to the same potential, and a potential different from that of the source and drain is applied to the gate for a certain period of time. The substrate temperature may be appropriately set according to the test purpose. Also when the potential applied to the gate is higher than the potentials of the source and drain, it is called a +BT test and when the potential applied to the gate is lower than the potentials of the source and drain, it is called a -BT test

[0175] The test intensity of the BT test can be determined by the substrate temperature, the electric field strength applied to the gate insulating film, and the electric field application time. The electric field strength applied to the gate insulating film is between the gate and the source and drain ​​​The potential difference of the call and the drain is determined by dividing it by the thickness of the gate insulating film. For example, when the electric field strength applied to a gate insulating film with a thickness of 100 nm is desired to be 2 MV / cm, the potential difference may be set to 20 V .

[0176] Note that voltage refers to the potential difference between two points, and potential refers to the electrostatic energy (electrical potential energy) possessed by a unit charge in the electrostatic field at a certain point. However , generally, the potential difference between the potential at a certain point and the reference potential (for example, the ground potential) is simply referred to as potential or voltage, and potential and voltage are often used as synonyms . Therefore, in this specification, unless otherwise specified, potential may be read as voltage, or voltage may be read as potential .

[0177] The BT test was performed with the substrate temperature at 80°C, the electric field strength applied to the gate insulating film at 3 MV / cm, and the application time (also called the stress time) at 100 seconds, 200 seconds, 500 seconds, 1000 seconds, 150 0 seconds, and 2000 seconds, and the +BT test and the -BT test were conducted

[0178] The results of the +BT test after 2000 seconds are shown in Fig. 22(A), and the results of the -BT test after 2000 seconds are shown in Fig. 22(B).

[0179] In Fig. 22(A), the threshold voltage Vth after the +BT test has changed by +0.63 V in the positive direction compared to the initial characteristics. In Fig. 22(B), the threshold voltage Vth after the -BT test has changed by +0.02 V in the positive direction compared to the initial characteristics. In both BT tests , the change amount ΔVth of the threshold voltage Vth is 1 V or less, and In-G including CAAC It has been confirmed that the transistor fabricated using the a-Zn-O-based oxide film has high reliability. It has been confirmed.

[0180] In addition, when conducting the BT test, it is important to use a transistor that has never been subjected to the BT test before. For example, if a -BT test is performed using a transistor that has already undergone a +BT test, the -BT test results cannot be correctly evaluated due to the influence of the previously conducted +BT test. Also, the same applies when a +BT test is performed again using a transistor that has already undergone a +BT test. However, this does not apply when deliberately repeating the BT test while taking these influences into account. For example, when performing a -BT test using a transistor that has already undergone a +BT test, the -BT test results cannot be correctly evaluated due to the influence of the previously conducted +BT test. For example, when performing a -BT test using a transistor that has already undergone a +BT test, the -BT test results cannot be correctly evaluated due to the influence of the previously conducted +BT test. In addition, when performing a +BT test again using a transistor that has already undergone a +BT test, the same applies. However, this does not apply when deliberately repeating the BT test while taking these influences into account. However, this does not apply when deliberately repeating the BT test while taking these influences into account.

[0181] In addition, the results of the +BT test (also referred to as light positive bias degradation) performed while irradiating light using an LED light source (white light with an illuminance of 10,000 lux) are shown in Fig. 23(A), and the results of the -BT test (also referred to as light negative bias degradation) performed while irradiating light using an LED light source are shown in Fig. 23(B). In addition, the results of the +BT test (also referred to as light positive bias degradation) performed while irradiating light using an LED light source (white light with an illuminance of 10,000 lux) are shown in Fig. 23(A), and the results of the -BT test (also referred to as light negative bias degradation) performed while irradiating light using an LED light source are shown in Fig. 23(B). In Fig. 23(A), the threshold voltage Vth after the +BT test has changed by +0.27 V in the positive direction compared to the initial characteristics. In Fig. 23(B), the threshold voltage Vth after the -BT test has changed by -0.23 V in the negative direction compared to the initial characteristics. In both BT tests during light irradiation, the change amount ΔVth of the threshold voltage Vth is 1 V or less, and it has been confirmed that the transistor fabricated using the In-Ga-Zn-O-based oxide film containing C In Fig. 23(A), the threshold voltage Vth after the +BT test has changed by +0.27 V in the positive direction compared to the initial characteristics. In Fig. 23(A), the threshold voltage Vth after the +BT test has changed by +0.27 V in the positive direction compared to the initial characteristics. In Fig. 23(B), the threshold voltage Vth after the -BT test has changed by -0.23 V in the negative direction compared to the initial characteristics. In both BT tests during light irradiation, the change amount ΔVth of the threshold voltage Vth is 1 V or less, and it has been confirmed that the transistor fabricated using the In-Ga-Zn-O-based oxide film containing C In Fig. 23(A), the threshold voltage Vth after the +BT test has changed by +0.27 V in the positive direction compared to the initial characteristics. In Fig. 23(B), the threshold voltage Vth after the -BT test has changed by -0.23 V in the negative direction compared to the initial characteristics. In both BT tests during light irradiation, the change amount ΔVth of the threshold voltage Vth is 1 V or less, and it has been confirmed that the transistor fabricated using the In-Ga-Zn-O-based oxide film containing C has high reliability.

[0182] In addition, Fig. 24 shows the time dependence of the change amount ΔVth of the threshold voltage Vth under various stress conditions. The vertical axis shows the change amount ΔVth of the threshold voltage Vth on a linear scale. In addition, Fig. 24 shows the time dependence of the change amount ΔVth of the threshold voltage Vth under various stress conditions. The vertical axis shows the change amount ΔVth of the threshold voltage Vth on a linear scale. On the other hand, the horizontal axis shows the stress time on a logarithmic scale.

[0183] FIG. 25(A) and FIG. 25(B) show schematic diagrams for explaining the mechanism of photo-negative bias degradation. FIG. 25(A) and FIG. 25(B) represent the interface between the oxide semiconductor and the gate insulating film. As shown in FIG. 25(A), when light hits the transistor, holes are generated. These holes are trapped and detrapped. As shown in FIG. 25(B), these holes are attracted to the gate insulating film to become fixed charges, causing the threshold voltage Vth to shift negatively. Therefore, the absence of oxygen vacancy levels is important for eliminating photo-negative bias degradation. That is, reducing oxygen deficiency is effective for eliminating photo-negative bias degradation. Since oxygen is less likely to escape from the crystalline surface than from the amorphous surface, transistors using an In-Ga-Zn-O oxide film containing CAAC have high reliability. Also, in order to reduce oxygen deficiency, using a film that releases oxygen by heating as the gate insulating film and the interlayer insulating film, or performing heat treatment in an oxidizing atmosphere is effective for enhancing reliability.

Explanation of Reference Numerals

[0184] 100 Substrate 102 Underlying insulating film 104 Gate electrode 106 Semiconductor film 112 Gate insulating film 116 Electrode 118 Interlayer insulating film 121 Region 126 Region 200 Pixel 210 Liquid crystal element 220 Capacitor 230 Transistor 300 Housing 301 Button 302 Microphone 303 Display unit 304 Speaker 305 Camera 310 Housing 311 Display unit 320 Housing 321 Button 322 Microphone 323 Display unit 1001 Area 1002 Area 1101 Solid line 1102 Solid line 1103 Solid line 1104 Solid line 1111 Solid line 1112 Solid line 1113 Solid line 1114 Solid line 1121 Solid line 1122 Solid line 1123 Solid line 1124 Solid line

Claims

【Claim 1】 An oxide material having a c-axis orientation and having a triangular or hexagonal atomic arrangement when viewed from the direction of the ab-plane, surface, or interface, and including crystals having different a-axis or b-axis orientations in the ab-plane, A transistor using the oxide material as an active layer.

Images